#include "Target/ARM/ARMBaseRegisterInfo.h"

Inheritance diagram for llvm::ARMBaseRegisterInfo:

[legend]

Public Member Functions
const MCPhysReg *	getCalleeSavedRegs (const MachineFunction *MF) const override
	Code Generation virtual methods...

const MCPhysReg *	getCalleeSavedRegsViaCopy (const MachineFunction *MF) const

const uint32_t *	getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override

const uint32_t *	getNoPreservedMask () const override

const uint32_t *	getTLSCallPreservedMask (const MachineFunction &MF) const

const uint32_t *	getSjLjDispatchPreservedMask (const MachineFunction &MF) const

const uint32_t *	getThisReturnPreservedMask (const MachineFunction &MF, CallingConv::ID) const
	getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e.

ArrayRef< MCPhysReg >	getIntraCallClobberedRegs (const MachineFunction *MF) const override

BitVector	getReservedRegs (const MachineFunction &MF) const override

bool	isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const override

bool	isInlineAsmReadOnlyReg (const MachineFunction &MF, unsigned PhysReg) const override

const TargetRegisterClass *	getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override

const TargetRegisterClass *	getCrossCopyRegClass (const TargetRegisterClass *RC) const override

const TargetRegisterClass *	getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override

unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override

bool	getRegAllocationHints (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap VRM, const LiveRegMatrix Matrix) const override

void	updateRegAllocHint (Register Reg, Register NewReg, MachineFunction &MF) const override

bool	hasBasePointer (const MachineFunction &MF) const

bool	canRealignStack (const MachineFunction &MF) const override

int64_t	getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override

bool	needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
	needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Register	materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
	materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic block.

void	resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override

bool	isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override

bool	cannotEliminateFrame (const MachineFunction &MF) const

Register	getFrameRegister (const MachineFunction &MF) const override

Register	getBaseRegister () const

virtual void	emitLoadConstPool (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
	emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.

bool	requiresRegisterScavenging (const MachineFunction &MF) const override
	Code Generation virtual methods...

bool	requiresFrameIndexScavenging (const MachineFunction &MF) const override

bool	requiresVirtualBaseRegisters (const MachineFunction &MF) const override

bool	eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

bool	shouldCoalesce (MachineInstr MI, const TargetRegisterClass SrcRC, unsigned SubReg, const TargetRegisterClass DstRC, unsigned DstSubReg, const TargetRegisterClass NewRC, LiveIntervals &LIS) const override
	SrcRC and DstRC will be morphed into NewRC if this returns true.

bool	shouldRewriteCopySrc (const TargetRegisterClass DefRC, unsigned DefSubReg, const TargetRegisterClass SrcRC, unsigned SrcSubReg) const override

int	getSEHRegNum (unsigned i) const

Protected Member Functions
	ARMBaseRegisterInfo ()

Protected Attributes
unsigned	BasePtr = ARM::R6
	BasePtr - ARM physical register used as a base ptr in complex stack frames.

Detailed Description

Definition at line 127 of file ARMBaseRegisterInfo.h.

Constructor & Destructor Documentation

◆ ARMBaseRegisterInfo()

ARMBaseRegisterInfo::ARMBaseRegisterInfo ( )

explicitprotected

Definition at line 57 of file ARMBaseRegisterInfo.cpp.

References llvm::ARM_MC::initLLVMToCVRegMapping().

Member Function Documentation

◆ cannotEliminateFrame()

bool ARMBaseRegisterInfo::cannotEliminateFrame ( const MachineFunction & MF ) const

Definition at line 475 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFrameInfo::adjustsStack(), llvm::TargetOptions::DisableFramePointerElim(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getTarget(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::MachineFrameInfo::isFrameAddressTaken(), and llvm::TargetMachine::Options.

Referenced by llvm::ARMFrameLowering::determineCalleeSaves().

◆ canRealignStack()

bool ARMBaseRegisterInfo::canRealignStack ( const MachineFunction & MF ) const

override

Definition at line 453 of file ARMBaseRegisterInfo.cpp.

References BasePtr, llvm::TargetRegisterInfo::canRealignStack(), llvm::ARMSubtarget::getFramePointerReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMFrameLowering::hasReservedCallFrame(), and MRI.

Referenced by checkNumAlignedDPRCS2Regs(), and needsFrameBaseReg().

◆ eliminateFrameIndex()

bool ARMBaseRegisterInfo::eliminateFrameIndex	(	MachineBasicBlock::iterator	II,
		int	SPAdj,
		unsigned	FIOperandNum,
		RegScavenger *	RS = `nullptr`
	)		const

override

Definition at line 790 of file ARMBaseRegisterInfo.cpp.

References llvm::ARMII::AddrMode4, llvm::ARMII::AddrMode6, llvm::ARMII::AddrModeMask, llvm::ARMII::AddrModeT2_i7, llvm::ARMII::AddrModeT2_i7s2, llvm::ARMII::AddrModeT2_i7s4, llvm::ARMCC::AL, assert(), llvm::TargetRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Done, llvm::emitARMRegPlusImmediate(), llvm::emitT2RegPlusImmediate(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMFrameLowering::hasReservedCallFrame(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::RegScavenger::isScavengingFrameIndex(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::Register::isVirtual(), MBB, MI, llvm::Offset, llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), and TII.

Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex().

◆ emitLoadConstPool()

void ARMBaseRegisterInfo::emitLoadConstPool	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator &	MBBI,
		const DebugLoc &	dl,
		Register	DestReg,
		unsigned	SubIdx,
		int	Val,
		ARMCC::CondCodes	Pred = `ARMCC::AL`,
		Register	PredReg = `Register()`,
		unsigned	MIFlags = `MachineInstr::NoFlags`
	)		const

virtual

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.

Reimplemented in llvm::ThumbRegisterInfo.

Definition at line 496 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::CallingConv::C, llvm::ConstantInt::get(), llvm::MachineFunction::getConstantPool(), llvm::Function::getContext(), llvm::getDefRegState(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::Type::getInt32Ty(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), Idx, MBB, MBBI, llvm::predOps(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks().

◆ getBaseRegister()

Register llvm::ARMBaseRegisterInfo::getBaseRegister ( ) const

inline

Definition at line 206 of file ARMBaseRegisterInfo.h.

References BasePtr.

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), and llvm::ARMFrameLowering::ResolveFrameIndexReference().

◆ getCalleeSavedRegs()

const MCPhysReg * ARMBaseRegisterInfo::getCalleeSavedRegs ( const MachineFunction * MF ) const

override

Code Generation virtual methods...

Definition at line 63 of file ARMBaseRegisterInfo.cpp.

References llvm::CallingConv::CFGuard_Check, llvm::CallingConv::CXX_FAST_TLS, F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::getTargetLowering(), llvm::CallingConv::GHC, llvm::ARMSubtarget::isMClass(), llvm::ARMFunctionInfo::isSplitCSR(), llvm::ARMSubtarget::isTargetDarwin(), llvm::ARMSubtarget::splitFramePointerPush(), llvm::ARMSubtarget::splitFramePushPop(), llvm::ARMTargetLowering::supportSwiftError(), and llvm::CallingConv::SwiftTail.

Referenced by llvm::ARMFrameLowering::determineCalleeSaves().

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction * MF ) const

Definition at line 121 of file ARMBaseRegisterInfo.cpp.

References assert(), llvm::CallingConv::CXX_FAST_TLS, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), and llvm::ARMFunctionInfo::isSplitCSR().

◆ getCallPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getCallPreservedMask	(	const MachineFunction &	MF,
		CallingConv::ID	CC
	)		const

override

Definition at line 131 of file ARMBaseRegisterInfo.cpp.

References CC, llvm::CallingConv::CFGuard_Check, llvm::CallingConv::CXX_FAST_TLS, llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::getTargetLowering(), llvm::CallingConv::GHC, llvm::AttributeList::hasAttrSomewhere(), llvm::ARMSubtarget::isTargetDarwin(), llvm::ARMTargetLowering::supportSwiftError(), and llvm::CallingConv::SwiftTail.

◆ getCrossCopyRegClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass * RC ) const

override

Definition at line 292 of file ARMBaseRegisterInfo.cpp.

◆ getFrameIndexInstrOffset()

int64_t ARMBaseRegisterInfo::getFrameIndexInstrOffset	(	const MachineInstr *	MI,
		int	Idx
	)		const

override

◆ getFrameRegister()

Register ARMBaseRegisterInfo::getFrameRegister ( const MachineFunction & MF ) const

override

Definition at line 485 of file ARMBaseRegisterInfo.cpp.

References llvm::ARMSubtarget::getFramePointerReg(), and llvm::MachineFunction::getSubtarget().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), needsFrameBaseReg(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), and llvm::Thumb1FrameLowering::spillCalleeSavedRegisters().

◆ getIntraCallClobberedRegs()

ArrayRef< MCPhysReg > ARMBaseRegisterInfo::getIntraCallClobberedRegs ( const MachineFunction * MF ) const

override

Definition at line 193 of file ARMBaseRegisterInfo.cpp.

◆ getLargestLegalSuperClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getLargestLegalSuperClass	(	const TargetRegisterClass *	RC,
		const MachineFunction &	MF
	)		const

override

Definition at line 256 of file ARMBaseRegisterInfo.cpp.

References llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getSubtarget(), llvm::TargetRegisterClass::getSuperClasses(), and I.

Referenced by llvm::ThumbRegisterInfo::getLargestLegalSuperClass().

◆ getNoPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getNoPreservedMask ( ) const

override

Definition at line 154 of file ARMBaseRegisterInfo.cpp.

◆ getPointerRegClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getPointerRegClass	(	const MachineFunction &	MF,
		unsigned	Kind = `0`
	)		const

override

Definition at line 286 of file ARMBaseRegisterInfo.cpp.

Referenced by llvm::ThumbRegisterInfo::getPointerRegClass().

◆ getRegAllocationHints()

bool ARMBaseRegisterInfo::getRegAllocationHints	(	Register	VirtReg,
		ArrayRef< MCPhysReg >	Order,
		SmallVectorImpl< MCPhysReg > &	Hints,
		const MachineFunction &	MF,
		const VirtRegMap *	VRM,
		const LiveRegMatrix *	Matrix
	)		const

override

Definition at line 336 of file ARMBaseRegisterInfo.cpp.

References getPairedGPR(), llvm::VirtRegMap::getPhys(), llvm::TargetRegisterInfo::getRegAllocationHints(), llvm::MachineFunction::getRegInfo(), llvm::VirtRegMap::hasPhys(), llvm::is_contained(), llvm::Register::isPhysical(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ARMRI::RegLR, llvm::ARMRI::RegPairEven, and llvm::ARMRI::RegPairOdd.

◆ getRegPressureLimit()

unsigned ARMBaseRegisterInfo::getRegPressureLimit	(	const TargetRegisterClass *	RC,
		MachineFunction &	MF
	)		const

override

Definition at line 299 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getSubtarget(), llvm::MachineFrameInfo::isMaxCallFrameSizeComputed(), and llvm::ARMSubtarget::isR9Reserved().

◆ getReservedRegs()

BitVector ARMBaseRegisterInfo::getReservedRegs ( const MachineFunction & MF ) const

override

Definition at line 199 of file ARMBaseRegisterInfo.cpp.

References assert(), BasePtr, llvm::ARM::D16, llvm::ARMSubtarget::getFramePointerReg(), llvm::MachineFunction::getSubtarget(), hasBasePointer(), llvm::ARMSubtarget::isR9Reserved(), and llvm::Reserved.

Referenced by isAsmClobberable().

◆ getSEHRegNum()

int llvm::ARMBaseRegisterInfo::getSEHRegNum ( unsigned i ) const

inline

Definition at line 242 of file ARMBaseRegisterInfo.h.

◆ getSjLjDispatchPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getSjLjDispatchPreservedMask ( const MachineFunction & MF ) const

Definition at line 166 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::hasVFP2Base(), and llvm::ARMSubtarget::isThumb1Only().

◆ getThisReturnPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getThisReturnPreservedMask	(	const MachineFunction &	MF,
		CallingConv::ID	CC
	)		const

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e.

it is a calling convention that uses the same register for the first i32 argument and an i32 return value)

Should return NULL in the case that the calling convention does not have this property

Definition at line 175 of file ARMBaseRegisterInfo.cpp.

References CC, llvm::MachineFunction::getSubtarget(), llvm::CallingConv::GHC, and llvm::ARMSubtarget::isTargetDarwin().

◆ getTLSCallPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getTLSCallPreservedMask ( const MachineFunction & MF ) const

Definition at line 159 of file ARMBaseRegisterInfo.cpp.

References assert(), llvm::MachineFunction::getSubtarget(), and llvm::ARMSubtarget::isTargetDarwin().

◆ hasBasePointer()

bool ARMBaseRegisterInfo::hasBasePointer ( const MachineFunction & MF ) const

Definition at line 416 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getLocalFrameSize(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), and llvm::ARMFunctionInfo::isThumb2Function().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), getReservedRegs(), isInlineAsmReadOnlyReg(), and llvm::ARMFrameLowering::ResolveFrameIndexReference().

◆ isAsmClobberable()

bool ARMBaseRegisterInfo::isAsmClobberable	(	const MachineFunction &	MF,
		MCRegister	PhysReg
	)		const

override

Definition at line 235 of file ARMBaseRegisterInfo.cpp.

References getReservedRegs(), and llvm::BitVector::test().

◆ isFrameOffsetLegal()

bool ARMBaseRegisterInfo::isFrameOffsetLegal	(	const MachineInstr *	MI,
		Register	BaseReg,
		int64_t	Offset
	)		const

override

◆ isInlineAsmReadOnlyReg()

bool ARMBaseRegisterInfo::isInlineAsmReadOnlyReg	(	const MachineFunction &	MF,
		unsigned	PhysReg
	)		const

override

Definition at line 240 of file ARMBaseRegisterInfo.cpp.

References assert(), BasePtr, llvm::ARMSubtarget::getFramePointerReg(), llvm::MachineFunction::getSubtarget(), hasBasePointer(), and llvm::Reserved.

◆ materializeFrameBaseRegister()

Register ARMBaseRegisterInfo::materializeFrameBaseRegister	(	MachineBasicBlock *	MBB,
		int	FrameIdx,
		int64_t	Offset
	)		const

override

materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic block.

Definition at line 665 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::condCodeOp(), DL, llvm::MachineBasicBlock::end(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, MRI, llvm::Offset, llvm::predOps(), and TII.

◆ needsFrameBaseReg()

bool ARMBaseRegisterInfo::needsFrameBaseReg	(	MachineInstr *	MI,
		int64_t	Offset
	)		const

override

needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.

Definition at line 583 of file ARMBaseRegisterInfo.cpp.

References assert(), canRealignStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getLocalFrameMaxAlign(), llvm::MachineFrameInfo::getLocalFrameSize(), llvm::TargetFrameLowering::getStackAlign(), llvm::ARMFrameLowering::hasFP(), llvm::MachineFrameInfo::hasVarSizedObjects(), isFrameOffsetLegal(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), MI, and llvm::Offset.

◆ requiresFrameIndexScavenging()

bool ARMBaseRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction & MF ) const

override

Definition at line 520 of file ARMBaseRegisterInfo.cpp.

◆ requiresRegisterScavenging()

bool ARMBaseRegisterInfo::requiresRegisterScavenging ( const MachineFunction & MF ) const

override

Code Generation virtual methods...

Definition at line 515 of file ARMBaseRegisterInfo.cpp.

◆ requiresVirtualBaseRegisters()

bool ARMBaseRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction & MF ) const

override

Definition at line 525 of file ARMBaseRegisterInfo.cpp.

◆ resolveFrameIndex()

void ARMBaseRegisterInfo::resolveFrameIndex	(	MachineInstr &	MI,
		Register	BaseReg,
		int64_t	Offset
	)		const

override

Definition at line 693 of file ARMBaseRegisterInfo.cpp.

References assert(), llvm::Done, llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, MI, llvm::Offset, llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), and TII.

Referenced by llvm::ThumbRegisterInfo::resolveFrameIndex().

◆ shouldCoalesce()

bool ARMBaseRegisterInfo::shouldCoalesce	(	MachineInstr *	MI,
		const TargetRegisterClass *	SrcRC,
		unsigned	SubReg,
		const TargetRegisterClass *	DstRC,
		unsigned	DstSubReg,
		const TargetRegisterClass *	NewRC,
		LiveIntervals &	LIS
	)		const

override

SrcRC and DstRC will be morphed into NewRC if this returns true.

Definition at line 877 of file ARMBaseRegisterInfo.cpp.

References llvm::dbgs(), llvm::ARMFunctionInfo::getCoalescedWeight(), llvm::MachineBasicBlock::getParent(), LLVM_DEBUG, MBB, MI, MRI, and llvm::MachineBasicBlock::size().

◆ shouldRewriteCopySrc()

bool ARMBaseRegisterInfo::shouldRewriteCopySrc	(	const TargetRegisterClass *	DefRC,
		unsigned	DefSubReg,
		const TargetRegisterClass *	SrcRC,
		unsigned	SrcSubReg
	)		const

override

Definition at line 936 of file ARMBaseRegisterInfo.cpp.

References llvm::TargetRegisterInfo::shouldRewriteCopySrc().

◆ updateRegAllocHint()

void ARMBaseRegisterInfo::updateRegAllocHint	(	Register	Reg,
		Register	NewReg,
		MachineFunction &	MF
	)		const

override

Definition at line 391 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getRegInfo(), llvm::Register::isVirtual(), MRI, llvm::ARMRI::RegPairEven, and llvm::ARMRI::RegPairOdd.

Member Data Documentation

◆ BasePtr

unsigned llvm::ARMBaseRegisterInfo::BasePtr = ARM::R6

protected

BasePtr - ARM physical register used as a base ptr in complex stack frames.

I.e., when we need a 3rd base, not just SP and FP, due to variable size stack objects.

Definition at line 132 of file ARMBaseRegisterInfo.h.

Referenced by canRealignStack(), getBaseRegister(), getReservedRegs(), and isInlineAsmReadOnlyReg().

The documentation for this class was generated from the following files:

lib/Target/ARM/ARMBaseRegisterInfo.h
lib/Target/ARM/ARMBaseRegisterInfo.cpp

Public Member Functions

Protected Member Functions

Protected Attributes

Detailed Description

Constructor & Destructor Documentation

◆ ARMBaseRegisterInfo()

Member Function Documentation

◆ cannotEliminateFrame()

◆ canRealignStack()

◆ eliminateFrameIndex()

◆ emitLoadConstPool()

◆ getBaseRegister()

◆ getCalleeSavedRegs()

◆ getCalleeSavedRegsViaCopy()

◆ getCallPreservedMask()

◆ getCrossCopyRegClass()

◆ getFrameIndexInstrOffset()

◆ getFrameRegister()

◆ getIntraCallClobberedRegs()

◆ getLargestLegalSuperClass()

◆ getNoPreservedMask()

◆ getPointerRegClass()

◆ getRegAllocationHints()

◆ getRegPressureLimit()

◆ getReservedRegs()

◆ getSEHRegNum()

◆ getSjLjDispatchPreservedMask()

◆ getThisReturnPreservedMask()

◆ getTLSCallPreservedMask()

◆ hasBasePointer()

◆ isAsmClobberable()

◆ isFrameOffsetLegal()

◆ isInlineAsmReadOnlyReg()

◆ materializeFrameBaseRegister()

◆ needsFrameBaseReg()

◆ requiresFrameIndexScavenging()

◆ requiresRegisterScavenging()

◆ requiresVirtualBaseRegisters()

◆ resolveFrameIndex()

◆ shouldCoalesce()

◆ shouldRewriteCopySrc()

◆ updateRegAllocHint()

Member Data Documentation

◆ BasePtr