LLVM  14.0.0git
ARMBaseRegisterInfo.cpp
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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the base ARM implementation of TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARM.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMFrameLowering.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Support/Debug.h"
47 #include <cassert>
48 #include <utility>
49 
50 #define DEBUG_TYPE "arm-register-info"
51 
52 #define GET_REGINFO_TARGET_DESC
53 #include "ARMGenRegisterInfo.inc"
54 
55 using namespace llvm;
56 
58  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {
60 }
61 
62 const MCPhysReg*
64  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
65  bool UseSplitPush = STI.splitFramePushPop(*MF);
66  const MCPhysReg *RegList =
67  STI.isTargetDarwin()
68  ? CSR_iOS_SaveList
69  : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
70 
71  const Function &F = MF->getFunction();
72  if (F.getCallingConv() == CallingConv::GHC) {
73  // GHC set of callee saved regs is empty as all those regs are
74  // used for passing STG regs around
75  return CSR_NoRegs_SaveList;
76  } else if (F.getCallingConv() == CallingConv::CFGuard_Check) {
77  return CSR_Win_AAPCS_CFGuard_Check_SaveList;
78  } else if (F.getCallingConv() == CallingConv::SwiftTail) {
79  return STI.isTargetDarwin()
80  ? CSR_iOS_SwiftTail_SaveList
81  : (UseSplitPush ? CSR_AAPCS_SplitPush_SwiftTail_SaveList
82  : CSR_AAPCS_SwiftTail_SaveList);
83  } else if (F.hasFnAttribute("interrupt")) {
84  if (STI.isMClass()) {
85  // M-class CPUs have hardware which saves the registers needed to allow a
86  // function conforming to the AAPCS to function as a handler.
87  return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
88  } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
89  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
90  // need to be saved to restore user-mode state.
91  return CSR_FIQ_SaveList;
92  } else {
93  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
94  // exception handling.
95  return CSR_GenericInt_SaveList;
96  }
97  }
98 
99  if (STI.getTargetLowering()->supportSwiftError() &&
100  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
101  if (STI.isTargetDarwin())
102  return CSR_iOS_SwiftError_SaveList;
103 
104  return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
105  CSR_AAPCS_SwiftError_SaveList;
106  }
107 
108  if (STI.isTargetDarwin() && F.getCallingConv() == CallingConv::CXX_FAST_TLS)
109  return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
110  ? CSR_iOS_CXX_TLS_PE_SaveList
111  : CSR_iOS_CXX_TLS_SaveList;
112  return RegList;
113 }
114 
116  const MachineFunction *MF) const {
117  assert(MF && "Invalid MachineFunction pointer.");
120  return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
121  return nullptr;
122 }
123 
124 const uint32_t *
126  CallingConv::ID CC) const {
127  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
128  if (CC == CallingConv::GHC)
129  // This is academic because all GHC calls are (supposed to be) tail calls
130  return CSR_NoRegs_RegMask;
131  if (CC == CallingConv::CFGuard_Check)
132  return CSR_Win_AAPCS_CFGuard_Check_RegMask;
133  if (CC == CallingConv::SwiftTail) {
134  return STI.isTargetDarwin() ? CSR_iOS_SwiftTail_RegMask
135  : CSR_AAPCS_SwiftTail_RegMask;
136  }
137  if (STI.getTargetLowering()->supportSwiftError() &&
138  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
139  return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
140  : CSR_AAPCS_SwiftError_RegMask;
141 
142  if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
143  return CSR_iOS_CXX_TLS_RegMask;
144  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
145 }
146 
147 const uint32_t*
149  return CSR_NoRegs_RegMask;
150 }
151 
152 const uint32_t *
155  "only know about special TLS call on Darwin");
156  return CSR_iOS_TLSCall_RegMask;
157 }
158 
159 const uint32_t *
161  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
162  if (!STI.useSoftFloat() && STI.hasVFP2Base() && !STI.isThumb1Only())
163  return CSR_NoRegs_RegMask;
164  else
165  return CSR_FPRegs_RegMask;
166 }
167 
168 const uint32_t *
170  CallingConv::ID CC) const {
171  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
172  // This should return a register mask that is the same as that returned by
173  // getCallPreservedMask but that additionally preserves the register used for
174  // the first i32 argument (which must also be the register used to return a
175  // single i32 return value)
176  //
177  // In case that the calling convention does not use the same register for
178  // both or otherwise does not want to enable this optimization, the function
179  // should return NULL
180  if (CC == CallingConv::GHC)
181  // This is academic because all GHC calls are (supposed to be) tail calls
182  return nullptr;
183  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
184  : CSR_AAPCS_ThisReturn_RegMask;
185 }
186 
188  const MachineFunction *MF) const {
189  static const MCPhysReg IntraCallClobberedRegs[] = {ARM::R12};
190  return ArrayRef<MCPhysReg>(IntraCallClobberedRegs);
191 }
192 
195  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
196  const ARMFrameLowering *TFI = getFrameLowering(MF);
197 
198  // FIXME: avoid re-calculating this every time.
199  BitVector Reserved(getNumRegs());
200  markSuperRegs(Reserved, ARM::SP);
201  markSuperRegs(Reserved, ARM::PC);
202  markSuperRegs(Reserved, ARM::FPSCR);
203  markSuperRegs(Reserved, ARM::APSR_NZCV);
204  if (TFI->hasFP(MF))
205  markSuperRegs(Reserved, STI.getFramePointerReg());
206  if (hasBasePointer(MF))
207  markSuperRegs(Reserved, BasePtr);
208  // Some targets reserve R9.
209  if (STI.isR9Reserved())
210  markSuperRegs(Reserved, ARM::R9);
211  // Reserve D16-D31 if the subtarget doesn't support them.
212  if (!STI.hasD32()) {
213  static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
214  for (unsigned R = 0; R < 16; ++R)
215  markSuperRegs(Reserved, ARM::D16 + R);
216  }
217  const TargetRegisterClass &RC = ARM::GPRPairRegClass;
218  for (unsigned Reg : RC)
219  for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
220  if (Reserved.test(*SI))
221  markSuperRegs(Reserved, Reg);
222  // For v8.1m architecture
223  markSuperRegs(Reserved, ARM::ZR);
224 
225  assert(checkAllSuperRegsMarked(Reserved));
226  return Reserved;
227 }
228 
230 isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const {
231  return !getReservedRegs(MF).test(PhysReg);
232 }
233 
235  unsigned PhysReg) const {
236  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
237  const ARMFrameLowering *TFI = getFrameLowering(MF);
238 
239  BitVector Reserved(getNumRegs());
240  markSuperRegs(Reserved, ARM::PC);
241  if (TFI->hasFP(MF))
242  markSuperRegs(Reserved, STI.getFramePointerReg());
243  if (hasBasePointer(MF))
244  markSuperRegs(Reserved, BasePtr);
245  assert(checkAllSuperRegsMarked(Reserved));
246  return Reserved.test(PhysReg);
247 }
248 
249 const TargetRegisterClass *
251  const MachineFunction &MF) const {
252  const TargetRegisterClass *Super = RC;
254  do {
255  switch (Super->getID()) {
256  case ARM::GPRRegClassID:
257  case ARM::SPRRegClassID:
258  case ARM::DPRRegClassID:
259  case ARM::GPRPairRegClassID:
260  return Super;
261  case ARM::QPRRegClassID:
262  case ARM::QQPRRegClassID:
263  case ARM::QQQQPRRegClassID:
264  if (MF.getSubtarget<ARMSubtarget>().hasNEON())
265  return Super;
266  }
267  Super = *I++;
268  } while (Super);
269  return RC;
270 }
271 
272 const TargetRegisterClass *
274  const {
275  return &ARM::GPRRegClass;
276 }
277 
278 const TargetRegisterClass *
280  if (RC == &ARM::CCRRegClass)
281  return &ARM::rGPRRegClass; // Can't copy CCR registers.
282  return RC;
283 }
284 
285 unsigned
287  MachineFunction &MF) const {
288  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
289  const ARMFrameLowering *TFI = getFrameLowering(MF);
290 
291  switch (RC->getID()) {
292  default:
293  return 0;
294  case ARM::tGPRRegClassID: {
295  // hasFP ends up calling getMaxCallFrameComputed() which may not be
296  // available when getPressureLimit() is called as part of
297  // ScheduleDAGRRList.
298  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
299  ? TFI->hasFP(MF) : true;
300  return 5 - HasFP;
301  }
302  case ARM::GPRRegClassID: {
303  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
304  ? TFI->hasFP(MF) : true;
305  return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
306  }
307  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
308  case ARM::DPRRegClassID:
309  return 32 - 10;
310  }
311 }
312 
313 // Get the other register in a GPRPair.
315  const MCRegisterInfo *RI) {
316  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
317  if (ARM::GPRPairRegClass.contains(*Supers))
318  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
319  return 0;
320 }
321 
322 // Resolve the RegPairEven / RegPairOdd register allocator hints.
324  Register VirtReg, ArrayRef<MCPhysReg> Order,
326  const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
327  const MachineRegisterInfo &MRI = MF.getRegInfo();
328  std::pair<Register, Register> Hint = MRI.getRegAllocationHint(VirtReg);
329 
330  unsigned Odd;
331  switch (Hint.first) {
332  case ARMRI::RegPairEven:
333  Odd = 0;
334  break;
335  case ARMRI::RegPairOdd:
336  Odd = 1;
337  break;
338  case ARMRI::RegLR:
339  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
340  if (MRI.getRegClass(VirtReg)->contains(ARM::LR))
341  Hints.push_back(ARM::LR);
342  return false;
343  default:
344  return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
345  }
346 
347  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
348  // Check if the other part of the pair has already been assigned, and provide
349  // the paired register as the first hint.
350  Register Paired = Hint.second;
351  if (!Paired)
352  return false;
353 
354  Register PairedPhys;
355  if (Paired.isPhysical()) {
356  PairedPhys = Paired;
357  } else if (VRM && VRM->hasPhys(Paired)) {
358  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
359  }
360 
361  // First prefer the paired physreg.
362  if (PairedPhys && is_contained(Order, PairedPhys))
363  Hints.push_back(PairedPhys);
364 
365  // Then prefer even or odd registers.
366  for (MCPhysReg Reg : Order) {
367  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
368  continue;
369  // Don't provide hints that are paired to a reserved register.
370  MCPhysReg Paired = getPairedGPR(Reg, !Odd, this);
371  if (!Paired || MRI.isReserved(Paired))
372  continue;
373  Hints.push_back(Reg);
374  }
375  return false;
376 }
377 
379  MachineFunction &MF) const {
381  std::pair<Register, Register> Hint = MRI->getRegAllocationHint(Reg);
382  if ((Hint.first == ARMRI::RegPairOdd || Hint.first == ARMRI::RegPairEven) &&
383  Hint.second.isVirtual()) {
384  // If 'Reg' is one of the even / odd register pair and it's now changed
385  // (e.g. coalesced) into a different register. The other register of the
386  // pair allocation hint must be updated to reflect the relationship
387  // change.
388  Register OtherReg = Hint.second;
389  Hint = MRI->getRegAllocationHint(OtherReg);
390  // Make sure the pair has not already divorced.
391  if (Hint.second == Reg) {
392  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
393  if (Register::isVirtualRegister(NewReg))
394  MRI->setRegAllocationHint(NewReg,
395  Hint.first == ARMRI::RegPairOdd
398  OtherReg);
399  }
400  }
401 }
402 
404  const MachineFrameInfo &MFI = MF.getFrameInfo();
405  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
406  const ARMFrameLowering *TFI = getFrameLowering(MF);
407 
408  // If we have stack realignment and VLAs, we have no pointer to use to
409  // access the stack. If we have stack realignment, and a large call frame,
410  // we have no place to allocate the emergency spill slot.
411  if (hasStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
412  return true;
413 
414  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
415  // negative range for ldr/str (255), and Thumb1 is positive offsets only.
416  //
417  // It's going to be better to use the SP or Base Pointer instead. When there
418  // are variable sized objects, we can't reference off of the SP, so we
419  // reserve a Base Pointer.
420  //
421  // For Thumb2, estimate whether a negative offset from the frame pointer
422  // will be sufficient to reach the whole stack frame. If a function has a
423  // smallish frame, it's less likely to have lots of spills and callee saved
424  // space, so it's all more likely to be within range of the frame pointer.
425  // If it's wrong, the scavenger will still enable access to work, it just
426  // won't be optimal. (We should always be able to reach the emergency
427  // spill slot from the frame pointer.)
428  if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() &&
429  MFI.getLocalFrameSize() >= 128)
430  return true;
431  // For Thumb1, if sp moves, nothing is in range, so force a base pointer.
432  // This is necessary for correctness in cases where we need an emergency
433  // spill slot. (In Thumb1, we can't use a negative offset from the frame
434  // pointer.)
435  if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF))
436  return true;
437  return false;
438 }
439 
441  const MachineRegisterInfo *MRI = &MF.getRegInfo();
442  const ARMFrameLowering *TFI = getFrameLowering(MF);
443  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
444  // We can't realign the stack if:
445  // 1. Dynamic stack realignment is explicitly disabled,
446  // 2. There are VLAs in the function and the base pointer is disabled.
448  return false;
449  // Stack realignment requires a frame pointer. If we already started
450  // register allocation with frame pointer elimination, it is too late now.
451  if (!MRI->canReserveReg(STI.getFramePointerReg()))
452  return false;
453  // We may also need a base pointer if there are dynamic allocas or stack
454  // pointer adjustments around calls.
455  if (TFI->hasReservedCallFrame(MF))
456  return true;
457  // A base pointer is required and allowed. Check that it isn't too late to
458  // reserve it.
459  return MRI->canReserveReg(BasePtr);
460 }
461 
464  const MachineFrameInfo &MFI = MF.getFrameInfo();
466  return true;
467  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
468  hasStackRealignment(MF);
469 }
470 
471 Register
473  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
474  const ARMFrameLowering *TFI = getFrameLowering(MF);
475 
476  if (TFI->hasFP(MF))
477  return STI.getFramePointerReg();
478  return ARM::SP;
479 }
480 
481 /// emitLoadConstPool - Emits a load from constpool to materialize the
482 /// specified immediate.
485  const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val,
486  ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
487  MachineFunction &MF = *MBB.getParent();
488  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
490  const Constant *C =
492  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));
493 
494  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
495  .addReg(DestReg, getDefRegState(true), SubIdx)
497  .addImm(0)
498  .add(predOps(Pred, PredReg))
499  .setMIFlags(MIFlags);
500 }
501 
504  return true;
505 }
506 
509  return true;
510 }
511 
514  return true;
515 }
516 
517 int64_t ARMBaseRegisterInfo::
518 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
519  const MCInstrDesc &Desc = MI->getDesc();
520  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
521  int64_t InstrOffs = 0;
522  int Scale = 1;
523  unsigned ImmIdx = 0;
524  switch (AddrMode) {
527  case ARMII::AddrMode_i12:
528  InstrOffs = MI->getOperand(Idx+1).getImm();
529  Scale = 1;
530  break;
531  case ARMII::AddrMode5: {
532  // VFP address mode.
533  const MachineOperand &OffOp = MI->getOperand(Idx+1);
534  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
535  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
536  InstrOffs = -InstrOffs;
537  Scale = 4;
538  break;
539  }
540  case ARMII::AddrMode2:
541  ImmIdx = Idx+2;
542  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
543  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
544  InstrOffs = -InstrOffs;
545  break;
546  case ARMII::AddrMode3:
547  ImmIdx = Idx+2;
548  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
549  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
550  InstrOffs = -InstrOffs;
551  break;
552  case ARMII::AddrModeT1_s:
553  ImmIdx = Idx+1;
554  InstrOffs = MI->getOperand(ImmIdx).getImm();
555  Scale = 4;
556  break;
557  default:
558  llvm_unreachable("Unsupported addressing mode!");
559  }
560 
561  return InstrOffs * Scale;
562 }
563 
564 /// needsFrameBaseReg - Returns true if the instruction's frame index
565 /// reference would be better served by a base register other than FP
566 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
567 /// references it should create new base registers for.
570  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
571  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
572  }
573 
574  // It's the load/store FI references that cause issues, as it can be difficult
575  // to materialize the offset if it won't fit in the literal field. Estimate
576  // based on the size of the local frame and some conservative assumptions
577  // about the rest of the stack frame (note, this is pre-regalloc, so
578  // we don't know everything for certain yet) whether this offset is likely
579  // to be out of range of the immediate. Return true if so.
580 
581  // We only generate virtual base registers for loads and stores, so
582  // return false for everything else.
583  unsigned Opc = MI->getOpcode();
584  switch (Opc) {
585  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
586  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
587  case ARM::t2LDRi12: case ARM::t2LDRi8:
588  case ARM::t2STRi12: case ARM::t2STRi8:
589  case ARM::VLDRS: case ARM::VLDRD:
590  case ARM::VSTRS: case ARM::VSTRD:
591  case ARM::tSTRspi: case ARM::tLDRspi:
592  break;
593  default:
594  return false;
595  }
596 
597  // Without a virtual base register, if the function has variable sized
598  // objects, all fixed-size local references will be via the frame pointer,
599  // Approximate the offset and see if it's legal for the instruction.
600  // Note that the incoming offset is based on the SP value at function entry,
601  // so it'll be negative.
602  MachineFunction &MF = *MI->getParent()->getParent();
603  const ARMFrameLowering *TFI = getFrameLowering(MF);
604  MachineFrameInfo &MFI = MF.getFrameInfo();
606 
607  // Estimate an offset from the frame pointer.
608  // Conservatively assume all callee-saved registers get pushed. R4-R6
609  // will be earlier than the FP, so we ignore those.
610  // R7, LR
611  int64_t FPOffset = Offset - 8;
612  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
613  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
614  FPOffset -= 80;
615  // Estimate an offset from the stack pointer.
616  // The incoming offset is relating to the SP at the start of the function,
617  // but when we access the local it'll be relative to the SP after local
618  // allocation, so adjust our SP-relative offset by that allocation size.
619  Offset += MFI.getLocalFrameSize();
620  // Assume that we'll have at least some spill slots allocated.
621  // FIXME: This is a total SWAG number. We should run some statistics
622  // and pick a real one.
623  Offset += 128; // 128 bytes of spill slots
624 
625  // If there's a frame pointer and the addressing mode allows it, try using it.
626  // The FP is only available if there is no dynamic realignment. We
627  // don't know for sure yet whether we'll need that, so we guess based
628  // on whether there are any local variables that would trigger it.
629  if (TFI->hasFP(MF) &&
630  !((MFI.getLocalFrameMaxAlign() > TFI->getStackAlign()) &&
631  canRealignStack(MF))) {
632  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
633  return false;
634  }
635  // If we can reference via the stack pointer, try that.
636  // FIXME: This (and the code that resolves the references) can be improved
637  // to only disallow SP relative references in the live range of
638  // the VLA(s). In practice, it's unclear how much difference that
639  // would make, but it may be worth doing.
640  if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
641  return false;
642 
643  // The offset likely isn't legal, we want to allocate a virtual base register.
644  return true;
645 }
646 
647 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
648 /// be a pointer to FrameIdx at the beginning of the basic block.
649 Register
651  int FrameIdx,
652  int64_t Offset) const {
654  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
655  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
656 
658  DebugLoc DL; // Defaults to "unknown"
659  if (Ins != MBB->end())
660  DL = Ins->getDebugLoc();
661 
662  const MachineFunction &MF = *MBB->getParent();
664  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
665  const MCInstrDesc &MCID = TII.get(ADDriOpc);
666  Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
667  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
668 
669  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
670  .addFrameIndex(FrameIdx).addImm(Offset);
671 
672  if (!AFI->isThumb1OnlyFunction())
674 
675  return BaseReg;
676 }
677 
679  int64_t Offset) const {
680  MachineBasicBlock &MBB = *MI.getParent();
681  MachineFunction &MF = *MBB.getParent();
682  const ARMBaseInstrInfo &TII =
683  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
685  int Off = Offset; // ARM doesn't need the general 64-bit offsets
686  unsigned i = 0;
687 
688  assert(!AFI->isThumb1OnlyFunction() &&
689  "This resolveFrameIndex does not support Thumb1!");
690 
691  while (!MI.getOperand(i).isFI()) {
692  ++i;
693  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
694  }
695  bool Done = false;
696  if (!AFI->isThumbFunction())
697  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
698  else {
699  assert(AFI->isThumb2Function());
700  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this);
701  }
702  assert(Done && "Unable to resolve frame index!");
703  (void)Done;
704 }
705 
707  Register BaseReg,
708  int64_t Offset) const {
709  const MCInstrDesc &Desc = MI->getDesc();
710  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
711  unsigned i = 0;
712  for (; !MI->getOperand(i).isFI(); ++i)
713  assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
714 
715  // AddrMode4 and AddrMode6 cannot handle any offset.
717  return Offset == 0;
718 
719  unsigned NumBits = 0;
720  unsigned Scale = 1;
721  bool isSigned = true;
722  switch (AddrMode) {
725  // i8 supports only negative, and i12 supports only positive, so
726  // based on Offset sign, consider the appropriate instruction
727  Scale = 1;
728  if (Offset < 0) {
729  NumBits = 8;
730  Offset = -Offset;
731  } else {
732  NumBits = 12;
733  }
734  break;
735  case ARMII::AddrMode5:
736  // VFP address mode.
737  NumBits = 8;
738  Scale = 4;
739  break;
740  case ARMII::AddrMode_i12:
741  case ARMII::AddrMode2:
742  NumBits = 12;
743  break;
744  case ARMII::AddrMode3:
745  NumBits = 8;
746  break;
747  case ARMII::AddrModeT1_s:
748  NumBits = (BaseReg == ARM::SP ? 8 : 5);
749  Scale = 4;
750  isSigned = false;
751  break;
752  default:
753  llvm_unreachable("Unsupported addressing mode!");
754  }
755 
757  // Make sure the offset is encodable for instructions that scale the
758  // immediate.
759  if ((Offset & (Scale-1)) != 0)
760  return false;
761 
762  if (isSigned && Offset < 0)
763  Offset = -Offset;
764 
765  unsigned Mask = (1 << NumBits) - 1;
766  if ((unsigned)Offset <= Mask * Scale)
767  return true;
768 
769  return false;
770 }
771 
772 void
774  int SPAdj, unsigned FIOperandNum,
775  RegScavenger *RS) const {
776  MachineInstr &MI = *II;
777  MachineBasicBlock &MBB = *MI.getParent();
778  MachineFunction &MF = *MBB.getParent();
779  const ARMBaseInstrInfo &TII =
780  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
781  const ARMFrameLowering *TFI = getFrameLowering(MF);
783  assert(!AFI->isThumb1OnlyFunction() &&
784  "This eliminateFrameIndex does not support Thumb1!");
785  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
786  Register FrameReg;
787 
788  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
789 
790  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
791  // call frame setup/destroy instructions have already been eliminated. That
792  // means the stack pointer cannot be used to access the emergency spill slot
793  // when !hasReservedCallFrame().
794 #ifndef NDEBUG
795  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
796  assert(TFI->hasReservedCallFrame(MF) &&
797  "Cannot use SP to access the emergency spill slot in "
798  "functions without a reserved call frame");
800  "Cannot use SP to access the emergency spill slot in "
801  "functions with variable sized frame objects");
802  }
803 #endif // NDEBUG
804 
805  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
806 
807  // Modify MI as necessary to handle as much of 'Offset' as possible
808  bool Done = false;
809  if (!AFI->isThumbFunction())
810  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
811  else {
812  assert(AFI->isThumb2Function());
813  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII, this);
814  }
815  if (Done)
816  return;
817 
818  // If we get here, the immediate doesn't fit into the instruction. We folded
819  // as much as possible above, handle the rest, providing a register that is
820  // SP+LargeImm.
821  assert(
822  (Offset ||
823  (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
824  (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 ||
825  (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 ||
826  (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 ||
827  (MI.getDesc().TSFlags & ARMII::AddrModeMask) ==
829  "This code isn't needed if offset already handled!");
830 
831  unsigned ScratchReg = 0;
832  int PIdx = MI.findFirstPredOperandIdx();
833  ARMCC::CondCodes Pred = (PIdx == -1)
834  ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
835  Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
836 
837  const MCInstrDesc &MCID = MI.getDesc();
838  const TargetRegisterClass *RegClass =
839  TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
840 
841  if (Offset == 0 &&
842  (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
843  // Must be addrmode4/6.
844  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
845  else {
846  ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
847  if (!AFI->isThumbFunction())
848  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
849  Offset, Pred, PredReg, TII);
850  else {
851  assert(AFI->isThumb2Function());
852  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
853  Offset, Pred, PredReg, TII);
854  }
855  // Update the original instruction to use the scratch register.
856  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
857  }
858 }
859 
861  const TargetRegisterClass *SrcRC,
862  unsigned SubReg,
863  const TargetRegisterClass *DstRC,
864  unsigned DstSubReg,
865  const TargetRegisterClass *NewRC,
866  LiveIntervals &LIS) const {
867  auto MBB = MI->getParent();
868  auto MF = MBB->getParent();
869  const MachineRegisterInfo &MRI = MF->getRegInfo();
870  // If not copying into a sub-register this should be ok because we shouldn't
871  // need to split the reg.
872  if (!DstSubReg)
873  return true;
874  // Small registers don't frequently cause a problem, so we can coalesce them.
875  if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
876  getRegSizeInBits(*SrcRC) < 256)
877  return true;
878 
879  auto NewRCWeight =
881  auto SrcRCWeight =
883  auto DstRCWeight =
885  // If the source register class is more expensive than the destination, the
886  // coalescing is probably profitable.
887  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
888  return true;
889  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
890  return true;
891 
892  // If the register allocator isn't constrained, we can always allow coalescing
893  // unfortunately we don't know yet if we will be constrained.
894  // The goal of this heuristic is to restrict how many expensive registers
895  // we allow to coalesce in a given basic block.
896  auto AFI = MF->getInfo<ARMFunctionInfo>();
897  auto It = AFI->getCoalescedWeight(MBB);
898 
899  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
900  << It->second << "\n");
901  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
902  << NewRCWeight.RegWeight << "\n");
903 
904  // This number is the largest round number that which meets the criteria:
905  // (1) addresses PR18825
906  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
907  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
908  // In practice the SizeMultiplier will only factor in for straight line code
909  // that uses a lot of NEON vectors, which isn't terribly common.
910  unsigned SizeMultiplier = MBB->size()/100;
911  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
912  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
913  It->second += NewRCWeight.RegWeight;
914  return true;
915  }
916  return false;
917 }
918 
920  unsigned DefSubReg,
921  const TargetRegisterClass *SrcRC,
922  unsigned SrcSubReg) const {
923  // We can't extract an SPR from an arbitary DPR (as opposed to a DPR_VFP2).
924  if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 &&
925  SrcRC == &ARM::DPRRegClass &&
926  (SrcSubReg == ARM::ssub_0 || SrcSubReg == ARM::ssub_1))
927  return false;
928 
929  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
930  SrcRC, SrcSubReg);
931 }
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::MachineFrameInfo::isMaxCallFrameSizeComputed
bool isMaxCallFrameSizeComputed() const
Definition: MachineFrameInfo.h:627
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:351
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::ARMBaseRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: ARMBaseRegisterInfo.cpp:63
llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
Definition: ARMBaseRegisterInfo.cpp:650
llvm::ARMII::AddrMode4
@ AddrMode4
Definition: ARMBaseInfo.h:190
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::ARMFunctionInfo::isSplitCSR
bool isSplitCSR() const
Definition: ARMMachineFunctionInfo.h:225
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: ARMBaseRegisterInfo.cpp:115
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition: ARMAddressingModes.h:450
llvm::ARMRI::RegLR
@ RegLR
Definition: ARMBaseRegisterInfo.h:39
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::AttributeList::hasAttrSomewhere
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
Definition: Attributes.cpp:1413
llvm::ARMBaseRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: ARMBaseRegisterInfo.cpp:919
MCInstrDesc.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::CallingConv::CFGuard_Check
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:87
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:61
llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
Definition: ARMBaseRegisterInfo.cpp:169
llvm::ARMBaseRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Definition: ARMBaseRegisterInfo.cpp:279
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::emitT2RegPlusImmediate
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Definition: Thumb2InstrInfo.cpp:275
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::ARMFunctionInfo::isThumb1OnlyFunction
bool isThumb1OnlyFunction() const
Definition: ARMMachineFunctionInfo.h:151
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::ARMBaseRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: ARMBaseRegisterInfo.cpp:273
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
ARMMachineFunctionInfo.h
llvm::ARMFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: ARMFrameLowering.cpp:218
llvm::MachineRegisterInfo::canReserveReg
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:897
MachineBasicBlock.h
llvm::ConstantPool
Definition: ConstantPools.h:43
llvm::ARMII::AddrMode3
@ AddrMode3
Definition: ARMBaseInfo.h:189
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition: ARMAddressingModes.h:451
llvm::ARMII::AddrMode2
@ AddrMode2
Definition: ARMBaseInfo.h:188
llvm::ARMBaseRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: ARMBaseRegisterInfo.cpp:706
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:566
TargetInstrInfo.h
llvm::ARM_AM::getAM2Offset
unsigned getAM2Offset(unsigned AM2Opc)
Definition: ARMAddressingModes.h:419
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
getPairedGPR
static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd, const MCRegisterInfo *RI)
Definition: ARMBaseRegisterInfo.cpp:314
STLExtras.h
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:299
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:203
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: ARMBaseRegisterInfo.cpp:518
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::RegScavenger::isScavengingFrameIndex
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
Definition: RegisterScavenging.h:128
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::ARMSubtarget::hasD32
bool hasD32() const
Definition: ARMSubtarget.h:730
llvm::ARMBaseRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
Definition: ARMBaseRegisterInfo.cpp:503
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:833
llvm::ARMII::AddrMode_i12
@ AddrMode_i12
Definition: ARMBaseInfo.h:202
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:91
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:478
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:632
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::ARMSubtarget::useSoftFloat
bool useSoftFloat() const
Definition: ARMSubtarget.h:808
ARMBaseInfo.h
Constants.h
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:720
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMBaseRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:472
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
llvm::ARM_AM::getAM2Op
AddrOpc getAM2Op(unsigned AM2Opc)
Definition: ARMAddressingModes.h:422
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:205
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
ARMGenRegisterInfo
llvm::ARMBaseRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: ARMBaseRegisterInfo.cpp:323
llvm::ARMBaseRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: ARMBaseRegisterInfo.cpp:125
BitVector.h
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:899
llvm::ARMBaseRegisterInfo::cannotEliminateFrame
bool cannotEliminateFrame(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:463
llvm::MachineFrameInfo::getLocalFrameMaxAlign
Align getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
Definition: MachineFrameInfo.h:428
llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:160
DebugLoc.h
llvm::BitVector
Definition: BitVector.h:74
llvm::ARMFunctionInfo::isThumbFunction
bool isThumbFunction() const
Definition: ARMMachineFunctionInfo.h:150
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::ARMBaseRegisterInfo::isInlineAsmReadOnlyReg
bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMBaseRegisterInfo.cpp:234
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:207
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::CallingConv::SwiftTail
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
Definition: CallingConv.h:92
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::ARMRI::RegPairOdd
@ RegPairOdd
Definition: ARMBaseRegisterInfo.h:36
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:249
llvm::VirtRegMap::hasPhys
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:100
llvm::ARMFunctionInfo::getCoalescedWeight
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
Definition: ARMMachineFunctionInfo.h:241
llvm::ARMFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: ARMFrameLowering.cpp:200
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:622
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
ARMBaseRegisterInfo.h
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:811
llvm::MachineFrameInfo::getLocalFrameSize
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Definition: MachineFrameInfo.h:419
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
VirtRegMap.h
llvm::ARMSubtarget::isR9Reserved
bool isR9Reserved() const
Definition: ARMSubtarget.h:819
llvm::ARMSubtarget::isMClass
bool isMClass() const
Definition: ARMSubtarget.h:814
llvm::rewriteT2FrameIndex
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
Definition: Thumb2InstrInfo.cpp:518
llvm::ARMII::AddrModeT1_s
@ AddrModeT1_s
Definition: ARMBaseInfo.h:196
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:549
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:106
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:421
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:823
MachineConstantPool.h
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1612
llvm::ARM_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: ARMMCTargetDesc.cpp:235
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::ARMRI::RegPairEven
@ RegPairEven
Definition: ARMBaseRegisterInfo.h:37
llvm::ARMFrameLowering::ResolveFrameIndexReference
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, int SPAdj) const
Definition: ARMFrameLowering.cpp:1032
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
llvm::ARMBaseRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: ARMBaseRegisterInfo.cpp:148
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:654
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::MachineBasicBlock::size
unsigned size() const
Definition: MachineBasicBlock.h:239
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:638
llvm::ARMBaseRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: ARMBaseRegisterInfo.cpp:678
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
ARMBaseInstrInfo.h
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:206
ARM.h
llvm::ARMBaseRegisterInfo::getTLSCallPreservedMask
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:153
llvm::ARMBaseRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition: ARMBaseRegisterInfo.cpp:860
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMBaseRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: ARMBaseRegisterInfo.cpp:230
TargetOptions.h
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::rewriteARMFrameIndex
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: ARMBaseInstrInfo.cpp:2605
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
ARMAddressingModes.h
llvm::ARMSubtarget::hasNEON
bool hasNEON() const
Definition: ARMSubtarget.h:653
llvm::ARMBaseRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Definition: ARMBaseRegisterInfo.cpp:569
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineRegisterInfo::setRegAllocationHint
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:765
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:250
llvm::ARMBaseRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:194
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:366
llvm::ARMII::AddrMode6
@ AddrMode6
Definition: ARMBaseInfo.h:192
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:412
llvm::ARMBaseRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:508
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
ARMFrameLowering.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:588
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:744
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:618
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:174
MachineFrameInfo.h
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::ARMBaseRegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:440
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::ARMII::AddrModeT2_i8
@ AddrModeT2_i8
Definition: ARMBaseInfo.h:198
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
Function.h
llvm::ARMBaseRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:286
llvm::ARMBaseRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:513
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:50
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::ARMBaseRegisterInfo::BasePtr
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
Definition: ARMBaseRegisterInfo.h:105
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::ARMBaseRegisterInfo::getIntraCallClobberedRegs
ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const override
Definition: ARMBaseRegisterInfo.cpp:187
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::ARMTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: ARMISelLowering.h:695
llvm::emitARMRegPlusImmediate
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
Definition: ARMBaseInstrInfo.cpp:2442
llvm::TargetRegisterInfo::getRegClassWeight
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl< MCPhysReg >
MachineOperand.h
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:403
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:541
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:575
RegisterScavenging.h
raw_ostream.h
MachineFunction.h
llvm::ARMBaseRegisterInfo::updateRegAllocHint
void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:378
llvm::ARMFunctionInfo::isThumb2Function
bool isThumb2Function() const
Definition: ARMMachineFunctionInfo.h:152
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ARMBaseRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: ARMBaseRegisterInfo.cpp:773
TargetRegisterInfo.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::ARMBaseRegisterInfo::emitLoadConstPool
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
Definition: ARMBaseRegisterInfo.cpp:483
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::ARMBaseRegisterInfo::ARMBaseRegisterInfo
ARMBaseRegisterInfo()
Definition: ARMBaseRegisterInfo.cpp:57
llvm::ARMSubtarget::hasVFP2Base
bool hasVFP2Base() const
Definition: ARMSubtarget.h:649
llvm::MachineRegisterInfo::getRegAllocationHint
std::pair< Register, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:795
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40