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43 return (
Value >> 32) & 0xffffffff;
53 return Value & 0xffffffff;
107 {
"fixup_ve_reflong", 0, 32, 0},
109 {
"fixup_ve_hi32", 0, 32, 0},
110 {
"fixup_ve_lo32", 0, 32, 0},
113 {
"fixup_ve_got_hi32", 0, 32, 0},
114 {
"fixup_ve_got_lo32", 0, 32, 0},
115 {
"fixup_ve_gotoff_hi32", 0, 32, 0},
116 {
"fixup_ve_gotoff_lo32", 0, 32, 0},
117 {
"fixup_ve_plt_hi32", 0, 32, 0},
118 {
"fixup_ve_plt_lo32", 0, 32, 0},
119 {
"fixup_ve_tls_gd_hi32", 0, 32, 0},
120 {
"fixup_ve_tls_gd_lo32", 0, 32, 0},
121 {
"fixup_ve_tpoff_hi32", 0, 32, 0},
122 {
"fixup_ve_tpoff_lo32", 0, 32, 0},
146 bool mayNeedRelaxation(
const MCInst &Inst,
164 void relaxInstruction(
MCInst &Inst,
172 if ((Count % 8) != 0)
176 support::endian::write<uint64_t>(OS, 0x7900000000000000ULL,
183 class ELFVEAsmBackend :
public VEAsmBackend {
188 : VEAsmBackend(
T), OSType(OSType) {}
205 assert(Offset + NumBytes <=
Data.size() &&
"Invalid fixup offset!");
209 for (
unsigned i = 0;
i != NumBytes; ++
i) {
215 std::unique_ptr<MCObjectTargetWriter>
216 createObjectTargetWriter()
const override {
@ fixup_ve_reflong
fixup_ve_reflong - 32-bit fixup corresponding to foo
@ fixup_ve_plt_hi32
fixup_ve_plt_hi32/lo32
@ fixup_ve_pc_lo32
fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
@ FK_PCRel_8
A eight-byte pc relative fixup.
std::unique_ptr< MCObjectTargetWriter > createVEELFObjectWriter(uint8_t OSABI)
Target - Wrapper for Target specific information.
@ fixup_ve_pc_hi32
fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo@pc_hi
MCAsmBackend * createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Instances of this class represent a single low-level machine instruction.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_Data_4
A four-byte fixup.
Generic interface to target specific assembler backends.
const Triple & getTargetTriple() const
@ fixup_ve_lo32
fixup_ve_lo32 - 32-bit fixup corresponding to foo@lo
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
Analysis containing CSE Info
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
OSType getOS() const
Get the parsed operating system type of this triple.
@ fixup_ve_tls_gd_hi32
fixups for Thread Local Storage
@ fixup_ve_gotoff_lo32
fixup_ve_gotoff_lo32 - 32-bit fixup corresponding to foo@gotoff_lo
static unsigned getFixupKindNumBytes(unsigned Kind)
getFixupKindNumBytes - The number of bytes the fixup may change.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
@ fixup_ve_gotoff_hi32
fixup_ve_gotoff_hi32 - 32-bit fixup corresponding to foo@gotoff_hi
@ fixup_ve_hi32
fixup_ve_hi32 - 32-bit fixup corresponding to foo@hi
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent information on a fixup kind.
@ fixup_ve_got_lo32
fixup_ve_got_lo32 - 32-bit fixup corresponding to foo@got_lo
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ fixup_ve_got_hi32
fixup_ve_got_hi32 - 32-bit fixup corresponding to foo@got_hi
PowerPC TLS Dynamic Call Fixup
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const Symbol *GOTSymbol)
Apply fixup expression for edge to block content.
unsigned const MachineRegisterInfo * MRI
Encapsulates the layout of an assembly file at a particular point in time.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_Data_8
A eight-byte fixup.
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
This represents an "assembler immediate".
@ fixup_ve_srel32
fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
@ FK_Data_2
A two-byte fixup.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.