LLVM  15.0.0git
VEAsmBackend.cpp
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1 //===-- VEAsmBackend.cpp - VE Assembler Backend ---------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCValue.h"
18 #include "llvm/MC/TargetRegistry.h"
20 
21 using namespace llvm;
22 
24  switch (Kind) {
25  default:
26  llvm_unreachable("Unknown fixup kind!");
27  case FK_Data_1:
28  case FK_Data_2:
29  case FK_Data_4:
30  case FK_Data_8:
31  case FK_PCRel_1:
32  case FK_PCRel_2:
33  case FK_PCRel_4:
34  case FK_PCRel_8:
35  return Value;
36  case VE::fixup_ve_hi32:
43  return (Value >> 32) & 0xffffffff;
46  case VE::fixup_ve_lo32:
53  return Value & 0xffffffff;
54  }
55 }
56 
57 /// getFixupKindNumBytes - The number of bytes the fixup may change.
58 static unsigned getFixupKindNumBytes(unsigned Kind) {
59  switch (Kind) {
60  default:
61  llvm_unreachable("Unknown fixup kind!");
62  case FK_Data_1:
63  case FK_PCRel_1:
64  return 1;
65  case FK_Data_2:
66  case FK_PCRel_2:
67  return 2;
68  return 4;
69  case FK_Data_4:
70  case FK_PCRel_4:
73  case VE::fixup_ve_hi32:
74  case VE::fixup_ve_lo32:
87  return 4;
88  case FK_Data_8:
89  case FK_PCRel_8:
90  return 8;
91  }
92 }
93 
94 namespace {
95 class VEAsmBackend : public MCAsmBackend {
96 protected:
97  const Target &TheTarget;
98 
99 public:
100  VEAsmBackend(const Target &T) : MCAsmBackend(support::little), TheTarget(T) {}
101 
102  unsigned getNumFixupKinds() const override { return VE::NumTargetFixupKinds; }
103 
104  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
105  const static MCFixupKindInfo Infos[VE::NumTargetFixupKinds] = {
106  // name, offset, bits, flags
107  {"fixup_ve_reflong", 0, 32, 0},
108  {"fixup_ve_srel32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
109  {"fixup_ve_hi32", 0, 32, 0},
110  {"fixup_ve_lo32", 0, 32, 0},
111  {"fixup_ve_pc_hi32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
112  {"fixup_ve_pc_lo32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
113  {"fixup_ve_got_hi32", 0, 32, 0},
114  {"fixup_ve_got_lo32", 0, 32, 0},
115  {"fixup_ve_gotoff_hi32", 0, 32, 0},
116  {"fixup_ve_gotoff_lo32", 0, 32, 0},
117  {"fixup_ve_plt_hi32", 0, 32, 0},
118  {"fixup_ve_plt_lo32", 0, 32, 0},
119  {"fixup_ve_tls_gd_hi32", 0, 32, 0},
120  {"fixup_ve_tls_gd_lo32", 0, 32, 0},
121  {"fixup_ve_tpoff_hi32", 0, 32, 0},
122  {"fixup_ve_tpoff_lo32", 0, 32, 0},
123  };
124 
127 
128  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
129  "Invalid kind!");
130  return Infos[Kind - FirstTargetFixupKind];
131  }
132 
133  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
134  const MCValue &Target) override {
135  switch ((VE::Fixups)Fixup.getKind()) {
136  default:
137  return false;
142  return true;
143  }
144  }
145 
146  bool mayNeedRelaxation(const MCInst &Inst,
147  const MCSubtargetInfo &STI) const override {
148  // Not implemented yet. For example, if we have a branch with
149  // lager than SIMM32 immediate value, we want to relaxation such
150  // branch instructions.
151  return false;
152  }
153 
154  /// fixupNeedsRelaxation - Target specific predicate for whether a given
155  /// fixup requires the associated instruction to be relaxed.
156  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
157  const MCRelaxableFragment *DF,
158  const MCAsmLayout &Layout) const override {
159  // Not implemented yet. For example, if we have a branch with
160  // lager than SIMM32 immediate value, we want to relaxation such
161  // branch instructions.
162  return false;
163  }
164  void relaxInstruction(MCInst &Inst,
165  const MCSubtargetInfo &STI) const override {
166  // Aurora VE doesn't support relaxInstruction yet.
167  llvm_unreachable("relaxInstruction() should not be called");
168  }
169 
170  bool writeNopData(raw_ostream &OS, uint64_t Count,
171  const MCSubtargetInfo *STI) const override {
172  if ((Count % 8) != 0)
173  return false;
174 
175  for (uint64_t i = 0; i < Count; i += 8)
176  support::endian::write<uint64_t>(OS, 0x7900000000000000ULL,
178 
179  return true;
180  }
181 };
182 
183 class ELFVEAsmBackend : public VEAsmBackend {
184  Triple::OSType OSType;
185 
186 public:
187  ELFVEAsmBackend(const Target &T, Triple::OSType OSType)
188  : VEAsmBackend(T), OSType(OSType) {}
189 
190  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
192  uint64_t Value, bool IsResolved,
193  const MCSubtargetInfo *STI) const override {
194  Value = adjustFixupValue(Fixup.getKind(), Value);
195  if (!Value)
196  return; // Doesn't change encoding.
197 
198  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
199 
200  // Shift the value into position.
201  Value <<= Info.TargetOffset;
202 
203  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
204  unsigned Offset = Fixup.getOffset();
205  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
206  // For each byte of the fragment that the fixup touches, mask in the bits
207  // from the fixup value. The Value has been "split up" into the
208  // appropriate bitfields above.
209  for (unsigned i = 0; i != NumBytes; ++i) {
210  unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i;
211  Data[Offset + Idx] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
212  }
213  }
214 
215  std::unique_ptr<MCObjectTargetWriter>
216  createObjectTargetWriter() const override {
217  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
218  return createVEELFObjectWriter(OSABI);
219  }
220 };
221 } // end anonymous namespace
222 
224  const MCSubtargetInfo &STI,
225  const MCRegisterInfo &MRI,
226  const MCTargetOptions &Options) {
227  return new ELFVEAsmBackend(T, STI.getTargetTriple().getOS());
228 }
llvm::VE::fixup_ve_reflong
@ fixup_ve_reflong
fixup_ve_reflong - 32-bit fixup corresponding to foo
Definition: VEFixupKinds.h:18
i
i
Definition: README.txt:29
llvm::VE::fixup_ve_plt_hi32
@ fixup_ve_plt_hi32
fixup_ve_plt_hi32/lo32
Definition: VEFixupKinds.h:48
llvm::VE::fixup_ve_pc_lo32
@ fixup_ve_pc_lo32
fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo
Definition: VEFixupKinds.h:33
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:78
llvm::FK_PCRel_8
@ FK_PCRel_8
A eight-byte pc relative fixup.
Definition: MCFixup.h:31
T
llvm::createVEELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createVEELFObjectWriter(uint8_t OSABI)
Definition: VEELFObjectWriter.cpp:158
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
llvm::VE::fixup_ve_pc_hi32
@ fixup_ve_pc_hi32
fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo@pc_hi
Definition: VEFixupKinds.h:30
llvm::VE::fixup_ve_tls_gd_lo32
@ fixup_ve_tls_gd_lo32
Definition: VEFixupKinds.h:53
MCFixupKindInfo.h
VEFixupKinds.h
llvm::createVEAsmBackend
MCAsmBackend * createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: VEAsmBackend.cpp:223
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::FK_PCRel_1
@ FK_PCRel_1
A one-byte pc relative fixup.
Definition: MCFixup.h:28
llvm::VE::Fixups
Fixups
Definition: VEFixupKinds.h:16
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
MCSubtargetInfo.h
llvm::VE::fixup_ve_lo32
@ fixup_ve_lo32
fixup_ve_lo32 - 32-bit fixup corresponding to foo@lo
Definition: VEFixupKinds.h:27
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
VEMCTargetDesc.h
llvm::VE::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: VEFixupKinds.h:59
llvm::MCAssembler
Definition: MCAssembler.h:73
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:406
uint64_t
llvm::Triple::getOS
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:346
llvm::VE::fixup_ve_tls_gd_hi32
@ fixup_ve_tls_gd_hi32
fixups for Thread Local Storage
Definition: VEFixupKinds.h:52
MCELFObjectWriter.h
llvm::VE::fixup_ve_gotoff_lo32
@ fixup_ve_gotoff_lo32
fixup_ve_gotoff_lo32 - 32-bit fixup corresponding to foo@gotoff_lo
Definition: VEFixupKinds.h:45
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
getFixupKindNumBytes - The number of bytes the fixup may change.
Definition: VEAsmBackend.cpp:58
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::VE::fixup_ve_gotoff_hi32
@ fixup_ve_gotoff_hi32
fixup_ve_gotoff_hi32 - 32-bit fixup corresponding to foo@gotoff_hi
Definition: VEFixupKinds.h:42
llvm::VE::fixup_ve_hi32
@ fixup_ve_hi32
fixup_ve_hi32 - 32-bit fixup corresponding to foo@hi
Definition: VEFixupKinds.h:24
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::VE::fixup_ve_got_lo32
@ fixup_ve_got_lo32
fixup_ve_got_lo32 - 32-bit fixup corresponding to foo@got_lo
Definition: VEFixupKinds.h:39
llvm::FK_PCRel_2
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::VE::fixup_ve_got_hi32
@ fixup_ve_got_hi32
fixup_ve_got_hi32 - 32-bit fixup corresponding to foo@got_hi
Definition: VEFixupKinds.h:36
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:233
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MCObjectWriter.h
llvm::Triple::OSType
OSType
Definition: Triple.h:173
llvm::VE::fixup_ve_tpoff_lo32
@ fixup_ve_tpoff_lo32
Definition: VEFixupKinds.h:55
EndianStream.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::VE::fixup_ve_plt_lo32
@ fixup_ve_plt_lo32
Definition: VEFixupKinds.h:49
MCValue.h
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
adjustFixupValue
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
Definition: VEAsmBackend.cpp:23
llvm::VE::fixup_ve_tpoff_hi32
@ fixup_ve_tpoff_hi32
Definition: VEFixupKinds.h:54
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::VE::fixup_ve_srel32
@ fixup_ve_srel32
fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
Definition: VEFixupKinds.h:21
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74