LLVM 18.0.0git
Classes | Enumerations | Functions | Variables
llvm::jitlink::aarch32 Namespace Reference

Classes

struct  ArmConfig
 JITLink sub-arch configuration for Arm CPU models. More...
 
struct  FixupInfo
 Collection of named constants per fixup kind. More...
 
struct  FixupInfo< Arm_Call >
 
struct  FixupInfo< Arm_Jump24 >
 
struct  FixupInfo< Arm_MovtAbs >
 
struct  FixupInfo< Arm_MovwAbsNC >
 
struct  FixupInfo< Thumb_Call >
 
struct  FixupInfo< Thumb_Jump24 >
 
struct  FixupInfo< Thumb_MovtAbs >
 
struct  FixupInfo< Thumb_MovtPrel >
 
struct  FixupInfo< Thumb_MovwAbsNC >
 
struct  FixupInfo< Thumb_MovwPrelNC >
 
struct  FixupInfoArm
 FixupInfo checks for Arm edge kinds work on 32-bit words. More...
 
struct  FixupInfoBase
 FixupInfo base class is required for dynamic lookups. More...
 
struct  FixupInfoThumb
 FixupInfo check for Thumb32 edge kinds work on a pair of 16-bit halfwords. More...
 
struct  HalfWords
 Immutable pair of halfwords, Hi and Lo, with overflow check. More...
 
class  StubsManager
 Stubs builder for a specific StubsFlavor. More...
 

Enumerations

enum  EdgeKind_aarch32 : Edge::Kind {
  FirstDataRelocation = Edge::FirstRelocation , Data_Delta32 = FirstDataRelocation , Data_Pointer32 , LastDataRelocation = Data_Pointer32 ,
  FirstArmRelocation , Arm_Call = FirstArmRelocation , Arm_Jump24 , Arm_MovwAbsNC ,
  Arm_MovtAbs , LastArmRelocation = Arm_MovtAbs , FirstThumbRelocation , Thumb_Call = FirstThumbRelocation ,
  Thumb_Jump24 , Thumb_MovwAbsNC , Thumb_MovtAbs , Thumb_MovwPrelNC ,
  Thumb_MovtPrel , LastThumbRelocation = Thumb_MovtPrel , LastRelocation = LastThumbRelocation
}
 JITLink-internal AArch32 fixup kinds. More...
 
enum  TargetFlags_aarch32 : TargetFlagsType { ThumbSymbol = 1 << 0 }
 Flags enum for AArch32-specific symbol properties. More...
 
enum  StubsFlavor { Unsupported = 0 , Thumbv7 }
 AArch32 uses stubs for a number of purposes, like branch range extension or interworking between Arm and Thumb instruction subsets. More...
 

Functions

bool hasTargetFlags (Symbol &Sym, TargetFlagsType Flags)
 Check whether the given target flags are set for this Symbol.
 
const chargetCPUArchName (ARMBuildAttrs::CPUArch K)
 Human-readable name for a given CPU architecture kind.
 
const chargetEdgeKindName (Edge::Kind K)
 Get a human-readable name for the given AArch32 edge kind.
 
ArmConfig getArmConfigForCPUArch (ARMBuildAttrs::CPUArch CPUArch)
 Obtain the sub-arch configuration for a given Arm CPU model.
 
Expected< int64_t > readAddendData (LinkGraph &G, Block &B, Edge::OffsetT Offset, Edge::Kind Kind)
 Helper function to read the initial addend for Data-class relocations.
 
Expected< int64_t > readAddendArm (LinkGraph &G, Block &B, Edge::OffsetT Offset, Edge::Kind Kind)
 Helper function to read the initial addend for Arm-class relocations.
 
Expected< int64_t > readAddendThumb (LinkGraph &G, Block &B, Edge::OffsetT Offset, Edge::Kind Kind, const ArmConfig &ArmCfg)
 Helper function to read the initial addend for Thumb-class relocations.
 
Expected< int64_t > readAddend (LinkGraph &G, Block &B, Edge::OffsetT Offset, Edge::Kind Kind, const ArmConfig &ArmCfg)
 Read the initial addend for a REL-type relocation.
 
Error applyFixupData (LinkGraph &G, Block &B, const Edge &E)
 Helper function to apply the fixup for Data-class relocations.
 
Error applyFixupArm (LinkGraph &G, Block &B, const Edge &E)
 Helper function to apply the fixup for Arm-class relocations.
 
Error applyFixupThumb (LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
 Helper function to apply the fixup for Thumb-class relocations.
 
Error applyFixup (LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
 Apply fixup expression for edge to block content.
 
HalfWords encodeImmBT4BlT1BlxT2 (int64_t Value)
 Encode 22-bit immediate value for branch instructions without J1J2 range extension (formats B T4, BL T1 and BLX T2).
 
int64_t decodeImmBT4BlT1BlxT2 (uint32_t Hi, uint32_t Lo)
 Decode 22-bit immediate value for branch instructions without J1J2 range extension (formats B T4, BL T1 and BLX T2).
 
HalfWords encodeImmBT4BlT1BlxT2_J1J2 (int64_t Value)
 Encode 25-bit immediate value for branch instructions with J1J2 range extension (formats B T4, BL T1 and BLX T2).
 
int64_t decodeImmBT4BlT1BlxT2_J1J2 (uint32_t Hi, uint32_t Lo)
 Decode 25-bit immediate value for branch instructions with J1J2 range extension (formats B T4, BL T1 and BLX T2).
 
uint32_t encodeImmBA1BlA1BlxA2 (int64_t Value)
 Encode 26-bit immediate value for branch instructions (formats B A1, BL A1 and BLX A2).
 
int64_t decodeImmBA1BlA1BlxA2 (int64_t Value)
 Decode 26-bit immediate value for branch instructions (formats B A1, BL A1 and BLX A2).
 
HalfWords encodeImmMovtT1MovwT3 (uint16_t Value)
 Encode 16-bit immediate value for move instruction formats MOVT T1 and MOVW T3.
 
uint16_t decodeImmMovtT1MovwT3 (uint32_t Hi, uint32_t Lo)
 Decode 16-bit immediate value from move instruction formats MOVT T1 and MOVW T3.
 
HalfWords encodeRegMovtT1MovwT3 (int64_t Value)
 Encode register ID for instruction formats MOVT T1 and MOVW T3.
 
int64_t decodeRegMovtT1MovwT3 (uint32_t Hi, uint32_t Lo)
 Decode register ID from instruction formats MOVT T1 and MOVW T3.
 
uint32_t encodeImmMovtA1MovwA2 (uint16_t Value)
 Encode 16-bit immediate value for move instruction formats MOVT A1 and MOVW A2.
 
uint16_t decodeImmMovtA1MovwA2 (uint64_t Value)
 Decode 16-bit immediate value for move instruction formats MOVT A1 and MOVW A2.
 
uint32_t encodeRegMovtA1MovwA2 (int64_t Value)
 Encode register ID for instruction formats MOVT A1 and MOVW A2.
 
int64_t decodeRegMovtA1MovwA2 (uint64_t Value)
 Decode register ID for instruction formats MOVT A1 and MOVW A2.
 
static Error checkOpcode (LinkGraph &G, const ArmRelocation &R, Edge::Kind Kind)
 
static Error checkOpcode (LinkGraph &G, const ThumbRelocation &R, Edge::Kind Kind)
 
template<EdgeKind_aarch32 Kind>
bool checkRegister (const ThumbRelocation &R, HalfWords Reg)
 
template<EdgeKind_aarch32 Kind>
bool checkRegister (const ArmRelocation &R, uint32_t Reg)
 
template<EdgeKind_aarch32 Kind>
void writeRegister (WritableThumbRelocation &R, HalfWords Reg)
 
template<EdgeKind_aarch32 Kind>
void writeRegister (WritableArmRelocation &R, uint32_t Reg)
 
template<EdgeKind_aarch32 Kind>
void writeImmediate (WritableThumbRelocation &R, HalfWords Imm)
 
template<EdgeKind_aarch32 Kind>
void writeImmediate (WritableArmRelocation &R, uint32_t Imm)
 

Variables

const uint8_t Thumbv7ABS []
 

Enumeration Type Documentation

◆ EdgeKind_aarch32

JITLink-internal AArch32 fixup kinds.

Enumerator
FirstDataRelocation 

Relocations of class Data respect target endianness (unless otherwise specified)

Data_Delta32 

Relative 32-bit value relocation.

Data_Pointer32 

Absolute 32-bit value relocation.

LastDataRelocation 
FirstArmRelocation 

Relocations of class Arm (covers fixed-width 4-byte instruction subset)

Arm_Call 

Write immediate value for unconditional PC-relative branch with link.

We patch the instruction opcode to account for an instruction-set state switch: we use the bl instruction to stay in ARM and the blx instruction to switch to Thumb.

Arm_Jump24 

Write immediate value for conditional PC-relative branch without link.

If the branch target is not ARM, we are forced to generate an explicit interworking stub.

Arm_MovwAbsNC 

Write immediate value to the lower halfword of the destination register.

Arm_MovtAbs 

Write immediate value to the top halfword of the destination register.

LastArmRelocation 
FirstThumbRelocation 

Relocations of class Thumb16 and Thumb32 (covers Thumb instruction subset)

Thumb_Call 

Write immediate value for unconditional PC-relative branch with link.

We patch the instruction opcode to account for an instruction-set state switch: we use the bl instruction to stay in Thumb and the blx instruction to switch to ARM.

Thumb_Jump24 

Write immediate value for PC-relative branch without link.

The instruction can be made conditional by an IT block. If the branch target is not ARM, we are forced to generate an explicit interworking stub.

Thumb_MovwAbsNC 

Write immediate value to the lower halfword of the destination register.

Thumb_MovtAbs 

Write immediate value to the top halfword of the destination register.

Thumb_MovwPrelNC 

Write PC-relative immediate value to the lower halfword of the destination register.

Thumb_MovtPrel 

Write PC-relative immediate value to the top halfword of the destination register.

LastThumbRelocation 
LastRelocation 

Definition at line 30 of file aarch32.h.

◆ StubsFlavor

AArch32 uses stubs for a number of purposes, like branch range extension or interworking between Arm and Thumb instruction subsets.

Stub implementations vary depending on CPU architecture (v4, v6, v7), instruction subset and branch type (absolute/PC-relative).

For each kind of stub, the StubsFlavor defines one concrete form that is used throughout the LinkGraph.

Stubs are often called "veneers" in the official docs and online.

Enumerator
Unsupported 
Thumbv7 

Definition at line 126 of file aarch32.h.

◆ TargetFlags_aarch32

Flags enum for AArch32-specific symbol properties.

Enumerator
ThumbSymbol 

Definition at line 105 of file aarch32.h.

Function Documentation

◆ applyFixup()

Error llvm::jitlink::aarch32::applyFixup ( LinkGraph G,
Block B,
const Edge E,
const ArmConfig ArmCfg 
)
inline

Apply fixup expression for edge to block content.

Definition at line 311 of file aarch32.h.

References applyFixupArm(), applyFixupData(), applyFixupThumb(), B, E, G, LastArmRelocation, LastDataRelocation, LastThumbRelocation, and llvm_unreachable.

◆ applyFixupArm()

Error llvm::jitlink::aarch32::applyFixupArm ( LinkGraph G,
Block B,
const Edge E 
)

◆ applyFixupData()

Error llvm::jitlink::aarch32::applyFixupData ( LinkGraph G,
Block B,
const Edge E 
)

Helper function to apply the fixup for Data-class relocations.

Definition at line 461 of file aarch32.cpp.

References assert(), B, Data_Delta32, Data_Pointer32, E, Endian, G, llvm::jitlink::Symbol::getAddress(), llvm::orc::ExecutorAddr::getValue(), llvm::little, LLVM_LIKELY, llvm::jitlink::makeTargetOutOfRangeError(), and llvm::Error::success().

Referenced by applyFixup().

◆ applyFixupThumb()

Error llvm::jitlink::aarch32::applyFixupThumb ( LinkGraph G,
Block B,
const Edge E,
const ArmConfig ArmCfg 
)

◆ checkOpcode() [1/2]

static Error llvm::jitlink::aarch32::checkOpcode ( LinkGraph G,
const ArmRelocation &  R,
Edge::Kind  Kind 
)
static

◆ checkOpcode() [2/2]

static Error llvm::jitlink::aarch32::checkOpcode ( LinkGraph G,
const ThumbRelocation &  R,
Edge::Kind  Kind 
)
static

◆ checkRegister() [1/2]

template<EdgeKind_aarch32 Kind>
bool llvm::jitlink::aarch32::checkRegister ( const ArmRelocation &  R,
uint32_t  Reg 
)

Definition at line 352 of file aarch32.cpp.

References Reg, and Wd.

◆ checkRegister() [2/2]

template<EdgeKind_aarch32 Kind>
bool llvm::jitlink::aarch32::checkRegister ( const ThumbRelocation &  R,
HalfWords  Reg 
)

Definition at line 345 of file aarch32.cpp.

References llvm::Hi, llvm::Lo, and Reg.

◆ decodeImmBA1BlA1BlxA2()

int64_t llvm::jitlink::aarch32::decodeImmBA1BlA1BlxA2 ( int64_t  Value)

Decode 26-bit immediate value for branch instructions (formats B A1, BL A1 and BLX A2).

00000000:Imm24 -> Imm24:00

Definition at line 101 of file aarch32.cpp.

Referenced by readAddendArm().

◆ decodeImmBT4BlT1BlxT2()

int64_t llvm::jitlink::aarch32::decodeImmBT4BlT1BlxT2 ( uint32_t  Hi,
uint32_t  Lo 
)

Decode 22-bit immediate value for branch instructions without J1J2 range extension (formats B T4, BL T1 and BLX T2).

[ 00000:Imm11H, 00000:Imm11L ] -> 00000:Imm11H:Imm11L:0 J1^ ^J2 will always be 1

Definition at line 53 of file aarch32.cpp.

References llvm::Hi, and llvm::Lo.

Referenced by readAddendThumb().

◆ decodeImmBT4BlT1BlxT2_J1J2()

int64_t llvm::jitlink::aarch32::decodeImmBT4BlT1BlxT2_J1J2 ( uint32_t  Hi,
uint32_t  Lo 
)

Decode 25-bit immediate value for branch instructions with J1J2 range extension (formats B T4, BL T1 and BLX T2).

[ 00000:S:Imm10, 00:J1:0:J2:Imm11] -> S:I1:I2:Imm10:Imm11:0

Definition at line 78 of file aarch32.cpp.

References llvm::Hi, and llvm::Lo.

Referenced by readAddendThumb().

◆ decodeImmMovtA1MovwA2()

uint16_t llvm::jitlink::aarch32::decodeImmMovtA1MovwA2 ( uint64_t  Value)

Decode 16-bit immediate value for move instruction formats MOVT A1 and MOVW A2.

000000000000:Imm4:0000:Imm12 -> Imm4:Imm12

Definition at line 167 of file aarch32.cpp.

Referenced by readAddendArm().

◆ decodeImmMovtT1MovwT3()

uint16_t llvm::jitlink::aarch32::decodeImmMovtT1MovwT3 ( uint32_t  Hi,
uint32_t  Lo 
)

Decode 16-bit immediate value from move instruction formats MOVT T1 and MOVW T3.

[ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ] -> Imm4:Imm1:Imm3:Imm8

Definition at line 123 of file aarch32.cpp.

References assert(), llvm::Hi, and llvm::Lo.

Referenced by readAddendThumb().

◆ decodeRegMovtA1MovwA2()

int64_t llvm::jitlink::aarch32::decodeRegMovtA1MovwA2 ( uint64_t  Value)

Decode register ID for instruction formats MOVT A1 and MOVW A2.

0000000000000000:Rd4:000000000000 -> Rd4

Definition at line 188 of file aarch32.cpp.

◆ decodeRegMovtT1MovwT3()

int64_t llvm::jitlink::aarch32::decodeRegMovtT1MovwT3 ( uint32_t  Hi,
uint32_t  Lo 
)

Decode register ID from instruction formats MOVT T1 and MOVW T3.

[0000000000000000, 0000:Rd4:00000000] -> Rd4

Definition at line 146 of file aarch32.cpp.

References llvm::Lo.

◆ encodeImmBA1BlA1BlxA2()

uint32_t llvm::jitlink::aarch32::encodeImmBA1BlA1BlxA2 ( int64_t  Value)

Encode 26-bit immediate value for branch instructions (formats B A1, BL A1 and BLX A2).

Imm24:00 -> 00000000:Imm24

Definition at line 92 of file aarch32.cpp.

Referenced by applyFixupArm().

◆ encodeImmBT4BlT1BlxT2()

HalfWords llvm::jitlink::aarch32::encodeImmBT4BlT1BlxT2 ( int64_t  Value)

Encode 22-bit immediate value for branch instructions without J1J2 range extension (formats B T4, BL T1 and BLX T2).

00000:Imm11H:Imm11L:0 -> [ 00000:Imm11H, 00000:Imm11L ] J1^ ^J2 will always be 1

Definition at line 40 of file aarch32.cpp.

Referenced by applyFixupThumb().

◆ encodeImmBT4BlT1BlxT2_J1J2()

HalfWords llvm::jitlink::aarch32::encodeImmBT4BlT1BlxT2_J1J2 ( int64_t  Value)

Encode 25-bit immediate value for branch instructions with J1J2 range extension (formats B T4, BL T1 and BLX T2).

S:I1:I2:Imm10:Imm11:0 -> [ 00000:S:Imm10, 00:J1:0:J2:Imm11 ]

Definition at line 64 of file aarch32.cpp.

Referenced by applyFixupThumb().

◆ encodeImmMovtA1MovwA2()

uint32_t llvm::jitlink::aarch32::encodeImmMovtA1MovwA2 ( uint16_t  Value)

Encode 16-bit immediate value for move instruction formats MOVT A1 and MOVW A2.

Imm4:Imm12 -> 000000000000:Imm4:0000:Imm12

Definition at line 156 of file aarch32.cpp.

Referenced by applyFixupArm().

◆ encodeImmMovtT1MovwT3()

HalfWords llvm::jitlink::aarch32::encodeImmMovtT1MovwT3 ( uint16_t  Value)

Encode 16-bit immediate value for move instruction formats MOVT T1 and MOVW T3.

Imm4:Imm1:Imm3:Imm8 -> [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ]

Definition at line 110 of file aarch32.cpp.

Referenced by applyFixupThumb().

◆ encodeRegMovtA1MovwA2()

uint32_t llvm::jitlink::aarch32::encodeRegMovtA1MovwA2 ( int64_t  Value)

Encode register ID for instruction formats MOVT A1 and MOVW A2.

Rd4 -> 0000000000000000:Rd4:000000000000

Definition at line 178 of file aarch32.cpp.

◆ encodeRegMovtT1MovwT3()

HalfWords llvm::jitlink::aarch32::encodeRegMovtT1MovwT3 ( int64_t  Value)

Encode register ID for instruction formats MOVT T1 and MOVW T3.

Rd4 -> [0000000000000000, 0000:Rd4:00000000]

Definition at line 137 of file aarch32.cpp.

Referenced by llvm::jitlink::aarch32::StubsManager< Flavor >::createEntry().

◆ getArmConfigForCPUArch()

ArmConfig llvm::jitlink::aarch32::getArmConfigForCPUArch ( ARMBuildAttrs::CPUArch  CPUArch)
inline

◆ getCPUArchName()

const char * llvm::jitlink::aarch32::getCPUArchName ( ARMBuildAttrs::CPUArch  K)

Human-readable name for a given CPU architecture kind.

Definition at line 729 of file aarch32.cpp.

References CPUARCH_NAME_CASE, and llvm_unreachable.

Referenced by llvm::jitlink::createLinkGraphFromELFObject_aarch32(), and getArmConfigForCPUArch().

◆ getEdgeKindName()

const char * llvm::jitlink::aarch32::getEdgeKindName ( Edge::Kind  K)

◆ hasTargetFlags()

bool llvm::jitlink::aarch32::hasTargetFlags ( Symbol Sym,
TargetFlagsType  Flags 
)

Check whether the given target flags are set for this Symbol.

Definition at line 30 of file aarch32.cpp.

References Sym.

Referenced by applyFixupArm(), and applyFixupThumb().

◆ readAddend()

Expected< int64_t > llvm::jitlink::aarch32::readAddend ( LinkGraph G,
Block B,
Edge::OffsetT  Offset,
Edge::Kind  Kind,
const ArmConfig ArmCfg 
)
inline

Read the initial addend for a REL-type relocation.

It's the value encoded in the immediate field of the fixup location by the compiler.

Definition at line 285 of file aarch32.h.

References B, G, LastArmRelocation, LastDataRelocation, LastThumbRelocation, llvm_unreachable, llvm::Offset, readAddendArm(), readAddendData(), and readAddendThumb().

◆ readAddendArm()

Expected< int64_t > llvm::jitlink::aarch32::readAddendArm ( LinkGraph G,
Block B,
Edge::OffsetT  Offset,
Edge::Kind  Kind 
)

Helper function to read the initial addend for Arm-class relocations.

Definition at line 407 of file aarch32.cpp.

References Arm_Call, Arm_Jump24, Arm_MovtAbs, Arm_MovwAbsNC, B, checkOpcode(), decodeImmBA1BlA1BlxA2(), decodeImmMovtA1MovwA2(), G, and llvm::Offset.

Referenced by readAddend().

◆ readAddendData()

Expected< int64_t > llvm::jitlink::aarch32::readAddendData ( LinkGraph G,
Block B,
Edge::OffsetT  Offset,
Edge::Kind  Kind 
)

Helper function to read the initial addend for Data-class relocations.

Definition at line 389 of file aarch32.cpp.

References B, Data_Delta32, Data_Pointer32, Endian, G, llvm::Offset, and llvm::support::endian::read32().

Referenced by readAddend().

◆ readAddendThumb()

Expected< int64_t > llvm::jitlink::aarch32::readAddendThumb ( LinkGraph G,
Block B,
Edge::OffsetT  Offset,
Edge::Kind  Kind,
const ArmConfig ArmCfg 
)

◆ writeImmediate() [1/2]

template<EdgeKind_aarch32 Kind>
void llvm::jitlink::aarch32::writeImmediate ( WritableArmRelocation &  R,
uint32_t  Imm 
)

Definition at line 383 of file aarch32.cpp.

References assert().

◆ writeImmediate() [2/2]

template<EdgeKind_aarch32 Kind>
void llvm::jitlink::aarch32::writeImmediate ( WritableThumbRelocation &  R,
HalfWords  Imm 
)

Definition at line 374 of file aarch32.cpp.

References assert().

◆ writeRegister() [1/2]

template<EdgeKind_aarch32 Kind>
void llvm::jitlink::aarch32::writeRegister ( WritableArmRelocation &  R,
uint32_t  Reg 
)

Definition at line 367 of file aarch32.cpp.

References assert(), and Reg.

◆ writeRegister() [2/2]

template<EdgeKind_aarch32 Kind>
void llvm::jitlink::aarch32::writeRegister ( WritableThumbRelocation &  R,
HalfWords  Reg 
)

Definition at line 358 of file aarch32.cpp.

References assert(), and Reg.

Variable Documentation

◆ Thumbv7ABS

const uint8_t llvm::jitlink::aarch32::Thumbv7ABS[]
Initial value:
= {
0x40, 0xf2, 0x00, 0x0c,
0xc0, 0xf2, 0x00, 0x0c,
0x60, 0x47
}

Definition at line 681 of file aarch32.cpp.

Referenced by llvm::jitlink::aarch32::StubsManager< Flavor >::createEntry().