LLVM  9.0.0svn
SIInstrInfo.cpp
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1 //===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI Implementation of TargetInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SIInstrInfo.h"
15 #include "AMDGPU.h"
16 #include "AMDGPUSubtarget.h"
17 #include "GCNHazardRecognizer.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "SIRegisterInfo.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "llvm/ADT/APInt.h"
24 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/StringRef.h"
46 #include "llvm/IR/DebugLoc.h"
47 #include "llvm/IR/DiagnosticInfo.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/InlineAsm.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/MC/MCInstrDesc.h"
52 #include "llvm/Support/Casting.h"
54 #include "llvm/Support/Compiler.h"
59 #include <cassert>
60 #include <cstdint>
61 #include <iterator>
62 #include <utility>
63 
64 using namespace llvm;
65 
66 #define GET_INSTRINFO_CTOR_DTOR
67 #include "AMDGPUGenInstrInfo.inc"
68 
69 namespace llvm {
70 namespace AMDGPU {
71 #define GET_D16ImageDimIntrinsics_IMPL
72 #define GET_ImageDimIntrinsicTable_IMPL
73 #define GET_RsrcIntrinsics_IMPL
74 #include "AMDGPUGenSearchableTables.inc"
75 }
76 }
77 
78 
79 // Must be at least 4 to be able to branch over minimum unconditional branch
80 // code. This is only for making it possible to write reasonably small tests for
81 // long branches.
82 static cl::opt<unsigned>
83 BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
84  cl::desc("Restrict range of branch instructions (DEBUG)"));
85 
87  : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
88  RI(ST), ST(ST) {}
89 
90 //===----------------------------------------------------------------------===//
91 // TargetInstrInfo callbacks
92 //===----------------------------------------------------------------------===//
93 
94 static unsigned getNumOperandsNoGlue(SDNode *Node) {
95  unsigned N = Node->getNumOperands();
96  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
97  --N;
98  return N;
99 }
100 
101 /// Returns true if both nodes have the same value for the given
102 /// operand \p Op, or if both nodes do not have this operand.
103 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
104  unsigned Opc0 = N0->getMachineOpcode();
105  unsigned Opc1 = N1->getMachineOpcode();
106 
107  int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
108  int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
109 
110  if (Op0Idx == -1 && Op1Idx == -1)
111  return true;
112 
113 
114  if ((Op0Idx == -1 && Op1Idx != -1) ||
115  (Op1Idx == -1 && Op0Idx != -1))
116  return false;
117 
118  // getNamedOperandIdx returns the index for the MachineInstr's operands,
119  // which includes the result as the first operand. We are indexing into the
120  // MachineSDNode's operands, so we need to skip the result operand to get
121  // the real index.
122  --Op0Idx;
123  --Op1Idx;
124 
125  return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
126 }
127 
129  AliasAnalysis *AA) const {
130  // TODO: The generic check fails for VALU instructions that should be
131  // rematerializable due to implicit reads of exec. We really want all of the
132  // generic logic for this except for this.
133  switch (MI.getOpcode()) {
134  case AMDGPU::V_MOV_B32_e32:
135  case AMDGPU::V_MOV_B32_e64:
136  case AMDGPU::V_MOV_B64_PSEUDO:
137  // No implicit operands.
138  return MI.getNumOperands() == MI.getDesc().getNumOperands();
139  default:
140  return false;
141  }
142 }
143 
145  int64_t &Offset0,
146  int64_t &Offset1) const {
147  if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
148  return false;
149 
150  unsigned Opc0 = Load0->getMachineOpcode();
151  unsigned Opc1 = Load1->getMachineOpcode();
152 
153  // Make sure both are actually loads.
154  if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
155  return false;
156 
157  if (isDS(Opc0) && isDS(Opc1)) {
158 
159  // FIXME: Handle this case:
160  if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
161  return false;
162 
163  // Check base reg.
164  if (Load0->getOperand(0) != Load1->getOperand(0))
165  return false;
166 
167  // Skip read2 / write2 variants for simplicity.
168  // TODO: We should report true if the used offsets are adjacent (excluded
169  // st64 versions).
170  int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
171  int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
172  if (Offset0Idx == -1 || Offset1Idx == -1)
173  return false;
174 
175  // XXX - be careful of datalesss loads
176  // getNamedOperandIdx returns the index for MachineInstrs. Since they
177  // include the output in the operand list, but SDNodes don't, we need to
178  // subtract the index by one.
179  Offset0Idx -= get(Opc0).NumDefs;
180  Offset1Idx -= get(Opc1).NumDefs;
181  Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
182  Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
183  return true;
184  }
185 
186  if (isSMRD(Opc0) && isSMRD(Opc1)) {
187  // Skip time and cache invalidation instructions.
188  if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
189  AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
190  return false;
191 
193 
194  // Check base reg.
195  if (Load0->getOperand(0) != Load1->getOperand(0))
196  return false;
197 
198  const ConstantSDNode *Load0Offset =
199  dyn_cast<ConstantSDNode>(Load0->getOperand(1));
200  const ConstantSDNode *Load1Offset =
201  dyn_cast<ConstantSDNode>(Load1->getOperand(1));
202 
203  if (!Load0Offset || !Load1Offset)
204  return false;
205 
206  Offset0 = Load0Offset->getZExtValue();
207  Offset1 = Load1Offset->getZExtValue();
208  return true;
209  }
210 
211  // MUBUF and MTBUF can access the same addresses.
212  if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
213 
214  // MUBUF and MTBUF have vaddr at different indices.
215  if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
216  !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
217  !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
218  return false;
219 
220  int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
221  int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
222 
223  if (OffIdx0 == -1 || OffIdx1 == -1)
224  return false;
225 
226  // getNamedOperandIdx returns the index for MachineInstrs. Since they
227  // include the output in the operand list, but SDNodes don't, we need to
228  // subtract the index by one.
229  OffIdx0 -= get(Opc0).NumDefs;
230  OffIdx1 -= get(Opc1).NumDefs;
231 
232  SDValue Off0 = Load0->getOperand(OffIdx0);
233  SDValue Off1 = Load1->getOperand(OffIdx1);
234 
235  // The offset might be a FrameIndexSDNode.
236  if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
237  return false;
238 
239  Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
240  Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
241  return true;
242  }
243 
244  return false;
245 }
246 
247 static bool isStride64(unsigned Opc) {
248  switch (Opc) {
249  case AMDGPU::DS_READ2ST64_B32:
250  case AMDGPU::DS_READ2ST64_B64:
251  case AMDGPU::DS_WRITE2ST64_B32:
252  case AMDGPU::DS_WRITE2ST64_B64:
253  return true;
254  default:
255  return false;
256  }
257 }
258 
260  const MachineOperand *&BaseOp,
261  int64_t &Offset,
262  const TargetRegisterInfo *TRI) const {
263  unsigned Opc = LdSt.getOpcode();
264 
265  if (isDS(LdSt)) {
266  const MachineOperand *OffsetImm =
267  getNamedOperand(LdSt, AMDGPU::OpName::offset);
268  if (OffsetImm) {
269  // Normal, single offset LDS instruction.
270  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
271  // TODO: ds_consume/ds_append use M0 for the base address. Is it safe to
272  // report that here?
273  if (!BaseOp)
274  return false;
275 
276  Offset = OffsetImm->getImm();
277  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
278  "operands of type register.");
279  return true;
280  }
281 
282  // The 2 offset instructions use offset0 and offset1 instead. We can treat
283  // these as a load with a single offset if the 2 offsets are consecutive. We
284  // will use this for some partially aligned loads.
285  const MachineOperand *Offset0Imm =
286  getNamedOperand(LdSt, AMDGPU::OpName::offset0);
287  const MachineOperand *Offset1Imm =
288  getNamedOperand(LdSt, AMDGPU::OpName::offset1);
289 
290  uint8_t Offset0 = Offset0Imm->getImm();
291  uint8_t Offset1 = Offset1Imm->getImm();
292 
293  if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
294  // Each of these offsets is in element sized units, so we need to convert
295  // to bytes of the individual reads.
296 
297  unsigned EltSize;
298  if (LdSt.mayLoad())
299  EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
300  else {
301  assert(LdSt.mayStore());
302  int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
303  EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
304  }
305 
306  if (isStride64(Opc))
307  EltSize *= 64;
308 
309  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
310  Offset = EltSize * Offset0;
311  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
312  "operands of type register.");
313  return true;
314  }
315 
316  return false;
317  }
318 
319  if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
320  const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset);
321  if (SOffset && SOffset->isReg())
322  return false;
323 
324  const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
325  if (!AddrReg)
326  return false;
327 
328  const MachineOperand *OffsetImm =
329  getNamedOperand(LdSt, AMDGPU::OpName::offset);
330  BaseOp = AddrReg;
331  Offset = OffsetImm->getImm();
332 
333  if (SOffset) // soffset can be an inline immediate.
334  Offset += SOffset->getImm();
335 
336  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
337  "operands of type register.");
338  return true;
339  }
340 
341  if (isSMRD(LdSt)) {
342  const MachineOperand *OffsetImm =
343  getNamedOperand(LdSt, AMDGPU::OpName::offset);
344  if (!OffsetImm)
345  return false;
346 
347  const MachineOperand *SBaseReg = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
348  BaseOp = SBaseReg;
349  Offset = OffsetImm->getImm();
350  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
351  "operands of type register.");
352  return true;
353  }
354 
355  if (isFLAT(LdSt)) {
356  const MachineOperand *VAddr = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
357  if (VAddr) {
358  // Can't analyze 2 offsets.
359  if (getNamedOperand(LdSt, AMDGPU::OpName::saddr))
360  return false;
361 
362  BaseOp = VAddr;
363  } else {
364  // scratch instructions have either vaddr or saddr.
365  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
366  }
367 
368  Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
369  assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
370  "operands of type register.");
371  return true;
372  }
373 
374  return false;
375 }
376 
377 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
378  const MachineOperand &BaseOp1,
379  const MachineInstr &MI2,
380  const MachineOperand &BaseOp2) {
381  // Support only base operands with base registers.
382  // Note: this could be extended to support FI operands.
383  if (!BaseOp1.isReg() || !BaseOp2.isReg())
384  return false;
385 
386  if (BaseOp1.isIdenticalTo(BaseOp2))
387  return true;
388 
389  if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
390  return false;
391 
392  auto MO1 = *MI1.memoperands_begin();
393  auto MO2 = *MI2.memoperands_begin();
394  if (MO1->getAddrSpace() != MO2->getAddrSpace())
395  return false;
396 
397  auto Base1 = MO1->getValue();
398  auto Base2 = MO2->getValue();
399  if (!Base1 || !Base2)
400  return false;
401  const MachineFunction &MF = *MI1.getParent()->getParent();
402  const DataLayout &DL = MF.getFunction().getParent()->getDataLayout();
403  Base1 = GetUnderlyingObject(Base1, DL);
404  Base2 = GetUnderlyingObject(Base1, DL);
405 
406  if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
407  return false;
408 
409  return Base1 == Base2;
410 }
411 
413  const MachineOperand &BaseOp2,
414  unsigned NumLoads) const {
415  const MachineInstr &FirstLdSt = *BaseOp1.getParent();
416  const MachineInstr &SecondLdSt = *BaseOp2.getParent();
417 
418  if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOp1, SecondLdSt, BaseOp2))
419  return false;
420 
421  const MachineOperand *FirstDst = nullptr;
422  const MachineOperand *SecondDst = nullptr;
423 
424  if ((isMUBUF(FirstLdSt) && isMUBUF(SecondLdSt)) ||
425  (isMTBUF(FirstLdSt) && isMTBUF(SecondLdSt)) ||
426  (isFLAT(FirstLdSt) && isFLAT(SecondLdSt))) {
427  const unsigned MaxGlobalLoadCluster = 6;
428  if (NumLoads > MaxGlobalLoadCluster)
429  return false;
430 
431  FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdata);
432  if (!FirstDst)
433  FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst);
434  SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdata);
435  if (!SecondDst)
436  SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst);
437  } else if (isSMRD(FirstLdSt) && isSMRD(SecondLdSt)) {
438  FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::sdst);
439  SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::sdst);
440  } else if (isDS(FirstLdSt) && isDS(SecondLdSt)) {
441  FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst);
442  SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst);
443  }
444 
445  if (!FirstDst || !SecondDst)
446  return false;
447 
448  // Try to limit clustering based on the total number of bytes loaded
449  // rather than the number of instructions. This is done to help reduce
450  // register pressure. The method used is somewhat inexact, though,
451  // because it assumes that all loads in the cluster will load the
452  // same number of bytes as FirstLdSt.
453 
454  // The unit of this value is bytes.
455  // FIXME: This needs finer tuning.
456  unsigned LoadClusterThreshold = 16;
457 
458  const MachineRegisterInfo &MRI =
459  FirstLdSt.getParent()->getParent()->getRegInfo();
460 
461  const unsigned Reg = FirstDst->getReg();
462 
464  ? MRI.getRegClass(Reg)
465  : RI.getPhysRegClass(Reg);
466 
467  return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold;
468 }
469 
470 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
471 // the first 16 loads will be interleaved with the stores, and the next 16 will
472 // be clustered as expected. It should really split into 2 16 store batches.
473 //
474 // Loads are clustered until this returns false, rather than trying to schedule
475 // groups of stores. This also means we have to deal with saying different
476 // address space loads should be clustered, and ones which might cause bank
477 // conflicts.
478 //
479 // This might be deprecated so it might not be worth that much effort to fix.
481  int64_t Offset0, int64_t Offset1,
482  unsigned NumLoads) const {
483  assert(Offset1 > Offset0 &&
484  "Second offset should be larger than first offset!");
485  // If we have less than 16 loads in a row, and the offsets are within 64
486  // bytes, then schedule together.
487 
488  // A cacheline is 64 bytes (for global memory).
489  return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
490 }
491 
494  const DebugLoc &DL, unsigned DestReg,
495  unsigned SrcReg, bool KillSrc) {
496  MachineFunction *MF = MBB.getParent();
497  DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(),
498  "illegal SGPR to VGPR copy",
499  DL, DS_Error);
500  LLVMContext &C = MF->getFunction().getContext();
501  C.diagnose(IllegalCopy);
502 
503  BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
504  .addReg(SrcReg, getKillRegState(KillSrc));
505 }
506 
509  const DebugLoc &DL, unsigned DestReg,
510  unsigned SrcReg, bool KillSrc) const {
511  const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
512 
513  if (RC == &AMDGPU::VGPR_32RegClass) {
514  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
515  AMDGPU::SReg_32RegClass.contains(SrcReg));
516  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
517  .addReg(SrcReg, getKillRegState(KillSrc));
518  return;
519  }
520 
521  if (RC == &AMDGPU::SReg_32_XM0RegClass ||
522  RC == &AMDGPU::SReg_32RegClass) {
523  if (SrcReg == AMDGPU::SCC) {
524  BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
525  .addImm(-1)
526  .addImm(0);
527  return;
528  }
529 
530  if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
531  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
532  return;
533  }
534 
535  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
536  .addReg(SrcReg, getKillRegState(KillSrc));
537  return;
538  }
539 
540  if (RC == &AMDGPU::SReg_64RegClass) {
541  if (DestReg == AMDGPU::VCC) {
542  if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
543  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
544  .addReg(SrcReg, getKillRegState(KillSrc));
545  } else {
546  // FIXME: Hack until VReg_1 removed.
547  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
548  BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
549  .addImm(0)
550  .addReg(SrcReg, getKillRegState(KillSrc));
551  }
552 
553  return;
554  }
555 
556  if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
557  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
558  return;
559  }
560 
561  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
562  .addReg(SrcReg, getKillRegState(KillSrc));
563  return;
564  }
565 
566  if (DestReg == AMDGPU::SCC) {
567  assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
568  BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
569  .addReg(SrcReg, getKillRegState(KillSrc))
570  .addImm(0);
571  return;
572  }
573 
574  unsigned EltSize = 4;
575  unsigned Opcode = AMDGPU::V_MOV_B32_e32;
576  if (RI.isSGPRClass(RC)) {
577  // TODO: Copy vec3/vec5 with s_mov_b64s then final s_mov_b32.
578  if (!(RI.getRegSizeInBits(*RC) % 64)) {
579  Opcode = AMDGPU::S_MOV_B64;
580  EltSize = 8;
581  } else {
582  Opcode = AMDGPU::S_MOV_B32;
583  EltSize = 4;
584  }
585 
586  if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) {
587  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
588  return;
589  }
590  }
591 
592  ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
593  bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
594 
595  for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
596  unsigned SubIdx;
597  if (Forward)
598  SubIdx = SubIndices[Idx];
599  else
600  SubIdx = SubIndices[SubIndices.size() - Idx - 1];
601 
602  MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
603  get(Opcode), RI.getSubReg(DestReg, SubIdx));
604 
605  Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
606 
607  if (Idx == 0)
608  Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
609 
610  bool UseKill = KillSrc && Idx == SubIndices.size() - 1;
611  Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
612  }
613 }
614 
615 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
616  int NewOpc;
617 
618  // Try to map original to commuted opcode
619  NewOpc = AMDGPU::getCommuteRev(Opcode);
620  if (NewOpc != -1)
621  // Check if the commuted (REV) opcode exists on the target.
622  return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
623 
624  // Try to map commuted to original opcode
625  NewOpc = AMDGPU::getCommuteOrig(Opcode);
626  if (NewOpc != -1)
627  // Check if the original (non-REV) opcode exists on the target.
628  return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
629 
630  return Opcode;
631 }
632 
635  const DebugLoc &DL, unsigned DestReg,
636  int64_t Value) const {
638  const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
639  if (RegClass == &AMDGPU::SReg_32RegClass ||
640  RegClass == &AMDGPU::SGPR_32RegClass ||
641  RegClass == &AMDGPU::SReg_32_XM0RegClass ||
642  RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
643  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
644  .addImm(Value);
645  return;
646  }
647 
648  if (RegClass == &AMDGPU::SReg_64RegClass ||
649  RegClass == &AMDGPU::SGPR_64RegClass ||
650  RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
651  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
652  .addImm(Value);
653  return;
654  }
655 
656  if (RegClass == &AMDGPU::VGPR_32RegClass) {
657  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
658  .addImm(Value);
659  return;
660  }
661  if (RegClass == &AMDGPU::VReg_64RegClass) {
662  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
663  .addImm(Value);
664  return;
665  }
666 
667  unsigned EltSize = 4;
668  unsigned Opcode = AMDGPU::V_MOV_B32_e32;
669  if (RI.isSGPRClass(RegClass)) {
670  if (RI.getRegSizeInBits(*RegClass) > 32) {
671  Opcode = AMDGPU::S_MOV_B64;
672  EltSize = 8;
673  } else {
674  Opcode = AMDGPU::S_MOV_B32;
675  EltSize = 4;
676  }
677  }
678 
679  ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
680  for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
681  int64_t IdxValue = Idx == 0 ? Value : 0;
682 
683  MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
684  get(Opcode), RI.getSubReg(DestReg, Idx));
685  Builder.addImm(IdxValue);
686  }
687 }
688 
689 const TargetRegisterClass *
691  return &AMDGPU::VGPR_32RegClass;
692 }
693 
696  const DebugLoc &DL, unsigned DstReg,
698  unsigned TrueReg,
699  unsigned FalseReg) const {
701  assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
702  "Not a VGPR32 reg");
703 
704  if (Cond.size() == 1) {
705  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
706  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
707  .add(Cond[0]);
708  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
709  .addImm(0)
710  .addReg(FalseReg)
711  .addImm(0)
712  .addReg(TrueReg)
713  .addReg(SReg);
714  } else if (Cond.size() == 2) {
715  assert(Cond[0].isImm() && "Cond[0] is not an immediate");
716  switch (Cond[0].getImm()) {
717  case SIInstrInfo::SCC_TRUE: {
718  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
719  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
720  .addImm(-1)
721  .addImm(0);
722  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
723  .addImm(0)
724  .addReg(FalseReg)
725  .addImm(0)
726  .addReg(TrueReg)
727  .addReg(SReg);
728  break;
729  }
730  case SIInstrInfo::SCC_FALSE: {
731  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
732  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
733  .addImm(0)
734  .addImm(-1);
735  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
736  .addImm(0)
737  .addReg(FalseReg)
738  .addImm(0)
739  .addReg(TrueReg)
740  .addReg(SReg);
741  break;
742  }
743  case SIInstrInfo::VCCNZ: {
744  MachineOperand RegOp = Cond[1];
745  RegOp.setImplicit(false);
746  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
747  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
748  .add(RegOp);
749  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
750  .addImm(0)
751  .addReg(FalseReg)
752  .addImm(0)
753  .addReg(TrueReg)
754  .addReg(SReg);
755  break;
756  }
757  case SIInstrInfo::VCCZ: {
758  MachineOperand RegOp = Cond[1];
759  RegOp.setImplicit(false);
760  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
761  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
762  .add(RegOp);
763  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
764  .addImm(0)
765  .addReg(TrueReg)
766  .addImm(0)
767  .addReg(FalseReg)
768  .addReg(SReg);
769  break;
770  }
771  case SIInstrInfo::EXECNZ: {
772  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
773  unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
774  BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
775  .addImm(0);
776  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
777  .addImm(-1)
778  .addImm(0);
779  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
780  .addImm(0)
781  .addReg(FalseReg)
782  .addImm(0)
783  .addReg(TrueReg)
784  .addReg(SReg);
785  break;
786  }
787  case SIInstrInfo::EXECZ: {
788  unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
789  unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
790  BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
791  .addImm(0);
792  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
793  .addImm(0)
794  .addImm(-1);
795  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
796  .addImm(0)
797  .addReg(FalseReg)
798  .addImm(0)
799  .addReg(TrueReg)
800  .addReg(SReg);
801  llvm_unreachable("Unhandled branch predicate EXECZ");
802  break;
803  }
804  default:
805  llvm_unreachable("invalid branch predicate");
806  }
807  } else {
808  llvm_unreachable("Can only handle Cond size 1 or 2");
809  }
810 }
811 
814  const DebugLoc &DL,
815  unsigned SrcReg, int Value) const {
817  unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
818  BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
819  .addImm(Value)
820  .addReg(SrcReg);
821 
822  return Reg;
823 }
824 
827  const DebugLoc &DL,
828  unsigned SrcReg, int Value) const {
830  unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
831  BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
832  .addImm(Value)
833  .addReg(SrcReg);
834 
835  return Reg;
836 }
837 
838 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
839 
840  if (RI.getRegSizeInBits(*DstRC) == 32) {
841  return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
842  } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
843  return AMDGPU::S_MOV_B64;
844  } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
845  return AMDGPU::V_MOV_B64_PSEUDO;
846  }
847  return AMDGPU::COPY;
848 }
849 
850 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
851  switch (Size) {
852  case 4:
853  return AMDGPU::SI_SPILL_S32_SAVE;
854  case 8:
855  return AMDGPU::SI_SPILL_S64_SAVE;
856  case 12:
857  return AMDGPU::SI_SPILL_S96_SAVE;
858  case 16:
859  return AMDGPU::SI_SPILL_S128_SAVE;
860  case 20:
861  return AMDGPU::SI_SPILL_S160_SAVE;
862  case 32:
863  return AMDGPU::SI_SPILL_S256_SAVE;
864  case 64:
865  return AMDGPU::SI_SPILL_S512_SAVE;
866  default:
867  llvm_unreachable("unknown register size");
868  }
869 }
870 
871 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
872  switch (Size) {
873  case 4:
874  return AMDGPU::SI_SPILL_V32_SAVE;
875  case 8:
876  return AMDGPU::SI_SPILL_V64_SAVE;
877  case 12:
878  return AMDGPU::SI_SPILL_V96_SAVE;
879  case 16:
880  return AMDGPU::SI_SPILL_V128_SAVE;
881  case 20:
882  return AMDGPU::SI_SPILL_V160_SAVE;
883  case 32:
884  return AMDGPU::SI_SPILL_V256_SAVE;
885  case 64:
886  return AMDGPU::SI_SPILL_V512_SAVE;
887  default:
888  llvm_unreachable("unknown register size");
889  }
890 }
891 
894  unsigned SrcReg, bool isKill,
895  int FrameIndex,
896  const TargetRegisterClass *RC,
897  const TargetRegisterInfo *TRI) const {
898  MachineFunction *MF = MBB.getParent();
900  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
901  const DebugLoc &DL = MBB.findDebugLoc(MI);
902 
903  unsigned Size = FrameInfo.getObjectSize(FrameIndex);
904  unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
905  MachinePointerInfo PtrInfo
906  = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
907  MachineMemOperand *MMO
909  Size, Align);
910  unsigned SpillSize = TRI->getSpillSize(*RC);
911 
912  if (RI.isSGPRClass(RC)) {
913  MFI->setHasSpilledSGPRs();
914 
915  // We are only allowed to create one new instruction when spilling
916  // registers, so we need to use pseudo instruction for spilling SGPRs.
917  const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
918 
919  // The SGPR spill/restore instructions only work on number sgprs, so we need
920  // to make sure we are using the correct register class.
921  if (TargetRegisterInfo::isVirtualRegister(SrcReg) && SpillSize == 4) {
923  MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
924  }
925 
926  MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc)
927  .addReg(SrcReg, getKillRegState(isKill)) // data
928  .addFrameIndex(FrameIndex) // addr
929  .addMemOperand(MMO)
931  .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
932  // Add the scratch resource registers as implicit uses because we may end up
933  // needing them, and need to ensure that the reserved registers are
934  // correctly handled.
935 
936  FrameInfo.setStackID(FrameIndex, SIStackID::SGPR_SPILL);
937  if (ST.hasScalarStores()) {
938  // m0 is used for offset to scalar stores if used to spill.
939  Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
940  }
941 
942  return;
943  }
944 
945  assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
946 
947  unsigned Opcode = getVGPRSpillSaveOpcode(SpillSize);
948  MFI->setHasSpilledVGPRs();
949  BuildMI(MBB, MI, DL, get(Opcode))
950  .addReg(SrcReg, getKillRegState(isKill)) // data
951  .addFrameIndex(FrameIndex) // addr
952  .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
953  .addReg(MFI->getFrameOffsetReg()) // scratch_offset
954  .addImm(0) // offset
955  .addMemOperand(MMO);
956 }
957 
958 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
959  switch (Size) {
960  case 4:
961  return AMDGPU::SI_SPILL_S32_RESTORE;
962  case 8:
963  return AMDGPU::SI_SPILL_S64_RESTORE;
964  case 12:
965  return AMDGPU::SI_SPILL_S96_RESTORE;
966  case 16:
967  return AMDGPU::SI_SPILL_S128_RESTORE;
968  case 20:
969  return AMDGPU::SI_SPILL_S160_RESTORE;
970  case 32:
971  return AMDGPU::SI_SPILL_S256_RESTORE;
972  case 64:
973  return AMDGPU::SI_SPILL_S512_RESTORE;
974  default:
975  llvm_unreachable("unknown register size");
976  }
977 }
978 
979 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
980  switch (Size) {
981  case 4:
982  return AMDGPU::SI_SPILL_V32_RESTORE;
983  case 8:
984  return AMDGPU::SI_SPILL_V64_RESTORE;
985  case 12:
986  return AMDGPU::SI_SPILL_V96_RESTORE;
987  case 16:
988  return AMDGPU::SI_SPILL_V128_RESTORE;
989  case 20:
990  return AMDGPU::SI_SPILL_V160_RESTORE;
991  case 32:
992  return AMDGPU::SI_SPILL_V256_RESTORE;
993  case 64:
994  return AMDGPU::SI_SPILL_V512_RESTORE;
995  default:
996  llvm_unreachable("unknown register size");
997  }
998 }
999 
1002  unsigned DestReg, int FrameIndex,
1003  const TargetRegisterClass *RC,
1004  const TargetRegisterInfo *TRI) const {
1005  MachineFunction *MF = MBB.getParent();
1007  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1008  const DebugLoc &DL = MBB.findDebugLoc(MI);
1009  unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
1010  unsigned Size = FrameInfo.getObjectSize(FrameIndex);
1011  unsigned SpillSize = TRI->getSpillSize(*RC);
1012 
1013  MachinePointerInfo PtrInfo
1014  = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1015 
1017  PtrInfo, MachineMemOperand::MOLoad, Size, Align);
1018 
1019  if (RI.isSGPRClass(RC)) {
1020  MFI->setHasSpilledSGPRs();
1021 
1022  // FIXME: Maybe this should not include a memoperand because it will be
1023  // lowered to non-memory instructions.
1024  const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1025  if (TargetRegisterInfo::isVirtualRegister(DestReg) && SpillSize == 4) {
1027  MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
1028  }
1029 
1030  FrameInfo.setStackID(FrameIndex, SIStackID::SGPR_SPILL);
1031  MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc, DestReg)
1032  .addFrameIndex(FrameIndex) // addr
1033  .addMemOperand(MMO)
1035  .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
1036 
1037  if (ST.hasScalarStores()) {
1038  // m0 is used for offset to scalar stores if used to spill.
1039  Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
1040  }
1041 
1042  return;
1043  }
1044 
1045  assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
1046 
1047  unsigned Opcode = getVGPRSpillRestoreOpcode(SpillSize);
1048  BuildMI(MBB, MI, DL, get(Opcode), DestReg)
1049  .addFrameIndex(FrameIndex) // vaddr
1050  .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
1051  .addReg(MFI->getFrameOffsetReg()) // scratch_offset
1052  .addImm(0) // offset
1053  .addMemOperand(MMO);
1054 }
1055 
1056 /// \param @Offset Offset in bytes of the FrameIndex being spilled
1058  MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg,
1059  unsigned FrameOffset, unsigned Size) const {
1060  MachineFunction *MF = MBB.getParent();
1062  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
1063  const DebugLoc &DL = MBB.findDebugLoc(MI);
1064  unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize();
1065  unsigned WavefrontSize = ST.getWavefrontSize();
1066 
1067  unsigned TIDReg = MFI->getTIDReg();
1068  if (!MFI->hasCalculatedTID()) {
1069  MachineBasicBlock &Entry = MBB.getParent()->front();
1070  MachineBasicBlock::iterator Insert = Entry.front();
1071  const DebugLoc &DL = Insert->getDebugLoc();
1072 
1073  TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
1074  *MF);
1075  if (TIDReg == AMDGPU::NoRegister)
1076  return TIDReg;
1077 
1079  WorkGroupSize > WavefrontSize) {
1080  unsigned TIDIGXReg
1082  unsigned TIDIGYReg
1084  unsigned TIDIGZReg
1086  unsigned InputPtrReg =
1088  for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
1089  if (!Entry.isLiveIn(Reg))
1090  Entry.addLiveIn(Reg);
1091  }
1092 
1093  RS->enterBasicBlock(Entry);
1094  // FIXME: Can we scavenge an SReg_64 and access the subregs?
1095  unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1096  unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1097  BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
1098  .addReg(InputPtrReg)
1100  BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
1101  .addReg(InputPtrReg)
1103 
1104  // NGROUPS.X * NGROUPS.Y
1105  BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
1106  .addReg(STmp1)
1107  .addReg(STmp0);
1108  // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
1109  BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
1110  .addReg(STmp1)
1111  .addReg(TIDIGXReg);
1112  // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
1113  BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
1114  .addReg(STmp0)
1115  .addReg(TIDIGYReg)
1116  .addReg(TIDReg);
1117  // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
1118  getAddNoCarry(Entry, Insert, DL, TIDReg)
1119  .addReg(TIDReg)
1120  .addReg(TIDIGZReg)
1121  .addImm(0); // clamp bit
1122  } else {
1123  // Get the wave id
1124  BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
1125  TIDReg)
1126  .addImm(-1)
1127  .addImm(0);
1128 
1129  BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
1130  TIDReg)
1131  .addImm(-1)
1132  .addReg(TIDReg);
1133  }
1134 
1135  BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
1136  TIDReg)
1137  .addImm(2)
1138  .addReg(TIDReg);
1139  MFI->setTIDReg(TIDReg);
1140  }
1141 
1142  // Add FrameIndex to LDS offset
1143  unsigned LDSOffset = MFI->getLDSSize() + (FrameOffset * WorkGroupSize);
1144  getAddNoCarry(MBB, MI, DL, TmpReg)
1145  .addImm(LDSOffset)
1146  .addReg(TIDReg)
1147  .addImm(0); // clamp bit
1148 
1149  return TmpReg;
1150 }
1151 
1154  int Count) const {
1155  DebugLoc DL = MBB.findDebugLoc(MI);
1156  while (Count > 0) {
1157  int Arg;
1158  if (Count >= 8)
1159  Arg = 7;
1160  else
1161  Arg = Count - 1;
1162  Count -= 8;
1163  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
1164  .addImm(Arg);
1165  }
1166 }
1167 
1170  insertWaitStates(MBB, MI, 1);
1171 }
1172 
1174  auto MF = MBB.getParent();
1176 
1177  assert(Info->isEntryFunction());
1178 
1179  if (MBB.succ_empty()) {
1180  bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
1181  if (HasNoTerminator) {
1182  if (Info->returnsVoid()) {
1183  BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1184  } else {
1185  BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
1186  }
1187  }
1188  }
1189 }
1190 
1192  switch (MI.getOpcode()) {
1193  default: return 1; // FIXME: Do wait states equal cycles?
1194 
1195  case AMDGPU::S_NOP:
1196  return MI.getOperand(0).getImm() + 1;
1197  }
1198 }
1199 
1201  MachineBasicBlock &MBB = *MI.getParent();
1202  DebugLoc DL = MBB.findDebugLoc(MI);
1203  switch (MI.getOpcode()) {
1204  default: return TargetInstrInfo::expandPostRAPseudo(MI);
1205  case AMDGPU::S_MOV_B64_term:
1206  // This is only a terminator to get the correct spill code placement during
1207  // register allocation.
1208  MI.setDesc(get(AMDGPU::S_MOV_B64));
1209  break;
1210 
1211  case AMDGPU::S_XOR_B64_term:
1212  // This is only a terminator to get the correct spill code placement during
1213  // register allocation.
1214  MI.setDesc(get(AMDGPU::S_XOR_B64));
1215  break;
1216 
1217  case AMDGPU::S_ANDN2_B64_term:
1218  // This is only a terminator to get the correct spill code placement during
1219  // register allocation.
1220  MI.setDesc(get(AMDGPU::S_ANDN2_B64));
1221  break;
1222 
1223  case AMDGPU::V_MOV_B64_PSEUDO: {
1224  unsigned Dst = MI.getOperand(0).getReg();
1225  unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1226  unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1227 
1228  const MachineOperand &SrcOp = MI.getOperand(1);
1229  // FIXME: Will this work for 64-bit floating point immediates?
1230  assert(!SrcOp.isFPImm());
1231  if (SrcOp.isImm()) {
1232  APInt Imm(64, SrcOp.getImm());
1233  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1234  .addImm(Imm.getLoBits(32).getZExtValue())
1235  .addReg(Dst, RegState::Implicit | RegState::Define);
1236  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1237  .addImm(Imm.getHiBits(32).getZExtValue())
1238  .addReg(Dst, RegState::Implicit | RegState::Define);
1239  } else {
1240  assert(SrcOp.isReg());
1241  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1242  .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1244  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1245  .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1247  }
1248  MI.eraseFromParent();
1249  break;
1250  }
1251  case AMDGPU::V_SET_INACTIVE_B32: {
1252  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1253  .addReg(AMDGPU::EXEC);
1254  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1255  .add(MI.getOperand(2));
1256  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1257  .addReg(AMDGPU::EXEC);
1258  MI.eraseFromParent();
1259  break;
1260  }
1261  case AMDGPU::V_SET_INACTIVE_B64: {
1262  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1263  .addReg(AMDGPU::EXEC);
1264  MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1265  MI.getOperand(0).getReg())
1266  .add(MI.getOperand(2));
1267  expandPostRAPseudo(*Copy);
1268  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1269  .addReg(AMDGPU::EXEC);
1270  MI.eraseFromParent();
1271  break;
1272  }
1273  case AMDGPU::V_MOVRELD_B32_V1:
1274  case AMDGPU::V_MOVRELD_B32_V2:
1275  case AMDGPU::V_MOVRELD_B32_V4:
1276  case AMDGPU::V_MOVRELD_B32_V8:
1277  case AMDGPU::V_MOVRELD_B32_V16: {
1278  const MCInstrDesc &MovRelDesc = get(AMDGPU::V_MOVRELD_B32_e32);
1279  unsigned VecReg = MI.getOperand(0).getReg();
1280  bool IsUndef = MI.getOperand(1).isUndef();
1281  unsigned SubReg = AMDGPU::sub0 + MI.getOperand(3).getImm();
1282  assert(VecReg == MI.getOperand(1).getReg());
1283 
1284  MachineInstr *MovRel =
1285  BuildMI(MBB, MI, DL, MovRelDesc)
1286  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1287  .add(MI.getOperand(2))
1288  .addReg(VecReg, RegState::ImplicitDefine)
1289  .addReg(VecReg,
1290  RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1291 
1292  const int ImpDefIdx =
1293  MovRelDesc.getNumOperands() + MovRelDesc.getNumImplicitUses();
1294  const int ImpUseIdx = ImpDefIdx + 1;
1295  MovRel->tieOperands(ImpDefIdx, ImpUseIdx);
1296 
1297  MI.eraseFromParent();
1298  break;
1299  }
1300  case AMDGPU::SI_PC_ADD_REL_OFFSET: {
1301  MachineFunction &MF = *MBB.getParent();
1302  unsigned Reg = MI.getOperand(0).getReg();
1303  unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1304  unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
1305 
1306  // Create a bundle so these instructions won't be re-ordered by the
1307  // post-RA scheduler.
1308  MIBundleBuilder Bundler(MBB, MI);
1309  Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
1310 
1311  // Add 32-bit offset from this instruction to the start of the
1312  // constant data.
1313  Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1314  .addReg(RegLo)
1315  .add(MI.getOperand(1)));
1316 
1317  MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1318  .addReg(RegHi);
1320  MIB.addImm(0);
1321  else
1322  MIB.add(MI.getOperand(2));
1323 
1324  Bundler.append(MIB);
1325  finalizeBundle(MBB, Bundler.begin());
1326 
1327  MI.eraseFromParent();
1328  break;
1329  }
1330  case AMDGPU::ENTER_WWM: {
1331  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1332  // WWM is entered.
1333  MI.setDesc(get(AMDGPU::S_OR_SAVEEXEC_B64));
1334  break;
1335  }
1336  case AMDGPU::EXIT_WWM: {
1337  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1338  // WWM is exited.
1339  MI.setDesc(get(AMDGPU::S_MOV_B64));
1340  break;
1341  }
1342  case TargetOpcode::BUNDLE: {
1343  if (!MI.mayLoad())
1344  return false;
1345 
1346  // If it is a load it must be a memory clause
1348  I->isBundledWithSucc(); ++I) {
1349  I->unbundleFromSucc();
1350  for (MachineOperand &MO : I->operands())
1351  if (MO.isReg())
1352  MO.setIsInternalRead(false);
1353  }
1354 
1355  MI.eraseFromParent();
1356  break;
1357  }
1358  }
1359  return true;
1360 }
1361 
1363  MachineOperand &Src0,
1364  unsigned Src0OpName,
1365  MachineOperand &Src1,
1366  unsigned Src1OpName) const {
1367  MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
1368  if (!Src0Mods)
1369  return false;
1370 
1371  MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
1372  assert(Src1Mods &&
1373  "All commutable instructions have both src0 and src1 modifiers");
1374 
1375  int Src0ModsVal = Src0Mods->getImm();
1376  int Src1ModsVal = Src1Mods->getImm();
1377 
1378  Src1Mods->setImm(Src0ModsVal);
1379  Src0Mods->setImm(Src1ModsVal);
1380  return true;
1381 }
1382 
1384  MachineOperand &RegOp,
1385  MachineOperand &NonRegOp) {
1386  unsigned Reg = RegOp.getReg();
1387  unsigned SubReg = RegOp.getSubReg();
1388  bool IsKill = RegOp.isKill();
1389  bool IsDead = RegOp.isDead();
1390  bool IsUndef = RegOp.isUndef();
1391  bool IsDebug = RegOp.isDebug();
1392 
1393  if (NonRegOp.isImm())
1394  RegOp.ChangeToImmediate(NonRegOp.getImm());
1395  else if (NonRegOp.isFI())
1396  RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
1397  else
1398  return nullptr;
1399 
1400  NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
1401  NonRegOp.setSubReg(SubReg);
1402 
1403  return &MI;
1404 }
1405 
1407  unsigned Src0Idx,
1408  unsigned Src1Idx) const {
1409  assert(!NewMI && "this should never be used");
1410 
1411  unsigned Opc = MI.getOpcode();
1412  int CommutedOpcode = commuteOpcode(Opc);
1413  if (CommutedOpcode == -1)
1414  return nullptr;
1415 
1416  assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
1417  static_cast<int>(Src0Idx) &&
1418  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
1419  static_cast<int>(Src1Idx) &&
1420  "inconsistency with findCommutedOpIndices");
1421 
1422  MachineOperand &Src0 = MI.getOperand(Src0Idx);
1423  MachineOperand &Src1 = MI.getOperand(Src1Idx);
1424 
1425  MachineInstr *CommutedMI = nullptr;
1426  if (Src0.isReg() && Src1.isReg()) {
1427  if (isOperandLegal(MI, Src1Idx, &Src0)) {
1428  // Be sure to copy the source modifiers to the right place.
1429  CommutedMI
1430  = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
1431  }
1432 
1433  } else if (Src0.isReg() && !Src1.isReg()) {
1434  // src0 should always be able to support any operand type, so no need to
1435  // check operand legality.
1436  CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1437  } else if (!Src0.isReg() && Src1.isReg()) {
1438  if (isOperandLegal(MI, Src1Idx, &Src0))
1439  CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1440  } else {
1441  // FIXME: Found two non registers to commute. This does happen.
1442  return nullptr;
1443  }
1444 
1445  if (CommutedMI) {
1446  swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
1447  Src1, AMDGPU::OpName::src1_modifiers);
1448 
1449  CommutedMI->setDesc(get(CommutedOpcode));
1450  }
1451 
1452  return CommutedMI;
1453 }
1454 
1455 // This needs to be implemented because the source modifiers may be inserted
1456 // between the true commutable operands, and the base
1457 // TargetInstrInfo::commuteInstruction uses it.
1459  unsigned &SrcOpIdx1) const {
1460  return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
1461 }
1462 
1463 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
1464  unsigned &SrcOpIdx1) const {
1465  if (!Desc.isCommutable())
1466  return false;
1467 
1468  unsigned Opc = Desc.getOpcode();
1469  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1470  if (Src0Idx == -1)
1471  return false;
1472 
1473  int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1474  if (Src1Idx == -1)
1475  return false;
1476 
1477  return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
1478 }
1479 
1480 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
1481  int64_t BrOffset) const {
1482  // BranchRelaxation should never have to check s_setpc_b64 because its dest
1483  // block is unanalyzable.
1484  assert(BranchOp != AMDGPU::S_SETPC_B64);
1485 
1486  // Convert to dwords.
1487  BrOffset /= 4;
1488 
1489  // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
1490  // from the next instruction.
1491  BrOffset -= 1;
1492 
1493  return isIntN(BranchOffsetBits, BrOffset);
1494 }
1495 
1497  const MachineInstr &MI) const {
1498  if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
1499  // This would be a difficult analysis to perform, but can always be legal so
1500  // there's no need to analyze it.
1501  return nullptr;
1502  }
1503 
1504  return MI.getOperand(0).getMBB();
1505 }
1506 
1508  MachineBasicBlock &DestBB,
1509  const DebugLoc &DL,
1510  int64_t BrOffset,
1511  RegScavenger *RS) const {
1512  assert(RS && "RegScavenger required for long branching");
1513  assert(MBB.empty() &&
1514  "new block should be inserted for expanding unconditional branch");
1515  assert(MBB.pred_size() == 1);
1516 
1517  MachineFunction *MF = MBB.getParent();
1518  MachineRegisterInfo &MRI = MF->getRegInfo();
1519 
1520  // FIXME: Virtual register workaround for RegScavenger not working with empty
1521  // blocks.
1522  unsigned PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1523 
1524  auto I = MBB.end();
1525 
1526  // We need to compute the offset relative to the instruction immediately after
1527  // s_getpc_b64. Insert pc arithmetic code before last terminator.
1528  MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
1529 
1530  // TODO: Handle > 32-bit block address.
1531  if (BrOffset >= 0) {
1532  BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
1533  .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1534  .addReg(PCReg, 0, AMDGPU::sub0)
1536  BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
1537  .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1538  .addReg(PCReg, 0, AMDGPU::sub1)
1539  .addImm(0);
1540  } else {
1541  // Backwards branch.
1542  BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
1543  .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1544  .addReg(PCReg, 0, AMDGPU::sub0)
1546  BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
1547  .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1548  .addReg(PCReg, 0, AMDGPU::sub1)
1549  .addImm(0);
1550  }
1551 
1552  // Insert the indirect branch after the other terminator.
1553  BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
1554  .addReg(PCReg);
1555 
1556  // FIXME: If spilling is necessary, this will fail because this scavenger has
1557  // no emergency stack slots. It is non-trivial to spill in this situation,
1558  // because the restore code needs to be specially placed after the
1559  // jump. BranchRelaxation then needs to be made aware of the newly inserted
1560  // block.
1561  //
1562  // If a spill is needed for the pc register pair, we need to insert a spill
1563  // restore block right before the destination block, and insert a short branch
1564  // into the old destination block's fallthrough predecessor.
1565  // e.g.:
1566  //
1567  // s_cbranch_scc0 skip_long_branch:
1568  //
1569  // long_branch_bb:
1570  // spill s[8:9]
1571  // s_getpc_b64 s[8:9]
1572  // s_add_u32 s8, s8, restore_bb
1573  // s_addc_u32 s9, s9, 0
1574  // s_setpc_b64 s[8:9]
1575  //
1576  // skip_long_branch:
1577  // foo;
1578  //
1579  // .....
1580  //
1581  // dest_bb_fallthrough_predecessor:
1582  // bar;
1583  // s_branch dest_bb
1584  //
1585  // restore_bb:
1586  // restore s[8:9]
1587  // fallthrough dest_bb
1588  ///
1589  // dest_bb:
1590  // buzz;
1591 
1592  RS->enterBasicBlockEnd(MBB);
1593  unsigned Scav = RS->scavengeRegisterBackwards(
1594  AMDGPU::SReg_64RegClass,
1595  MachineBasicBlock::iterator(GetPC), false, 0);
1596  MRI.replaceRegWith(PCReg, Scav);
1597  MRI.clearVirtRegs();
1598  RS->setRegUsed(Scav);
1599 
1600  return 4 + 8 + 4 + 4;
1601 }
1602 
1603 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
1604  switch (Cond) {
1605  case SIInstrInfo::SCC_TRUE:
1606  return AMDGPU::S_CBRANCH_SCC1;
1607  case SIInstrInfo::SCC_FALSE:
1608  return AMDGPU::S_CBRANCH_SCC0;
1609  case SIInstrInfo::VCCNZ:
1610  return AMDGPU::S_CBRANCH_VCCNZ;
1611  case SIInstrInfo::VCCZ:
1612  return AMDGPU::S_CBRANCH_VCCZ;
1613  case SIInstrInfo::EXECNZ:
1614  return AMDGPU::S_CBRANCH_EXECNZ;
1615  case SIInstrInfo::EXECZ:
1616  return AMDGPU::S_CBRANCH_EXECZ;
1617  default:
1618  llvm_unreachable("invalid branch predicate");
1619  }
1620 }
1621 
1622 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
1623  switch (Opcode) {
1624  case AMDGPU::S_CBRANCH_SCC0:
1625  return SCC_FALSE;
1626  case AMDGPU::S_CBRANCH_SCC1:
1627  return SCC_TRUE;
1628  case AMDGPU::S_CBRANCH_VCCNZ:
1629  return VCCNZ;
1630  case AMDGPU::S_CBRANCH_VCCZ:
1631  return VCCZ;
1632  case AMDGPU::S_CBRANCH_EXECNZ:
1633  return EXECNZ;
1634  case AMDGPU::S_CBRANCH_EXECZ:
1635  return EXECZ;
1636  default:
1637  return INVALID_BR;
1638  }
1639 }
1640 
1643  MachineBasicBlock *&TBB,
1644  MachineBasicBlock *&FBB,
1646  bool AllowModify) const {
1647  if (I->getOpcode() == AMDGPU::S_BRANCH) {
1648  // Unconditional Branch
1649  TBB = I->getOperand(0).getMBB();
1650  return false;
1651  }
1652 
1653  MachineBasicBlock *CondBB = nullptr;
1654 
1655  if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
1656  CondBB = I->getOperand(1).getMBB();
1657  Cond.push_back(I->getOperand(0));
1658  } else {
1659  BranchPredicate Pred = getBranchPredicate(I->getOpcode());
1660  if (Pred == INVALID_BR)
1661  return true;
1662 
1663  CondBB = I->getOperand(0).getMBB();
1665  Cond.push_back(I->getOperand(1)); // Save the branch register.
1666  }
1667  ++I;
1668 
1669  if (I == MBB.end()) {
1670  // Conditional branch followed by fall-through.
1671  TBB = CondBB;
1672  return false;
1673  }
1674 
1675  if (I->getOpcode() == AMDGPU::S_BRANCH) {
1676  TBB = CondBB;
1677  FBB = I->getOperand(0).getMBB();
1678  return false;
1679  }
1680 
1681  return true;
1682 }
1683 
1685  MachineBasicBlock *&FBB,
1687  bool AllowModify) const {
1689  auto E = MBB.end();
1690  if (I == E)
1691  return false;
1692 
1693  // Skip over the instructions that are artificially terminators for special
1694  // exec management.
1695  while (I != E && !I->isBranch() && !I->isReturn() &&
1696  I->getOpcode() != AMDGPU::SI_MASK_BRANCH) {
1697  switch (I->getOpcode()) {
1698  case AMDGPU::SI_MASK_BRANCH:
1699  case AMDGPU::S_MOV_B64_term:
1700  case AMDGPU::S_XOR_B64_term:
1701  case AMDGPU::S_ANDN2_B64_term:
1702  break;
1703  case AMDGPU::SI_IF:
1704  case AMDGPU::SI_ELSE:
1705  case AMDGPU::SI_KILL_I1_TERMINATOR:
1706  case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
1707  // FIXME: It's messy that these need to be considered here at all.
1708  return true;
1709  default:
1710  llvm_unreachable("unexpected non-branch terminator inst");
1711  }
1712 
1713  ++I;
1714  }
1715 
1716  if (I == E)
1717  return false;
1718 
1719  if (I->getOpcode() != AMDGPU::SI_MASK_BRANCH)
1720  return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
1721 
1722  ++I;
1723 
1724  // TODO: Should be able to treat as fallthrough?
1725  if (I == MBB.end())
1726  return true;
1727 
1728  if (analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify))
1729  return true;
1730 
1731  MachineBasicBlock *MaskBrDest = I->getOperand(0).getMBB();
1732 
1733  // Specifically handle the case where the conditional branch is to the same
1734  // destination as the mask branch. e.g.
1735  //
1736  // si_mask_branch BB8
1737  // s_cbranch_execz BB8
1738  // s_cbranch BB9
1739  //
1740  // This is required to understand divergent loops which may need the branches
1741  // to be relaxed.
1742  if (TBB != MaskBrDest || Cond.empty())
1743  return true;
1744 
1745  auto Pred = Cond[0].getImm();
1746  return (Pred != EXECZ && Pred != EXECNZ);
1747 }
1748 
1750  int *BytesRemoved) const {
1752 
1753  unsigned Count = 0;
1754  unsigned RemovedSize = 0;
1755  while (I != MBB.end()) {
1756  MachineBasicBlock::iterator Next = std::next(I);
1757  if (I->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
1758  I = Next;
1759  continue;
1760  }
1761 
1762  RemovedSize += getInstSizeInBytes(*I);
1763  I->eraseFromParent();
1764  ++Count;
1765  I = Next;
1766  }
1767 
1768  if (BytesRemoved)
1769  *BytesRemoved = RemovedSize;
1770 
1771  return Count;
1772 }
1773 
1774 // Copy the flags onto the implicit condition register operand.
1776  const MachineOperand &OrigCond) {
1777  CondReg.setIsUndef(OrigCond.isUndef());
1778  CondReg.setIsKill(OrigCond.isKill());
1779 }
1780 
1782  MachineBasicBlock *TBB,
1783  MachineBasicBlock *FBB,
1785  const DebugLoc &DL,
1786  int *BytesAdded) const {
1787  if (!FBB && Cond.empty()) {
1788  BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
1789  .addMBB(TBB);
1790  if (BytesAdded)
1791  *BytesAdded = 4;
1792  return 1;
1793  }
1794 
1795  if(Cond.size() == 1 && Cond[0].isReg()) {
1796  BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
1797  .add(Cond[0])
1798  .addMBB(TBB);
1799  return 1;
1800  }
1801 
1802  assert(TBB && Cond[0].isImm());
1803 
1804  unsigned Opcode
1805  = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
1806 
1807  if (!FBB) {
1808  Cond[1].isUndef();
1809  MachineInstr *CondBr =
1810  BuildMI(&MBB, DL, get(Opcode))
1811  .addMBB(TBB);
1812 
1813  // Copy the flags onto the implicit condition register operand.
1814  preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
1815 
1816  if (BytesAdded)
1817  *BytesAdded = 4;
1818  return 1;
1819  }
1820 
1821  assert(TBB && FBB);
1822 
1823  MachineInstr *CondBr =
1824  BuildMI(&MBB, DL, get(Opcode))
1825  .addMBB(TBB);
1826  BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
1827  .addMBB(FBB);
1828 
1829  MachineOperand &CondReg = CondBr->getOperand(1);
1830  CondReg.setIsUndef(Cond[1].isUndef());
1831  CondReg.setIsKill(Cond[1].isKill());
1832 
1833  if (BytesAdded)
1834  *BytesAdded = 8;
1835 
1836  return 2;
1837 }
1838 
1840  SmallVectorImpl<MachineOperand> &Cond) const {
1841  if (Cond.size() != 2) {
1842  return true;
1843  }
1844 
1845  if (Cond[0].isImm()) {
1846  Cond[0].setImm(-Cond[0].getImm());
1847  return false;
1848  }
1849 
1850  return true;
1851 }
1852 
1855  unsigned TrueReg, unsigned FalseReg,
1856  int &CondCycles,
1857  int &TrueCycles, int &FalseCycles) const {
1858  switch (Cond[0].getImm()) {
1859  case VCCNZ:
1860  case VCCZ: {
1861  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1862  const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
1863  assert(MRI.getRegClass(FalseReg) == RC);
1864 
1865  int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
1866  CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
1867 
1868  // Limit to equal cost for branch vs. N v_cndmask_b32s.
1869  return !RI.isSGPRClass(RC) && NumInsts <= 6;
1870  }
1871  case SCC_TRUE:
1872  case SCC_FALSE: {
1873  // FIXME: We could insert for VGPRs if we could replace the original compare
1874  // with a vector one.
1875  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1876  const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
1877  assert(MRI.getRegClass(FalseReg) == RC);
1878 
1879  int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
1880 
1881  // Multiples of 8 can do s_cselect_b64
1882  if (NumInsts % 2 == 0)
1883  NumInsts /= 2;
1884 
1885  CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
1886  return RI.isSGPRClass(RC);
1887  }
1888  default:
1889  return false;
1890  }
1891 }
1892 
1895  unsigned DstReg, ArrayRef<MachineOperand> Cond,
1896  unsigned TrueReg, unsigned FalseReg) const {
1897  BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
1898  if (Pred == VCCZ || Pred == SCC_FALSE) {
1899  Pred = static_cast<BranchPredicate>(-Pred);
1900  std::swap(TrueReg, FalseReg);
1901  }
1902 
1904  const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
1905  unsigned DstSize = RI.getRegSizeInBits(*DstRC);
1906 
1907  if (DstSize == 32) {
1908  unsigned SelOp = Pred == SCC_TRUE ?
1909  AMDGPU::S_CSELECT_B32 : AMDGPU::V_CNDMASK_B32_e32;
1910 
1911  // Instruction's operands are backwards from what is expected.
1912  MachineInstr *Select =
1913  BuildMI(MBB, I, DL, get(SelOp), DstReg)
1914  .addReg(FalseReg)
1915  .addReg(TrueReg);
1916 
1917  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
1918  return;
1919  }
1920 
1921  if (DstSize == 64 && Pred == SCC_TRUE) {
1922  MachineInstr *Select =
1923  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
1924  .addReg(FalseReg)
1925  .addReg(TrueReg);
1926 
1927  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
1928  return;
1929  }
1930 
1931  static const int16_t Sub0_15[] = {
1932  AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
1933  AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
1934  AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
1935  AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
1936  };
1937 
1938  static const int16_t Sub0_15_64[] = {
1939  AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
1940  AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
1941  AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
1942  AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
1943  };
1944 
1945  unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
1946  const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
1947  const int16_t *SubIndices = Sub0_15;
1948  int NElts = DstSize / 32;
1949 
1950  // 64-bit select is only available for SALU.
1951  // TODO: Split 96-bit into 64-bit and 32-bit, not 3x 32-bit.
1952  if (Pred == SCC_TRUE) {
1953  if (NElts % 2) {
1954  SelOp = AMDGPU::S_CSELECT_B32;
1955  EltRC = &AMDGPU::SGPR_32RegClass;
1956  } else {
1957  SelOp = AMDGPU::S_CSELECT_B64;
1958  EltRC = &AMDGPU::SGPR_64RegClass;
1959  SubIndices = Sub0_15_64;
1960  NElts /= 2;
1961  }
1962  }
1963 
1965  MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
1966 
1967  I = MIB->getIterator();
1968 
1970  for (int Idx = 0; Idx != NElts; ++Idx) {
1971  unsigned DstElt = MRI.createVirtualRegister(EltRC);
1972  Regs.push_back(DstElt);
1973 
1974  unsigned SubIdx = SubIndices[Idx];
1975 
1976  MachineInstr *Select =
1977  BuildMI(MBB, I, DL, get(SelOp), DstElt)
1978  .addReg(FalseReg, 0, SubIdx)
1979  .addReg(TrueReg, 0, SubIdx);
1980  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
1981 
1982  MIB.addReg(DstElt)
1983  .addImm(SubIdx);
1984  }
1985 }
1986 
1988  switch (MI.getOpcode()) {
1989  case AMDGPU::V_MOV_B32_e32:
1990  case AMDGPU::V_MOV_B32_e64:
1991  case AMDGPU::V_MOV_B64_PSEUDO: {
1992  // If there are additional implicit register operands, this may be used for
1993  // register indexing so the source register operand isn't simply copied.
1994  unsigned NumOps = MI.getDesc().getNumOperands() +
1995  MI.getDesc().getNumImplicitUses();
1996 
1997  return MI.getNumOperands() == NumOps;
1998  }
1999  case AMDGPU::S_MOV_B32:
2000  case AMDGPU::S_MOV_B64:
2001  case AMDGPU::COPY:
2002  return true;
2003  default:
2004  return false;
2005  }
2006 }
2007 
2009  unsigned Kind) const {
2010  switch(Kind) {
2021  }
2022  return AMDGPUAS::FLAT_ADDRESS;
2023 }
2024 
2026  unsigned Opc = MI.getOpcode();
2027  int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2028  AMDGPU::OpName::src0_modifiers);
2029  int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2030  AMDGPU::OpName::src1_modifiers);
2031  int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2032  AMDGPU::OpName::src2_modifiers);
2033 
2034  MI.RemoveOperand(Src2ModIdx);
2035  MI.RemoveOperand(Src1ModIdx);
2036  MI.RemoveOperand(Src0ModIdx);
2037 }
2038 
2040  unsigned Reg, MachineRegisterInfo *MRI) const {
2041  if (!MRI->hasOneNonDBGUse(Reg))
2042  return false;
2043 
2044  switch (DefMI.getOpcode()) {
2045  default:
2046  return false;
2047  case AMDGPU::S_MOV_B64:
2048  // TODO: We could fold 64-bit immediates, but this get compilicated
2049  // when there are sub-registers.
2050  return false;
2051 
2052  case AMDGPU::V_MOV_B32_e32:
2053  case AMDGPU::S_MOV_B32:
2054  break;
2055  }
2056 
2057  const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
2058  assert(ImmOp);
2059  // FIXME: We could handle FrameIndex values here.
2060  if (!ImmOp->isImm())
2061  return false;
2062 
2063  unsigned Opc = UseMI.getOpcode();
2064  if (Opc == AMDGPU::COPY) {
2065  bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
2066  unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2067  UseMI.setDesc(get(NewOpc));
2068  UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
2069  UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
2070  return true;
2071  }
2072 
2073  if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
2074  Opc == AMDGPU::V_MAD_F16 || Opc == AMDGPU::V_MAC_F16_e64 ||
2075  Opc == AMDGPU::V_FMA_F32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2076  Opc == AMDGPU::V_FMA_F16 || Opc == AMDGPU::V_FMAC_F16_e64) {
2077  // Don't fold if we are using source or output modifiers. The new VOP2
2078  // instructions don't have them.
2079  if (hasAnyModifiersSet(UseMI))
2080  return false;
2081 
2082  // If this is a free constant, there's no reason to do this.
2083  // TODO: We could fold this here instead of letting SIFoldOperands do it
2084  // later.
2085  MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2086 
2087  // Any src operand can be used for the legality check.
2088  if (isInlineConstant(UseMI, *Src0, *ImmOp))
2089  return false;
2090 
2091  bool IsF32 = Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
2092  Opc == AMDGPU::V_FMA_F32 || Opc == AMDGPU::V_FMAC_F32_e64;
2093  bool IsFMA = Opc == AMDGPU::V_FMA_F32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2094  Opc == AMDGPU::V_FMA_F16 || Opc == AMDGPU::V_FMAC_F16_e64;
2095  MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
2096  MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
2097 
2098  // Multiplied part is the constant: Use v_madmk_{f16, f32}.
2099  // We should only expect these to be on src0 due to canonicalizations.
2100  if (Src0->isReg() && Src0->getReg() == Reg) {
2101  if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2102  return false;
2103 
2104  if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2105  return false;
2106 
2107  unsigned NewOpc =
2108  IsFMA ? (IsF32 ? AMDGPU::V_FMAMK_F32 : AMDGPU::V_FMAMK_F16)
2109  : (IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16);
2110  if (pseudoToMCOpcode(NewOpc) == -1)
2111  return false;
2112 
2113  // We need to swap operands 0 and 1 since madmk constant is at operand 1.
2114 
2115  const int64_t Imm = ImmOp->getImm();
2116 
2117  // FIXME: This would be a lot easier if we could return a new instruction
2118  // instead of having to modify in place.
2119 
2120  // Remove these first since they are at the end.
2121  UseMI.RemoveOperand(
2122  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2123  UseMI.RemoveOperand(
2124  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2125 
2126  unsigned Src1Reg = Src1->getReg();
2127  unsigned Src1SubReg = Src1->getSubReg();
2128  Src0->setReg(Src1Reg);
2129  Src0->setSubReg(Src1SubReg);
2130  Src0->setIsKill(Src1->isKill());
2131 
2132  if (Opc == AMDGPU::V_MAC_F32_e64 ||
2133  Opc == AMDGPU::V_MAC_F16_e64 ||
2134  Opc == AMDGPU::V_FMAC_F32_e64 ||
2135  Opc == AMDGPU::V_FMAC_F16_e64)
2136  UseMI.untieRegOperand(
2137  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2138 
2139  Src1->ChangeToImmediate(Imm);
2140 
2141  removeModOperands(UseMI);
2142  UseMI.setDesc(get(NewOpc));
2143 
2144  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2145  if (DeleteDef)
2146  DefMI.eraseFromParent();
2147 
2148  return true;
2149  }
2150 
2151  // Added part is the constant: Use v_madak_{f16, f32}.
2152  if (Src2->isReg() && Src2->getReg() == Reg) {
2153  // Not allowed to use constant bus for another operand.
2154  // We can however allow an inline immediate as src0.
2155  bool Src0Inlined = false;
2156  if (Src0->isReg()) {
2157  // Try to inline constant if possible.
2158  // If the Def moves immediate and the use is single
2159  // We are saving VGPR here.
2160  MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
2161  if (Def && Def->isMoveImmediate() &&
2162  isInlineConstant(Def->getOperand(1)) &&
2163  MRI->hasOneUse(Src0->getReg())) {
2164  Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2165  Src0Inlined = true;
2166  } else if ((RI.isPhysicalRegister(Src0->getReg()) &&
2167  (ST.getConstantBusLimit(Opc) <= 1 &&
2168  RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2169  (RI.isVirtualRegister(Src0->getReg()) &&
2170  (ST.getConstantBusLimit(Opc) <= 1 &&
2171  RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2172  return false;
2173  // VGPR is okay as Src0 - fallthrough
2174  }
2175 
2176  if (Src1->isReg() && !Src0Inlined ) {
2177  // We have one slot for inlinable constant so far - try to fill it
2178  MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
2179  if (Def && Def->isMoveImmediate() &&
2180  isInlineConstant(Def->getOperand(1)) &&
2181  MRI->hasOneUse(Src1->getReg()) &&
2182  commuteInstruction(UseMI)) {
2183  Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2184  } else if ((RI.isPhysicalRegister(Src1->getReg()) &&
2185  RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
2186  (RI.isVirtualRegister(Src1->getReg()) &&
2187  RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
2188  return false;
2189  // VGPR is okay as Src1 - fallthrough
2190  }
2191 
2192  unsigned NewOpc =
2193  IsFMA ? (IsF32 ? AMDGPU::V_FMAAK_F32 : AMDGPU::V_FMAAK_F16)
2194  : (IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16);
2195  if (pseudoToMCOpcode(NewOpc) == -1)
2196  return false;
2197 
2198  const int64_t Imm = ImmOp->getImm();
2199 
2200  // FIXME: This would be a lot easier if we could return a new instruction
2201  // instead of having to modify in place.
2202 
2203  // Remove these first since they are at the end.
2204  UseMI.RemoveOperand(
2205  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2206  UseMI.RemoveOperand(
2207  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2208 
2209  if (Opc == AMDGPU::V_MAC_F32_e64 ||
2210  Opc == AMDGPU::V_MAC_F16_e64 ||
2211  Opc == AMDGPU::V_FMAC_F32_e64 ||
2212  Opc == AMDGPU::V_FMAC_F16_e64)
2213  UseMI.untieRegOperand(
2214  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2215 
2216  // ChangingToImmediate adds Src2 back to the instruction.
2217  Src2->ChangeToImmediate(Imm);
2218 
2219  // These come before src2.
2220  removeModOperands(UseMI);
2221  UseMI.setDesc(get(NewOpc));
2222 
2223  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2224  if (DeleteDef)
2225  DefMI.eraseFromParent();
2226 
2227  return true;
2228  }
2229  }
2230 
2231  return false;
2232 }
2233 
2234 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
2235  int WidthB, int OffsetB) {
2236  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2237  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2238  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2239  return LowOffset + LowWidth <= HighOffset;
2240 }
2241 
2242 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
2243  const MachineInstr &MIb) const {
2244  const MachineOperand *BaseOp0, *BaseOp1;
2245  int64_t Offset0, Offset1;
2246 
2247  if (getMemOperandWithOffset(MIa, BaseOp0, Offset0, &RI) &&
2248  getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) {
2249  if (!BaseOp0->isIdenticalTo(*BaseOp1))
2250  return false;
2251 
2252  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
2253  // FIXME: Handle ds_read2 / ds_write2.
2254  return false;
2255  }
2256  unsigned Width0 = (*MIa.memoperands_begin())->getSize();
2257  unsigned Width1 = (*MIb.memoperands_begin())->getSize();
2258  if (offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
2259  return true;
2260  }
2261  }
2262 
2263  return false;
2264 }
2265 
2267  const MachineInstr &MIb,
2268  AliasAnalysis *AA) const {
2269  assert((MIa.mayLoad() || MIa.mayStore()) &&
2270  "MIa must load from or modify a memory location");
2271  assert((MIb.mayLoad() || MIb.mayStore()) &&
2272  "MIb must load from or modify a memory location");
2273 
2275  return false;
2276 
2277  // XXX - Can we relax this between address spaces?
2278  if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2279  return false;
2280 
2281  // TODO: Should we check the address space from the MachineMemOperand? That
2282  // would allow us to distinguish objects we know don't alias based on the
2283  // underlying address space, even if it was lowered to a different one,
2284  // e.g. private accesses lowered to use MUBUF instructions on a scratch
2285  // buffer.
2286  if (isDS(MIa)) {
2287  if (isDS(MIb))
2288  return checkInstOffsetsDoNotOverlap(MIa, MIb);
2289 
2290  return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
2291  }
2292 
2293  if (isMUBUF(MIa) || isMTBUF(MIa)) {
2294  if (isMUBUF(MIb) || isMTBUF(MIb))
2295  return checkInstOffsetsDoNotOverlap(MIa, MIb);
2296 
2297  return !isFLAT(MIb) && !isSMRD(MIb);
2298  }
2299 
2300  if (isSMRD(MIa)) {
2301  if (isSMRD(MIb))
2302  return checkInstOffsetsDoNotOverlap(MIa, MIb);
2303 
2304  return !isFLAT(MIb) && !isMUBUF(MIa) && !isMTBUF(MIa);
2305  }
2306 
2307  if (isFLAT(MIa)) {
2308  if (isFLAT(MIb))
2309  return checkInstOffsetsDoNotOverlap(MIa, MIb);
2310 
2311  return false;
2312  }
2313 
2314  return false;
2315 }
2316 
2317 static int64_t getFoldableImm(const MachineOperand* MO) {
2318  if (!MO->isReg())
2319  return false;
2320  const MachineFunction *MF = MO->getParent()->getParent()->getParent();
2321  const MachineRegisterInfo &MRI = MF->getRegInfo();
2322  auto Def = MRI.getUniqueVRegDef(MO->getReg());
2323  if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
2324  Def->getOperand(1).isImm())
2325  return Def->getOperand(1).getImm();
2326  return AMDGPU::NoRegister;
2327 }
2328 
2330  MachineInstr &MI,
2331  LiveVariables *LV) const {
2332  unsigned Opc = MI.getOpcode();
2333  bool IsF16 = false;
2334  bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2335  Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64;
2336 
2337  switch (Opc) {
2338  default:
2339  return nullptr;
2340  case AMDGPU::V_MAC_F16_e64:
2341  case AMDGPU::V_FMAC_F16_e64:
2342  IsF16 = true;
2344  case AMDGPU::V_MAC_F32_e64:
2345  case AMDGPU::V_FMAC_F32_e64:
2346  break;
2347  case AMDGPU::V_MAC_F16_e32:
2348  case AMDGPU::V_FMAC_F16_e32:
2349  IsF16 = true;
2351  case AMDGPU::V_MAC_F32_e32:
2352  case AMDGPU::V_FMAC_F32_e32: {
2353  int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
2354  AMDGPU::OpName::src0);
2355  const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
2356  if (!Src0->isReg() && !Src0->isImm())
2357  return nullptr;
2358 
2359  if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
2360  return nullptr;
2361 
2362  break;
2363  }
2364  }
2365 
2366  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
2367  const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
2368  const MachineOperand *Src0Mods =
2369  getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
2370  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2371  const MachineOperand *Src1Mods =
2372  getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
2373  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2374  const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
2375  const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
2376 
2377  if (!Src0Mods && !Src1Mods && !Clamp && !Omod &&
2378  // If we have an SGPR input, we will violate the constant bus restriction.
2379  (ST.getConstantBusLimit(Opc) > 1 ||
2380  !Src0->isReg() ||
2381  !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
2382  if (auto Imm = getFoldableImm(Src2)) {
2383  unsigned NewOpc =
2384  IsFMA ? (IsF16 ? AMDGPU::V_FMAAK_F16 : AMDGPU::V_FMAAK_F32)
2385  : (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
2386  if (pseudoToMCOpcode(NewOpc) != -1)
2387  return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2388  .add(*Dst)
2389  .add(*Src0)
2390  .add(*Src1)
2391  .addImm(Imm);
2392  }
2393  unsigned NewOpc =
2394  IsFMA ? (IsF16 ? AMDGPU::V_FMAMK_F16 : AMDGPU::V_FMAMK_F32)
2395  : (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
2396  if (auto Imm = getFoldableImm(Src1)) {
2397  if (pseudoToMCOpcode(NewOpc) != -1)
2398  return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2399  .add(*Dst)
2400  .add(*Src0)
2401  .addImm(Imm)
2402  .add(*Src2);
2403  }
2404  if (auto Imm = getFoldableImm(Src0)) {
2405  if (pseudoToMCOpcode(NewOpc) != -1 &&
2407  AMDGPU::OpName::src0), Src1))
2408  return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2409  .add(*Dst)
2410  .add(*Src1)
2411  .addImm(Imm)
2412  .add(*Src2);
2413  }
2414  }
2415 
2416  unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16 : AMDGPU::V_FMA_F32)
2417  : (IsF16 ? AMDGPU::V_MAD_F16 : AMDGPU::V_MAD_F32);
2418  if (pseudoToMCOpcode(NewOpc) == -1)
2419  return nullptr;
2420 
2421  return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2422  .add(*Dst)
2423  .addImm(Src0Mods ? Src0Mods->getImm() : 0)
2424  .add(*Src0)
2425  .addImm(Src1Mods ? Src1Mods->getImm() : 0)
2426  .add(*Src1)
2427  .addImm(0) // Src mods
2428  .add(*Src2)
2429  .addImm(Clamp ? Clamp->getImm() : 0)
2430  .addImm(Omod ? Omod->getImm() : 0);
2431 }
2432 
2433 // It's not generally safe to move VALU instructions across these since it will
2434 // start using the register as a base index rather than directly.
2435 // XXX - Why isn't hasSideEffects sufficient for these?
2437  switch (MI.getOpcode()) {
2438  case AMDGPU::S_SET_GPR_IDX_ON:
2439  case AMDGPU::S_SET_GPR_IDX_MODE:
2440  case AMDGPU::S_SET_GPR_IDX_OFF:
2441  return true;
2442  default:
2443  return false;
2444  }
2445 }
2446 
2448  const MachineBasicBlock *MBB,
2449  const MachineFunction &MF) const {
2450  // XXX - Do we want the SP check in the base implementation?
2451 
2452  // Target-independent instructions do not have an implicit-use of EXEC, even
2453  // when they operate on VGPRs. Treating EXEC modifications as scheduling
2454  // boundaries prevents incorrect movements of such instructions.
2455  return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF) ||
2456  MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
2457  MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
2458  MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
2460 }
2461 
2462 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
2463  return Opcode == AMDGPU::DS_ORDERED_COUNT ||
2464  Opcode == AMDGPU::DS_GWS_INIT ||
2465  Opcode == AMDGPU::DS_GWS_SEMA_V ||
2466  Opcode == AMDGPU::DS_GWS_SEMA_BR ||
2467  Opcode == AMDGPU::DS_GWS_SEMA_P ||
2468  Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
2469  Opcode == AMDGPU::DS_GWS_BARRIER;
2470 }
2471 
2473  unsigned Opcode = MI.getOpcode();
2474 
2475  if (MI.mayStore() && isSMRD(MI))
2476  return true; // scalar store or atomic
2477 
2478  // These instructions cause shader I/O that may cause hardware lockups
2479  // when executed with an empty EXEC mask.
2480  //
2481  // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
2482  // EXEC = 0, but checking for that case here seems not worth it
2483  // given the typical code patterns.
2484  if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
2485  Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE ||
2486  Opcode == AMDGPU::DS_ORDERED_COUNT)
2487  return true;
2488 
2489  if (MI.isInlineAsm())
2490  return true; // conservative assumption
2491 
2492  // These are like SALU instructions in terms of effects, so it's questionable
2493  // whether we should return true for those.
2494  //
2495  // However, executing them with EXEC = 0 causes them to operate on undefined
2496  // data, which we avoid by returning true here.
2497  if (Opcode == AMDGPU::V_READFIRSTLANE_B32 || Opcode == AMDGPU::V_READLANE_B32)
2498  return true;
2499 
2500  return false;
2501 }
2502 
2504  const MachineInstr &MI) const {
2505  if (MI.isMetaInstruction())
2506  return false;
2507 
2508  // This won't read exec if this is an SGPR->SGPR copy.
2509  if (MI.isCopyLike()) {
2510  if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
2511  return true;
2512 
2513  // Make sure this isn't copying exec as a normal operand
2514  return MI.readsRegister(AMDGPU::EXEC, &RI);
2515  }
2516 
2517  // Be conservative with any unhandled generic opcodes.
2518  if (!isTargetSpecificOpcode(MI.getOpcode()))
2519  return true;
2520 
2521  return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
2522 }
2523 
2524 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
2525  switch (Imm.getBitWidth()) {
2526  case 1: // This likely will be a condition code mask.
2527  return true;
2528 
2529  case 32:
2531  ST.hasInv2PiInlineImm());
2532  case 64:
2534  ST.hasInv2PiInlineImm());
2535  case 16:
2536  return ST.has16BitInsts() &&
2538  ST.hasInv2PiInlineImm());
2539  default:
2540  llvm_unreachable("invalid bitwidth");
2541  }
2542 }
2543 
2545  uint8_t OperandType) const {
2546  if (!MO.isImm() ||
2547  OperandType < AMDGPU::OPERAND_SRC_FIRST ||
2548  OperandType > AMDGPU::OPERAND_SRC_LAST)
2549  return false;
2550 
2551  // MachineOperand provides no way to tell the true operand size, since it only
2552  // records a 64-bit value. We need to know the size to determine if a 32-bit
2553  // floating point immediate bit pattern is legal for an integer immediate. It
2554  // would be for any 32-bit integer operand, but would not be for a 64-bit one.
2555 
2556  int64_t Imm = MO.getImm();
2557  switch (OperandType) {
2562  int32_t Trunc = static_cast<int32_t>(Imm);
2564  }
2570  ST.hasInv2PiInlineImm());
2575  if (isInt<16>(Imm) || isUInt<16>(Imm)) {
2576  // A few special case instructions have 16-bit operands on subtargets
2577  // where 16-bit instructions are not legal.
2578  // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
2579  // constants in these cases
2580  int16_t Trunc = static_cast<int16_t>(Imm);
2581  return ST.has16BitInsts() &&
2583  }
2584 
2585  return false;
2586  }
2591  uint32_t Trunc = static_cast<uint32_t>(Imm);
2593  }
2594  default:
2595  llvm_unreachable("invalid bitwidth");
2596  }
2597 }
2598 
2600  const MCOperandInfo &OpInfo) const {
2601  switch (MO.getType()) {
2603  return false;
2605  return !isInlineConstant(MO, OpInfo);
2611  return true;
2612  default:
2613  llvm_unreachable("unexpected operand type");
2614  }
2615 }
2616 
2617 static bool compareMachineOp(const MachineOperand &Op0,
2618  const MachineOperand &Op1) {
2619  if (Op0.getType() != Op1.getType())
2620  return false;
2621 
2622  switch (Op0.getType()) {
2624  return Op0.getReg() == Op1.getReg();
2626  return Op0.getImm() == Op1.getImm();
2627  default:
2628  llvm_unreachable("Didn't expect to be comparing these operand types");
2629  }
2630 }
2631 
2633  const MachineOperand &MO) const {
2634  const MCInstrDesc &InstDesc = MI.getDesc();
2635  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
2636 
2637  assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
2638 
2639  if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
2640  return true;
2641 
2642  if (OpInfo.RegClass < 0)
2643  return false;
2644 
2645  if (MO.isImm() && isInlineConstant(MO, OpInfo))
2646  return RI.opCanUseInlineConstant(OpInfo.OperandType);
2647 
2648  if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
2649  return false;
2650 
2651  if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
2652  return true;
2653 
2654  const MachineFunction *MF = MI.getParent()->getParent();
2655  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2656  return ST.hasVOP3Literal();
2657 }
2658 
2659 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
2660  int Op32 = AMDGPU::getVOPe32(Opcode);
2661  if (Op32 == -1)
2662  return false;
2663 
2664  return pseudoToMCOpcode(Op32) != -1;
2665 }
2666 
2667 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
2668  // The src0_modifier operand is present on all instructions
2669  // that have modifiers.
2670 
2671  return AMDGPU::getNamedOperandIdx(Opcode,
2672  AMDGPU::OpName::src0_modifiers) != -1;
2673 }
2674 
2676  unsigned OpName) const {
2677  const MachineOperand *Mods = getNamedOperand(MI, OpName);
2678  return Mods && Mods->getImm();
2679 }
2680 
2682  return hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
2683  hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
2684  hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers) ||
2685  hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
2686  hasModifiersSet(MI, AMDGPU::OpName::omod);
2687 }
2688 
2690  const MachineRegisterInfo &MRI) const {
2691  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2692  // Can't shrink instruction with three operands.
2693  // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
2694  // a special case for it. It can only be shrunk if the third operand
2695  // is vcc, and src0_modifiers and src1_modifiers are not set.
2696  // We should handle this the same way we handle vopc, by addding
2697  // a register allocation hint pre-regalloc and then do the shrinking
2698  // post-regalloc.
2699  if (Src2) {
2700  switch (MI.getOpcode()) {
2701  default: return false;
2702 
2703  case AMDGPU::V_ADDC_U32_e64:
2704  case AMDGPU::V_SUBB_U32_e64:
2705  case AMDGPU::V_SUBBREV_U32_e64: {
2706  const MachineOperand *Src1
2707  = getNamedOperand(MI, AMDGPU::OpName::src1);
2708  if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
2709  return false;
2710  // Additional verification is needed for sdst/src2.
2711  return true;
2712  }
2713  case AMDGPU::V_MAC_F32_e64:
2714  case AMDGPU::V_MAC_F16_e64:
2715  case AMDGPU::V_FMAC_F32_e64:
2716  case AMDGPU::V_FMAC_F16_e64:
2717  if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
2718  hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
2719  return false;
2720  break;
2721 
2722  case AMDGPU::V_CNDMASK_B32_e64:
2723  break;
2724  }
2725  }
2726 
2727  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2728  if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
2729  hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
2730  return false;
2731 
2732  // We don't need to check src0, all input types are legal, so just make sure
2733  // src0 isn't using any modifiers.
2734  if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
2735  return false;
2736 
2737  // Can it be shrunk to a valid 32 bit opcode?
2738  if (!hasVALU32BitEncoding(MI.getOpcode()))
2739  return false;
2740 
2741  // Check output modifiers
2742  return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
2743  !hasModifiersSet(MI, AMDGPU::OpName::clamp);
2744 }
2745 
2746 // Set VCC operand with all flags from \p Orig, except for setting it as
2747 // implicit.
2749  const MachineOperand &Orig) {
2750 
2751  for (MachineOperand &Use : MI.implicit_operands()) {
2752  if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
2753  Use.setIsUndef(Orig.isUndef());
2754  Use.setIsKill(Orig.isKill());
2755  return;
2756  }
2757  }
2758 }
2759 
2761  unsigned Op32) const {
2762  MachineBasicBlock *MBB = MI.getParent();;
2763  MachineInstrBuilder Inst32 =
2764  BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32));
2765 
2766  // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
2767  // For VOPC instructions, this is replaced by an implicit def of vcc.
2768  int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
2769  if (Op32DstIdx != -1) {
2770  // dst
2771  Inst32.add(MI.getOperand(0));
2772  } else {
2773  assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
2774  "Unexpected case");
2775  }
2776 
2777  Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
2778 
2779  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2780  if (Src1)
2781  Inst32.add(*Src1);
2782 
2783  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2784 
2785  if (Src2) {
2786  int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
2787  if (Op32Src2Idx != -1) {
2788  Inst32.add(*Src2);
2789  } else {
2790  // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
2791  // replaced with an implicit read of vcc. This was already added
2792  // during the initial BuildMI, so find it to preserve the flags.
2793  copyFlagsToImplicitVCC(*Inst32, *Src2);
2794  }
2795  }
2796 
2797  return Inst32;
2798 }
2799 
2801  const MachineOperand &MO,
2802  const MCOperandInfo &OpInfo) const {
2803  // Literal constants use the constant bus.
2804  //if (isLiteralConstantLike(MO, OpInfo))
2805  // return true;
2806  if (MO.isImm())
2807  return !isInlineConstant(MO, OpInfo);
2808 
2809  if (!MO.isReg())
2810  return true; // Misc other operands like FrameIndex
2811 
2812  if (!MO.isUse())
2813  return false;
2814 
2816  return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
2817 
2818  // FLAT_SCR is just an SGPR pair.
2819  if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
2820  return true;
2821 
2822  // EXEC register uses the constant bus.
2823  if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
2824  return true;
2825 
2826  // SGPRs use the constant bus
2827  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 ||
2828  (!MO.isImplicit() &&
2829  (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
2830  AMDGPU::SGPR_64RegClass.contains(MO.getReg()))));
2831 }
2832 
2833 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
2834  for (const MachineOperand &MO : MI.implicit_operands()) {
2835  // We only care about reads.
2836  if (MO.isDef())
2837  continue;
2838 
2839  switch (MO.getReg()) {
2840  case AMDGPU::VCC:
2841  case AMDGPU::M0:
2842  case AMDGPU::FLAT_SCR:
2843  return MO.getReg();
2844 
2845  default:
2846  break;
2847  }
2848  }
2849 
2850  return AMDGPU::NoRegister;
2851 }
2852 
2853 static bool shouldReadExec(const MachineInstr &MI) {
2854  if (SIInstrInfo::isVALU(MI)) {
2855  switch (MI.getOpcode()) {
2856  case AMDGPU::V_READLANE_B32:
2857  case AMDGPU::V_READLANE_B32_gfx6_gfx7:
2858  case AMDGPU::V_READLANE_B32_gfx10:
2859  case AMDGPU::V_READLANE_B32_vi:
2860  case AMDGPU::V_WRITELANE_B32:
2861  case AMDGPU::V_WRITELANE_B32_gfx6_gfx7:
2862  case AMDGPU::V_WRITELANE_B32_gfx10:
2863  case AMDGPU::V_WRITELANE_B32_vi:
2864  return false;
2865  }
2866 
2867  return true;
2868  }
2869 
2870  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
2871  SIInstrInfo::isSALU(MI) ||
2872  SIInstrInfo::isSMRD(MI))
2873  return false;
2874 
2875  return true;
2876 }
2877 
2878 static bool isSubRegOf(const SIRegisterInfo &TRI,
2879  const MachineOperand &SuperVec,
2880  const MachineOperand &SubReg) {
2882  return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
2883 
2884  return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
2885  SubReg.getReg() == SuperVec.getReg();
2886 }
2887 
2889  StringRef &ErrInfo) const {
2890  uint16_t Opcode = MI.getOpcode();
2891  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
2892  return true;
2893 
2894  const MachineFunction *MF = MI.getParent()->getParent();
2895  const MachineRegisterInfo &MRI = MF->getRegInfo();
2896 
2897  int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
2898  int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
2899  int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
2900 
2901  // Make sure the number of operands is correct.
2902  const MCInstrDesc &Desc = get(Opcode);
2903  if (!Desc.isVariadic() &&
2904  Desc.getNumOperands() != MI.getNumExplicitOperands()) {
2905  ErrInfo = "Instruction has wrong number of operands.";
2906  return false;
2907  }
2908 
2909  if (MI.isInlineAsm()) {
2910  // Verify register classes for inlineasm constraints.
2911  for (unsigned I = InlineAsm::MIOp_FirstOperand, E = MI.getNumOperands();
2912  I != E; ++I) {
2913  const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
2914  if (!RC)
2915  continue;
2916 
2917  const MachineOperand &Op = MI.getOperand(I);
2918  if (!Op.isReg())
2919  continue;
2920 
2921  unsigned Reg = Op.getReg();
2922  if (!TargetRegisterInfo::isVirtualRegister(Reg) && !RC->contains(Reg)) {
2923  ErrInfo = "inlineasm operand has incorrect register class.";
2924  return false;
2925  }
2926  }
2927 
2928  return true;
2929  }
2930 
2931  // Make sure the register classes are correct.
2932  for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
2933  if (MI.getOperand(i).isFPImm()) {
2934  ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
2935  "all fp values to integers.";
2936  return false;
2937  }
2938 
2939  int RegClass = Desc.OpInfo[i].RegClass;
2940 
2941  switch (Desc.OpInfo[i].OperandType) {
2943  if (MI.getOperand(i).isImm()) {
2944  ErrInfo = "Illegal immediate value for operand.";
2945  return false;
2946  }
2947  break;
2950  break;
2957  const MachineOperand &MO = MI.getOperand(i);
2958  if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
2959  ErrInfo = "Illegal immediate value for operand.";
2960  return false;
2961  }
2962  break;
2963  }
2966  // Check if this operand is an immediate.
2967  // FrameIndex operands will be replaced by immediates, so they are
2968  // allowed.
2969  if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
2970  ErrInfo = "Expected immediate, but got non-immediate";
2971  return false;
2972  }
2974  default:
2975  continue;
2976  }
2977 
2978  if (!MI.getOperand(i).isReg())
2979  continue;
2980 
2981  if (RegClass != -1) {
2982  unsigned Reg = MI.getOperand(i).getReg();
2983  if (Reg == AMDGPU::NoRegister ||
2985  continue;
2986 
2987  const TargetRegisterClass *RC = RI.getRegClass(RegClass);
2988  if (!RC->contains(Reg)) {
2989  ErrInfo = "Operand has incorrect register class.";
2990  return false;
2991  }
2992  }
2993  }
2994 
2995  // Verify SDWA
2996  if (isSDWA(MI)) {
2997  if (!ST.hasSDWA()) {
2998  ErrInfo = "SDWA is not supported on this target";
2999  return false;
3000  }
3001 
3002  int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
3003 
3004  const int OpIndicies[] = { DstIdx, Src0Idx, Src1Idx, Src2Idx };
3005 
3006  for (int OpIdx: OpIndicies) {
3007  if (OpIdx == -1)
3008  continue;
3009  const MachineOperand &MO = MI.getOperand(OpIdx);
3010 
3011  if (!ST.hasSDWAScalar()) {
3012  // Only VGPRS on VI
3013  if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
3014  ErrInfo = "Only VGPRs allowed as operands in SDWA instructions on VI";
3015  return false;
3016  }
3017  } else {
3018  // No immediates on GFX9
3019  if (!MO.isReg()) {
3020  ErrInfo = "Only reg allowed as operands in SDWA instructions on GFX9";
3021  return false;
3022  }
3023  }
3024  }
3025 
3026  if (!ST.hasSDWAOmod()) {
3027  // No omod allowed on VI
3028  const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3029  if (OMod != nullptr &&
3030  (!OMod->isImm() || OMod->getImm() != 0)) {
3031  ErrInfo = "OMod not allowed in SDWA instructions on VI";
3032  return false;
3033  }
3034  }
3035 
3036  uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
3037  if (isVOPC(BasicOpcode)) {
3038  if (!ST.hasSDWASdst() && DstIdx != -1) {
3039  // Only vcc allowed as dst on VI for VOPC
3040  const MachineOperand &Dst = MI.getOperand(DstIdx);
3041  if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
3042  ErrInfo = "Only VCC allowed as dst in SDWA instructions on VI";
3043  return false;
3044  }
3045  } else if (!ST.hasSDWAOutModsVOPC()) {
3046  // No clamp allowed on GFX9 for VOPC
3047  const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3048  if (Clamp && (!Clamp->isImm() || Clamp->getImm() != 0)) {
3049  ErrInfo = "Clamp not allowed in VOPC SDWA instructions on VI";
3050  return false;
3051  }
3052 
3053  // No omod allowed on GFX9 for VOPC
3054  const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3055  if (OMod && (!OMod->isImm() || OMod->getImm() != 0)) {
3056  ErrInfo = "OMod not allowed in VOPC SDWA instructions on VI";
3057  return false;
3058  }
3059  }
3060  }
3061 
3062  const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused);
3063  if (DstUnused && DstUnused->isImm() &&
3064  DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) {
3065  const MachineOperand &Dst = MI.getOperand(DstIdx);
3066  if (!Dst.isReg() || !Dst.isTied()) {
3067  ErrInfo = "Dst register should have tied register";
3068  return false;
3069  }
3070 
3071  const MachineOperand &TiedMO =
3072  MI.getOperand(MI.findTiedOperandIdx(DstIdx));
3073  if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
3074  ErrInfo =
3075  "Dst register should be tied to implicit use of preserved register";
3076  return false;
3077  } else if (TargetRegisterInfo::isPhysicalRegister(TiedMO.getReg()) &&
3078  Dst.getReg() != TiedMO.getReg()) {
3079  ErrInfo = "Dst register should use same physical register as preserved";
3080  return false;
3081  }
3082  }
3083  }
3084 
3085  // Verify MIMG
3086  if (isMIMG(MI.getOpcode()) && !MI.mayStore()) {
3087  // Ensure that the return type used is large enough for all the options
3088  // being used TFE/LWE require an extra result register.
3089  const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask);
3090  if (DMask) {
3091  uint64_t DMaskImm = DMask->getImm();
3092  uint32_t RegCount =
3093  isGather4(MI.getOpcode()) ? 4 : countPopulation(DMaskImm);
3094  const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
3095  const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
3096  const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3097 
3098  // Adjust for packed 16 bit values
3099  if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
3100  RegCount >>= 1;
3101 
3102  // Adjust if using LWE or TFE
3103  if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
3104  RegCount += 1;
3105 
3106  const uint32_t DstIdx =
3107  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
3108  const MachineOperand &Dst = MI.getOperand(DstIdx);
3109  if (Dst.isReg()) {
3110  const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
3111  uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
3112  if (RegCount > DstSize) {
3113  ErrInfo = "MIMG instruction returns too many registers for dst "
3114  "register class";
3115  return false;
3116  }
3117  }
3118  }
3119  }
3120 
3121  // Verify VOP*. Ignore multiple sgpr operands on writelane.
3122  if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
3123  && (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isVOPC(MI) || isSDWA(MI))) {
3124  // Only look at the true operands. Only a real operand can use the constant
3125  // bus, and we don't want to check pseudo-operands like the source modifier
3126  // flags.
3127  const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
3128 
3129  unsigned ConstantBusCount = 0;
3130  unsigned LiteralCount = 0;
3131 
3132  if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
3133  ++ConstantBusCount;
3134 
3135  SmallVector<unsigned, 2> SGPRsUsed;
3136  unsigned SGPRUsed = findImplicitSGPRRead(MI);
3137  if (SGPRUsed != AMDGPU::NoRegister) {
3138  ++ConstantBusCount;
3139  SGPRsUsed.push_back(SGPRUsed);
3140  }
3141 
3142  for (int OpIdx : OpIndices) {
3143  if (OpIdx == -1)
3144  break;
3145  const MachineOperand &MO = MI.getOperand(OpIdx);
3146  if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3147  if (MO.isReg()) {
3148  SGPRUsed = MO.getReg();
3149  if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) {
3150  return !RI.regsOverlap(SGPRUsed, SGPR);
3151  })) {
3152  ++ConstantBusCount;
3153  SGPRsUsed.push_back(SGPRUsed);
3154  }
3155  } else {
3156  ++ConstantBusCount;
3157  ++LiteralCount;
3158  }
3159  }
3160  }
3161  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3162  // v_writelane_b32 is an exception from constant bus restriction:
3163  // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
3164  if (ConstantBusCount > ST.getConstantBusLimit(Opcode) &&
3165  Opcode != AMDGPU::V_WRITELANE_B32) {
3166  ErrInfo = "VOP* instruction violates constant bus restriction";
3167  return false;
3168  }
3169 
3170  if (isVOP3(MI) && LiteralCount) {
3171  if (LiteralCount && !ST.hasVOP3Literal()) {
3172  ErrInfo = "VOP3 instruction uses literal";
3173  return false;
3174  }
3175  if (LiteralCount > 1) {
3176  ErrInfo = "VOP3 instruction uses more than one literal";
3177  return false;
3178  }
3179  }
3180  }
3181 
3182  // Verify misc. restrictions on specific instructions.
3183  if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
3184  Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
3185  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3186  const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3187  const MachineOperand &Src2 = MI.getOperand(Src2Idx);
3188  if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3189  if (!compareMachineOp(Src0, Src1) &&
3190  !compareMachineOp(Src0, Src2)) {
3191  ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
3192  return false;
3193  }
3194  }
3195  }
3196 
3197  if (isSOP2(MI) || isSOPC(MI)) {
3198  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3199  const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3200  unsigned Immediates = 0;
3201 
3202  if (!Src0.isReg() &&
3203  !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
3204  Immediates++;
3205  if (!Src1.isReg() &&
3206  !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
3207  Immediates++;
3208 
3209  if (Immediates > 1) {
3210  ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
3211  return false;
3212  }
3213  }
3214 
3215  if (isSOPK(MI)) {
3216  auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
3217  if (Desc.isBranch()) {
3218  if (!Op->isMBB()) {
3219  ErrInfo = "invalid branch target for SOPK instruction";
3220  return false;
3221  }
3222  } else {
3223  uint64_t Imm = Op->getImm();
3224  if (sopkIsZext(MI)) {
3225  if (!isUInt<16>(Imm)) {
3226  ErrInfo = "invalid immediate for SOPK instruction";
3227  return false;
3228  }
3229  } else {
3230  if (!isInt<16>(Imm)) {
3231  ErrInfo = "invalid immediate for SOPK instruction";
3232  return false;
3233  }
3234  }
3235  }
3236  }
3237 
3238  if (Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e32 ||
3239  Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e64 ||
3240  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
3241  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64) {
3242  const bool IsDst = Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
3243  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64;
3244 
3245  const unsigned StaticNumOps = Desc.getNumOperands() +
3246  Desc.getNumImplicitUses();
3247  const unsigned NumImplicitOps = IsDst ? 2 : 1;
3248 
3249  // Allow additional implicit operands. This allows a fixup done by the post
3250  // RA scheduler where the main implicit operand is killed and implicit-defs
3251  // are added for sub-registers that remain live after this instruction.
3252  if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
3253  ErrInfo = "missing implicit register operands";
3254  return false;
3255  }
3256 
3257  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3258  if (IsDst) {
3259  if (!Dst->isUse()) {
3260  ErrInfo = "v_movreld_b32 vdst should be a use operand";
3261  return false;
3262  }
3263 
3264  unsigned UseOpIdx;
3265  if (!MI.isRegTiedToUseOperand(StaticNumOps, &UseOpIdx) ||
3266  UseOpIdx != StaticNumOps + 1) {
3267  ErrInfo = "movrel implicit operands should be tied";
3268  return false;
3269  }
3270  }
3271 
3272  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3273  const MachineOperand &ImpUse
3274  = MI.getOperand(StaticNumOps + NumImplicitOps - 1);
3275  if (!ImpUse.isReg() || !ImpUse.isUse() ||
3276  !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
3277  ErrInfo = "src0 should be subreg of implicit vector use";
3278  return false;
3279  }
3280  }
3281 
3282  // Make sure we aren't losing exec uses in the td files. This mostly requires
3283  // being careful when using let Uses to try to add other use registers.
3284  if (shouldReadExec(MI)) {
3285  if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
3286  ErrInfo = "VALU instruction does not implicitly read exec mask";
3287  return false;
3288  }
3289  }
3290 
3291  if (isSMRD(MI)) {
3292  if (MI.mayStore()) {
3293  // The register offset form of scalar stores may only use m0 as the
3294  // soffset register.
3295  const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
3296  if (Soff && Soff->getReg() != AMDGPU::M0) {
3297  ErrInfo = "scalar stores must use m0 as offset register";
3298  return false;
3299  }
3300  }
3301  }
3302 
3303  if (isFLAT(MI) && !MF->getSubtarget<GCNSubtarget>().hasFlatInstOffsets()) {
3304  const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
3305  if (Offset->getImm() != 0) {
3306  ErrInfo = "subtarget does not support offsets in flat instructions";
3307  return false;
3308  }
3309  }
3310 
3311  if (isMIMG(MI)) {
3312  const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
3313  if (DimOp) {
3314  int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode,
3315  AMDGPU::OpName::vaddr0);
3316  int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
3317  const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opcode);
3318  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3320  const AMDGPU::MIMGDimInfo *Dim =
3322 
3323  if (!Dim) {
3324  ErrInfo = "dim is out of range";
3325  return false;
3326  }
3327 
3328  bool IsNSA = SRsrcIdx - VAddr0Idx > 1;
3329  unsigned AddrWords = BaseOpcode->NumExtraArgs +
3330  (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
3331  (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
3332  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
3333 
3334  unsigned VAddrWords;
3335  if (IsNSA) {
3336  VAddrWords = SRsrcIdx - VAddr0Idx;
3337  } else {
3338  const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
3339  VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
3340  if (AddrWords > 8)
3341  AddrWords = 16;
3342  else if (AddrWords > 4)
3343  AddrWords = 8;
3344  else if (AddrWords == 3 && VAddrWords == 4) {
3345  // CodeGen uses the V4 variant of instructions for three addresses,
3346  // because the selection DAG does not support non-power-of-two types.
3347  AddrWords = 4;
3348  }
3349  }
3350 
3351  if (VAddrWords != AddrWords) {
3352  ErrInfo = "bad vaddr size";
3353  return false;
3354  }
3355  }
3356  }
3357 
3358  const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
3359  if (DppCt) {
3360  using namespace AMDGPU::DPP;
3361 
3362  unsigned DC = DppCt->getImm();
3363  if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 ||
3364  DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST ||
3369  ErrInfo = "Invalid dpp_ctrl value";
3370  return false;
3371  }
3372  }
3373 
3374  return true;
3375 }
3376 
3377 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
3378  switch (MI.getOpcode()) {
3379  default: return AMDGPU::INSTRUCTION_LIST_END;
3380  case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
3381  case AMDGPU::COPY: return AMDGPU::COPY;
3382  case AMDGPU::PHI: return AMDGPU::PHI;
3383  case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
3384  case AMDGPU::WQM: return AMDGPU::WQM;
3385  case AMDGPU::WWM: return AMDGPU::WWM;
3386  case AMDGPU::S_MOV_B32:
3387  return MI.getOperand(1).isReg() ?
3388  AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
3389  case AMDGPU::S_ADD_I32:
3390  return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_I32_e32;
3391  case AMDGPU::S_ADDC_U32:
3392  return AMDGPU::V_ADDC_U32_e32;
3393  case AMDGPU::S_SUB_I32:
3394  return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32;
3395  // FIXME: These are not consistently handled, and selected when the carry is
3396  // used.
3397  case AMDGPU::S_ADD_U32:
3398  return AMDGPU::V_ADD_I32_e32;
3399  case AMDGPU::S_SUB_U32:
3400  return AMDGPU::V_SUB_I32_e32;
3401  case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
3402  case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_U32;
3403  case AMDGPU::S_MUL_HI_U32: return AMDGPU::V_MUL_HI_U32;
3404  case AMDGPU::S_MUL_HI_I32: return AMDGPU::V_MUL_HI_I32;
3405  case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;
3406  case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e64;
3407  case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e64;
3408  case AMDGPU::S_XNOR_B32:
3409  return ST.hasDLInsts() ? AMDGPU::V_XNOR_B32_e64 : AMDGPU::INSTRUCTION_LIST_END;
3410  case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e64;
3411  case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e64;
3412  case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e64;
3413  case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e64;
3414  case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
3415  case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
3416  case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
3417  case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
3418  case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
3419  case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
3420  case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
3421  case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
3422  case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
3423  case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
3424  case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
3425  case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
3426  case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
3427  case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
3428  case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
3429  case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
3430  case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
3431  case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
3432  case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
3433  case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
3434  case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e32;
3435  case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e32;
3436  case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e32;
3437  case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32;
3438  case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32;
3439  case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32;
3440  case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e32;
3441  case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e32;
3442  case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
3443  case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
3444  case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
3445  case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
3446  case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ;
3447  case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ;
3448  }
3450  "Unexpected scalar opcode without corresponding vector one!");
3451 }
3452 
3454  unsigned OpNo) const {
3456  const MCInstrDesc &Desc = get(MI.getOpcode());
3457  if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
3458  Desc.OpInfo[OpNo].RegClass == -1) {
3459  unsigned Reg = MI.getOperand(OpNo).getReg();
3460 
3462  return MRI.getRegClass(Reg);
3463  return RI.getPhysRegClass(Reg);
3464  }
3465 
3466  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
3467  return RI.getRegClass(RCID);
3468 }
3469 
3470 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
3472  MachineBasicBlock *MBB = MI.getParent();
3473  MachineOperand &MO = MI.getOperand(OpIdx);
3475  const SIRegisterInfo *TRI =
3476  static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
3477  unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
3478  const TargetRegisterClass *RC = RI.getRegClass(RCID);
3479  unsigned Size = TRI->getRegSizeInBits(*RC);
3480  unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32;
3481  if (MO.isReg())
3482  Opcode = AMDGPU::COPY;
3483  else if (RI.isSGPRClass(RC))
3484  Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
3485 
3486  const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
3487  if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
3488  VRC = &AMDGPU::VReg_64RegClass;
3489  else
3490  VRC = &AMDGPU::VGPR_32RegClass;
3491 
3492  unsigned Reg = MRI.createVirtualRegister(VRC);
3493  DebugLoc DL = MBB->findDebugLoc(I);
3494  BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
3495  MO.ChangeToRegister(Reg, false);
3496 }
3497 
3500  MachineOperand &SuperReg,
3501  const TargetRegisterClass *SuperRC,
3502  unsigned SubIdx,
3503  const TargetRegisterClass *SubRC)
3504  const {
3505  MachineBasicBlock *MBB = MI->getParent();
3506  DebugLoc DL = MI->getDebugLoc();
3507  unsigned SubReg = MRI.createVirtualRegister(SubRC);
3508 
3509  if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
3510  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3511  .addReg(SuperReg.getReg(), 0, SubIdx);
3512  return SubReg;
3513  }
3514 
3515  // Just in case the super register is itself a sub-register, copy it to a new
3516  // value so we don't need to worry about merging its subreg index with the
3517  // SubIdx passed to this function. The register coalescer should be able to
3518  // eliminate this extra copy.
3519  unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
3520 
3521  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
3522  .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
3523 
3524  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3525  .addReg(NewSuperReg, 0, SubIdx);
3526 
3527  return SubReg;
3528 }
3529 
3533  MachineOperand &Op,
3534  const TargetRegisterClass *SuperRC,
3535  unsigned SubIdx,
3536  const TargetRegisterClass *SubRC) const {
3537  if (Op.isImm()) {
3538  if (SubIdx == AMDGPU::sub0)
3539  return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
3540  if (SubIdx == AMDGPU::sub1)
3541  return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
3542 
3543  llvm_unreachable("Unhandled register index for immediate");
3544  }
3545 
3546  unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
3547  SubIdx, SubRC);
3548  return MachineOperand::CreateReg(SubReg, false);
3549 }
3550 
3551 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
3552 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
3553  assert(Inst.getNumExplicitOperands() == 3);
3554  MachineOperand Op1 = Inst.getOperand(1);
3555  Inst.RemoveOperand(1);
3556  Inst.addOperand(Op1);
3557 }
3558 
3560  const MCOperandInfo &OpInfo,
3561  const MachineOperand &MO) const {
3562  if (!MO.isReg())
3563  return false;
3564 
3565  unsigned Reg = MO.getReg();
3566  const TargetRegisterClass *RC =
3568  MRI.getRegClass(Reg) :
3569  RI.getPhysRegClass(Reg);
3570 
3571  const SIRegisterInfo *TRI =
3572  static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
3573  RC = TRI->getSubRegClass(RC, MO.getSubReg());
3574 
3575  // In order to be legal, the common sub-class must be equal to the
3576  // class of the current operand. For example:
3577  //
3578  // v_mov_b32 s0 ; Operand defined as vsrc_b32
3579  // ; RI.getCommonSubClass(s0,vsrc_b32) = sgpr ; LEGAL
3580  //
3581  // s_sendmsg 0, s0 ; Operand defined as m0reg
3582  // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
3583 
3584  return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
3585 }
3586 
3588  const MCOperandInfo &OpInfo,
3589  const MachineOperand &MO) const {
3590  if (MO.isReg())
3591  return isLegalRegOperand(MRI, OpInfo, MO);
3592 
3593  // Handle non-register types that are treated like immediates.
3594  assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
3595  return true;
3596 }
3597 
3598 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
3599  const MachineOperand *MO) const {
3600  const MachineFunction &MF = *MI.getParent()->getParent();
3601  const MachineRegisterInfo &MRI = MF.getRegInfo();
3602  const MCInstrDesc &InstDesc = MI.getDesc();
3603  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
3604  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
3605  const TargetRegisterClass *DefinedRC =
3606  OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
3607  if (!MO)
3608  MO = &MI.getOperand(OpIdx);
3609 
3610  int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode());
3611  int VOP3LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
3612  if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
3613  if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--)
3614  return false;
3615 
3616  SmallDenseSet<RegSubRegPair> SGPRsUsed;
3617  if (MO->isReg())
3618  SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg()));
3619 
3620  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3621  if (i == OpIdx)
3622  continue;
3623  const MachineOperand &Op = MI.getOperand(i);
3624  if (Op.isReg()) {
3625  RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
3626  if (!SGPRsUsed.count(SGPR) &&
3627  usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
3628  if (--ConstantBusLimit <= 0)
3629  return false;
3630  SGPRsUsed.insert(SGPR);
3631  }
3632  } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
3633  if (--ConstantBusLimit <= 0)
3634  return false;
3635  } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&
3636  isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
3637  if (!VOP3LiteralLimit--)
3638  return false;
3639  if (--ConstantBusLimit <= 0)
3640  return false;
3641  }
3642  }
3643  }
3644 
3645  if (MO->isReg()) {
3646  assert(DefinedRC);
3647  return isLegalRegOperand(MRI, OpInfo, *MO);
3648  }
3649 
3650  // Handle non-register types that are treated like immediates.
3651  assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
3652 
3653  if (!DefinedRC) {
3654  // This operand expects an immediate.
3655  return true;
3656  }
3657 
3658  return isImmOperandLegal(MI, OpIdx, *MO);
3659 }
3660 
3662  MachineInstr &MI) const {
3663  unsigned Opc = MI.getOpcode();
3664  const MCInstrDesc &InstrDesc = get(Opc);
3665 
3666  int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
3667  MachineOperand &Src1 = MI.getOperand(Src1Idx);
3668 
3669  // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
3670  // we need to only have one constant bus use before GFX10.
3671  bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister;
3672  if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1) {
3673  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3674  MachineOperand &Src0 = MI.getOperand(Src0Idx);
3675 
3676  if (Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
3677  isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
3678  legalizeOpWithMove(MI, Src0Idx);
3679  }
3680 
3681  // Special case: V_WRITELANE_B32 accepts only immediate or SGPR operands for
3682  // both the value to write (src0) and lane select (src1). Fix up non-SGPR
3683  // src0/src1 with V_READFIRSTLANE.
3684  if (Opc == AMDGPU::V_WRITELANE_B32) {
3685  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3686  MachineOperand &Src0 = MI.getOperand(Src0Idx);
3687  const DebugLoc &DL = MI.getDebugLoc();
3688  if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
3689  unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3690  BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
3691  .add(Src0);
3692  Src0.ChangeToRegister(Reg, false);
3693  }
3694  if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
3695  unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3696  const DebugLoc &DL = MI.getDebugLoc();
3697  BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
3698  .add(Src1);
3699  Src1.ChangeToRegister(Reg, false);
3700  }
3701  return;
3702  }
3703 
3704  // VOP2 src0 instructions support all operand types, so we don't need to check
3705  // their legality. If src1 is already legal, we don't need to do anything.
3706  if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
3707  return;
3708 
3709  // Special case: V_READLANE_B32 accepts only immediate or SGPR operands for
3710  // lane select. Fix up using V_READFIRSTLANE, since we assume that the lane
3711  // select is uniform.
3712  if (Opc == AMDGPU::V_READLANE_B32 && Src1.isReg() &&
3713  RI.isVGPR(MRI, Src1.getReg())) {
3714  unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3715  const DebugLoc &DL = MI.getDebugLoc();
3716  BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
3717  .add(Src1);
3718  Src1.ChangeToRegister(Reg, false);
3719  return;
3720  }
3721 
3722  // We do not use commuteInstruction here because it is too aggressive and will
3723  // commute if it is possible. We only want to commute here if it improves
3724  // legality. This can be called a fairly large number of times so don't waste
3725  // compile time pointlessly swapping and checking legality again.
3726  if (HasImplicitSGPR || !MI.isCommutable()) {
3727  legalizeOpWithMove(MI, Src1Idx);
3728  return;
3729  }
3730 
3731  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3732  MachineOperand &Src0 = MI.getOperand(Src0Idx);
3733 
3734  // If src0 can be used as src1, commuting will make the operands legal.
3735  // Otherwise we have to give up and insert a move.
3736  //
3737  // TODO: Other immediate-like operand kinds could be commuted if there was a
3738  // MachineOperand::ChangeTo* for them.
3739  if ((!Src1.isImm() && !Src1.isReg()) ||
3740  !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
3741  legalizeOpWithMove(MI, Src1Idx);
3742  return;
3743  }
3744 
3745  int CommutedOpc = commuteOpcode(MI);
3746  if (CommutedOpc == -1) {
3747  legalizeOpWithMove(MI, Src1Idx);
3748  return;
3749  }
3750 
3751  MI.setDesc(get(CommutedOpc));
3752 
3753  unsigned Src0Reg = Src0.getReg();
3754  unsigned Src0SubReg = Src0.getSubReg();
3755  bool Src0Kill = Src0.isKill();
3756 
3757  if (Src1.isImm())
3758  Src0.ChangeToImmediate(Src1.getImm());
3759  else if (Src1.isReg()) {
3760  Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
3761  Src0.setSubReg(Src1.getSubReg());
3762  } else
3763  llvm_unreachable("Should only have register or immediate operands");
3764 
3765  Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
3766  Src1.setSubReg(Src0SubReg);
3767 }
3768 
3769 // Legalize VOP3 operands. All operand types are supported for any operand
3770 // but only one literal constant and only starting from GFX10.
3772  MachineInstr &MI) const {
3773  unsigned Opc = MI.getOpcode();
3774 
3775  int VOP3Idx[3] = {
3776  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
3777  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
3778  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
3779  };
3780 
3781  // Find the one SGPR operand we are allowed to use.
3782  int ConstantBusLimit = ST.getConstantBusLimit(Opc);
3783  int LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
3784  SmallDenseSet<unsigned> SGPRsUsed;
3785  unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
3786  if (SGPRReg != AMDGPU::NoRegister) {
3787  SGPRsUsed.insert(SGPRReg);
3788  --ConstantBusLimit;
3789  }
3790 
3791  for (unsigned i = 0; i < 3; ++i) {
3792  int Idx = VOP3Idx[i];
3793  if (Idx == -1)
3794  break;
3795  MachineOperand &MO = MI.getOperand(Idx);
3796 
3797  if (!MO.isReg()) {
3798  if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx]))
3799  continue;
3800 
3801  if (LiteralLimit > 0 && ConstantBusLimit > 0) {
3802  --LiteralLimit;
3803  --ConstantBusLimit;
3804  continue;
3805  }
3806 
3807  --LiteralLimit;
3808  --ConstantBusLimit;
3809  legalizeOpWithMove(MI, Idx);
3810  continue;
3811  }
3812 
3813  if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
3814  continue; // VGPRs are legal
3815 
3816  // We can use one SGPR in each VOP3 instruction prior to GFX10
3817  // and two starting from GFX10.
3818  if (SGPRsUsed.count(MO.getReg()))
3819  continue;
3820  if (ConstantBusLimit > 0) {
3821  SGPRsUsed.insert(MO.getReg());
3822  --ConstantBusLimit;
3823  continue;
3824  }
3825 
3826  // If we make it this far, then the operand is not legal and we must
3827  // legalize it.
3828  legalizeOpWithMove(MI, Idx);
3829  }
3830 }
3831 
3833  MachineRegisterInfo &MRI) const {
3834  const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
3835  const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
3836  unsigned DstReg = MRI.createVirtualRegister(SRC);
3837  unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
3838 
3839  if (SubRegs == 1) {
3840  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
3841  get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
3842  .addReg(SrcReg);
3843  return DstReg;
3844  }
3845 
3847  for (unsigned i = 0; i < SubRegs; ++i) {
3848  unsigned SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3849  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
3850  get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
3851  .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
3852  SRegs.push_back(SGPR);
3853  }
3854 
3855  MachineInstrBuilder MIB =
3856  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
3857  get(AMDGPU::REG_SEQUENCE), DstReg);
3858  for (unsigned i = 0; i < SubRegs; ++i) {
3859  MIB.addReg(SRegs[i]);
3860  MIB.addImm(RI.getSubRegFromChannel(i));
3861  }
3862  return DstReg;
3863 }
3864 
3866  MachineInstr &MI) const {
3867 
3868  // If the pointer is store in VGPRs, then we need to move them to
3869  // SGPRs using v_readfirstlane. This is safe because we only select
3870  // loads with uniform pointers to SMRD instruction so we know the
3871  // pointer value is uniform.
3872  MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase);
3873  if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
3874  unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI);
3875  SBase->setReg(SGPR);
3876  }
3877  MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soff);
3878  if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
3879  unsigned SGPR = readlaneVGPRToSGPR(SOff->getReg(), MI, MRI);
3880  SOff->setReg(SGPR);
3881  }
3882 }
3883 
3886  const TargetRegisterClass *DstRC,
3887  MachineOperand &Op,
3889  const DebugLoc &DL) const {
3890  unsigned OpReg = Op.getReg();
3891  unsigned OpSubReg = Op.getSubReg();
3892 
3893  const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg(
3894  RI.getRegClassForReg(MRI, OpReg), OpSubReg);
3895 
3896  // Check if operand is already the correct register class.
3897  if (DstRC == OpRC)
3898  return;
3899 
3900  unsigned DstReg = MRI.createVirtualRegister(DstRC);
3901  MachineInstr *Copy =
3902  BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
3903 
3904  Op.setReg(DstReg);
3905  Op.setSubReg(0);
3906 
3907  MachineInstr *Def = MRI.getVRegDef(OpReg);
3908  if (!Def)
3909  return;
3910 
3911  // Try to eliminate the copy if it is copying an immediate value.
3912  if (Def->isMoveImmediate())
3913  FoldImmediate(*Copy, *Def, OpReg, &MRI);
3914 }
3915 
3916 // Emit the actual waterfall loop, executing the wrapped instruction for each
3917 // unique value of \p Rsrc across all lanes. In the best case we execute 1
3918 // iteration, in the worst case we execute 64 (once per lane).
3919 static void
3921  MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
3922  const DebugLoc &DL, MachineOperand &Rsrc) {
3923  MachineBasicBlock::iterator I = LoopBB.begin();
3924 
3925  unsigned VRsrc = Rsrc.getReg();
3926  unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
3927 
3928  unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3929  unsigned CondReg0 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3930  unsigned CondReg1 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3931  unsigned AndCond = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3932  unsigned SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3933  unsigned SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3934  unsigned SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3935  unsigned SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3936  unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
3937 
3938  // Beginning of the loop, read the next Rsrc variant.
3939  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
3940  .addReg(VRsrc, VRsrcUndef, AMDGPU::sub0);
3941  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
3942  .addReg(VRsrc, VRsrcUndef, AMDGPU::sub1);
3943  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
3944  .addReg(VRsrc, VRsrcUndef, AMDGPU::sub2);
3945  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
3946  .addReg(VRsrc, VRsrcUndef, AMDGPU::sub3);
3947 
3948  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
3949  .addReg(SRsrcSub0)
3950  .addImm(AMDGPU::sub0)
3951  .addReg(SRsrcSub1)
3952  .addImm(AMDGPU::sub1)
3953  .addReg(SRsrcSub2)
3954  .addImm(AMDGPU::sub2)
3955  .addReg(SRsrcSub3)
3956  .addImm(AMDGPU::sub3);
3957 
3958  // Update Rsrc operand to use the SGPR Rsrc.
3959  Rsrc.setReg(SRsrc);
3960  Rsrc.setIsKill(true);
3961 
3962  // Identify all lanes with identical Rsrc operands in their VGPRs.
3963  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
3964  .addReg(SRsrc, 0, AMDGPU::sub0_sub1)
3965  .addReg(VRsrc, 0, AMDGPU::sub0_sub1);
3966  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
3967  .addReg(SRsrc, 0, AMDGPU::sub2_sub3)
3968  .addReg(VRsrc, 0, AMDGPU::sub2_sub3);
3969  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_B64), AndCond)
3970  .addReg(CondReg0)
3971  .addReg(CondReg1);
3972 
3973  MRI.setSimpleHint(SaveExec, AndCond);
3974 
3975  // Update EXEC to matching lanes, saving original to SaveExec.
3976  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_SAVEEXEC_B64), SaveExec)
3977  .addReg(AndCond, RegState::Kill);
3978 
3979  // The original instruction is here; we insert the terminators after it.
3980  I = LoopBB.end();
3981 
3982  // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3983  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_XOR_B64_term), AMDGPU::EXEC)
3984  .addReg(AMDGPU::EXEC)
3985  .addReg(SaveExec);
3986  BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
3987 }
3988 
3989 // Build a waterfall loop around \p MI, replacing the VGPR \p Rsrc register
3990 // with SGPRs by iterating over all unique values across all lanes.
3992  MachineOperand &Rsrc, MachineDominatorTree *MDT) {
3993  MachineBasicBlock &MBB = *MI.getParent();
3994  MachineFunction &MF = *MBB.getParent();
3997  const DebugLoc &DL = MI.getDebugLoc();
3998 
3999  unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
4000 
4001  // Save the EXEC mask
4002  BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B64), SaveExec)
4003  .addReg(AMDGPU::EXEC);
4004 
4005  // Killed uses in the instruction we are waterfalling around will be
4006  // incorrect due to the added control-flow.
4007  for (auto &MO : MI.uses()) {
4008  if (MO.isReg() && MO.isUse()) {
4009  MRI.clearKillFlags(MO.getReg());
4010  }
4011  }
4012 
4013  // To insert the loop we need to split the block. Move everything after this
4014  // point to a new block, and insert a new empty block between the two.
4016  MachineBasicBlock *RemainderBB = MF.CreateMachineBasicBlock();
4017  MachineFunction::iterator MBBI(MBB);
4018  ++MBBI;
4019 
4020  MF.insert(MBBI, LoopBB);
4021  MF.insert(MBBI, RemainderBB);
4022 
4023  LoopBB->addSuccessor(LoopBB);
4024  LoopBB->addSuccessor(RemainderBB);
4025 
4026  // Move MI to the LoopBB, and the remainder of the block to RemainderBB.
4028  RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
4029  RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
4030  LoopBB->splice(LoopBB->begin(), &MBB, J);
4031 
4032  MBB.addSuccessor(LoopBB);
4033 
4034  // Update dominators. We know that MBB immediately dominates LoopBB, that
4035  // LoopBB immediately dominates RemainderBB, and that RemainderBB immediately
4036  // dominates all of the successors transferred to it from MBB that MBB used
4037  // to dominate.
4038  if (MDT) {
4039  MDT->addNewBlock(LoopBB, &MBB);
4040  MDT->addNewBlock(RemainderBB, LoopBB);
4041  for (auto &Succ : RemainderBB->successors()) {
4042  if (MDT->dominates(&MBB, Succ)) {
4043  MDT->changeImmediateDominator(Succ, RemainderBB);
4044  }
4045  }
4046  }
4047 
4048  emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);
4049 
4050  // Restore the EXEC mask
4051  MachineBasicBlock::iterator First = RemainderBB->begin();
4052  BuildMI(*RemainderBB, First, DL, TII.get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
4053  .addReg(SaveExec);
4054 }
4055 
4056 // Extract pointer from Rsrc and return a zero-value Rsrc replacement.
4057 static std::tuple<unsigned, unsigned>
4059  MachineBasicBlock &MBB = *MI.getParent();
4060  MachineFunction &MF = *MBB.getParent();
4062 
4063  // Extract the ptr from the resource descriptor.
4064  unsigned RsrcPtr =
4065  TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass,
4066  AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
4067 
4068  // Create an empty resource descriptor
4069  unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
4070  unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4071  unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4072  unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
4073  uint64_t RsrcDataFormat = TII.getDefaultRsrcDataFormat();
4074 
4075  // Zero64 = 0
4076  BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64)
4077  .addImm(0);
4078 
4079  // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
4080  BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
4081  .addImm(RsrcDataFormat & 0xFFFFFFFF);
4082 
4083  // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
4084  BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
4085  .addImm(RsrcDataFormat >> 32);
4086 
4087  // NewSRsrc = {Zero64, SRsrcFormat}
4088  BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
4089  .addReg(Zero64)
4090  .addImm(AMDGPU::sub0_sub1)
4091  .addReg(SRsrcFormatLo)
4092  .addImm(AMDGPU::sub2)
4093  .addReg(SRsrcFormatHi)
4094  .addImm(AMDGPU::sub3);
4095 
4096  return std::make_tuple(RsrcPtr, NewSRsrc);
4097 }
4098 
4100  MachineDominatorTree *MDT) const {
4101  MachineFunction &MF = *MI.getParent()->getParent();
4103 
4104  // Legalize VOP2
4105  if (isVOP2(MI) || isVOPC(MI)) {
4106  legalizeOperandsVOP2(MRI, MI);
4107  return;
4108  }
4109 
4110  // Legalize VOP3
4111  if (isVOP3(MI)) {
4112  legalizeOperandsVOP3(MRI, MI);
4113  return;
4114  }
4115 
4116  // Legalize SMRD
4117  if (isSMRD(MI)) {
4118  legalizeOperandsSMRD(MRI, MI);
4119  return;
4120  }
4121 
4122  // Legalize REG_SEQUENCE and PHI
4123  // The register class of the operands much be the same type as the register
4124  // class of the output.
4125  if (MI.getOpcode() == AMDGPU::PHI) {
4126  const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
4127  for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
4128  if (!MI.getOperand(i).isReg() ||
4130  continue;
4131  const TargetRegisterClass *OpRC =
4132  MRI.getRegClass(MI.getOperand(i).getReg());
4133  if (RI.hasVGPRs(OpRC)) {
4134  VRC = OpRC;
4135  } else {
4136  SRC = OpRC;
4137  }
4138  }
4139 
4140  // If any of the operands are VGPR registers, then they all most be
4141  // otherwise we will create illegal VGPR->SGPR copies when legalizing
4142  // them.
4143  if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {
4144  if (!VRC) {
4145  assert(SRC);
4146  VRC = RI.getEquivalentVGPRClass(SRC);
4147  }
4148  RC = VRC;
4149  } else {
4150  RC = SRC;
4151  }
4152 
4153  // Update all the operands so they have the same type.
4154  for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
4155  MachineOperand &Op = MI.getOperand(I);
4157  continue;
4158 
4159  // MI is a PHI instruction.
4160  MachineBasicBlock *InsertBB = MI.getOperand(I + 1).getMBB();
4161  MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
4162 
4163  // Avoid creating no-op copies with the same src and dst reg class. These
4164  // confuse some of the machine passes.
4165  legalizeGenericOperand(*InsertBB, Insert, RC, Op, MRI, MI.getDebugLoc());
4166  }
4167  }
4168 
4169  // REG_SEQUENCE doesn't really require operand legalization, but if one has a
4170  // VGPR dest type and SGPR sources, insert copies so all operands are
4171  // VGPRs. This seems to help operand folding / the register coalescer.
4172  if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) {
4173  MachineBasicBlock *MBB = MI.getParent();
4174  const TargetRegisterClass *DstRC = getOpRegClass(MI, 0);
4175  if (RI.hasVGPRs(DstRC)) {
4176  // Update all the operands so they are VGPR register classes. These may
4177  // not be the same register class because REG_SEQUENCE supports mixing
4178  // subregister index types e.g. sub0_sub1 + sub2 + sub3
4179  for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
4180  MachineOperand &Op = MI.getOperand(I);
4182  continue;
4183 
4184  const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4185  const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
4186  if (VRC == OpRC)
4187  continue;
4188 
4189  legalizeGenericOperand(*MBB, MI, VRC, Op, MRI, MI.getDebugLoc());
4190  Op.setIsKill();
4191  }
4192  }
4193 
4194  return;
4195  }
4196 
4197  // Legalize INSERT_SUBREG
4198  // src0 must have the same register class as dst
4199  if (MI.getOpcode() == AMDGPU::INSERT_SUBREG) {
4200  unsigned Dst = MI.getOperand(0).getReg();
4201  unsigned Src0 = MI.getOperand(1).getReg();
4202  const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
4203  const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
4204  if (DstRC != Src0RC) {
4205  MachineBasicBlock *MBB = MI.getParent();
4206  MachineOperand &Op = MI.getOperand(1);
4207  legalizeGenericOperand(*MBB, MI, DstRC, Op, MRI, MI.getDebugLoc());
4208  }
4209  return;
4210  }
4211 
4212  // Legalize SI_INIT_M0
4213  if (MI.getOpcode() == AMDGPU::SI_INIT_M0) {
4214  MachineOperand &Src = MI.getOperand(0);
4215  if (Src.isReg() && RI.hasVGPRs(MRI.getRegClass(Src.getReg())))
4216  Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
4217  return;
4218  }
4219 
4220  // Legalize MIMG and MUBUF/MTBUF for shaders.
4221  //
4222  // Shaders only generate MUBUF/MTBUF instructions via intrinsics or via
4223  // scratch memory access. In both cases, the legalization never involves
4224  // conversion to the addr64 form.
4225  if (isMIMG(MI) ||
4227  (isMUBUF(MI) || isMTBUF(MI)))) {
4228  MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
4229  if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4230  unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
4231  SRsrc->setReg(SGPR);
4232  }
4233 
4234  MachineOperand *SSamp = getNamedOperand(MI, AMDGPU::OpName::ssamp);
4235  if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
4236  unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI);
4237  SSamp->setReg(SGPR);
4238  }
4239  return;
4240  }
4241 
4242  // Legalize MUBUF* instructions.
4243  int RsrcIdx =
4244  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
4245  if (RsrcIdx != -1) {
4246  // We have an MUBUF instruction
4247  MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
4248  unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
4249  if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
4250  RI.getRegClass(RsrcRC))) {
4251  // The operands are legal.
4252  // FIXME: We may need to legalize operands besided srsrc.
4253  return;
4254  }
4255 
4256  // Legalize a VGPR Rsrc.
4257  //
4258  // If the instruction is _ADDR64, we can avoid a waterfall by extracting
4259  // the base pointer from the VGPR Rsrc, adding it to the VAddr, then using
4260  // a zero-value SRsrc.
4261  //
4262  // If the instruction is _OFFSET (both idxen and offen disabled), and we
4263  // support ADDR64 instructions, we can convert to ADDR64 and do the same as
4264  // above.
4265  //
4266  // Otherwise we are on non-ADDR64 hardware, and/or we have
4267  // idxen/offen/bothen and we fall back to a waterfall loop.
4268 
4269  MachineBasicBlock &MBB = *MI.getParent();
4270 
4271  MachineOperand *VAddr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
4272  if (VAddr && AMDGPU::getIfAddr64Inst(MI.getOpcode()) != -1) {
4273  // This is already an ADDR64 instruction so we need to add the pointer
4274  // extracted from the resource descriptor to the current value of VAddr.
4275  unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4276  unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4277  unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4278 
4279  unsigned RsrcPtr, NewSRsrc;
4280  std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
4281 
4282  // NewVaddrLo = RsrcPtr:sub0 + VAddr:sub0
4283  DebugLoc DL = MI.getDebugLoc();
4284  BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
4285  .addReg(RsrcPtr, 0, AMDGPU::sub0)
4286  .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
4287 
4288  // NewVaddrHi = RsrcPtr:sub1 + VAddr:sub1
4289  BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
4290  .addReg(RsrcPtr, 0, AMDGPU::sub1)
4291  .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
4292 
4293  // NewVaddr = {NewVaddrHi, NewVaddrLo}
4294  BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
4295  .addReg(NewVAddrLo)
4296  .addImm(AMDGPU::sub0)
4297  .addReg(NewVAddrHi)
4298  .addImm(AMDGPU::sub1);
4299 
4300  VAddr->setReg(NewVAddr);
4301  Rsrc->setReg(NewSRsrc);
4302  } else if (!VAddr && ST.hasAddr64()) {
4303  // This instructions is the _OFFSET variant, so we need to convert it to
4304  // ADDR64.
4305  assert(MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration()
4307  "FIXME: Need to emit flat atomics here");
4308 
4309  unsigned RsrcPtr, NewSRsrc;
4310  std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
4311 
4312  unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4313  MachineOperand *VData = getNamedOperand(MI, AMDGPU::OpName::vdata);
4314  MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
4315  MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset);
4316  unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI.getOpcode());
4317 
4318  // Atomics rith return have have an additional tied operand and are
4319  // missing some of the special bits.
4320  MachineOperand *VDataIn = getNamedOperand(MI, AMDGPU::OpName::vdata_in);
4321  MachineInstr *Addr64;
4322 
4323  if (!VDataIn) {
4324  // Regular buffer load / store.
4325  MachineInstrBuilder MIB =
4326  BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4327  .add(*VData)
4328  .addReg(NewVAddr)
4329  .addReg(NewSRsrc)
4330  .add(*SOffset)
4331  .add(*Offset);
4332 
4333  // Atomics do not have this operand.
4334  if (const MachineOperand *GLC =
4335  getNamedOperand(MI, AMDGPU::OpName::glc)) {
4336  MIB.addImm(GLC->getImm());
4337  }
4338  if (const MachineOperand *DLC =
4339  getNamedOperand(MI, AMDGPU::OpName::dlc)) {
4340  MIB.addImm(DLC->getImm());
4341  }
4342 
4343  MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc));
4344 
4345  if (const MachineOperand *TFE =
4346  getNamedOperand(MI, AMDGPU::OpName::tfe)) {
4347  MIB.addImm(TFE->getImm());
4348  }
4349 
4350  MIB.cloneMemRefs(MI);
4351  Addr64 = MIB;
4352  } else {
4353  // Atomics with return.
4354  Addr64 = BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4355  .add(*VData)
4356  .add(*VDataIn)
4357  .addReg(NewVAddr)
4358  .addReg(NewSRsrc)
4359  .add(*SOffset)
4360  .add(*Offset)
4361  .addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc))
4362  .cloneMemRefs(MI);
4363  }
4364 
4365  MI.removeFromParent();
4366 
4367  // NewVaddr = {NewVaddrHi, NewVaddrLo}
4368  BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
4369  NewVAddr)
4370  .addReg(RsrcPtr, 0, AMDGPU::sub0)
4371  .addImm(AMDGPU::sub0)
4372  .addReg(RsrcPtr, 0, AMDGPU::sub1)
4373  .addImm(AMDGPU::sub1);
4374  } else {
4375  // This is another variant; legalize Rsrc with waterfall loop from VGPRs
4376  // to SGPRs.
4377  loadSRsrcFromVGPR(*this, MI, *Rsrc, MDT);
4378  }
4379  }
4380 }
4381 
4383  MachineDominatorTree *MDT) const {
4384  SetVectorType Worklist;
4385  Worklist.insert(&TopInst);
4386 
4387  while (!Worklist.empty()) {
4388  MachineInstr &Inst = *Worklist.pop_back_val();
4389  MachineBasicBlock *MBB = Inst.getParent();
4391 
4392  unsigned Opcode = Inst.getOpcode();
4393  unsigned NewOpcode = getVALUOp(Inst);
4394 
4395  // Handle some special cases
4396  switch (Opcode) {
4397  default:
4398  break;
4399  case AMDGPU::S_ADD_U64_PSEUDO:
4400  case AMDGPU::S_SUB_U64_PSEUDO:
4401  splitScalar64BitAddSub(Worklist, Inst, MDT);
4402  Inst.eraseFromParent();
4403  continue;
4404  case AMDGPU::S_ADD_I32:
4405  case AMDGPU::S_SUB_I32:
4406  // FIXME: The u32 versions currently selected use the carry.
4407  if (moveScalarAddSub(Worklist, Inst, MDT))
4408  continue;
4409 
4410  // Default handling
4411  break;
4412  case AMDGPU::S_AND_B64:
4413  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT);
4414  Inst.eraseFromParent();
4415  continue;
4416 
4417  case AMDGPU::S_OR_B64:
4418  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32, MDT);
4419  Inst.eraseFromParent();
4420  continue;
4421 
4422  case AMDGPU::S_XOR_B64:
4423  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32, MDT);
4424  Inst.eraseFromParent();
4425  continue;
4426 
4427  case AMDGPU::S_NAND_B64:
4428  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NAND_B32, MDT);
4429  Inst.eraseFromParent();
4430  continue;
4431 
4432  case AMDGPU::S_NOR_B64:
4433  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NOR_B32, MDT);
4434  Inst.eraseFromParent();
4435  continue;
4436 
4437  case AMDGPU::S_XNOR_B64:
4438  if (ST.hasDLInsts())
4439  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XNOR_B32, MDT);
4440  else
4441  splitScalar64BitXnor(Worklist, Inst, MDT);
4442  Inst.eraseFromParent();
4443  continue;
4444 
4445  case AMDGPU::S_ANDN2_B64:
4446  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ANDN2_B32, MDT);
4447  Inst.eraseFromParent();
4448  continue;
4449 
4450  case AMDGPU::S_ORN2_B64:
4451  splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ORN2_B32, MDT);
4452  Inst.eraseFromParent();
4453  continue;
4454 
4455  case AMDGPU::S_NOT_B64:
4456  splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
4457  Inst.eraseFromParent();
4458  continue;
4459 
4460  case AMDGPU::S_BCNT1_I32_B64:
4461  splitScalar64BitBCNT(Worklist, Inst);
4462  Inst.eraseFromParent();
4463  continue;
4464 
4465  case AMDGPU::S_BFE_I64:
4466  splitScalar64BitBFE(Worklist, Inst);
4467  Inst.eraseFromParent();
4468  continue;
4469 
4470  case AMDGPU::S_LSHL_B32:
4471  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4472  NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
4473  swapOperands(Inst);
4474  }
4475  break;
4476  case AMDGPU::S_ASHR_I32:
4477  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4478  NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
4479  swapOperands(Inst);
4480  }
4481  break;
4482  case AMDGPU::S_LSHR_B32:
4483  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4484  NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
4485  swapOperands(Inst);
4486  }
4487  break;
4488  case AMDGPU::S_LSHL_B64:
4489  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4490  NewOpcode = AMDGPU::V_LSHLREV_B64;
4491  swapOperands(Inst);
4492  }
4493  break;
4494  case AMDGPU::S_ASHR_I64:
4495  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4496  NewOpcode = AMDGPU::V_ASHRREV_I64;
4497  swapOperands(Inst);
4498  }
4499  break;
4500  case AMDGPU::S_LSHR_B64:
4501  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4502  NewOpcode = AMDGPU::V_LSHRREV_B64;
4503  swapOperands(Inst);
4504  }
4505  break;
4506 
4507  case AMDGPU::S_ABS_I32:
4508  lowerScalarAbs(Worklist, Inst);
4509  Inst.eraseFromParent();
4510  continue;
4511 
4512  case AMDGPU::S_CBRANCH_SCC0:
4513  case AMDGPU::S_CBRANCH_SCC1:
4514  // Clear unused bits of vcc
4515  BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
4516  AMDGPU::VCC)
4517  .addReg(AMDGPU::EXEC)
4518  .addReg(AMDGPU::VCC);
4519  break;
4520 
4521  case AMDGPU::S_BFE_U64:
4522  case AMDGPU::S_BFM_B64:
4523  llvm_unreachable("Moving this op to VALU not implemented");
4524 
4525  case AMDGPU::S_PACK_LL_B32_B16:
4526  case AMDGPU::S_PACK_LH_B32_B16:
4527  case AMDGPU::S_PACK_HH_B32_B16:
4528  movePackToVALU(Worklist, MRI, Inst);
4529  Inst.eraseFromParent();
4530  continue;
4531 
4532  case AMDGPU::S_XNOR_B32:
4533  lowerScalarXnor(Worklist, Inst);
4534  Inst.eraseFromParent();
4535  continue;
4536 
4537  case AMDGPU::S_NAND_B32:
4538  splitScalarNotBinop(Worklist, Inst, AMDGPU::S_AND_B32);
4539  Inst.eraseFromParent();
4540  continue;
4541 
4542  case AMDGPU::S_NOR_B32:
4543  splitScalarNotBinop(Worklist, Inst, AMDGPU::S_OR_B32);
4544  Inst.eraseFromParent();
4545  continue;
4546 
4547  case AMDGPU::S_ANDN2_B32:
4548  splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_AND_B32);
4549  Inst.eraseFromParent();
4550  continue;
4551 
4552  case AMDGPU::S_ORN2_B32:
4553  splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);
4554  Inst.eraseFromParent();
4555  continue;
4556  }
4557 
4558  if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
4559  // We cannot move this instruction to the VALU, so we should try to
4560  // legalize its operands instead.
4561  legalizeOperands(Inst, MDT);
4562  continue;
4563  }
4564 
4565  // Use the new VALU Opcode.
4566  const MCInstrDesc &NewDesc = get(NewOpcode);
4567  Inst.setDesc(NewDesc);
4568 
4569  // Remove any references to SCC. Vector instructions can't read from it, and
4570  // We're just about to add the implicit use / defs of VCC, and we don't want
4571  // both.
4572  for (unsigned i = Inst.getNumOperands() - 1; i > 0; --i) {
4573  MachineOperand &Op = Inst.getOperand(i);
4574  if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
4575  // Only propagate through live-def of SCC.
4576  if (Op.isDef() && !Op.isDead())
4577  addSCCDefUsersToVALUWorklist(Op, Inst, Worklist);
4578  Inst.RemoveOperand(i);
4579  }
4580  }
4581 
4582  if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
4583  // We are converting these to a BFE, so we need to add the missing
4584  // operands for the size and offset.
4585  unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
4588 
4589  } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
4590  // The VALU version adds the second operand to the result, so insert an
4591  // extra 0 operand.
4593  }
4594 
4596 
4597  if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
4598  const MachineOperand &OffsetWidthOp = Inst.getOperand(2);
4599  // If we need to move this to VGPRs, we need to unpack the second operand
4600  // back into the 2 separate ones for bit offset and width.
4601  assert(OffsetWidthOp.isImm() &&
4602  "Scalar BFE is only implemented for constant width and offset");
4603  uint32_t Imm = OffsetWidthOp.getImm();
4604 
4605  uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
4606  uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
4607  Inst.RemoveOperand(2); // Remove old immediate.
4608  Inst.addOperand(MachineOperand::CreateImm(Offset));
4609  Inst.addOperand(MachineOperand::CreateImm(BitWidth));
4610  }
4611 
4612  bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
4613  unsigned NewDstReg = AMDGPU::NoRegister;
4614  if (HasDst) {
4615  unsigned DstReg = Inst.getOperand(0).getReg();
4617  continue;
4618 
4619  // Update the destination register class.
4620  const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
4621  if (!NewDstRC)
4622  continue;
4623 
4624  if (Inst.isCopy() &&
4626  NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {
4627  // Instead of creating a copy where src and dst are the same register
4628  // class, we just replace all uses of dst with src. These kinds of
4629  // copies interfere with the heuristics MachineSink uses to decide
4630  // whether or not to split a critical edge. Since the pass assumes
4631  // that copies will end up as machine instructions and not be
4632  // eliminated.
4633  addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
4634  MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
4635  MRI.clearKillFlags(Inst.getOperand(1).getReg());
4636  Inst.getOperand(0).setReg(DstReg);
4637 
4638  // Make sure we don't leave around a dead VGPR->SGPR copy. Normally
4639  // these are deleted later, but at -O0 it would leave a suspicious
4640  // looking illegal copy of an undef register.
4641  for (unsigned I = Inst.getNumOperands() - 1; I != 0; --I)
4642  Inst.RemoveOperand(I);
4643  Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
4644  continue;
4645  }
4646 
4647  NewDstReg = MRI.createVirtualRegister(NewDstRC);
4648  MRI.replaceRegWith(DstReg, NewDstReg);
4649  }
4650 
4651  // Legalize the operands
4652  legalizeOperands(Inst, MDT);
4653 
4654  if (HasDst)
4655  addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
4656  }
4657 }
4658 
4659 // Add/sub require special handling to deal with carry outs.
4660 bool SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
4661  MachineDominatorTree *MDT) const {
4662  if (ST.hasAddNoCarry()) {
4663  // Assume there is no user of scc since we don't select this in that case.
4664  // Since scc isn't used, it doesn't really matter if the i32 or u32 variant
4665  // is used.
4666 
4667  MachineBasicBlock &MBB = *Inst.getParent();
4669 
4670  unsigned OldDstReg = Inst.getOperand(0).getReg();
4671  unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4672 
4673  unsigned Opc = Inst.getOpcode();
4674  assert(Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32);
4675 
4676  unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ?
4677  AMDGPU::V_ADD_U32_e64 : AMDGPU::V_SUB_U32_e64;
4678 
4679  assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
4680  Inst.RemoveOperand(3);
4681 
4682  Inst.setDesc(get(NewOpc));
4683  Inst.addOperand(MachineOperand::CreateImm(0)); // clamp bit
4684  Inst.addImplicitDefUseOperands(*MBB.getParent());
4685  MRI.replaceRegWith(OldDstReg, ResultReg);
4686  legalizeOperands(Inst, MDT);
4687 
4688  addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4689  return true;
4690  }
4691 
4692  return false;
4693 }
4694 
4695 void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,
4696  MachineInstr &Inst) const {
4697  MachineBasicBlock &MBB = *Inst.getParent();
4699  MachineBasicBlock::iterator MII = Inst;
4700  DebugLoc DL = Inst.getDebugLoc();
4701 
4702  MachineOperand &Dest = Inst.getOperand(0);
4703  MachineOperand &Src = Inst.getOperand(1);
4704  unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4705  unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4706 
4707  unsigned SubOp = ST.hasAddNoCarry() ?
4708  AMDGPU::V_SUB_U32_e32 : AMDGPU::V_SUB_I32_e32;
4709 
4710  BuildMI(MBB, MII, DL, get(SubOp), TmpReg)
4711  .addImm(0)
4712  .addReg(Src.getReg());
4713 
4714  BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
4715  .addReg(Src.getReg())
4716  .addReg(TmpReg);
4717 
4718  MRI.replaceRegWith(Dest.getReg(), ResultReg);
4719  addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4720 }
4721 
4722 void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
4723  MachineInstr &Inst) const {
4724  MachineBasicBlock &MBB = *Inst.getParent();
4726  MachineBasicBlock::iterator MII = Inst;
4727  const DebugLoc &DL = Inst.getDebugLoc();
4728 
4729  MachineOperand &Dest = Inst.getOperand(0);
4730  MachineOperand &Src0 = Inst.getOperand(1);
4731  MachineOperand &Src1 = Inst.getOperand(2);
4732 
4733  if (ST.hasDLInsts()) {
4734  unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4735  legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
4736  legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src1, MRI, DL);
4737 
4738  BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest)
4739  .add(Src0)
4740  .add(Src1);
4741 
4742  MRI.replaceRegWith(Dest.getReg(), NewDest);
4743  addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4744  } else {
4745  // Using the identity !(x ^ y) == (!x ^ y) == (x ^ !y), we can
4746  // invert either source and then perform the XOR. If either source is a
4747  // scalar register, then we can leave the inversion on the scalar unit to
4748  // acheive a better distrubution of scalar and vector instructions.
4749  bool Src0IsSGPR = Src0.isReg() &&
4750  RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
4751  bool Src1IsSGPR = Src1.isReg() &&
4752  RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
4753  MachineInstr *Not = nullptr;
4754  MachineInstr *Xor = nullptr;
4755  unsigned Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4756  unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4757 
4758  // Build a pair of scalar instructions and add them to the work list.
4759  // The next iteration over the work list will lower these to the vector
4760  // unit as necessary.
4761  if (Src0IsSGPR) {
4762  Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp)
4763  .add(Src0);
4764  Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
4765  .addReg(Temp)
4766  .add(Src1);
4767  } else if (Src1IsSGPR) {
4768  Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp)
4769  .add(Src1);
4770  Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
4771  .add(Src0)
4772  .addReg(Temp);
4773  } else {
4774  Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
4775  .add(Src0)
4776  .add(Src1);
4777  Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
4778  .addReg(Temp);
4779  Worklist.insert(Not);
4780  }
4781 
4782  MRI.replaceRegWith(Dest.getReg(), NewDest);
4783 
4784  Worklist.insert(Xor);
4785 
4786  addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4787  }
4788 }
4789 
4790 void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,
4791  MachineInstr &Inst,
4792  unsigned Opcode) const {
4793  MachineBasicBlock &MBB = *Inst.getParent();
4795  MachineBasicBlock::iterator MII = Inst;
4796  const DebugLoc &DL = Inst.getDebugLoc();
4797 
4798  MachineOperand &Dest = Inst.getOperand(0);
4799  MachineOperand &Src0 = Inst.getOperand(1);
4800  MachineOperand &Src1 = Inst.getOperand(2);
4801 
4802  unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4803  unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4804 
4805  MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
4806  .add(Src0)
4807  .add(Src1);
4808 
4809  MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
4810  .addReg(Interm);
4811 
4812  Worklist.insert(&Op);
4813  Worklist.insert(&Not);
4814 
4815  MRI.replaceRegWith(Dest.getReg(), NewDest);
4816  addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4817 }
4818 
4819 void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,
4820  MachineInstr &Inst,
4821  unsigned Opcode) const {
4822  MachineBasicBlock &MBB = *Inst.getParent();
4824  MachineBasicBlock::iterator MII = Inst;
4825  const DebugLoc &DL = Inst.getDebugLoc();
4826 
4827  MachineOperand &Dest = Inst.getOperand(0);
4828  MachineOperand &Src0 = Inst.getOperand(1);
4829  MachineOperand &Src1 = Inst.getOperand(2);
4830 
4831  unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4832  unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4833 
4834  MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm)
4835  .add(Src1);
4836 
4837  MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest)
4838  .add(Src0)
4839  .addReg(Interm);
4840 
4841  Worklist.insert(&Not);
4842  Worklist.insert(&Op);
4843 
4844  MRI.replaceRegWith(Dest.getReg(), NewDest);
4845  addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4846 }
4847 
4848 void SIInstrInfo::splitScalar64BitUnaryOp(
4849  SetVectorType &Worklist, MachineInstr &Inst,
4850  unsigned Opcode) const {
4851  MachineBasicBlock &MBB = *Inst.getParent();
4853 
4854  MachineOperand &Dest = Inst.getOperand(0);
4855  MachineOperand &Src0 = Inst.getOperand(1);
4856  DebugLoc DL = Inst.getDebugLoc();
4857 
4858  MachineBasicBlock::iterator MII = Inst;
4859 
4860  const MCInstrDesc &InstDesc = get(Opcode);
4861  const TargetRegisterClass *Src0RC = Src0.isReg() ?
4862  MRI.getRegClass(Src0.getReg()) :
4863  &AMDGPU::SGPR_32RegClass;
4864 
4865  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
4866 
4867  MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4868  AMDGPU::sub0, Src0SubRC);
4869 
4870  const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
4871  const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
4872  const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
4873 
4874  unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
4875  MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
4876 
4877  MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4878  AMDGPU::sub1, Src0SubRC);
4879 
4880  unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
4881  MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
4882 
4883  unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
4884  BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
4885  .addReg(DestSub0)
4886  .addImm(AMDGPU::sub0)
4887  .addReg(DestSub1)
4888  .addImm(AMDGPU::sub1);
4889 
4890  MRI.replaceRegWith(Dest.getReg(), FullDestReg);
4891 
4892  Worklist.insert(&LoHalf);
4893  Worklist.insert(&HiHalf);
4894 
4895  // We don't need to legalizeOperands here because for a single operand, src0
4896  // will support any kind of input.
4897 
4898  // Move all users of this moved value.
4899  addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
4900 }
4901 
4902 void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,
4903  MachineInstr &Inst,
4904  MachineDominatorTree *MDT) const {
4905  bool IsAdd = (Inst.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
4906 
4907  MachineBasicBlock &MBB = *Inst.getParent();
4909 
4910  unsigned FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4911  unsigned DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4912  unsigned DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4913 
4914  unsigned CarryReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
4915  unsigned DeadCarryReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
4916 
4917  MachineOperand &Dest = Inst.getOperand(0);
4918  MachineOperand &Src0 = Inst.getOperand(1);
4919  MachineOperand &Src1 = Inst.getOperand(2);
4920  const DebugLoc &DL = Inst.getDebugLoc();
4921  MachineBasicBlock::iterator MII = Inst;
4922 
4923  const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
4924  const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
4925  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
4926  const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
4927 
4928  MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4929  AMDGPU::sub0, Src0SubRC);
4930  MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
4931  AMDGPU::sub0, Src1SubRC);
4932 
4933 
4934  MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4935  AMDGPU::sub1, Src0SubRC);
4936  MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
4937  AMDGPU::sub1, Src1SubRC);
4938 
4939  unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
4940  MachineInstr *LoHalf =
4941  BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
4942  .addReg(CarryReg, RegState::Define)
4943  .add(SrcReg0Sub0)
4944  .add(SrcReg1Sub0)
4945  .addImm(0); // clamp bit
4946 
4947  unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
4948  MachineInstr *HiHalf =
4949  BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
4950  .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
4951  .add(SrcReg0Sub1)
4952  .add(SrcReg1Sub1)
4953  .addReg(CarryReg, RegState::Kill)
4954  .addImm(0); // clamp bit
4955 
4956  BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
4957  .addReg(DestSub0)
4958  .addImm(AMDGPU::sub0)
4959  .addReg(DestSub1)
4960  .addImm(AMDGPU::sub1);
4961 
4962  MRI.replaceRegWith(Dest.getReg(), FullDestReg);
4963 
4964  // Try to legalize the operands in case we need to swap the order to keep it
4965  // valid.
4966  legalizeOperands(*LoHalf, MDT);
4967  legalizeOperands(*HiHalf, MDT);
4968 
4969  // Move all users of this moved vlaue.
4970  addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
4971 }
4972 
4973 void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,
4974  MachineInstr &Inst, unsigned Opcode,
4975  MachineDominatorTree *MDT) const {
4976  MachineBasicBlock &MBB = *Inst.getParent();
4978 
4979  MachineOperand &Dest = Inst.getOperand(0);
4980  MachineOperand &Src0 = Inst.getOperand(1);
4981  MachineOperand &Src1 = Inst.getOperand(2);
4982  DebugLoc DL = Inst.getDebugLoc();
4983 
4984  MachineBasicBlock::iterator MII = Inst;
4985 
4986  const MCInstrDesc &InstDesc = get(Opcode);
4987  const TargetRegisterClass *Src0RC = Src0.isReg() ?
4988  MRI.getRegClass(Src0.getReg()) :
4989  &AMDGPU::SGPR_32RegClass;
4990 
4991  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
4992  const TargetRegisterClass *Src1RC = Src1.isReg() ?
4993  MRI.getRegClass(Src1.getReg()) :
4994  &AMDGPU::SGPR_32RegClass;
4995 
4996  const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
4997 
4998  MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4999  AMDGPU::sub0, Src0SubRC);
5000  MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5001  AMDGPU::sub0, Src1SubRC);
5002  MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5003  AMDGPU::sub1, Src0SubRC);
5004  MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5005  AMDGPU::sub1, Src1SubRC);
5006 
5007  const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5008  const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5009  const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
5010 
5011  unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5012  MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
5013  .add(SrcReg0Sub0)
5014  .add(SrcReg1Sub0);
5015 
5016  unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5017  MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
5018  .add(SrcReg0Sub1)
5019  .add(SrcReg1Sub1);
5020 
5021  unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
5022  BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5023  .addReg(DestSub0)
5024  .addImm(AMDGPU::sub0)
5025  .addReg(DestSub1)
5026  .addImm(AMDGPU::sub1);
5027 
5028  MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5029 
5030  Worklist.insert(&LoHalf);
5031  Worklist.insert(&HiHalf);
5032 
5033  // Move all users of this moved vlaue.
5034  addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5035 }
5036 
5037 void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,
5038  MachineInstr &Inst,
5039  MachineDominatorTree *MDT) const {
5040  MachineBasicBlock &MBB = *Inst.getParent();
5042 
5043  MachineOperand &Dest = Inst.getOperand(0);
5044  MachineOperand &Src0 = Inst.getOperand(1);
5045  MachineOperand &Src1 = Inst.getOperand(2);
5046  const DebugLoc &DL = Inst.getDebugLoc();
5047 
5048  MachineBasicBlock::iterator MII = Inst;
5049 
5050  const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5051 
5052  unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5053 
5054  MachineOperand* Op0;
5055  MachineOperand* Op1;
5056 
5057  if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
5058  Op0 = &Src0;
5059  Op1 = &Src1;
5060  } else {
5061  Op0 = &Src1;
5062  Op1 = &Src0;
5063  }
5064 
5065  BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm)
5066  .add(*Op0);
5067 
5068  unsigned NewDest = MRI.createVirtualRegister(DestRC);
5069 
5070  MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
5071  .addReg(Interm)
5072  .add(*Op1);
5073 
5074  MRI.replaceRegWith(Dest.getReg(), NewDest);
5075 
5076  Worklist.insert(&Xor);
5077 }
5078 
5079 void SIInstrInfo::splitScalar64BitBCNT(
5080  SetVectorType &Worklist, MachineInstr &Inst) const {
5081  MachineBasicBlock &MBB = *Inst.getParent();
5083 
5084  MachineBasicBlock::iterator MII = Inst;
5085  const DebugLoc &DL = Inst.getDebugLoc();
5086 
5087  MachineOperand &Dest = Inst.getOperand(0);
5088  MachineOperand &Src = Inst.getOperand(1);
5089 
5090  const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
5091  const TargetRegisterClass *SrcRC = Src.isReg() ?
5092  MRI.getRegClass(Src.getReg()) :
5093  &AMDGPU::SGPR_32RegClass;
5094 
5095  unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5096  unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5097 
5098  const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
5099 
5100  MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
5101  AMDGPU::sub0, SrcSubRC);
5102  MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
5103  AMDGPU::sub1, SrcSubRC);
5104 
5105  BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
5106 
5107  BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
5108 
5109  MRI.replaceRegWith(Dest.getReg(), ResultReg);
5110 
5111  // We don't need to legalize operands here. src0 for etiher instruction can be
5112  // an SGPR, and the second input is unused or determined here.
5113  addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5114 }
5115 
5116 void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,
5117  MachineInstr &Inst) const {
5118  MachineBasicBlock &MBB = *Inst.getParent();
5120  MachineBasicBlock::iterator MII = Inst;
5121  const DebugLoc &DL = Inst.getDebugLoc();
5122 
5123  MachineOperand &Dest = Inst.getOperand(0);
5124  uint32_t Imm = Inst.getOperand(2).getImm();
5125  uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
5126  uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
5127 
5128  (void) Offset;
5129 
5130  // Only sext_inreg cases handled.
5131  assert(Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <= 32 &&
5132  Offset == 0 && "Not implemented");
5133 
5134  if (BitWidth < 32) {
5135  unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5136  unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5137  unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5138 
5139  BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
5140  .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
5141  .addImm(0)
5142  .addImm(BitWidth);
5143 
5144  BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
5145  .addImm(31)
5146  .addReg(MidRegLo);
5147 
5148  BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5149  .addReg(MidRegLo)
5150  .addImm(AMDGPU::sub0)
5151  .addReg(MidRegHi)
5152  .addImm(AMDGPU::sub1);
5153 
5154  MRI.replaceRegWith(Dest.getReg(), ResultReg);
5155  addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5156  return;
5157  }
5158 
5159  MachineOperand &Src = Inst.getOperand(1);
5160  unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5161  unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5162 
5163  BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
5164  .addImm(31)
5165  .addReg(Src.getReg(), 0, AMDGPU::sub0);
5166 
5167  BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5168  .addReg(Src.getReg(), 0, AMDGPU::sub0)
5169  .addImm(AMDGPU::sub0)
5170  .addReg(TmpReg)
5171  .addImm(AMDGPU::sub1);
5172 
5173  MRI.replaceRegWith(Dest.getReg(), ResultReg);
5174  addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5175 }
5176 
5177 void SIInstrInfo::addUsersToMoveToVALUWorklist(
5178  unsigned DstReg,
5180  SetVectorType &Worklist) const {
5181  for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
5182  E = MRI.use_end(); I != E;) {
5183  MachineInstr &UseMI = *I->getParent();
5184 
5185  unsigned OpNo = 0;
5186 
5187  switch (UseMI.getOpcode()) {
5188  case AMDGPU::COPY:
5189  case AMDGPU::WQM:
5190  case AMDGPU::WWM:
5191  case AMDGPU::REG_SEQUENCE:
5192  case AMDGPU::PHI:
5193  case AMDGPU::INSERT_SUBREG:
5194  break;
5195  default:
5196  OpNo = I.getOperandNo();
5197  break;
5198  }
5199 
5200  if (!RI.hasVGPRs(getOpRegClass(UseMI, OpNo))) {
5201  Worklist.insert(&UseMI);
5202 
5203  do {
5204  ++I;
5205  } while (I != E && I->getParent() == &UseMI);
5206  } else {
5207  ++I;
5208  }
5209  }
5210 }
5211 
5212 void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,
5213  MachineRegisterInfo &MRI,
5214  MachineInstr &Inst) const {
5215  unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5216  MachineBasicBlock *MBB = Inst.getParent();
5217  MachineOperand &Src0 = Inst.getOperand(1);
5218  MachineOperand &Src1 = Inst.getOperand(2);
5219  const DebugLoc &DL = Inst.getDebugLoc();
5220 
5221  switch (Inst.getOpcode()) {
5222  case AMDGPU::S_PACK_LL_B32_B16: {
5223  unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5224  unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5225 
5226  // FIXME: Can do a lot better if we know the high bits of src0 or src1 are
5227  // 0.
5228  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5229  .addImm(0xffff);
5230 
5231  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg)
5232  .addReg(ImmReg, RegState::Kill)
5233  .add(Src0);
5234 
5235  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
5236  .add(Src1)
5237  .addImm(16)
5238  .addReg(TmpReg, RegState::Kill);
5239  break;
5240  }
5241  case AMDGPU::S_PACK_LH_B32_B16: {
5242  unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5243  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5244  .addImm(0xffff);
5245  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
5246  .addReg(ImmReg, RegState::Kill)
5247  .add(Src0)
5248  .add(Src1);
5249  break;
5250  }
5251  case AMDGPU::S_PACK_HH_B32_B16: {
5252  unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5253  unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5254  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
5255  .addImm(16)
5256  .add(Src0);
5257  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5258  .addImm(0xffff0000);
5259  BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
5260  .add(Src1)
5261  .addReg(ImmReg, RegState::Kill)
5262  .addReg(TmpReg, RegState::Kill);
5263  break;
5264  }
5265  default:
5266  llvm_unreachable("unhandled s_pack_* instruction");
5267  }
5268 
5269  MachineOperand &Dest = Inst.getOperand(0);
5270  MRI.replaceRegWith(Dest.getReg(), ResultReg);
5271  addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5272 }
5273 
5274 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
5275  MachineInstr &SCCDefInst,
5276  SetVectorType &Worklist) const {
5277  // Ensure that def inst defines SCC, which is still live.
5278  assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
5279  !Op.isDead() && Op.getParent() == &SCCDefInst);
5280  // This assumes that all the users of SCC are in the same block
5281  // as the SCC def.
5282  for (MachineInstr &MI : // Skip the def inst itself.
5283  make_range(std::next(MachineBasicBlock::iterator(SCCDefInst)),
5284  SCCDefInst.getParent()->end())) {
5285  // Check if SCC is used first.
5286  if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1)
5287  Worklist.insert(&MI);
5288  // Exit if we find another SCC def.
5289  if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
5290  return;
5291  }
5292 }
5293 
5294 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(