#include "AArch64GlobalISelUtils.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "GISel/AArch64LegalizerInfo.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "TargetInfo/AArch64TargetInfo.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/InitializePasses.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "AArch64GenPostLegalizeGILowering.inc"

Include dependency graph for AArch64PostLegalizerLowering.cpp:

Classes
struct	ShuffleVectorPseudo
	Represents a pseudo instruction which replaces a G_SHUFFLE_VECTOR. More...

Namespaces
	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE "aarch64-postlegalizer-lowering"

#define	AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_DEPS

#define	AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_H

#define	AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_CPP

Functions
static bool	isREVMask (ArrayRef< int > M, unsigned EltSize, unsigned NumElts, unsigned BlockSize)
	Check if a vector shuffle corresponds to a REV instruction with the specified blocksize. More...

static bool	isTRNMask (ArrayRef< int > M, unsigned NumElts, unsigned &WhichResult)
	Determines if `M` is a shuffle vector mask for a TRN of `NumElts`. More...

static Optional< std::pair< bool, uint64_t > >	getExtMask (ArrayRef< int > M, unsigned NumElts)
	Check if a G_EXT instruction can handle a shuffle mask `M` when the vector sources of the shuffle are different. More...

static bool	isUZPMask (ArrayRef< int > M, unsigned NumElts, unsigned &WhichResult)
	Determines if `M` is a shuffle vector mask for a UZP of `NumElts`. More...

static bool	isZipMask (ArrayRef< int > M, unsigned NumElts, unsigned &WhichResult)

static Optional< std::pair< bool, int > >	isINSMask (ArrayRef< int > M, int NumInputElements)
	Helper function for matchINS. More...

static bool	matchREV (MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)

static bool	matchTRN (MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)

static bool	matchUZP (MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)

static bool	matchZip (MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)

static bool	matchDupFromInsertVectorElt (int Lane, MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)
	Helper function for matchDup. More...

static bool	matchDupFromBuildVector (int Lane, MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)
	Helper function for matchDup. More...

static bool	matchDup (MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)

static bool	matchEXT (MachineInstr &MI, MachineRegisterInfo &MRI, ShuffleVectorPseudo &MatchInfo)

static bool	applyShuffleVectorPseudo (MachineInstr &MI, ShuffleVectorPseudo &MatchInfo)
	Replace a G_SHUFFLE_VECTOR instruction with a pseudo. More...

static bool	applyEXT (MachineInstr &MI, ShuffleVectorPseudo &MatchInfo)
	Replace a G_SHUFFLE_VECTOR instruction with G_EXT. More...

static bool	matchINS (MachineInstr &MI, MachineRegisterInfo &MRI, std::tuple< Register, int, Register, int > &MatchInfo)
	Match a G_SHUFFLE_VECTOR with a mask which corresponds to a G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT pair. More...

static bool	applyINS (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &Builder, std::tuple< Register, int, Register, int > &MatchInfo)

static bool	isVShiftRImm (Register Reg, MachineRegisterInfo &MRI, LLT Ty, int64_t &Cnt)
	isVShiftRImm - Check if this is a valid vector for the immediate operand of a vector shift right operation. More...

static bool	matchVAshrLshrImm (MachineInstr &MI, MachineRegisterInfo &MRI, int64_t &Imm)
	Match a vector G_ASHR or G_LSHR with a valid immediate shift. More...

static bool	applyVAshrLshrImm (MachineInstr &MI, MachineRegisterInfo &MRI, int64_t &Imm)

Optional< std::pair< uint64_t, CmpInst::Predicate > >	tryAdjustICmpImmAndPred (Register RHS, CmpInst::Predicate P, const MachineRegisterInfo &MRI)
	Determine if it is possible to modify the `RHS` and predicate `P` of a G_ICMP instruction such that the right-hand side is an arithmetic immediate. More...

bool	matchAdjustICmpImmAndPred (MachineInstr &MI, const MachineRegisterInfo &MRI, std::pair< uint64_t, CmpInst::Predicate > &MatchInfo)
	Determine whether or not it is possible to update the RHS and predicate of a G_ICMP instruction such that the RHS will be selected as an arithmetic immediate. More...

bool	applyAdjustICmpImmAndPred (MachineInstr &MI, std::pair< uint64_t, CmpInst::Predicate > &MatchInfo, MachineIRBuilder &MIB, GISelChangeObserver &Observer)

bool	matchDupLane (MachineInstr &MI, MachineRegisterInfo &MRI, std::pair< unsigned, int > &MatchInfo)

bool	applyDupLane (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, std::pair< unsigned, int > &MatchInfo)

static bool	matchBuildVectorToDup (MachineInstr &MI, MachineRegisterInfo &MRI)

static bool	applyBuildVectorToDup (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B)

static unsigned	getCmpOperandFoldingProfit (Register CmpOp, const MachineRegisterInfo &MRI)

static bool	trySwapICmpOperands (MachineInstr &MI, const MachineRegisterInfo &MRI)

static bool	applySwapICmpOperands (MachineInstr &MI, GISelChangeObserver &Observer)

static std::function< Register(MachineIRBuilder &)>	getVectorFCMP (AArch64CC::CondCode CC, Register LHS, Register RHS, bool IsZero, bool NoNans, MachineRegisterInfo &MRI)

static bool	lowerVectorFCMP (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIB)
	Try to lower a vector G_FCMP `MI` into an AArch64-specific pseudo. More...

static bool	matchFormTruncstore (MachineInstr &MI, MachineRegisterInfo &MRI, Register &SrcReg)

static bool	applyFormTruncstore (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer, Register &SrcReg)

	INITIALIZE_PASS_BEGIN (AArch64PostLegalizerLowering, DEBUG_TYPE, "Lower AArch64 MachineInstrs after legalization", false, false) INITIALIZE_PASS_END(AArch64PostLegalizerLowering

FunctionPass *	llvm::createAArch64PostLegalizerLowering ()

Variables
	DEBUG_TYPE

Lower AArch64 MachineInstrs after	legalization

Lower AArch64 MachineInstrs after	false

Detailed Description

Post-legalization lowering for instructions.

This is used to offload pattern matching from the selector.

For example, this combiner will notice that a G_SHUFFLE_VECTOR is actually a G_ZIP, G_UZP, etc.

General optimization combines should be handled by either the AArch64PostLegalizerCombiner or the AArch64PreLegalizerCombiner.

Definition in file AArch64PostLegalizerLowering.cpp.

Macro Definition Documentation

◆ AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_CPP

#define AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_CPP

Definition at line 1012 of file AArch64PostLegalizerLowering.cpp.

◆ AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_DEPS

#define AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_DEPS

Definition at line 979 of file AArch64PostLegalizerLowering.cpp.

◆ AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_H

#define AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_H

Definition at line 984 of file AArch64PostLegalizerLowering.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE "aarch64-postlegalizer-lowering"

Definition at line 45 of file AArch64PostLegalizerLowering.cpp.

Function Documentation

◆ applyAdjustICmpImmAndPred()

bool applyAdjustICmpImmAndPred	(	MachineInstr &	MI,
		std::pair< uint64_t, CmpInst::Predicate > &	MatchInfo,
		MachineIRBuilder &	MIB,
		GISelChangeObserver &	Observer
	)

Definition at line 629 of file AArch64PostLegalizerLowering.cpp.

References llvm::MachineIRBuilder::buildConstant(), llvm::GISelChangeObserver::changedInstr(), llvm::GISelChangeObserver::changingInstr(), llvm::MachineRegisterInfo::cloneVirtualRegister(), llvm::MachineIRBuilder::getMRI(), MI, MRI, RHS, and llvm::MachineIRBuilder::setInstrAndDebugLoc().

◆ applyBuildVectorToDup()

static bool applyBuildVectorToDup	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	B
	)

static

Definition at line 736 of file AArch64PostLegalizerLowering.cpp.

References B, getReg(), and MI.

◆ applyDupLane()

bool applyDupLane	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	B,
		std::pair< unsigned, int > &	MatchInfo
	)

Definition at line 696 of file AArch64PostLegalizerLowering.cpp.

References assert(), B, llvm::LLT::changeElementCount(), llvm::LLT::fixed_vector(), llvm::LinearPolySize< ElementCount >::getFixed(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), MI, MRI, llvm::LLT::scalar(), and llvm::RegState::Undef.

◆ applyEXT()

static bool applyEXT	(	MachineInstr &	MI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Replace a G_SHUFFLE_VECTOR instruction with G_EXT.

Special-cased because the constant operand must be emitted as a G_CONSTANT for the imported tablegen patterns to work.

Definition at line 407 of file AArch64PostLegalizerLowering.cpp.

References llvm::MachineIRBuilder::buildConstant(), llvm::MachineIRBuilder::buildInstr(), MI, ShuffleVectorPseudo::Opc, llvm::LLT::scalar(), and ShuffleVectorPseudo::SrcOps.

◆ applyFormTruncstore()

static bool applyFormTruncstore	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	B,
		GISelChangeObserver &	Observer,
		Register &	SrcReg
	)

static

Definition at line 968 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::GISelChangeObserver::changedInstr(), llvm::GISelChangeObserver::changingInstr(), and MI.

◆ applyINS()

static bool applyINS	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	Builder,
		std::tuple< Register, int, Register, int > &	MatchInfo
	)

static

Definition at line 456 of file AArch64PostLegalizerLowering.cpp.

References Builder, llvm::LLT::getElementType(), llvm::MachineRegisterInfo::getType(), MI, MRI, and llvm::LLT::scalar().

◆ applyShuffleVectorPseudo()

static bool applyShuffleVectorPseudo	(	MachineInstr &	MI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Replace a G_SHUFFLE_VECTOR instruction with a pseudo.

Opc is the opcode to use. MI is the G_SHUFFLE_VECTOR.

Definition at line 396 of file AArch64PostLegalizerLowering.cpp.

References llvm::MachineIRBuilder::buildInstr(), MI, ShuffleVectorPseudo::Opc, and ShuffleVectorPseudo::SrcOps.

◆ applySwapICmpOperands()

static bool applySwapICmpOperands	(	MachineInstr &	MI,
		GISelChangeObserver &	Observer
	)

static

Definition at line 839 of file AArch64PostLegalizerLowering.cpp.

References llvm::GISelChangeObserver::changedInstr(), llvm::CmpInst::getSwappedPredicate(), LHS, MI, and RHS.

◆ applyVAshrLshrImm()

static bool applyVAshrLshrImm	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		int64_t &	Imm
	)

static

Definition at line 499 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::MachineIRBuilder::buildConstant(), llvm::MachineIRBuilder::buildInstr(), llvm::RISCVMatInt::Imm, MI, and llvm::LLT::scalar().

◆ getCmpOperandFoldingProfit()

static unsigned getCmpOperandFoldingProfit	(	Register	CmpOp,
		const MachineRegisterInfo &	MRI
	)

static

Returns: how many instructions would be saved by folding a G_ICMP's shift and/or extension operations.

Definition at line 747 of file AArch64PostLegalizerLowering.cpp.

References llvm::tgtok::Def, llvm::getDefIgnoringCopies(), llvm::getIConstantVRegValWithLookThrough(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::LLT::isVector(), llvm::BitmaskEnumDetail::Mask(), MI, and MRI.

Referenced by trySwapICmpOperands().

◆ getExtMask()

static Optional<std::pair<bool, uint64_t> > getExtMask	(	ArrayRef< int >	M,
		unsigned	NumElts
	)

static

Check if a G_EXT instruction can handle a shuffle mask M when the vector sources of the shuffle are different.

Definition at line 111 of file AArch64PostLegalizerLowering.cpp.

References llvm::any_of(), llvm::find_if(), llvm::APInt::getZExtValue(), llvm::RISCVMatInt::Imm, llvm::APInt::logBase2(), M, llvm::make_range(), and llvm::None.

Referenced by matchEXT().

◆ getVectorFCMP()

static std::function<Register(MachineIRBuilder &)> getVectorFCMP	(	AArch64CC::CondCode	CC,
		Register	LHS,
		Register	RHS,
		bool	IsZero,
		bool	NoNans,
		MachineRegisterInfo &	MRI
	)

static

Returns: a function which builds a vector floating point compare instruction for a condition code CC.

Parameters

[in]	IsZero	- True if the comparison is against 0.
[in]	NoNans	- True if the target has NoNansFPMath.

Definition at line 857 of file AArch64PostLegalizerLowering.cpp.

References assert(), CC, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, getReg(), llvm::MachineRegisterInfo::getType(), llvm::AArch64CC::GT, llvm::LLT::isVector(), LHS, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::MI, MRI, llvm::AArch64CC::NE, and RHS.

Referenced by lowerVectorFCMP().

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	AArch64PostLegalizerLowering	,
		DEBUG_TYPE	,
		"Lower AArch64 MachineInstrs after legalization"	,
		false	,
		false
	)

◆ isINSMask()

static Optional<std::pair<bool, int> > isINSMask	(	ArrayRef< int >	M,
		int	NumInputElements
	)

static

Helper function for matchINS.

Returns: a value when M is an ins mask for NumInputElements.

First element of the returned pair is true when the produced G_INSERT_VECTOR_ELT destination should be the LHS of the G_SHUFFLE_VECTOR.

Second element is the destination lane for the G_INSERT_VECTOR_ELT.

Definition at line 193 of file AArch64PostLegalizerLowering.cpp.

References M, and llvm::None.

Referenced by matchINS().

◆ isREVMask()

static bool isREVMask	(	ArrayRef< int >	M,
		unsigned	EltSize,
		unsigned	NumElts,
		unsigned	BlockSize
	)

static

Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.

Definition at line 66 of file AArch64PostLegalizerLowering.cpp.

References assert(), BlockSize, i, and M.

Referenced by matchREV().

◆ isTRNMask()

static bool isTRNMask	(	ArrayRef< int >	M,
		unsigned	NumElts,
		unsigned &	WhichResult
	)

static

Determines if M is a shuffle vector mask for a TRN of NumElts.

Whether or not G_TRN1 or G_TRN2 should be used is stored in WhichResult.

Definition at line 95 of file AArch64PostLegalizerLowering.cpp.

References i, and M.

Referenced by matchTRN().

◆ isUZPMask()

static bool isUZPMask	(	ArrayRef< int >	M,
		unsigned	NumElts,
		unsigned &	WhichResult
	)

static

Determines if M is a shuffle vector mask for a UZP of NumElts.

Whether or not G_UZP1 or G_UZP2 should be used is stored in WhichResult.

Definition at line 153 of file AArch64PostLegalizerLowering.cpp.

References i, and M.

Referenced by matchUZP().

◆ isVShiftRImm()

static bool isVShiftRImm	(	Register	Reg,
		MachineRegisterInfo &	MRI,
		LLT	Ty,
		int64_t &	Cnt
	)

static

isVShiftRImm - Check if this is a valid vector for the immediate operand of a vector shift right operation.

The value must be in the range: 1 <= Value <= ElementBits for a right shift.

Definition at line 476 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::AArch64GISelUtils::getAArch64VectorSplatScalar(), llvm::LLT::getScalarSizeInBits(), llvm::MachineRegisterInfo::getVRegDef(), llvm::LLT::isVector(), MI, and MRI.

Referenced by matchVAshrLshrImm().

◆ isZipMask()

static bool isZipMask	(	ArrayRef< int >	M,
		unsigned	NumElts,
		unsigned &	WhichResult
	)

static

Returns: true if M is a zip mask for a shuffle vector of NumElts. Whether or not G_ZIP1 or G_ZIP2 should be used is stored in WhichResult.

Definition at line 168 of file AArch64PostLegalizerLowering.cpp.

References i, and M.

Referenced by matchZip().

◆ lowerVectorFCMP()

static bool lowerVectorFCMP	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	MIB
	)

static

Try to lower a vector G_FCMP MI into an AArch64-specific pseudo.

Definition at line 911 of file AArch64PostLegalizerLowering.cpp.

References llvm::AArch64CC::AL, assert(), llvm::MachineIRBuilder::buildNot(), llvm::MachineIRBuilder::buildOr(), CC, llvm::AArch64GISelUtils::changeVectorFCMPPredToAArch64CC(), llvm::AArch64GISelUtils::getAArch64VectorSplat(), llvm::MachineInstrBuilder::getReg(), llvm::LLT::getScalarSizeInBits(), llvm::MachineRegisterInfo::getType(), getVectorFCMP(), llvm::MachineRegisterInfo::getVRegDef(), llvm::LLT::isVector(), LHS, MI, MRI, llvm::MachineRegisterInfo::replaceRegWith(), RHS, llvm::MachineIRBuilder::setInstrAndDebugLoc(), and llvm::ARM_MB::ST.

◆ matchAdjustICmpImmAndPred()

bool matchAdjustICmpImmAndPred	(	MachineInstr &	MI,
		const MachineRegisterInfo &	MRI,
		std::pair< uint64_t, CmpInst::Predicate > &	MatchInfo
	)

Determine whether or not it is possible to update the RHS and predicate of a G_ICMP instruction such that the RHS will be selected as an arithmetic immediate.

MI - The G_ICMP instruction MatchInfo - The new RHS immediate and predicate on success

See tryAdjustICmpImmAndPred for valid transformations.

Definition at line 616 of file AArch64PostLegalizerLowering.cpp.

References assert(), MI, MRI, RHS, and tryAdjustICmpImmAndPred().

◆ matchBuildVectorToDup()

static bool matchBuildVectorToDup	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI
	)

static

Definition at line 722 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::AArch64GISelUtils::getAArch64VectorSplat(), MI, and MRI.

◆ matchDup()

static bool matchDup	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Definition at line 356 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::getSplatIndex(), matchDupFromBuildVector(), matchDupFromInsertVectorElt(), MI, and MRI.

◆ matchDupFromBuildVector()

static bool matchDupFromBuildVector	(	int	Lane,
		MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Helper function for matchDup.

Definition at line 340 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::getOpcodeDef(), MI, and MRI.

Referenced by matchDup().

◆ matchDupFromInsertVectorElt()

static bool matchDupFromInsertVectorElt	(	int	Lane,
		MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Helper function for matchDup.

Definition at line 301 of file AArch64PostLegalizerLowering.cpp.

References llvm::getOpcodeDef(), llvm::MIPatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), and MRI.

Referenced by matchDup().

◆ matchDupLane()

bool matchDupLane	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		std::pair< unsigned, int > &	MatchInfo
	)

Definition at line 644 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::getSplatIndex(), llvm::MachineRegisterInfo::getType(), MI, and MRI.

◆ matchEXT()

static bool matchEXT	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Definition at line 373 of file AArch64PostLegalizerLowering.cpp.

References assert(), getExtMask(), llvm::LLT::getNumElements(), llvm::LLT::getScalarSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::RISCVMatInt::Imm, MI, MRI, std::swap(), and llvm::NVPTX::PTXLdStInstCode::V2.

◆ matchFormTruncstore()

static bool matchFormTruncstore	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		Register &	SrcReg
	)

static

Definition at line 955 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isVector(), llvm::MIPatternMatch::m_GTrunc(), llvm::MIPatternMatch::m_Reg(), MI, llvm::MIPatternMatch::mi_match(), and MRI.

◆ matchINS()

static bool matchINS	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		std::tuple< Register, int, Register, int > &	MatchInfo
	)

static

Match a G_SHUFFLE_VECTOR with a mask which corresponds to a G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT pair.

e.g. shuf = G_SHUFFLE_VECTOR left, right, shufflemask(0, 0)

Can be represented as

extract = G_EXTRACT_VECTOR_ELT left, 0 ins = G_INSERT_VECTOR_ELT left, extract, 1

Definition at line 429 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), isINSMask(), llvm::Left, MI, MRI, and Right.

◆ matchREV()

static bool matchREV	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Returns: true if a G_SHUFFLE_VECTOR instruction MI can be replaced with a G_REV instruction. Returns the appropriate G_REV opcode in Opc.

Definition at line 218 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::LLT::getScalarSizeInBits(), llvm::MachineRegisterInfo::getType(), isREVMask(), MI, and MRI.

◆ matchTRN()

static bool matchTRN	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Returns: true if a G_SHUFFLE_VECTOR instruction MI can be replaced with a G_TRN1 or G_TRN2 instruction.

Definition at line 247 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), isTRNMask(), MI, MRI, and llvm::NVPTX::PTXLdStInstCode::V2.

◆ matchUZP()

static bool matchUZP	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Returns: true if a G_SHUFFLE_VECTOR instruction MI can be replaced with a G_UZP1 or G_UZP2 instruction.

Parameters

[in]	MI	- The shuffle vector instruction.
[out]	MatchInfo	- Either G_UZP1 or G_UZP2 on success.

Definition at line 268 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), isUZPMask(), MI, MRI, and llvm::NVPTX::PTXLdStInstCode::V2.

◆ matchVAshrLshrImm()

static bool matchVAshrLshrImm	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		int64_t &	Imm
	)

static

Match a vector G_ASHR or G_LSHR with a valid immediate shift.

Definition at line 489 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::MachineRegisterInfo::getType(), llvm::RISCVMatInt::Imm, llvm::LLT::isVector(), isVShiftRImm(), MI, and MRI.

◆ matchZip()

static bool matchZip	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		ShuffleVectorPseudo &	MatchInfo
	)

static

Definition at line 284 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), isZipMask(), MI, MRI, and llvm::NVPTX::PTXLdStInstCode::V2.

◆ tryAdjustICmpImmAndPred()

Optional<std::pair<uint64_t, CmpInst::Predicate> > tryAdjustICmpImmAndPred	(	Register	RHS,
		CmpInst::Predicate	P,
		const MachineRegisterInfo &	MRI
	)

Determine if it is possible to modify the RHS and predicate P of a G_ICMP instruction such that the right-hand side is an arithmetic immediate.

Returns: A pair containing the updated immediate and predicate which may be used to optimize the instruction.

Note: This assumes that the comparison has been legalized.

Definition at line 520 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::getIConstantVRegValWithLookThrough(), llvm::MachineRegisterInfo::getType(), llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, INT64_MAX, INT64_MIN, isLegalArithImmed(), MRI, llvm::None, P, RHS, and UINT64_MAX.

Referenced by matchAdjustICmpImmAndPred().

◆ trySwapICmpOperands()

static bool trySwapICmpOperands	(	MachineInstr &	MI,
		const MachineRegisterInfo &	MRI
	)

static

Returns: true if it would be profitable to swap the LHS and RHS of a G_ICMP instruction MI.

Definition at line 802 of file AArch64PostLegalizerLowering.cpp.

References assert(), llvm::tgtok::Def, getCmpOperandFoldingProfit(), llvm::getDefIgnoringCopies(), llvm::getIConstantVRegValWithLookThrough(), isCMN(), isLegalArithImmed(), LHS, MI, MRI, and RHS.

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 1062 of file AArch64PostLegalizerLowering.cpp.

◆ false

Lower AArch64 MachineInstrs after false

Definition at line 1063 of file AArch64PostLegalizerLowering.cpp.

◆ legalization

Lower AArch64 MachineInstrs after legalization

Definition at line 1063 of file AArch64PostLegalizerLowering.cpp.

Classes

Namespaces

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_CPP

◆ AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_DEPS

◆ AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_H

◆ DEBUG_TYPE

Function Documentation

◆ applyAdjustICmpImmAndPred()

◆ applyBuildVectorToDup()

◆ applyDupLane()

◆ applyEXT()

◆ applyFormTruncstore()

◆ applyINS()

◆ applyShuffleVectorPseudo()

◆ applySwapICmpOperands()

◆ applyVAshrLshrImm()

◆ getCmpOperandFoldingProfit()

◆ getExtMask()

◆ getVectorFCMP()

◆ INITIALIZE_PASS_BEGIN()

◆ isINSMask()

◆ isREVMask()

◆ isTRNMask()

◆ isUZPMask()

◆ isVShiftRImm()

◆ isZipMask()

◆ lowerVectorFCMP()

◆ matchAdjustICmpImmAndPred()

◆ matchBuildVectorToDup()

◆ matchDup()

◆ matchDupFromBuildVector()

◆ matchDupFromInsertVectorElt()

◆ matchDupLane()

◆ matchEXT()

◆ matchFormTruncstore()

◆ matchINS()

◆ matchREV()

◆ matchTRN()

◆ matchUZP()

◆ matchVAshrLshrImm()

◆ matchZip()

◆ tryAdjustICmpImmAndPred()

◆ trySwapICmpOperands()

Variable Documentation

◆ DEBUG_TYPE

◆ false

◆ legalization