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13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
95 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
96 bool ATTRIBUTE = DEFAULT;
97 #include "AArch64GenSubtargetInfo.inc"
146 void initializeProperties();
152 const std::string &TuneCPU,
const std::string &
FS,
154 unsigned MinSVEVectorSizeInBitsOverride = 0,
155 unsigned MaxSVEVectorSizeInBitsOverride = 0);
158 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
159 bool GETTER() const { return ATTRIBUTE; }
160 #include "AArch64GenSubtargetInfo.inc"
207 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
208 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
209 hasFuseAdrpAdd() || hasFuseLiterals();
217 unsigned NumStridedMemAccesses,
218 unsigned NumPrefetches,
219 bool HasCall)
const override {
258 bool useAA()
const override;
291 unsigned NumRegionInstrs)
const override;
319 unsigned Major = TT.getOSVersion().getMajor();
340 assert(HasSVE &&
"Tried to get SVE vector length without SVE support!");
345 assert(HasSVE &&
"Tried to get SVE vector length without SVE support!");
bool isTargetWindows() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
This is an optimization pass for GlobalISel generic memory operations.
unsigned getVectorInsertExtractBaseCost() const
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
unsigned MaxJumpTableSize
bool isTargetCOFF() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
unsigned getPrefFunctionLogAlignment() const
unsigned getMinSVEVectorSizeInBits() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
uint8_t MaxInterleaveFactor
std::unique_ptr< InstructionSelector > InstSelector
bool isTargetDarwin() const
Triple - Helper class for working with autoconf configuration names.
AArch64TargetLowering TLInfo
const AArch64InstrInfo * getInstrInfo() const override
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
uint16_t MinPrefetchStride
uint8_t VectorInsertExtractBaseCost
bool isOSLinux() const
Tests whether the OS is Linux.
bool isXRegCustomCalleeSaved(size_t i) const
unsigned MaxBytesForLoopAlignment
unsigned getPrefetchDistance() const override
unsigned PrefLoopLogAlignment
const AArch64TargetLowering * getTargetLowering() const override
bool enablePostRAScheduler() const override
bool addrSinkUsingGEPs() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
unsigned getMinVectorRegisterBitWidth() const
bool isAndroid() const
Tests whether the target is Android.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned MinSVEVectorSizeInBits
InstructionSelector * getInstructionSelector() const override
bool isLittleEndian() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
unsigned getMaximumJumpTableSize() const
bool isTargetILP32() const
size_type count() const
count - Returns the number of bits which are set.
bool enableEarlyIfConversion() const override
void mirFileLoaded(MachineFunction &MF) const override
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
bool isXRaySupported() const override
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
unsigned getCacheLineSize() const override
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
unsigned PrefFunctionLogAlignment
unsigned MaxSVEVectorSizeInBits
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
const CallLowering * getCallLowering() const override
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
BitVector ReserveXRegister
bool useSVEForFixedLengthVectors() const
bool any() const
any - Returns true if any bit is set.
bool useSmallAddressing() const
bool isArch32Bit() const
Test whether the architecture is 32-bit.
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
bool enableMachineScheduler() const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
bool isTargetLinux() const
unsigned MinVectorRegisterBitWidth
bool isCallingConvWin64(CallingConv::ID CC) const
AArch64SelectionDAGInfo TSInfo
unsigned getMaxInterleaveFactor() const
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool hasCustomCallingConv() const
bool isXRegisterReserved(size_t i) const
StringRef - Represent a constant reference to a string, i.e.
std::unique_ptr< LegalizerInfo > Legalizer
const Triple & getTargetTriple() const
@ C
C - The default llvm calling convention, compatible with C.
const AArch64FrameLowering * getFrameLowering() const override
unsigned getVScaleForTuning() const
unsigned getMaxBytesForLoopAlignment() const
bool isiOS() const
Is this an iOS triple.
bool isOSWindows() const
Tests whether the OS is Windows.
const AArch64RegisterInfo * getRegisterInfo() const override
const TargetMachine & getTargetMachine() const
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getNumXRegisterReserved() const
const RegisterBankInfo * getRegBankInfo() const override
unsigned getMaxSVEVectorSizeInBits() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
CodeModel::Model getCodeModel() const
Returns the code model.
uint16_t PrefetchDistance
unsigned MaxPrefetchIterationsAhead
bool isTargetFuchsia() const
AArch64InstrInfo InstrInfo
bool isTargetMachO() const
unsigned getMaxPrefetchIterationsAhead() const override
unsigned getPrefLoopLogAlignment() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
const LegalizerInfo * getLegalizerInfo() const override
const char LLVMTargetMachineRef TM
BitVector CustomCallSavedXRegs
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
bool useAA() const override
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
AArch64FrameLowering FrameLowering
bool isTargetAndroid() const