13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
30#define GET_SUBTARGETINFO_HEADER
31#include "AArch64GenSubtargetInfo.inc"
101#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
102 bool ATTRIBUTE = DEFAULT;
103#include "AArch64GenSubtargetInfo.inc"
156 void initializeProperties();
163 unsigned MinSVEVectorSizeInBitsOverride = 0,
164 unsigned MaxSVEVectorSizeInBitsOverride = 0,
168#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
169 bool GETTER() const { return ATTRIBUTE; }
170#include "AArch64GenSubtargetInfo.inc"
214 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
217 return AllReservedX.
count();
226 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
227 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
228 hasFuseAdrpAdd() || hasFuseLiterals();
236 unsigned NumStridedMemAccesses,
237 unsigned NumPrefetches,
238 bool HasCall)
const override {
278 bool useAA()
const override;
319 unsigned NumRegionInstrs)
const override;
347 unsigned Major = TT.getOSVersion().getMajor();
371 "Tried to get SVE vector length without SVE support!");
377 "Tried to get SVE vector length without SVE support!");
395 return "__chkstk_arm64ec";
401 return "__security_check_cookie_arm64ec";
402 return "__security_check_cookie";
This file describes how to lower LLVM calls to machine code calls.
This file describes how to lower LLVM inline asm to machine code INLINEASM.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool isTargetWindows() const
BitVector ReserveXRegisterForRA
BitVector ReserveXRegister
bool isStreamingSVEModeDisabled() const
const CallLowering * getCallLowering() const override
const AArch64RegisterInfo * getRegisterInfo() const override
bool forceStreamingCompatibleSVE() const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
BitVector CustomCallSavedXRegs
bool addrSinkUsingGEPs() const override
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
const AArch64InstrInfo * getInstrInfo() const override
bool useSmallAddressing() const
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
AArch64SelectionDAGInfo TSInfo
const char * getSecurityCheckCookieName() const
unsigned getMaximumJumpTableSize() const
bool StreamingSVEModeDisabled
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
AArch64FrameLowering FrameLowering
bool isTargetDarwin() const
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned MaxPrefetchIterationsAhead
unsigned getCacheLineSize() const override
bool isTargetILP32() const
unsigned getVectorInsertExtractBaseCost() const
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
uint8_t VectorInsertExtractBaseCost
const AArch64TargetLowering * getTargetLowering() const override
Align getPrefLoopAlignment() const
Align getPrefFunctionAlignment() const
bool isTargetMachO() const
unsigned getMaxBytesForLoopAlignment() const
uint16_t PrefetchDistance
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
unsigned getMaxInterleaveFactor() const
bool isTargetAndroid() const
Align PrefFunctionAlignment
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override
This function is design to compatible with the function def in other targets and escape build error a...
const Triple & getTargetTriple() const
unsigned MinVectorRegisterBitWidth
bool isCallingConvWin64(CallingConv::ID CC) const
const char * getChkStkName() const
bool isXRegCustomCalleeSaved(size_t i) const
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
uint16_t MinPrefetchStride
bool useSVEForFixedLengthVectors() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
bool isLittleEndian() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned MaxJumpTableSize
unsigned getMinVectorRegisterBitWidth() const
bool isWindowsArm64EC() const
unsigned MinSVEVectorSizeInBits
bool isXRegisterReserved(size_t i) const
unsigned getMaxPrefetchIterationsAhead() const override
bool isTargetFuchsia() const
const LegalizerInfo * getLegalizerInfo() const override
bool enableMachineScheduler() const override
bool enablePostRAScheduler() const override
unsigned MaxSVEVectorSizeInBits
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
uint8_t MaxInterleaveFactor
unsigned getMaxSVEVectorSizeInBits() const
unsigned getVScaleForTuning() const
bool isTargetLinux() const
unsigned getMinSVEVectorSizeInBits() const
AArch64InstrInfo InstrInfo
AArch64TargetLowering TLInfo
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned MaxBytesForLoopAlignment
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
bool isTargetCOFF() const
bool isXRaySupported() const override
bool hasCustomCallingConv() const
const AArch64FrameLowering * getFrameLowering() const override
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
unsigned getPrefetchDistance() const override
size_type count() const
count - Returns the number of bits which are set.
bool any() const
any - Returns true if any bit is set.
Provides the logic to select generic machine instructions.
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
const TargetMachine & getTargetMachine() const
Primary interface to the complete machine description for the target machine.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
bool isAndroid() const
Tests whether the target is Android.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSLinux() const
Tests whether the OS is Linux.
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
bool isWindowsArm64EC() const
bool isiOS() const
Is this an iOS triple.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
@ Swift
Calling convention for Swift.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.