LLVM  16.0.0git
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
90  };
91 
92 protected:
93  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
95 
96  // Enable 64-bit vectorization in SLP.
98 
99 // Bool members corresponding to the SubtargetFeatures defined in tablegen
100 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
101  bool ATTRIBUTE = DEFAULT;
102 #include "AArch64GenSubtargetInfo.inc"
103 
104  uint8_t MaxInterleaveFactor = 2;
109  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
111  unsigned PrefLoopLogAlignment = 0;
113  unsigned MaxJumpTableSize = 0;
114 
115  // ReserveXRegister[i] - X#i is not available as a general purpose register.
117 
118  // ReserveXRegisterForRA[i] - X#i is not available for register allocator.
120 
121  // CustomCallUsedXRegister[i] - X#i call saved.
123 
124  bool IsLittle;
125 
129  unsigned VScaleForTuning = 2;
130 
131  /// TargetTriple - What processor and OS we're targeting.
133 
138 
139  /// GlobalISel related APIs.
140  std::unique_ptr<CallLowering> CallLoweringInfo;
141  std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
142  std::unique_ptr<InstructionSelector> InstSelector;
143  std::unique_ptr<LegalizerInfo> Legalizer;
144  std::unique_ptr<RegisterBankInfo> RegBankInfo;
145 
146 private:
147  /// initializeSubtargetDependencies - Initializes using CPUString and the
148  /// passed in feature string so that we can use initializer lists for
149  /// subtarget initialization.
150  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
151  StringRef CPUString,
152  StringRef TuneCPUString);
153 
154  /// Initialize properties based on the selected processor family.
155  void initializeProperties();
156 
157 public:
158  /// This constructor initializes the data members to match that
159  /// of the specified triple.
160  AArch64Subtarget(const Triple &TT, const std::string &CPU,
161  const std::string &TuneCPU, const std::string &FS,
162  const TargetMachine &TM, bool LittleEndian,
163  unsigned MinSVEVectorSizeInBitsOverride = 0,
164  unsigned MaxSVEVectorSizeInBitsOverride = 0,
165  bool StreamingSVEModeDisabled = true);
166 
167 // Getters for SubtargetFeatures defined in tablegen
168 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
169  bool GETTER() const { return ATTRIBUTE; }
170 #include "AArch64GenSubtargetInfo.inc"
171 
173  return &TSInfo;
174  }
175  const AArch64FrameLowering *getFrameLowering() const override {
176  return &FrameLowering;
177  }
178  const AArch64TargetLowering *getTargetLowering() const override {
179  return &TLInfo;
180  }
181  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
182  const AArch64RegisterInfo *getRegisterInfo() const override {
183  return &getInstrInfo()->getRegisterInfo();
184  }
185  const CallLowering *getCallLowering() const override;
186  const InlineAsmLowering *getInlineAsmLowering() const override;
188  const LegalizerInfo *getLegalizerInfo() const override;
189  const RegisterBankInfo *getRegBankInfo() const override;
190  const Triple &getTargetTriple() const { return TargetTriple; }
191  bool enableMachineScheduler() const override { return true; }
192  bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
193 
194  /// Returns ARM processor family.
195  /// Avoid this function! CPU specifics should be kept local to this class
196  /// and preferably modeled with SubtargetFeatures or properties in
197  /// initializeProperties().
199  return ARMProcFamily;
200  }
201 
202  bool isXRaySupported() const override { return true; }
203 
204  unsigned getMinVectorRegisterBitWidth() const {
205  // Don't assume any minimum vector size when PSTATE.SM may not be 0.
207  return 0;
209  }
210 
211  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
212  bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
213  unsigned getNumXRegisterReserved() const {
214  BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
215  AllReservedX |= ReserveXRegister;
216  AllReservedX |= ReserveXRegisterForRA;
217  return AllReservedX.count();
218  }
219  bool isXRegCustomCalleeSaved(size_t i) const {
220  return CustomCallSavedXRegs[i];
221  }
222  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
223 
224  /// Return true if the CPU supports any kind of instruction fusion.
225  bool hasFusion() const {
226  return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
227  hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
228  hasFuseAdrpAdd() || hasFuseLiterals();
229  }
230 
231  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
232  unsigned getVectorInsertExtractBaseCost() const;
233  unsigned getCacheLineSize() const override { return CacheLineSize; }
234  unsigned getPrefetchDistance() const override { return PrefetchDistance; }
235  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
236  unsigned NumStridedMemAccesses,
237  unsigned NumPrefetches,
238  bool HasCall) const override {
239  return MinPrefetchStride;
240  }
241  unsigned getMaxPrefetchIterationsAhead() const override {
243  }
244  unsigned getPrefFunctionLogAlignment() const {
246  }
247  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
248 
249  unsigned getMaxBytesForLoopAlignment() const {
251  }
252 
253  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
254 
255  /// CPU has TBI (top byte of addresses is ignored during HW address
256  /// translation) and OS enables it.
257  bool supportsAddressTopByteIgnored() const;
258 
259  bool isLittleEndian() const { return IsLittle; }
260 
261  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
262  bool isTargetIOS() const { return TargetTriple.isiOS(); }
263  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
264  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
265  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
266  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
267  bool isWindowsArm64EC() const { return TargetTriple.isWindowsArm64EC(); }
268 
269  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
270  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
271  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
272 
273  bool isTargetILP32() const {
274  return TargetTriple.isArch32Bit() ||
276  }
277 
278  bool useAA() const override;
279 
280  bool addrSinkUsingGEPs() const override {
281  // Keeping GEPs inbounds is important for exploiting AArch64
282  // addressing-modes in ILP32 mode.
283  return useAA() || isTargetILP32();
284  }
285 
286  bool useSmallAddressing() const {
287  switch (TLInfo.getTargetMachine().getCodeModel()) {
288  case CodeModel::Kernel:
289  // Kernel is currently allowed only for Fuchsia targets,
290  // where it is the same as Small for almost all purposes.
291  case CodeModel::Small:
292  return true;
293  default:
294  return false;
295  }
296  }
297 
298  /// ParseSubtargetFeatures - Parses features string setting specified
299  /// subtarget options. Definition of function is auto generated by tblgen.
301 
302  /// ClassifyGlobalReference - Find the target operand flags that describe
303  /// how a global value should be referenced for the current subtarget.
304  unsigned ClassifyGlobalReference(const GlobalValue *GV,
305  const TargetMachine &TM) const;
306 
307  unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
308  const TargetMachine &TM) const;
309 
310  /// This function is design to compatible with the function def in other
311  /// targets and escape build error about the virtual function def in base
312  /// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
313  unsigned char
314  classifyGlobalFunctionReference(const GlobalValue *GV) const override {
315  return 0;
316  }
317 
319  unsigned NumRegionInstrs) const override;
320 
321  bool enableEarlyIfConversion() const override;
322 
323  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
324 
326  switch (CC) {
327  case CallingConv::C:
328  case CallingConv::Fast:
329  case CallingConv::Swift:
330  return isTargetWindows();
331  case CallingConv::Win64:
332  return true;
333  default:
334  return false;
335  }
336  }
337 
338  /// Return whether FrameLowering should always set the "extended frame
339  /// present" bit in FP, or set it based on a symbol in the runtime.
341  // Older OS versions (particularly system unwinders) are confused by the
342  // Swift extended frame, so when building code that might be run on them we
343  // must dynamically query the concurrency library to determine whether
344  // extended frames should be flagged as present.
345  const Triple &TT = getTargetTriple();
346 
347  unsigned Major = TT.getOSVersion().getMajor();
348  switch(TT.getOS()) {
349  default:
350  return false;
351  case Triple::IOS:
352  case Triple::TvOS:
353  return Major < 15;
354  case Triple::WatchOS:
355  return Major < 8;
356  case Triple::MacOSX:
357  case Triple::Darwin:
358  return Major < 12;
359  }
360  }
361 
362  void mirFileLoaded(MachineFunction &MF) const override;
363 
364  bool hasSVEorSME() const { return hasSVE() || hasSME(); }
365 
366  // Return the known range for the bit length of SVE data registers. A value
367  // of 0 means nothing is known about that particular limit beyong what's
368  // implied by the architecture.
369  unsigned getMaxSVEVectorSizeInBits() const {
370  assert(hasSVEorSME() &&
371  "Tried to get SVE vector length without SVE support!");
372  return MaxSVEVectorSizeInBits;
373  }
374 
375  unsigned getMinSVEVectorSizeInBits() const {
376  assert(hasSVEorSME() &&
377  "Tried to get SVE vector length without SVE support!");
378  return MinSVEVectorSizeInBits;
379  }
380 
383  return true;
384 
385  // Prefer NEON unless larger SVE registers are available.
386  return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
387  }
388 
389  bool forceStreamingCompatibleSVE() const;
390 
391  unsigned getVScaleForTuning() const { return VScaleForTuning; }
392 
393  const char* getChkStkName() const {
394  if (isWindowsArm64EC())
395  return "__chkstk_arm64ec";
396  return "__chkstk";
397  }
398 
399  const char* getSecurityCheckCookieName() const {
400  if (isWindowsArm64EC())
401  return "__security_check_cookie_arm64ec";
402  return "__security_check_cookie";
403  }
404 
406 };
407 } // End llvm namespace
408 
409 #endif
i
i
Definition: README.txt:29
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:54
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:46
llvm::AArch64Subtarget::isTargetWindows
bool isTargetWindows() const
Definition: AArch64Subtarget.h:264
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
AArch64RegisterInfo.h
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:430
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64Subtarget::getVectorInsertExtractBaseCost
unsigned getVectorInsertExtractBaseCost() const
Definition: AArch64Subtarget.cpp:72
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:94
llvm::AArch64Subtarget::swiftAsyncContextIsDynamicallySet
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
Definition: AArch64Subtarget.h:340
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:83
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:239
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:113
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:57
CallLowering.h
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::isTargetIOS
bool isTargetIOS() const
Definition: AArch64Subtarget.h:262
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:85
llvm::AArch64Subtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: AArch64Subtarget.h:269
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:88
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:678
llvm::AArch64Subtarget::CortexX1C
@ CortexX1C
Definition: AArch64Subtarget.h:70
llvm::AArch64Subtarget::getPrefFunctionLogAlignment
unsigned getPrefFunctionLogAlignment() const
Definition: AArch64Subtarget.h:244
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:63
llvm::Triple::Darwin
@ Darwin
Definition: Triple.h:189
llvm::AArch64Subtarget::getMinSVEVectorSizeInBits
unsigned getMinSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:375
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:144
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:59
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:140
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:78
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:62
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:104
RegisterBankInfo.h
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:142
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:261
llvm::AArch64Subtarget::isTargetELF
bool isTargetELF() const
Definition: AArch64Subtarget.h:270
llvm::Triple::IOS
@ IOS
Definition: Triple.h:193
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AArch64Subtarget::TLInfo
AArch64TargetLowering TLInfo
Definition: AArch64Subtarget.h:137
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEModeDisabled=true)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:278
llvm::AArch64Subtarget::getInstrInfo
const AArch64InstrInfo * getInstrInfo() const override
Definition: AArch64Subtarget.h:181
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:108
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:105
llvm::AArch64Subtarget::ReserveXRegisterForRA
BitVector ReserveXRegisterForRA
Definition: AArch64Subtarget.h:119
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override
This function is design to compatible with the function def in other targets and escape build error a...
Definition: AArch64Subtarget.h:314
llvm::AArch64Subtarget::getSecurityCheckCookieName
const char * getSecurityCheckCookieName() const
Definition: AArch64Subtarget.h:399
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:636
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:52
llvm::AArch64Subtarget::isXRegCustomCalleeSaved
bool isXRegCustomCalleeSaved(size_t i) const
Definition: AArch64Subtarget.h:219
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:84
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:89
llvm::AArch64Subtarget::CortexX2
@ CortexX2
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:47
llvm::AArch64Subtarget::MaxBytesForLoopAlignment
unsigned MaxBytesForLoopAlignment
Definition: AArch64Subtarget.h:112
llvm::AArch64Subtarget::isStreamingSVEModeDisabled
bool isStreamingSVEModeDisabled() const
Definition: AArch64Subtarget.h:405
llvm::AArch64Subtarget::AppleA15
@ AppleA15
Definition: AArch64Subtarget.h:50
AArch64SelectionDAGInfo.h
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::AArch64Subtarget::getPrefetchDistance
unsigned getPrefetchDistance() const override
Definition: AArch64Subtarget.h:234
llvm::AArch64Subtarget::isWindowsArm64EC
bool isWindowsArm64EC() const
Definition: AArch64Subtarget.h:267
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:111
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:64
LegalizerInfo.h
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:77
llvm::Triple::WatchOS
@ WatchOS
Definition: Triple.h:215
llvm::AArch64Subtarget::CortexA715
@ CortexA715
Definition: AArch64Subtarget.h:67
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:178
llvm::AArch64Subtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
Definition: AArch64Subtarget.h:192
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:80
llvm::AArch64Subtarget::addrSinkUsingGEPs
bool addrSinkUsingGEPs() const override
Definition: AArch64Subtarget.h:280
llvm::AArch64FrameLowering
Definition: AArch64FrameLowering.h:21
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:444
llvm::AArch64Subtarget::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AArch64Subtarget.h:204
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:723
llvm::AArch64SelectionDAGInfo
Definition: AArch64SelectionDAGInfo.h:20
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:673
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:331
AArch64InstrInfo.h
llvm::AArch64Subtarget::MinSVEVectorSizeInBits
unsigned MinSVEVectorSizeInBits
Definition: AArch64Subtarget.h:127
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:335
InlineAsmLowering.h
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:36
llvm::Triple::TvOS
@ TvOS
Definition: Triple.h:214
llvm::AArch64Subtarget::isLittleEndian
bool isLittleEndian() const
Definition: AArch64Subtarget.h:259
llvm::AArch64Subtarget::AppleA16
@ AppleA16
Definition: AArch64Subtarget.h:51
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:517
llvm::AArch64Subtarget::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Definition: AArch64Subtarget.h:253
llvm::AArch64Subtarget::isTargetILP32
bool isTargetILP32() const
Definition: AArch64Subtarget.h:273
llvm::CallingConv::Swift
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
llvm::BitVector::count
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:155
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:106
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:426
llvm::AArch64Subtarget::Neoverse512TVB
@ Neoverse512TVB
Definition: AArch64Subtarget.h:79
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:448
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:686
AArch64GenSubtargetInfo
llvm::AArch64Subtarget::isXRaySupported
bool isXRaySupported() const override
Definition: AArch64Subtarget.h:202
llvm::AArch64Subtarget::VScaleForTuning
unsigned VScaleForTuning
Definition: AArch64Subtarget.h:129
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:65
llvm::BitVector
Definition: BitVector.h:75
llvm::AArch64Subtarget::getProcFamily
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
Definition: AArch64Subtarget.h:198
llvm::AArch64Subtarget::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: AArch64Subtarget.h:233
llvm::AArch64Subtarget::IsLittle
bool IsLittle
Definition: AArch64Subtarget.h:124
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:110
llvm::Triple::isOSFuchsia
bool isOSFuchsia() const
Definition: Triple.h:547
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:69
llvm::AArch64Subtarget::MaxSVEVectorSizeInBits
unsigned MaxSVEVectorSizeInBits
Definition: AArch64Subtarget.h:128
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:87
InstructionSelector.h
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:156
llvm::AArch64Subtarget::getSelectionDAGInfo
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: AArch64Subtarget.h:172
llvm::AArch64Subtarget::forceStreamingCompatibleSVE
bool forceStreamingCompatibleSVE() const
Definition: AArch64Subtarget.cpp:460
llvm::AArch64Subtarget::isXRegisterReservedForRA
bool isXRegisterReservedForRA(size_t i) const
Definition: AArch64Subtarget.h:212
llvm::Triple::MacOSX
@ MacOSX
Definition: Triple.h:197
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:327
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:116
llvm::Triple::isWindowsArm64EC
bool isWindowsArm64EC() const
Definition: Triple.h:598
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:61
AArch64FrameLowering.h
llvm::AArch64Subtarget::useSVEForFixedLengthVectors
bool useSVEForFixedLengthVectors() const
Definition: AArch64Subtarget.h:381
llvm::BitVector::any
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:163
llvm::AArch64Subtarget::Ampere1
@ Ampere1
Definition: AArch64Subtarget.h:43
llvm::AArch64Subtarget::getChkStkName
const char * getChkStkName() const
Definition: AArch64Subtarget.h:393
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:286
llvm::Triple::isArch32Bit
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1466
llvm::AArch64Subtarget::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
Definition: AArch64Subtarget.h:235
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:49
llvm::AArch64Subtarget::hasSVEorSME
bool hasSVEorSME() const
Definition: AArch64Subtarget.h:364
llvm::AArch64Subtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: AArch64Subtarget.h:191
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:76
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::AArch64Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: AArch64Subtarget.h:263
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:97
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:325
llvm::AArch64Subtarget::TSInfo
AArch64SelectionDAGInfo TSInfo
Definition: AArch64Subtarget.h:136
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AArch64Subtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: AArch64Subtarget.h:231
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: AArch64Subtarget.cpp:385
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:222
llvm::AArch64Subtarget::CortexA710
@ CortexA710
Definition: AArch64Subtarget.h:66
llvm::AArch64Subtarget::isXRegisterReserved
bool isXRegisterReserved(size_t i) const
Definition: AArch64Subtarget.h:211
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::AArch64Subtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: AArch64Subtarget.h:143
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:190
llvm::AArch64Subtarget::getFrameLowering
const AArch64FrameLowering * getFrameLowering() const override
Definition: AArch64Subtarget.h:175
TargetSubtargetInfo.h
llvm::AArch64Subtarget::getVScaleForTuning
unsigned getVScaleForTuning() const
Definition: AArch64Subtarget.h:391
llvm::AArch64Subtarget::getMaxBytesForLoopAlignment
unsigned getMaxBytesForLoopAlignment() const
Definition: AArch64Subtarget.h:249
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:493
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:44
AArch64ISelLowering.h
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:86
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:53
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:582
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:55
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:182
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:349
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:46
llvm::AArch64Subtarget::getNumXRegisterReserved
unsigned getNumXRegisterReserved() const
Definition: AArch64Subtarget.h:213
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:343
llvm::AArch64Subtarget::getMaxSVEVectorSizeInBits
unsigned getMaxSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:369
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:73
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:350
llvm::AArch64Subtarget::NeoverseV2
@ NeoverseV2
Definition: AArch64Subtarget.h:81
uint16_t
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:141
llvm::AArch64Subtarget::CortexX3
@ CortexX3
Definition: AArch64Subtarget.h:72
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:75
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:107
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:109
llvm::AArch64Subtarget::isTargetFuchsia
bool isTargetFuchsia() const
Definition: AArch64Subtarget.h:266
llvm::AArch64Subtarget::InstrInfo
AArch64InstrInfo InstrInfo
Definition: AArch64Subtarget.h:135
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:271
llvm::AArch64Subtarget::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const override
Definition: AArch64Subtarget.h:241
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:60
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:82
llvm::AArch64Subtarget::StreamingSVEModeDisabled
bool StreamingSVEModeDisabled
Definition: AArch64Subtarget.h:126
llvm::AArch64Subtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: AArch64Subtarget.h:247
llvm::CallingConv::Fast
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:132
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:371
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:339
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1182
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::CortexA510
@ CortexA510
Definition: AArch64Subtarget.h:56
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:68
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.h:225
llvm::AArch64Subtarget::CustomCallSavedXRegs
BitVector CustomCallSavedXRegs
Definition: AArch64Subtarget.h:122
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:181
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:498
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:458
llvm::CallLowering
Definition: CallLowering.h:44
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:74
llvm::AArch64Subtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: AArch64Subtarget.h:225
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:414
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:45
llvm::AArch64Subtarget::FrameLowering
AArch64FrameLowering FrameLowering
Definition: AArch64Subtarget.h:134
llvm::AArch64Subtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: AArch64Subtarget.h:265
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:48
llvm::AArch64Subtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: AArch64Subtarget.h:40
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:58