LLVM 17.0.0git
AArch64Subtarget.h
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1//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15
17#include "AArch64ISelLowering.h"
18#include "AArch64InstrInfo.h"
19#include "AArch64RegisterInfo.h"
27#include "llvm/IR/DataLayout.h"
28#include <string>
29
30#define GET_SUBTARGETINFO_HEADER
31#include "AArch64GenSubtargetInfo.inc"
32
33namespace llvm {
34class GlobalValue;
35class StringRef;
36class Triple;
37
39public:
40 enum ARMProcFamilyEnum : uint8_t {
90 TSV110
91 };
92
93protected:
94 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
96
97 // Enable 64-bit vectorization in SLP.
99
100// Bool members corresponding to the SubtargetFeatures defined in tablegen
101#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
102 bool ATTRIBUTE = DEFAULT;
103#include "AArch64GenSubtargetInfo.inc"
104
110 unsigned MaxPrefetchIterationsAhead = UINT_MAX;
114 unsigned MaxJumpTableSize = 0;
115
116 // ReserveXRegister[i] - X#i is not available as a general purpose register.
118
119 // ReserveXRegisterForRA[i] - X#i is not available for register allocator.
121
122 // CustomCallUsedXRegister[i] - X#i call saved.
124
126
130 unsigned VScaleForTuning = 2;
131
132 /// TargetTriple - What processor and OS we're targeting.
134
139
140 /// GlobalISel related APIs.
141 std::unique_ptr<CallLowering> CallLoweringInfo;
142 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
143 std::unique_ptr<InstructionSelector> InstSelector;
144 std::unique_ptr<LegalizerInfo> Legalizer;
145 std::unique_ptr<RegisterBankInfo> RegBankInfo;
146
147private:
148 /// initializeSubtargetDependencies - Initializes using CPUString and the
149 /// passed in feature string so that we can use initializer lists for
150 /// subtarget initialization.
151 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
152 StringRef CPUString,
153 StringRef TuneCPUString);
154
155 /// Initialize properties based on the selected processor family.
156 void initializeProperties();
157
158public:
159 /// This constructor initializes the data members to match that
160 /// of the specified triple.
161 AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
162 StringRef FS, const TargetMachine &TM, bool LittleEndian,
163 unsigned MinSVEVectorSizeInBitsOverride = 0,
164 unsigned MaxSVEVectorSizeInBitsOverride = 0,
165 bool StreamingSVEModeDisabled = true);
166
167// Getters for SubtargetFeatures defined in tablegen
168#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
169 bool GETTER() const { return ATTRIBUTE; }
170#include "AArch64GenSubtargetInfo.inc"
171
173 return &TSInfo;
174 }
175 const AArch64FrameLowering *getFrameLowering() const override {
176 return &FrameLowering;
177 }
178 const AArch64TargetLowering *getTargetLowering() const override {
179 return &TLInfo;
180 }
181 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
182 const AArch64RegisterInfo *getRegisterInfo() const override {
183 return &getInstrInfo()->getRegisterInfo();
184 }
185 const CallLowering *getCallLowering() const override;
186 const InlineAsmLowering *getInlineAsmLowering() const override;
188 const LegalizerInfo *getLegalizerInfo() const override;
189 const RegisterBankInfo *getRegBankInfo() const override;
190 const Triple &getTargetTriple() const { return TargetTriple; }
191 bool enableMachineScheduler() const override { return true; }
192 bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
193
194 /// Returns ARM processor family.
195 /// Avoid this function! CPU specifics should be kept local to this class
196 /// and preferably modeled with SubtargetFeatures or properties in
197 /// initializeProperties().
199 return ARMProcFamily;
200 }
201
202 bool isXRaySupported() const override { return true; }
203
205 // Don't assume any minimum vector size when PSTATE.SM may not be 0.
207 return 0;
209 }
210
211 bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
212 bool isXRegisterReservedForRA(size_t i) const { return ReserveXRegisterForRA[i]; }
213 unsigned getNumXRegisterReserved() const {
214 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());
215 AllReservedX |= ReserveXRegister;
216 AllReservedX |= ReserveXRegisterForRA;
217 return AllReservedX.count();
218 }
219 bool isXRegCustomCalleeSaved(size_t i) const {
220 return CustomCallSavedXRegs[i];
221 }
223
224 /// Return true if the CPU supports any kind of instruction fusion.
225 bool hasFusion() const {
226 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
227 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
228 hasFuseAdrpAdd() || hasFuseLiterals();
229 }
230
231 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
232 unsigned getVectorInsertExtractBaseCost() const;
233 unsigned getCacheLineSize() const override { return CacheLineSize; }
234 unsigned getPrefetchDistance() const override { return PrefetchDistance; }
235 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
236 unsigned NumStridedMemAccesses,
237 unsigned NumPrefetches,
238 bool HasCall) const override {
239 return MinPrefetchStride;
240 }
241 unsigned getMaxPrefetchIterationsAhead() const override {
243 }
246 }
248
251 }
252
253 unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
254
255 /// CPU has TBI (top byte of addresses is ignored during HW address
256 /// translation) and OS enables it.
258
259 bool isLittleEndian() const { return IsLittle; }
260
261 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
262 bool isTargetIOS() const { return TargetTriple.isiOS(); }
263 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
264 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
265 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
266 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
268
269 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
270 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
272
273 bool isTargetILP32() const {
274 return TargetTriple.isArch32Bit() ||
276 }
277
278 bool useAA() const override;
279
280 bool addrSinkUsingGEPs() const override {
281 // Keeping GEPs inbounds is important for exploiting AArch64
282 // addressing-modes in ILP32 mode.
283 return useAA() || isTargetILP32();
284 }
285
286 bool useSmallAddressing() const {
289 // Kernel is currently allowed only for Fuchsia targets,
290 // where it is the same as Small for almost all purposes.
291 case CodeModel::Small:
292 return true;
293 default:
294 return false;
295 }
296 }
297
298 /// ParseSubtargetFeatures - Parses features string setting specified
299 /// subtarget options. Definition of function is auto generated by tblgen.
301
302 /// ClassifyGlobalReference - Find the target operand flags that describe
303 /// how a global value should be referenced for the current subtarget.
304 unsigned ClassifyGlobalReference(const GlobalValue *GV,
305 const TargetMachine &TM) const;
306
308 const TargetMachine &TM) const;
309
310 /// This function is design to compatible with the function def in other
311 /// targets and escape build error about the virtual function def in base
312 /// class TargetSubtargetInfo. Updeate me if AArch64 target need to use it.
313 unsigned char
315 return 0;
316 }
317
319 unsigned NumRegionInstrs) const override;
320
321 bool enableEarlyIfConversion() const override;
322
323 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
324
326 switch (CC) {
327 case CallingConv::C:
330 return isTargetWindows();
332 return true;
333 default:
334 return false;
335 }
336 }
337
338 /// Return whether FrameLowering should always set the "extended frame
339 /// present" bit in FP, or set it based on a symbol in the runtime.
341 // Older OS versions (particularly system unwinders) are confused by the
342 // Swift extended frame, so when building code that might be run on them we
343 // must dynamically query the concurrency library to determine whether
344 // extended frames should be flagged as present.
345 const Triple &TT = getTargetTriple();
346
347 unsigned Major = TT.getOSVersion().getMajor();
348 switch(TT.getOS()) {
349 default:
350 return false;
351 case Triple::IOS:
352 case Triple::TvOS:
353 return Major < 15;
354 case Triple::WatchOS:
355 return Major < 8;
356 case Triple::MacOSX:
357 case Triple::Darwin:
358 return Major < 12;
359 }
360 }
361
362 void mirFileLoaded(MachineFunction &MF) const override;
363
364 bool hasSVEorSME() const { return hasSVE() || hasSME(); }
365
366 // Return the known range for the bit length of SVE data registers. A value
367 // of 0 means nothing is known about that particular limit beyong what's
368 // implied by the architecture.
369 unsigned getMaxSVEVectorSizeInBits() const {
371 "Tried to get SVE vector length without SVE support!");
373 }
374
375 unsigned getMinSVEVectorSizeInBits() const {
377 "Tried to get SVE vector length without SVE support!");
379 }
380
383 return true;
384
385 // Prefer NEON unless larger SVE registers are available.
386 return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
387 }
388
389 bool forceStreamingCompatibleSVE() const;
390
391 unsigned getVScaleForTuning() const { return VScaleForTuning; }
392
393 const char* getChkStkName() const {
394 if (isWindowsArm64EC())
395 return "__chkstk_arm64ec";
396 return "__chkstk";
397 }
398
399 const char* getSecurityCheckCookieName() const {
400 if (isWindowsArm64EC())
401 return "__security_check_cookie_arm64ec";
402 return "__security_check_cookie";
403 }
404
406};
407} // End llvm namespace
408
409#endif
This file describes how to lower LLVM calls to machine code calls.
This file describes how to lower LLVM inline asm to machine code INLINEASM.
Interface for Targets to specify which operations they can successfully select and how the others sho...
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool isStreamingSVEModeDisabled() const
const CallLowering * getCallLowering() const override
const AArch64RegisterInfo * getRegisterInfo() const override
bool forceStreamingCompatibleSVE() const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
bool addrSinkUsingGEPs() const override
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
const AArch64InstrInfo * getInstrInfo() const override
bool useSmallAddressing() const
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
AArch64SelectionDAGInfo TSInfo
const char * getSecurityCheckCookieName() const
unsigned getMaximumJumpTableSize() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
AArch64FrameLowering FrameLowering
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getCacheLineSize() const override
unsigned getVectorInsertExtractBaseCost() const
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
Align getPrefLoopAlignment() const
Align getPrefFunctionAlignment() const
unsigned getMaxBytesForLoopAlignment() const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
unsigned getMaxInterleaveFactor() const
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override
This function is design to compatible with the function def in other targets and escape build error a...
const Triple & getTargetTriple() const
bool isCallingConvWin64(CallingConv::ID CC) const
const char * getChkStkName() const
bool isXRegCustomCalleeSaved(size_t i) const
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
bool useSVEForFixedLengthVectors() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getMinVectorRegisterBitWidth() const
bool isXRegisterReserved(size_t i) const
unsigned getMaxPrefetchIterationsAhead() const override
const LegalizerInfo * getLegalizerInfo() const override
bool enableMachineScheduler() const override
bool enablePostRAScheduler() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
unsigned getMaxSVEVectorSizeInBits() const
unsigned getVScaleForTuning() const
unsigned getMinSVEVectorSizeInBits() const
AArch64InstrInfo InstrInfo
AArch64TargetLowering TLInfo
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
bool isXRaySupported() const override
bool hasCustomCallingConv() const
const AArch64FrameLowering * getFrameLowering() const override
bool swiftAsyncContextIsDynamicallySet() const
Return whether FrameLowering should always set the "extended frame present" bit in FP,...
unsigned getPrefetchDistance() const override
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:162
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:170
Provides the logic to select generic machine instructions.
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
const TargetMachine & getTargetMachine() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:725
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:688
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:680
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:373
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:584
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:638
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:519
bool isWindowsArm64EC() const
Definition: Triple.h:600
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:495
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1477
bool isOSFuchsia() const
Definition: Triple.h:549
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:156
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.