LLVM  14.0.0git
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AMDGPUBaseInfo.cpp File Reference
#include "AMDGPUBaseInfo.h"
#include "AMDGPU.h"
#include "AMDGPUAsmUtils.h"
#include "AMDKernelCodeT.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetParser.h"
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"
Include dependency graph for AMDGPUBaseInfo.cpp:

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Classes

struct  llvm::AMDGPU::MUBUFInfo
 
struct  llvm::AMDGPU::MTBUFInfo
 
struct  llvm::AMDGPU::SMInfo
 
struct  llvm::AMDGPU::VOPInfo
 
struct  llvm::AMDGPU::Exp::ExpTgt
 

Namespaces

 llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
 llvm::AMDGPU
 
 llvm::AMDGPU::IsaInfo
 
 llvm::AMDGPU::Hwreg
 
 llvm::AMDGPU::Exp
 
 llvm::AMDGPU::MTBUFFormat
 
 llvm::AMDGPU::SendMsg
 

Macros

#define GET_INSTRINFO_NAMED_OPS
 
#define GET_INSTRMAP_INFO
 
#define GET_MIMGBaseOpcodesTable_IMPL
 
#define GET_MIMGDimInfoTable_IMPL
 
#define GET_MIMGInfoTable_IMPL
 
#define GET_MIMGLZMappingTable_IMPL
 
#define GET_MIMGMIPMappingTable_IMPL
 
#define GET_MIMGG16MappingTable_IMPL
 
#define GET_MTBUFInfoTable_DECL
 
#define GET_MTBUFInfoTable_IMPL
 
#define GET_MUBUFInfoTable_DECL
 
#define GET_MUBUFInfoTable_IMPL
 
#define GET_SMInfoTable_DECL
 
#define GET_SMInfoTable_IMPL
 
#define GET_VOP1InfoTable_DECL
 
#define GET_VOP1InfoTable_IMPL
 
#define GET_VOP2InfoTable_DECL
 
#define GET_VOP2InfoTable_IMPL
 
#define GET_VOP3InfoTable_DECL
 
#define GET_VOP3InfoTable_IMPL
 
#define MAP_REG2REG
 
#define CASE_CI_VI(node)
 
#define CASE_VI_GFX9PLUS(node)   case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
 
#define CASE_CI_VI(node)   case node##_ci: case node##_vi: return node;
 
#define CASE_VI_GFX9PLUS(node)   case node##_vi: case node##_gfx9plus: return node;
 
#define GET_SourcesOfDivergence_IMPL
 
#define GET_Gfx9BufferFormat_IMPL
 
#define GET_Gfx10PlusBufferFormat_IMPL
 

Functions

Optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion2 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion3 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion4 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion3Or4 (const MCSubtargetInfo *STI)
 
int llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
unsigned llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
 
int llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int llvm::AMDGPU::getMTBUFElements (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc)
 
int llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int llvm::AMDGPU::getMUBUFElements (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc)
 
bool llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc)
 
bool llvm::AMDGPU::getVOP1IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::getVOP2IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::getVOP3IsSingle (unsigned Opc)
 
int llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)
 
static TargetIDSetting llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString (StringRef FeatureString)
 
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
 
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
 
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)
 
unsigned llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
 
void llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
 
int llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, intllvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
Waitcnt llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
 
unsigned llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
 
int64_t llvm::AMDGPU::Hwreg::getHwregId (const StringRef Name)
 
static unsigned llvm::AMDGPU::Hwreg::getLastSymbolicHwreg (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::Hwreg::isValidHwreg (int64_t Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::Hwreg::isValidHwreg (int64_t Id)
 
bool llvm::AMDGPU::Hwreg::isValidHwregOffset (int64_t Offset)
 
bool llvm::AMDGPU::Hwreg::isValidHwregWidth (int64_t Width)
 
uint64_t llvm::AMDGPU::Hwreg::encodeHwreg (uint64_t Id, uint64_t Offset, uint64_t Width)
 
StringRef llvm::AMDGPU::Hwreg::getHwreg (unsigned Id, const MCSubtargetInfo &STI)
 
void llvm::AMDGPU::Hwreg::decodeHwreg (unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
 
bool llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index)
 
unsigned llvm::AMDGPU::Exp::getTgtId (const StringRef Name)
 
bool llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name)
 
StringRef llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id)
 
static const StringLiteralllvm::AMDGPU::MTBUFFormat::getNfmtLookupTable (const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI)
 
StringRef llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt)
 
void llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
 
int64_t llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name)
 
StringRef llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id)
 
bool llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id)
 
int64_t llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt)
 
bool llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI)
 
unsigned llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::SendMsg::getMsgId (const StringRef Name)
 
bool llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
 
StringRef llvm::AMDGPU::SendMsg::getMsgName (int64_t MsgId)
 
int64_t llvm::AMDGPU::SendMsg::getMsgOpId (int64_t MsgId, const StringRef Name)
 
bool llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
 
StringRef llvm::AMDGPU::SendMsg::getMsgOpName (int64_t MsgId, int64_t OpId)
 
bool llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
 
bool llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId)
 
bool llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId)
 
void llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId)
 
uint64_t llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
 
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
 
bool llvm::AMDGPU::getHasColorExport (const Function &F)
 
bool llvm::AMDGPU::getHasDepthExport (const Function &F)
 
bool llvm::AMDGPU::isShader (CallingConv::ID cc)
 
bool llvm::AMDGPU::isGraphics (CallingConv::ID cc)
 
bool llvm::AMDGPU::isCompute (CallingConv::ID cc)
 
bool llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)
 
bool llvm::AMDGPU::isModuleEntryFunctionCC (CallingConv::ID CC)
 
bool llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasGFX10A16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool llvm::AMDGPU::isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned llvm::AMDGPU::mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this operand support only inlinable literals? More...
 
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableIntLiteralV216 (int32_t Literal)
 
bool llvm::AMDGPU::isFoldableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)
 
static bool llvm::AMDGPU::hasSMEMByteOffset (const MCSubtargetInfo &ST)
 
static bool llvm::AMDGPU::hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
 
bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
 
bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
 
static bool llvm::AMDGPU::isDwordAligned (uint64_t ByteOffset)
 
uint64_t llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
 Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets. More...
 
Optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
 
Optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
unsigned llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST, bool Signed)
 For FLAT segment the offset must be positive; MSB is ignored and forced to zero. More...
 
bool llvm::AMDGPU::splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
 
bool llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID)
 
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
 
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
 
raw_ostream & llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S)
 

Variables

static llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion ("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4), llvm::cl::ZeroOrMore)
 
static constexpr ExpTgt llvm::AMDGPU::Exp::ExpTgtInfo []
 

Macro Definition Documentation

◆ CASE_CI_VI [1/2]

#define CASE_CI_VI (   node)
Value:
assert(!isSI(STI)); \
case node: return isCI(STI) ? node##_ci : node##_vi;

Definition at line 1554 of file AMDGPUBaseInfo.cpp.

◆ CASE_CI_VI [2/2]

#define CASE_CI_VI (   node)    case node##_ci: case node##_vi: return node;

Definition at line 1554 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [1/2]

#define CASE_VI_GFX9PLUS (   node)    case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;

Definition at line 1555 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [2/2]

#define CASE_VI_GFX9PLUS (   node)    case node##_vi: case node##_gfx9plus: return node;

Definition at line 1555 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx10PlusBufferFormat_IMPL

#define GET_Gfx10PlusBufferFormat_IMPL

Definition at line 2011 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx9BufferFormat_IMPL

#define GET_Gfx9BufferFormat_IMPL

Definition at line 2010 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 27 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 28 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGBaseOpcodesTable_IMPL

#define GET_MIMGBaseOpcodesTable_IMPL

Definition at line 130 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGDimInfoTable_IMPL

#define GET_MIMGDimInfoTable_IMPL

Definition at line 131 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGG16MappingTable_IMPL

#define GET_MIMGG16MappingTable_IMPL

Definition at line 135 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGInfoTable_IMPL

#define GET_MIMGInfoTable_IMPL

Definition at line 132 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGLZMappingTable_IMPL

#define GET_MIMGLZMappingTable_IMPL

Definition at line 133 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGMIPMappingTable_IMPL

#define GET_MIMGMIPMappingTable_IMPL

Definition at line 134 of file AMDGPUBaseInfo.cpp.

◆ GET_MTBUFInfoTable_DECL

#define GET_MTBUFInfoTable_DECL

Definition at line 215 of file AMDGPUBaseInfo.cpp.

◆ GET_MTBUFInfoTable_IMPL

#define GET_MTBUFInfoTable_IMPL

Definition at line 216 of file AMDGPUBaseInfo.cpp.

◆ GET_MUBUFInfoTable_DECL

#define GET_MUBUFInfoTable_DECL

Definition at line 217 of file AMDGPUBaseInfo.cpp.

◆ GET_MUBUFInfoTable_IMPL

#define GET_MUBUFInfoTable_IMPL

Definition at line 218 of file AMDGPUBaseInfo.cpp.

◆ GET_SMInfoTable_DECL

#define GET_SMInfoTable_DECL

Definition at line 219 of file AMDGPUBaseInfo.cpp.

◆ GET_SMInfoTable_IMPL

#define GET_SMInfoTable_IMPL

Definition at line 220 of file AMDGPUBaseInfo.cpp.

◆ GET_SourcesOfDivergence_IMPL

#define GET_SourcesOfDivergence_IMPL

Definition at line 2009 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP1InfoTable_DECL

#define GET_VOP1InfoTable_DECL

Definition at line 221 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP1InfoTable_IMPL

#define GET_VOP1InfoTable_IMPL

Definition at line 222 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP2InfoTable_DECL

#define GET_VOP2InfoTable_DECL

Definition at line 223 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP2InfoTable_IMPL

#define GET_VOP2InfoTable_IMPL

Definition at line 224 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3InfoTable_DECL

#define GET_VOP3InfoTable_DECL

Definition at line 225 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3InfoTable_IMPL

#define GET_VOP3InfoTable_IMPL

Definition at line 226 of file AMDGPUBaseInfo.cpp.

◆ MAP_REG2REG

#define MAP_REG2REG

Definition at line 1497 of file AMDGPUBaseInfo.cpp.

Variable Documentation

◆ AmdhsaCodeObjectVersion

llvm::cl::opt<unsigned> AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4), llvm::cl::ZeroOrMore)
static

◆ Intr

unsigned Intr
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1437
node
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper node
Definition: README-SSE.txt:406
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1433