69#include "llvm/IR/IntrinsicsPowerPC.h"
103#define DEBUG_TYPE "ppc-lowering"
106 "disable-p10-store-forward",
130 cl::desc(
"disable vector permute decomposition"),
134 "disable-auto-paired-vec-st",
135 cl::desc(
"disable automatically generated 32byte paired vector stores"),
140 cl::desc(
"Set minimum number of entries to use a jump table on PPC"));
144 cl::desc(
"max depth when checking alias info in GatherAllAliases()"));
148 cl::desc(
"Set inclusive limit count of TLS local-dynamic access(es) in a "
149 "function to use initial-exec"));
154 "Number of shuffles lowered to a VPERM or XXPERM");
155STATISTIC(NumDynamicAllocaProbed,
"Number of dynamic stack allocation probed");
178 initializeAddrModeMap();
181 bool isPPC64 = Subtarget.
isPPC64();
191 if (!Subtarget.hasEFPU2())
203 if (!Subtarget.hasP10Vector()) {
226 if (Subtarget.isISA3_0()) {
256 if (!Subtarget.hasSPE()) {
264 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
265 for (
MVT VT : ScalarIntVTs) {
272 if (Subtarget.useCRBits()) {
275 if (isPPC64 || Subtarget.hasFPCVT()) {
341 if (Subtarget.isISA3_0()) {
376 if (!Subtarget.hasSPE()) {
381 if (Subtarget.hasVSX()) {
386 if (Subtarget.hasFSQRT()) {
391 if (Subtarget.hasFPRND()) {
432 if (Subtarget.hasSPE()) {
442 if (Subtarget.hasSPE())
446 if (!Subtarget.hasFSQRT() &&
447 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
451 if (!Subtarget.hasFSQRT() &&
452 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
453 Subtarget.hasFRES()))
456 if (Subtarget.hasFCPSGN()) {
464 if (Subtarget.hasFPRND()) {
478 if (Subtarget.isISA3_1()) {
484 (Subtarget.hasP9Vector() && isPPC64) ?
Custom :
Expand);
488 if (Subtarget.isISA3_0()) {
508 if (!Subtarget.useCRBits()) {
521 if (!Subtarget.useCRBits())
524 if (Subtarget.hasFPU()) {
535 if (!Subtarget.useCRBits())
540 if (Subtarget.hasSPE()) {
564 if (Subtarget.hasDirectMove() && isPPC64) {
569 if (TM.Options.UnsafeFPMath) {
672 if (Subtarget.hasSPE()) {
694 if (Subtarget.has64BitSupport()) {
709 if (Subtarget.hasLFIWAX() || isPPC64) {
715 if (Subtarget.hasSPE()) {
725 if (Subtarget.hasFPCVT()) {
726 if (Subtarget.has64BitSupport()) {
747 if (Subtarget.use64BitRegs()) {
765 if (Subtarget.has64BitSupport()) {
772 if (Subtarget.hasVSX()) {
779 if (Subtarget.hasAltivec()) {
780 for (
MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
795 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
808 if (Subtarget.hasVSX()) {
814 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
824 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
898 if (!Subtarget.hasP8Vector()) {
940 if (Subtarget.hasAltivec())
941 for (
auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
944 if (Subtarget.hasP8Altivec())
955 if (Subtarget.hasVSX()) {
961 if (Subtarget.hasP8Altivec())
966 if (Subtarget.isISA3_1()) {
1012 if (Subtarget.hasVSX()) {
1015 if (Subtarget.hasP8Vector()) {
1019 if (Subtarget.hasDirectMove() && isPPC64) {
1033 if (TM.Options.UnsafeFPMath) {
1070 if (Subtarget.hasP8Vector())
1079 if (Subtarget.hasP8Altivec()) {
1106 if (Subtarget.isISA3_1())
1209 if (Subtarget.hasP8Altivec()) {
1214 if (Subtarget.hasP9Vector()) {
1219 if (Subtarget.useCRBits()) {
1279 }
else if (Subtarget.hasVSX()) {
1304 for (
MVT VT : {MVT::f32, MVT::f64}) {
1323 if (Subtarget.hasP9Altivec()) {
1324 if (Subtarget.isISA3_1()) {
1347 if (Subtarget.hasP10Vector()) {
1352 if (Subtarget.pairedVectorMemops()) {
1357 if (Subtarget.hasMMA()) {
1358 if (Subtarget.isISAFuture())
1367 if (Subtarget.has64BitSupport())
1370 if (Subtarget.isISA3_1())
1388 if (Subtarget.hasAltivec()) {
1405 if (Subtarget.hasFPCVT())
1408 if (Subtarget.useCRBits())
1417 if (Subtarget.useCRBits()) {
1448 setLibcallName(RTLIB::MEMCPY, isPPC64 ?
"___memmove64" :
"___memmove");
1449 setLibcallName(RTLIB::MEMMOVE, isPPC64 ?
"___memmove64" :
"___memmove");
1450 setLibcallName(RTLIB::MEMSET, isPPC64 ?
"___memset64" :
"___memset");
1451 setLibcallName(RTLIB::BZERO, isPPC64 ?
"___bzero64" :
"___bzero");
1456 if (Subtarget.useCRBits()) {
1562void PPCTargetLowering::initializeAddrModeMap() {
1613 if (MaxAlign == MaxMaxAlign)
1615 if (
VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1616 if (MaxMaxAlign >= 32 &&
1617 VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
1618 MaxAlign =
Align(32);
1619 else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
1621 MaxAlign =
Align(16);
1622 }
else if (
ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1625 if (EltAlign > MaxAlign)
1626 MaxAlign = EltAlign;
1627 }
else if (
StructType *STy = dyn_cast<StructType>(Ty)) {
1628 for (
auto *EltTy : STy->elements()) {
1631 if (EltAlign > MaxAlign)
1632 MaxAlign = EltAlign;
1633 if (MaxAlign == MaxMaxAlign)
1646 if (Subtarget.hasAltivec())
1656 return Subtarget.hasSPE();
1664 Type *VectorTy,
unsigned ElemSizeInBits,
unsigned &Index)
const {
1665 if (!Subtarget.
isPPC64() || !Subtarget.hasVSX())
1668 if (
auto *VTy = dyn_cast<VectorType>(VectorTy)) {
1669 if (VTy->getScalarType()->isIntegerTy()) {
1671 if (ElemSizeInBits == 32) {
1675 if (ElemSizeInBits == 64) {
1701 return "PPCISD::FTSQRT";
1703 return "PPCISD::FSQRT";
1708 return "PPCISD::XXSPLTI_SP_TO_DP";
1710 return "PPCISD::XXSPLTI32DX";
1714 return "PPCISD::XXPERM";
1734 return "PPCISD::CALL_RM";
1736 return "PPCISD::CALL_NOP_RM";
1738 return "PPCISD::CALL_NOTOC_RM";
1743 return "PPCISD::BCTRL_RM";
1745 return "PPCISD::BCTRL_LOAD_TOC_RM";
1757 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1759 return "PPCISD::ANDI_rec_1_EQ_BIT";
1761 return "PPCISD::ANDI_rec_1_GT_BIT";
1776 return "PPCISD::ST_VSR_SCAL_INT";
1805 return "PPCISD::PADDI_DTPREL";
1821 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1823 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1833 return "PPCISD::STRICT_FADDRTZ";
1835 return "PPCISD::STRICT_FCTIDZ";
1837 return "PPCISD::STRICT_FCTIWZ";
1839 return "PPCISD::STRICT_FCTIDUZ";
1841 return "PPCISD::STRICT_FCTIWUZ";
1843 return "PPCISD::STRICT_FCFID";
1845 return "PPCISD::STRICT_FCFIDU";
1847 return "PPCISD::STRICT_FCFIDS";
1849 return "PPCISD::STRICT_FCFIDUS";
1852 return "PPCISD::STORE_COND";
1854 return "PPCISD::SETBC";
1856 return "PPCISD::SETBCR";
1864 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1881 return CFP->getValueAPF().isZero();
1885 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1886 return CFP->getValueAPF().isZero();
1894 return Op < 0 ||
Op == Val;
1906 if (ShuffleKind == 0) {
1909 for (
unsigned i = 0; i != 16; ++i)
1912 }
else if (ShuffleKind == 2) {
1915 for (
unsigned i = 0; i != 16; ++i)
1918 }
else if (ShuffleKind == 1) {
1919 unsigned j = IsLE ? 0 : 1;
1920 for (
unsigned i = 0; i != 8; ++i)
1937 if (ShuffleKind == 0) {
1940 for (
unsigned i = 0; i != 16; i += 2)
1944 }
else if (ShuffleKind == 2) {
1947 for (
unsigned i = 0; i != 16; i += 2)
1951 }
else if (ShuffleKind == 1) {
1952 unsigned j = IsLE ? 0 : 2;
1953 for (
unsigned i = 0; i != 8; i += 2)
1974 if (!Subtarget.hasP8Vector())
1978 if (ShuffleKind == 0) {
1981 for (
unsigned i = 0; i != 16; i += 4)
1987 }
else if (ShuffleKind == 2) {
1990 for (
unsigned i = 0; i != 16; i += 4)
1996 }
else if (ShuffleKind == 1) {
1997 unsigned j = IsLE ? 0 : 4;
1998 for (
unsigned i = 0; i != 8; i += 4)
2015 unsigned LHSStart,
unsigned RHSStart) {
2016 if (
N->getValueType(0) != MVT::v16i8)
2018 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
2019 "Unsupported merge size!");
2021 for (
unsigned i = 0; i != 8/UnitSize; ++i)
2022 for (
unsigned j = 0; j != UnitSize; ++j) {
2024 LHSStart+j+i*UnitSize) ||
2026 RHSStart+j+i*UnitSize))
2041 if (ShuffleKind == 1)
2043 else if (ShuffleKind == 2)
2048 if (ShuffleKind == 1)
2050 else if (ShuffleKind == 0)
2066 if (ShuffleKind == 1)
2068 else if (ShuffleKind == 2)
2073 if (ShuffleKind == 1)
2075 else if (ShuffleKind == 0)
2125 unsigned RHSStartValue) {
2126 if (
N->getValueType(0) != MVT::v16i8)
2129 for (
unsigned i = 0; i < 2; ++i)
2130 for (
unsigned j = 0; j < 4; ++j)
2132 i*RHSStartValue+j+IndexOffset) ||
2134 i*RHSStartValue+j+IndexOffset+8))
2156 unsigned indexOffset = CheckEven ? 4 : 0;
2157 if (ShuffleKind == 1)
2159 else if (ShuffleKind == 2)
2165 unsigned indexOffset = CheckEven ? 0 : 4;
2166 if (ShuffleKind == 1)
2168 else if (ShuffleKind == 0)
2184 if (
N->getValueType(0) != MVT::v16i8)
2191 for (i = 0; i != 16 && SVOp->
getMaskElt(i) < 0; ++i)
2194 if (i == 16)
return -1;
2199 if (ShiftAmt < i)
return -1;
2204 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2206 for (++i; i != 16; ++i)
2209 }
else if (ShuffleKind == 1) {
2211 for (++i; i != 16; ++i)
2218 ShiftAmt = 16 - ShiftAmt;
2227 EVT VT =
N->getValueType(0);
2228 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2229 return EltSize == 8 &&
N->getMaskElt(0) ==
N->getMaskElt(1);
2232 EltSize <= 8 &&
"Can only handle 1,2,4,8 byte element sizes");
2236 if (
N->getMaskElt(0) % EltSize != 0)
2241 unsigned ElementBase =
N->getMaskElt(0);
2244 if (ElementBase >= 16)
2249 for (
unsigned i = 1; i != EltSize; ++i)
2250 if (
N->getMaskElt(i) < 0 ||
N->getMaskElt(i) != (
int)(i+ElementBase))
2253 for (
unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2254 if (
N->getMaskElt(i) < 0)
continue;
2255 for (
unsigned j = 0; j != EltSize; ++j)
2256 if (
N->getMaskElt(i+j) !=
N->getMaskElt(j))
2273 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
2274 "Unexpected element width.");
2275 assert((StepLen == 1 || StepLen == -1) &&
"Unexpected element width.");
2277 unsigned NumOfElem = 16 / Width;
2278 unsigned MaskVal[16];
2279 for (
unsigned i = 0; i < NumOfElem; ++i) {
2280 MaskVal[0] =
N->getMaskElt(i * Width);
2281 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2283 }
else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2287 for (
unsigned int j = 1; j < Width; ++j) {
2288 MaskVal[j] =
N->getMaskElt(i * Width + j);
2289 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2299 unsigned &InsertAtByte,
bool &Swap,
bool IsLE) {
2304 unsigned M0 =
N->getMaskElt(0) / 4;
2305 unsigned M1 =
N->getMaskElt(4) / 4;
2306 unsigned M2 =
N->getMaskElt(8) / 4;
2307 unsigned M3 =
N->getMaskElt(12) / 4;
2308 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2309 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2314 if ((
M0 > 3 &&
M1 == 1 && M2 == 2 && M3 == 3) ||
2315 (
M0 < 4 &&
M1 == 5 && M2 == 6 && M3 == 7)) {
2316 ShiftElts = IsLE ? LittleEndianShifts[
M0 & 0x3] : BigEndianShifts[
M0 & 0x3];
2317 InsertAtByte = IsLE ? 12 : 0;
2322 if ((
M1 > 3 &&
M0 == 0 && M2 == 2 && M3 == 3) ||
2323 (
M1 < 4 &&
M0 == 4 && M2 == 6 && M3 == 7)) {
2324 ShiftElts = IsLE ? LittleEndianShifts[
M1 & 0x3] : BigEndianShifts[
M1 & 0x3];
2325 InsertAtByte = IsLE ? 8 : 4;
2330 if ((M2 > 3 &&
M0 == 0 &&
M1 == 1 && M3 == 3) ||
2331 (M2 < 4 &&
M0 == 4 &&
M1 == 5 && M3 == 7)) {
2332 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2333 InsertAtByte = IsLE ? 4 : 8;
2338 if ((M3 > 3 &&
M0 == 0 &&
M1 == 1 && M2 == 2) ||
2339 (M3 < 4 &&
M0 == 4 &&
M1 == 5 && M2 == 6)) {
2340 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2341 InsertAtByte = IsLE ? 0 : 12;
2348 if (
N->getOperand(1).isUndef()) {
2351 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2352 if (
M0 == XXINSERTWSrcElem &&
M1 == 1 && M2 == 2 && M3 == 3) {
2353 InsertAtByte = IsLE ? 12 : 0;
2356 if (
M0 == 0 &&
M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2357 InsertAtByte = IsLE ? 8 : 4;
2360 if (
M0 == 0 &&
M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2361 InsertAtByte = IsLE ? 4 : 8;
2364 if (
M0 == 0 &&
M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2365 InsertAtByte = IsLE ? 0 : 12;
2374 bool &Swap,
bool IsLE) {
2375 assert(
N->getValueType(0) == MVT::v16i8 &&
"Shuffle vector expects v16i8");
2381 unsigned M0 =
N->getMaskElt(0) / 4;
2382 unsigned M1 =
N->getMaskElt(4) / 4;
2383 unsigned M2 =
N->getMaskElt(8) / 4;
2384 unsigned M3 =
N->getMaskElt(12) / 4;
2388 if (
N->getOperand(1).isUndef()) {
2389 assert(
M0 < 4 &&
"Indexing into an undef vector?");
2390 if (
M1 != (
M0 + 1) % 4 || M2 != (
M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2393 ShiftElts = IsLE ? (4 -
M0) % 4 :
M0;
2399 if (
M1 != (
M0 + 1) % 8 || M2 != (
M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2403 if (
M0 == 0 ||
M0 == 7 ||
M0 == 6 ||
M0 == 5) {
2408 ShiftElts = (8 -
M0) % 8;
2409 }
else if (
M0 == 4 ||
M0 == 3 ||
M0 == 2 ||
M0 == 1) {
2414 ShiftElts = (4 -
M0) % 4;
2419 if (
M0 == 0 ||
M0 == 1 ||
M0 == 2 ||
M0 == 3) {
2424 }
else if (
M0 == 4 ||
M0 == 5 ||
M0 == 6 ||
M0 == 7) {
2436 assert(
N->getValueType(0) == MVT::v16i8 &&
"Shuffle vector expects v16i8");
2441 for (
int i = 0; i < 16; i += Width)
2442 if (
N->getMaskElt(i) != i + Width - 1)
2473 bool &Swap,
bool IsLE) {
2474 assert(
N->getValueType(0) == MVT::v16i8 &&
"Shuffle vector expects v16i8");
2480 unsigned M0 =
N->getMaskElt(0) / 8;
2481 unsigned M1 =
N->getMaskElt(8) / 8;
2482 assert(((
M0 |
M1) < 4) &&
"A mask element out of bounds?");
2486 if (
N->getOperand(1).isUndef()) {
2487 if ((
M0 |
M1) < 2) {
2488 DM = IsLE ? (((~M1) & 1) << 1) + ((~
M0) & 1) : (
M0 << 1) + (
M1 & 1);
2496 if (
M0 > 1 &&
M1 < 2) {
2498 }
else if (M0 < 2 && M1 > 1) {
2506 DM = (((~M1) & 1) << 1) + ((~
M0) & 1);
2509 if (M0 < 2 && M1 > 1) {
2511 }
else if (
M0 > 1 &&
M1 < 2) {
2519 DM = (
M0 << 1) + (
M1 & 1);
2534 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2539 return (16 / EltSize) - 1 - (SVOp->
getMaskElt(0) / EltSize);
2555 unsigned EltSize = 16/
N->getNumOperands();
2556 if (EltSize < ByteSize) {
2557 unsigned Multiple = ByteSize/EltSize;
2559 assert(Multiple > 1 && Multiple <= 4 &&
"How can this happen?");
2562 for (
unsigned i = 0, e =
N->getNumOperands(); i != e; ++i) {
2563 if (
N->getOperand(i).isUndef())
continue;
2565 if (!isa<ConstantSDNode>(
N->getOperand(i)))
return SDValue();
2567 if (!UniquedVals[i&(Multiple-1)].
getNode())
2568 UniquedVals[i&(Multiple-1)] =
N->getOperand(i);
2569 else if (UniquedVals[i&(Multiple-1)] !=
N->getOperand(i))
2579 bool LeadingZero =
true;
2580 bool LeadingOnes =
true;
2581 for (
unsigned i = 0; i != Multiple-1; ++i) {
2582 if (!UniquedVals[i].
getNode())
continue;
2589 if (!UniquedVals[Multiple-1].
getNode())
2596 if (!UniquedVals[Multiple-1].
getNode())
2598 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2607 for (
unsigned i = 0, e =
N->getNumOperands(); i != e; ++i) {
2608 if (
N->getOperand(i).isUndef())
continue;
2610 OpVal =
N->getOperand(i);
2611 else if (OpVal !=
N->getOperand(i))
2617 unsigned ValSizeInBytes = EltSize;
2620 Value = CN->getZExtValue();
2622 assert(CN->getValueType(0) == MVT::f32 &&
"Only one legal FP vector type!");
2623 Value = llvm::bit_cast<uint32_t>(CN->getValueAPF().convertToFloat());
2629 if (ValSizeInBytes < ByteSize)
return SDValue();
2640 if (MaskVal == 0)
return SDValue();
2643 if (SignExtend32<5>(MaskVal) == MaskVal)
2657 if (!isa<ConstantSDNode>(
N))
2660 Imm = (int16_t)
N->getAsZExtVal();
2661 if (
N->getValueType(0) == MVT::i32)
2662 return Imm == (int32_t)
N->getAsZExtVal();
2664 return Imm == (int64_t)
N->getAsZExtVal();
2682 return (~(LHSKnown.
Zero | RHSKnown.
Zero) == 0);
2690 for (
SDNode *U :
N->users()) {
2691 if (
MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2692 if (Memop->getMemoryVT() == MVT::f64) {
2693 Base =
N.getOperand(0);
2694 Index =
N.getOperand(1);
2706 if (!isa<ConstantSDNode>(
N))
2709 Imm = (int64_t)cast<ConstantSDNode>(
N)->getSExtValue();
2710 return isInt<34>(Imm);
2737 (!EncodingAlignment ||
isAligned(*EncodingAlignment, Imm)))
2742 Base =
N.getOperand(0);
2743 Index =
N.getOperand(1);
2745 }
else if (
N.getOpcode() ==
ISD::OR) {
2747 (!EncodingAlignment ||
isAligned(*EncodingAlignment, Imm)))
2759 if (~(LHSKnown.
Zero | RHSKnown.
Zero) == 0) {
2760 Base =
N.getOperand(0);
2761 Index =
N.getOperand(1);
2831 (!EncodingAlignment ||
isAligned(*EncodingAlignment, imm))) {
2837 Base =
N.getOperand(0);
2840 }
else if (
N.getOperand(1).getOpcode() ==
PPCISD::Lo) {
2842 assert(!
N.getOperand(1).getConstantOperandVal(1) &&
2843 "Cannot handle constant offsets yet!");
2844 Disp =
N.getOperand(1).getOperand(0);
2849 Base =
N.getOperand(0);
2852 }
else if (
N.getOpcode() ==
ISD::OR) {
2855 (!EncodingAlignment ||
isAligned(*EncodingAlignment, imm))) {
2865 dyn_cast<FrameIndexSDNode>(
N.getOperand(0))) {
2869 Base =
N.getOperand(0);
2882 (!EncodingAlignment ||
isAligned(*EncodingAlignment, Imm))) {
2885 CN->getValueType(0));
2890 if ((CN->getValueType(0) == MVT::i32 ||
2891 (int64_t)CN->getZExtValue() == (
int)CN->getZExtValue()) &&
2892 (!EncodingAlignment ||
2893 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2894 int Addr = (int)CN->getZExtValue();
2901 unsigned Opc = CN->
getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2922 if (
N.getValueType() != MVT::i64)
2935 Base =
N.getOperand(0);
2951 Base =
N.getOperand(0);
2984 !
N.getOperand(1).hasOneUse() || !
N.getOperand(0).hasOneUse())) {
2985 Base =
N.getOperand(0);
2986 Index =
N.getOperand(1);
2998 Ty *PCRelCand = dyn_cast<Ty>(
N);
3010 if (isValidPCRelNode<ConstantPoolSDNode>(
N) ||
3011 isValidPCRelNode<GlobalAddressSDNode>(
N) ||
3012 isValidPCRelNode<JumpTableSDNode>(
N) ||
3013 isValidPCRelNode<BlockAddressSDNode>(
N))
3029 EVT MemVT = LD->getMemoryVT();
3036 if (!ST.hasP8Vector())
3041 if (!ST.hasP9Vector())
3053 if (
Use.getResNo() == 0 &&
3075 Ptr = LD->getBasePtr();
3076 VT = LD->getMemoryVT();
3077 Alignment = LD->getAlign();
3078 }
else if (
StoreSDNode *ST = dyn_cast<StoreSDNode>(
N)) {
3079 Ptr = ST->getBasePtr();
3080 VT = ST->getMemoryVT();
3081 Alignment = ST->getAlign();
3104 if (isa<FrameIndexSDNode>(
Base) || isa<RegisterSDNode>(
Base))
3107 SDValue Val = cast<StoreSDNode>(
N)->getValue();
3120 if (VT != MVT::i64) {
3125 if (Alignment <
Align(4))
3135 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3137 isa<ConstantSDNode>(
Offset))
3152 unsigned &HiOpFlags,
unsigned &LoOpFlags,
3208 EVT PtrVT =
Op.getValueType();
3224 return getTOCEntry(DAG,
SDLoc(CP), GA);
3227 unsigned MOHiFlag, MOLoFlag;
3234 return getTOCEntry(DAG,
SDLoc(CP), GA);
3294 EVT PtrVT =
Op.getValueType();
3312 return getTOCEntry(DAG,
SDLoc(JT), GA);
3315 unsigned MOHiFlag, MOLoFlag;
3322 return getTOCEntry(DAG,
SDLoc(GA), GA);
3332 EVT PtrVT =
Op.getValueType();
3351 return getTOCEntry(DAG,
SDLoc(BASDN), GA);
3360 unsigned MOHiFlag, MOLoFlag;
3371 return LowerGlobalTLSAddressAIX(
Op, DAG);
3373 return LowerGlobalTLSAddressLinux(
Op, DAG);
3395 if (
I.getOpcode() == Instruction::Call)
3396 if (
const CallInst *CI = dyn_cast<const CallInst>(&
I))
3397 if (
Function *CF = CI->getCalledFunction())
3398 if (CF->isDeclaration() &&
3399 CF->getIntrinsicID() == Intrinsic::threadlocal_address)
3401 dyn_cast<GlobalValue>(
I.getOperand(0))) {
3407 unsigned TLSGVCnt = TLSGV.
size();
3417 <<
" function is using the TLS-IE model for TLS-LD access.\n");
3432 bool Is64Bit = Subtarget.
isPPC64();
3436 if (Subtarget.hasAIXShLibTLSModelOpt())
3446 bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
3447 bool HasAIXSmallTLSGlobalAttr =
false;
3450 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3454 if (GVar->hasAttribute(
"aix-small-tls"))
3455 HasAIXSmallTLSGlobalAttr =
true;
3474 if ((HasAIXSmallLocalExecTLS || HasAIXSmallTLSGlobalAttr) &&
3475 IsTLSLocalExecModel) {
3495 if (HasAIXSmallLocalExecTLS || HasAIXSmallTLSGlobalAttr)
3497 "currently only supported on AIX (64-bit mode).");
3503 bool HasAIXSmallLocalDynamicTLS = Subtarget.hasAIXSmallLocalDynamicTLS();
3507 if (!Is64Bit && HasAIXSmallLocalDynamicTLS)
3509 "currently only supported on AIX (64-bit mode).");
3517 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3521 dyn_cast_or_null<GlobalVariable>(
M->getOrInsertGlobal(
3524 assert(TLSGV &&
"Not able to create GV for _$TLSML.");
3527 SDValue ModuleHandleTOC = getTOCEntry(DAG, dl, ModuleHandleTGA);
3538 if (HasAIXSmallLocalDynamicTLS) {
3547 return DAG.
getNode(
ISD::ADD, dl, PtrVT, ModuleHandle, VariableOffset);
3560 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3561 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3579 bool is64bit = Subtarget.
isPPC64();
3626 if (!
TM.isPositionIndependent())
3685 PtrVT, GOTPtr, TGA, TGA);
3687 PtrVT, TLSAddr, TGA);