LLVM 19.0.0git
PPCISelLowering.cpp
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1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
16#include "PPC.h"
17#include "PPCCCState.h"
18#include "PPCCallingConv.h"
19#include "PPCFrameLowering.h"
20#include "PPCInstrInfo.h"
22#include "PPCPerfectShuffle.h"
23#include "PPCRegisterInfo.h"
24#include "PPCSubtarget.h"
25#include "PPCTargetMachine.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/APInt.h"
28#include "llvm/ADT/APSInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/DenseMap.h"
31#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallSet.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringRef.h"
60#include "llvm/IR/CallingConv.h"
61#include "llvm/IR/Constant.h"
62#include "llvm/IR/Constants.h"
63#include "llvm/IR/DataLayout.h"
64#include "llvm/IR/DebugLoc.h"
66#include "llvm/IR/Function.h"
67#include "llvm/IR/GlobalValue.h"
68#include "llvm/IR/IRBuilder.h"
70#include "llvm/IR/Intrinsics.h"
71#include "llvm/IR/IntrinsicsPowerPC.h"
72#include "llvm/IR/Module.h"
73#include "llvm/IR/Type.h"
74#include "llvm/IR/Use.h"
75#include "llvm/IR/Value.h"
76#include "llvm/MC/MCContext.h"
77#include "llvm/MC/MCExpr.h"
87#include "llvm/Support/Debug.h"
89#include "llvm/Support/Format.h"
95#include <algorithm>
96#include <cassert>
97#include <cstdint>
98#include <iterator>
99#include <list>
100#include <optional>
101#include <utility>
102#include <vector>
103
104using namespace llvm;
105
106#define DEBUG_TYPE "ppc-lowering"
107
108static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
109cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
110
111static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
112cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
113
114static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
115cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
116
117static cl::opt<bool> DisableSCO("disable-ppc-sco",
118cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
119
120static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
121cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
122
123static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
124cl::desc("use absolute jump tables on ppc"), cl::Hidden);
125
126static cl::opt<bool>
127 DisablePerfectShuffle("ppc-disable-perfect-shuffle",
128 cl::desc("disable vector permute decomposition"),
129 cl::init(true), cl::Hidden);
130
132 "disable-auto-paired-vec-st",
133 cl::desc("disable automatically generated 32byte paired vector stores"),
134 cl::init(true), cl::Hidden);
135
137 "ppc-min-jump-table-entries", cl::init(64), cl::Hidden,
138 cl::desc("Set minimum number of entries to use a jump table on PPC"));
139
141 "ppc-gather-alias-max-depth", cl::init(18), cl::Hidden,
142 cl::desc("max depth when checking alias info in GatherAllAliases()"));
143
145 "ppc-aix-shared-lib-tls-model-opt-limit", cl::init(1), cl::Hidden,
146 cl::desc("Set inclusive limit count of TLS local-dynamic access(es) in a "
147 "function to use initial-exec"));
148
149STATISTIC(NumTailCalls, "Number of tail calls");
150STATISTIC(NumSiblingCalls, "Number of sibling calls");
151STATISTIC(ShufflesHandledWithVPERM,
152 "Number of shuffles lowered to a VPERM or XXPERM");
153STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
154
155static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
156
157static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
158
159static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
160
161// A faster local-[exec|dynamic] TLS access sequence (enabled with the
162// -maix-small-local-[exec|dynamic]-tls option) can be produced for TLS
163// variables; consistent with the IBM XL compiler, we apply a max size of
164// slightly under 32KB.
166
167// FIXME: Remove this once the bug has been fixed!
169
171 const PPCSubtarget &STI)
172 : TargetLowering(TM), Subtarget(STI) {
173 // Initialize map that relates the PPC addressing modes to the computed flags
174 // of a load/store instruction. The map is used to determine the optimal
175 // addressing mode when selecting load and stores.
176 initializeAddrModeMap();
177 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
178 // arguments are at least 4/8 bytes aligned.
179 bool isPPC64 = Subtarget.isPPC64();
180 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
181
182 // Set up the register classes.
183 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
184 if (!useSoftFloat()) {
185 if (hasSPE()) {
186 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
187 // EFPU2 APU only supports f32
188 if (!Subtarget.hasEFPU2())
189 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
190 } else {
191 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
192 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
193 }
194 }
195
196 // Match BITREVERSE to customized fast code sequence in the td file.
199
200 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
202
203 // Custom lower inline assembly to check for special registers.
206
207 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
208 for (MVT VT : MVT::integer_valuetypes()) {
211 }
212
213 if (Subtarget.isISA3_0()) {
214 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
215 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
216 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
217 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
218 } else {
219 // No extending loads from f16 or HW conversions back and forth.
220 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
223 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
226 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
227 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
228 }
229
230 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
231
232 // PowerPC has pre-inc load and store's.
243 if (!Subtarget.hasSPE()) {
248 }
249
250 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
251 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
252 for (MVT VT : ScalarIntVTs) {
257 }
258
259 if (Subtarget.useCRBits()) {
261
262 if (isPPC64 || Subtarget.hasFPCVT()) {
265 isPPC64 ? MVT::i64 : MVT::i32);
268 isPPC64 ? MVT::i64 : MVT::i32);
269
272 isPPC64 ? MVT::i64 : MVT::i32);
275 isPPC64 ? MVT::i64 : MVT::i32);
276
279 isPPC64 ? MVT::i64 : MVT::i32);
282 isPPC64 ? MVT::i64 : MVT::i32);
283
286 isPPC64 ? MVT::i64 : MVT::i32);
289 isPPC64 ? MVT::i64 : MVT::i32);
290 } else {
295 }
296
297 // PowerPC does not support direct load/store of condition registers.
300
301 // FIXME: Remove this once the ANDI glue bug is fixed:
302 if (ANDIGlueBug)
304
305 for (MVT VT : MVT::integer_valuetypes()) {
308 setTruncStoreAction(VT, MVT::i1, Expand);
309 }
310
311 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
312 }
313
314 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
315 // PPC (the libcall is not available).
320
321 // We do not currently implement these libm ops for PowerPC.
322 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
323 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
324 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
325 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
327 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
328
329 // PowerPC has no SREM/UREM instructions unless we are on P9
330 // On P9 we may use a hardware instruction to compute the remainder.
331 // When the result of both the remainder and the division is required it is
332 // more efficient to compute the remainder from the result of the division
333 // rather than use the remainder instruction. The instructions are legalized
334 // directly because the DivRemPairsPass performs the transformation at the IR
335 // level.
336 if (Subtarget.isISA3_0()) {
341 } else {
346 }
347
348 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
357
358 // Handle constrained floating-point operations of scalar.
359 // TODO: Handle SPE specific operation.
365
370
371 if (!Subtarget.hasSPE()) {
374 }
375
376 if (Subtarget.hasVSX()) {
379 }
380
381 if (Subtarget.hasFSQRT()) {
384 }
385
386 if (Subtarget.hasFPRND()) {
391
396 }
397
398 // We don't support sin/cos/sqrt/fmod/pow
409
410 // MASS transformation for LLVM intrinsics with replicating fast-math flag
411 // to be consistent to PPCGenScalarMASSEntries pass
412 if (TM.getOptLevel() == CodeGenOptLevel::Aggressive) {
425 }
426
427 if (Subtarget.hasSPE()) {
430 } else {
431 setOperationAction(ISD::FMA , MVT::f64, Legal);
432 setOperationAction(ISD::FMA , MVT::f32, Legal);
433 }
434
435 if (Subtarget.hasSPE())
436 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
437
439
440 // If we're enabling GP optimizations, use hardware square root
441 if (!Subtarget.hasFSQRT() &&
442 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
443 Subtarget.hasFRE()))
445
446 if (!Subtarget.hasFSQRT() &&
447 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
448 Subtarget.hasFRES()))
450
451 if (Subtarget.hasFCPSGN()) {
454 } else {
457 }
458
459 if (Subtarget.hasFPRND()) {
464
469 }
470
471 // Prior to P10, PowerPC does not have BSWAP, but we can use vector BSWAP
472 // instruction xxbrd to speed up scalar BSWAP64.
473 if (Subtarget.isISA3_1()) {
476 } else {
479 ISD::BSWAP, MVT::i64,
480 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
481 }
482
483 // CTPOP or CTTZ were introduced in P8/P9 respectively
484 if (Subtarget.isISA3_0()) {
485 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
486 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
487 } else {
488 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
489 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
490 }
491
492 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
495 } else {
498 }
499
500 // PowerPC does not have ROTR
503
504 if (!Subtarget.useCRBits()) {
505 // PowerPC does not have Select
510 }
511
512 // PowerPC wants to turn select_cc of FP into fsel when possible.
515
516 // PowerPC wants to optimize integer setcc a bit
517 if (!Subtarget.useCRBits())
519
520 if (Subtarget.hasFPU()) {
524
528 }
529
530 // PowerPC does not have BRCOND which requires SetCC
531 if (!Subtarget.useCRBits())
533
535
536 if (Subtarget.hasSPE()) {
537 // SPE has built-in conversions
544
545 // SPE supports signaling compare of f32/f64.
548 } else {
549 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
552
553 // PowerPC does not have [U|S]INT_TO_FP
558 }
559
560 if (Subtarget.hasDirectMove() && isPPC64) {
565 if (TM.Options.UnsafeFPMath) {
574 }
575 } else {
580 }
581
582 // We cannot sextinreg(i1). Expand to shifts.
584
585 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
586 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
587 // support continuation, user-level threading, and etc.. As a result, no
588 // other SjLj exception interfaces are implemented and please don't build
589 // your own exception handling based on them.
590 // LLVM/Clang supports zero-cost DWARF exception handling.
593
594 // We want to legalize GlobalAddress and ConstantPool nodes into the
595 // appropriate instructions to materialize the address.
606
607 // TRAP is legal.
608 setOperationAction(ISD::TRAP, MVT::Other, Legal);
609
610 // TRAMPOLINE is custom lowered.
613
614 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
616
617 if (Subtarget.is64BitELFABI()) {
618 // VAARG always uses double-word chunks, so promote anything smaller.
620 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
622 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
624 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
626 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
628 } else if (Subtarget.is32BitELFABI()) {
629 // VAARG is custom lowered with the 32-bit SVR4 ABI.
632 } else
634
635 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
636 if (Subtarget.is32BitELFABI())
638 else
640
641 // Use the default implementation.
642 setOperationAction(ISD::VAEND , MVT::Other, Expand);
651
652 // We want to custom lower some of our intrinsics.
658
659 // To handle counter-based loop conditions.
661
666
667 // Comparisons that require checking two conditions.
668 if (Subtarget.hasSPE()) {
673 }
686
689
690 if (Subtarget.has64BitSupport()) {
691 // They also have instructions for converting between i64 and fp.
700 // This is just the low 32 bits of a (signed) fp->i64 conversion.
701 // We cannot do this with Promote because i64 is not a legal type.
704
705 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
708 }
709 } else {
710 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
711 if (Subtarget.hasSPE()) {
714 } else {
717 }
718 }
719
720 // With the instructions enabled under FPCVT, we can do everything.
721 if (Subtarget.hasFPCVT()) {
722 if (Subtarget.has64BitSupport()) {
731 }
732
741 }
742
743 if (Subtarget.use64BitRegs()) {
744 // 64-bit PowerPC implementations can support i64 types directly
745 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
746 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
748 // 64-bit PowerPC wants to expand i128 shifts itself.
752 } else {
753 // 32-bit PowerPC wants to expand i64 shifts itself.
757 }
758
759 // PowerPC has better expansions for funnel shifts than the generic
760 // TargetLowering::expandFunnelShift.
761 if (Subtarget.has64BitSupport()) {
764 }
767
768 if (Subtarget.hasVSX()) {
773 }
774
775 if (Subtarget.hasAltivec()) {
776 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
781 }
782 // First set operation action for all vector types to expand. Then we
783 // will selectively turn on ones that can be effectively codegen'd.
785 // add/sub are legal for all supported vector VT's.
788
789 // For v2i64, these are only valid with P8Vector. This is corrected after
790 // the loop.
791 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
796 }
797 else {
802 }
803
804 if (Subtarget.hasVSX()) {
807 }
808
809 // Vector instructions introduced in P8
810 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
813 }
814 else {
817 }
818
819 // Vector instructions introduced in P9
820 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
822 else
824
825 // We promote all shuffles to v16i8.
827 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
828
829 // We promote all non-typed operations to v4i32.
831 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
833 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
835 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
837 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
839 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
842 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
844 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
845
846 // No other operations are legal.
885
886 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
887 setTruncStoreAction(VT, InnerVT, Expand);
890 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
891 }
892 }
894 if (!Subtarget.hasP8Vector()) {
895 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
896 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
897 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
898 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
899 }
900
901 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
902 // with merges, splats, etc.
904
905 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
906 // are cheap, so handle them before they get expanded to scalar.
912
913 setOperationAction(ISD::AND , MVT::v4i32, Legal);
914 setOperationAction(ISD::OR , MVT::v4i32, Legal);
915 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
916 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
918 Subtarget.useCRBits() ? Legal : Expand);
919 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
929 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
932
933 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
934 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
935 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
936 if (Subtarget.hasAltivec())
937 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
939 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
940 if (Subtarget.hasP8Altivec())
941 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
942
943 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
944 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
945 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
946 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
947
948 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
949 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
950
951 if (Subtarget.hasVSX()) {
952 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
955 }
956
957 if (Subtarget.hasP8Altivec())
958 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
959 else
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961
962 if (Subtarget.isISA3_1()) {
963 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
964 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
965 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
966 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
967 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
968 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
969 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
970 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
971 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
972 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
973 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
974 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
975 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
976 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
977 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
978 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
979 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
980 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
981 }
982
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
985
988
993
994 // Altivec does not contain unordered floating-point compare instructions
995 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
997 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
999
1000 if (Subtarget.hasVSX()) {
1003 if (Subtarget.hasP8Vector()) {
1006 }
1007 if (Subtarget.hasDirectMove() && isPPC64) {
1016 }
1018
1019 // The nearbyint variants are not allowed to raise the inexact exception
1020 // so we can only code-gen them with unsafe math.
1021 if (TM.Options.UnsafeFPMath) {
1024 }
1025
1026 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1027 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1028 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1030 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1031 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
1034
1036 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1037 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1040
1041 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1042 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1043
1044 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1045 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1046
1047 // Share the Altivec comparison restrictions.
1048 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
1049 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
1050 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
1051 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
1052
1053 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1054 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1055
1057
1058 if (Subtarget.hasP8Vector())
1059 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1060
1061 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1062
1063 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1064 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1065 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1066
1067 if (Subtarget.hasP8Altivec()) {
1068 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1069 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1070 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1071
1072 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1073 // SRL, but not for SRA because of the instructions available:
1074 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1075 // doing
1076 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1077 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1078 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1079
1080 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1081 }
1082 else {
1083 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1084 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1085 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1086
1087 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1088
1089 // VSX v2i64 only supports non-arithmetic operations.
1090 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1091 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1092 }
1093
1094 if (Subtarget.isISA3_1())
1095 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1096 else
1097 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1098
1099 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1100 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1102 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1103
1105
1114
1115 // Custom handling for partial vectors of integers converted to
1116 // floating point. We already have optimal handling for v2i32 through
1117 // the DAG combine, so those aren't necessary.
1134
1135 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1136 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1137 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1138 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1141
1144
1145 // Handle constrained floating-point operations of vector.
1146 // The predictor is `hasVSX` because altivec instruction has
1147 // no exception but VSX vector instruction has.
1161
1175
1176 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1177 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1178
1179 for (MVT FPT : MVT::fp_valuetypes())
1180 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1181
1182 // Expand the SELECT to SELECT_CC
1184
1185 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1186 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1187
1188 // No implementation for these ops for PowerPC.
1190 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1191 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1192 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1194 setOperationAction(ISD::FREM, MVT::f128, Expand);
1195 }
1196
1197 if (Subtarget.hasP8Altivec()) {
1198 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1199 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1200 }
1201
1202 if (Subtarget.hasP9Vector()) {
1205
1206 // Test data class instructions store results in CR bits.
1207 if (Subtarget.useCRBits()) {
1211 }
1212
1213 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1214 // SRL, but not for SRA because of the instructions available:
1215 // VS{RL} and VS{RL}O.
1216 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1217 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1218 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1219
1220 setOperationAction(ISD::FADD, MVT::f128, Legal);
1221 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1222 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1223 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1225
1226 setOperationAction(ISD::FMA, MVT::f128, Legal);
1233
1235 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1237 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1240
1244
1245 // Handle constrained floating-point operations of fp128
1262 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1263 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1264 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1265 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1266 } else if (Subtarget.hasVSX()) {
1269
1270 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1271 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1272
1273 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1274 // fp_to_uint and int_to_fp.
1277
1278 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1279 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1280 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1281 setOperationAction(ISD::FABS, MVT::f128, Expand);
1283 setOperationAction(ISD::FMA, MVT::f128, Expand);
1285
1286 // Expand the fp_extend if the target type is fp128.
1289
1290 // Expand the fp_round if the source type is fp128.
1291 for (MVT VT : {MVT::f32, MVT::f64}) {
1294 }
1295
1300
1301 // Lower following f128 select_cc pattern:
1302 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1304
1305 // We need to handle f128 SELECT_CC with integer result type.
1307 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1308 }
1309
1310 if (Subtarget.hasP9Altivec()) {
1311 if (Subtarget.isISA3_1()) {
1316 } else {
1319 }
1327
1328 setOperationAction(ISD::ABDU, MVT::v16i8, Legal);
1329 setOperationAction(ISD::ABDU, MVT::v8i16, Legal);
1330 setOperationAction(ISD::ABDU, MVT::v4i32, Legal);
1331 setOperationAction(ISD::ABDS, MVT::v4i32, Legal);
1332 }
1333
1334 if (Subtarget.hasP10Vector()) {
1336 }
1337 }
1338
1339 if (Subtarget.pairedVectorMemops()) {
1340 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1341 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1342 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1343 }
1344 if (Subtarget.hasMMA()) {
1345 if (Subtarget.isISAFuture())
1346 addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass);
1347 else
1348 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1349 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1350 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1352 }
1353
1354 if (Subtarget.has64BitSupport())
1356
1357 if (Subtarget.isISA3_1())
1358 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1359
1360 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1361
1362 if (!isPPC64) {
1365 }
1366
1371 }
1372
1374
1375 if (Subtarget.hasAltivec()) {
1376 // Altivec instructions set fields to all zeros or all ones.
1378 }
1379
1380 setLibcallName(RTLIB::MULO_I128, nullptr);
1381 if (!isPPC64) {
1382 // These libcalls are not available in 32-bit.
1383 setLibcallName(RTLIB::SHL_I128, nullptr);
1384 setLibcallName(RTLIB::SRL_I128, nullptr);
1385 setLibcallName(RTLIB::SRA_I128, nullptr);
1386 setLibcallName(RTLIB::MUL_I128, nullptr);
1387 setLibcallName(RTLIB::MULO_I64, nullptr);
1388 }
1389
1392 else if (isPPC64)
1394 else
1396
1397 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1398
1399 // We have target-specific dag combine patterns for the following nodes:
1402 if (Subtarget.hasFPCVT())
1405 if (Subtarget.useCRBits())
1409
1411
1413
1414 if (Subtarget.useCRBits()) {
1416 }
1417
1418 setLibcallName(RTLIB::LOG_F128, "logf128");
1419 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1420 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1421 setLibcallName(RTLIB::EXP_F128, "expf128");
1422 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1423 setLibcallName(RTLIB::SIN_F128, "sinf128");
1424 setLibcallName(RTLIB::COS_F128, "cosf128");
1425 setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
1426 setLibcallName(RTLIB::POW_F128, "powf128");
1427 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1428 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1429 setLibcallName(RTLIB::REM_F128, "fmodf128");
1430 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1431 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1432 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1433 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1434 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1435 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1436 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1437 setLibcallName(RTLIB::RINT_F128, "rintf128");
1438 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1439 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1440 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1441 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1442 setLibcallName(RTLIB::FREXP_F128, "frexpf128");
1443
1444 if (Subtarget.isAIXABI()) {
1445 setLibcallName(RTLIB::MEMCPY, isPPC64 ? "___memmove64" : "___memmove");
1446 setLibcallName(RTLIB::MEMMOVE, isPPC64 ? "___memmove64" : "___memmove");
1447 setLibcallName(RTLIB::MEMSET, isPPC64 ? "___memset64" : "___memset");
1448 setLibcallName(RTLIB::BZERO, isPPC64 ? "___bzero64" : "___bzero");
1449 }
1450
1451 // With 32 condition bits, we don't need to sink (and duplicate) compares
1452 // aggressively in CodeGenPrep.
1453 if (Subtarget.useCRBits()) {
1456 }
1457
1458 // TODO: The default entry number is set to 64. This stops most jump table
1459 // generation on PPC. But it is good for current PPC HWs because the indirect
1460 // branch instruction mtctr to the jump table may lead to bad branch predict.
1461 // Re-evaluate this value on future HWs that can do better with mtctr.
1463
1465
1466 switch (Subtarget.getCPUDirective()) {
1467 default: break;
1468 case PPC::DIR_970:
1469 case PPC::DIR_A2:
1470 case PPC::DIR_E500:
1471 case PPC::DIR_E500mc:
1472 case PPC::DIR_E5500:
1473 case PPC::DIR_PWR4:
1474 case PPC::DIR_PWR5:
1475 case PPC::DIR_PWR5X:
1476 case PPC::DIR_PWR6:
1477 case PPC::DIR_PWR6X:
1478 case PPC::DIR_PWR7:
1479 case PPC::DIR_PWR8:
1480 case PPC::DIR_PWR9:
1481 case PPC::DIR_PWR10:
1485 break;
1486 }
1487
1488 if (Subtarget.enableMachineScheduler())
1490 else
1492
1494
1495 // The Freescale cores do better with aggressive inlining of memcpy and
1496 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1497 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1498 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1499 MaxStoresPerMemset = 32;
1501 MaxStoresPerMemcpy = 32;
1505 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1506 // The A2 also benefits from (very) aggressive inlining of memcpy and
1507 // friends. The overhead of a the function call, even when warm, can be
1508 // over one hundred cycles.
1509 MaxStoresPerMemset = 128;
1510 MaxStoresPerMemcpy = 128;
1511 MaxStoresPerMemmove = 128;
1512 MaxLoadsPerMemcmp = 128;
1513 } else {
1516 }
1517
1518 IsStrictFPEnabled = true;
1519
1520 // Let the subtarget (CPU) decide if a predictable select is more expensive
1521 // than the corresponding branch. This information is used in CGP to decide
1522 // when to convert selects into branches.
1524
1526}
1527
1528// *********************************** NOTE ************************************
1529// For selecting load and store instructions, the addressing modes are defined
1530// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1531// patterns to match the load the store instructions.
1532//
1533// The TD definitions for the addressing modes correspond to their respective
1534// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1535// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1536// address mode flags of a particular node. Afterwards, the computed address
1537// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1538// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1539// accordingly, based on the preferred addressing mode.
1540//
1541// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1542// MemOpFlags contains all the possible flags that can be used to compute the
1543// optimal addressing mode for load and store instructions.
1544// AddrMode contains all the possible load and store addressing modes available
1545// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1546//
1547// When adding new load and store instructions, it is possible that new address
1548// flags may need to be added into MemOpFlags, and a new addressing mode will
1549// need to be added to AddrMode. An entry of the new addressing mode (consisting
1550// of the minimal and main distinguishing address flags for the new load/store
1551// instructions) will need to be added into initializeAddrModeMap() below.
1552// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1553// need to be updated to account for selecting the optimal addressing mode.
1554// *****************************************************************************
1555/// Initialize the map that relates the different addressing modes of the load
1556/// and store instructions to a set of flags. This ensures the load/store
1557/// instruction is correctly matched during instruction selection.
1558void PPCTargetLowering::initializeAddrModeMap() {
1559 AddrModesMap[PPC::AM_DForm] = {
1560 // LWZ, STW
1565 // LBZ, LHZ, STB, STH
1570 // LHA
1575 // LFS, LFD, STFS, STFD
1580 };
1581 AddrModesMap[PPC::AM_DSForm] = {
1582 // LWA
1586 // LD, STD
1590 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1594 };
1595 AddrModesMap[PPC::AM_DQForm] = {
1596 // LXV, STXV
1600 };
1601 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1603 // TODO: Add mapping for quadword load/store.
1604}
1605
1606/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1607/// the desired ByVal argument alignment.
1608static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1609 if (MaxAlign == MaxMaxAlign)
1610 return;
1611 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1612 if (MaxMaxAlign >= 32 &&
1613 VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
1614 MaxAlign = Align(32);
1615 else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
1616 MaxAlign < 16)
1617 MaxAlign = Align(16);
1618 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1619 Align EltAlign;
1620 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1621 if (EltAlign > MaxAlign)
1622 MaxAlign = EltAlign;
1623 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1624 for (auto *EltTy : STy->elements()) {
1625 Align EltAlign;
1626 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1627 if (EltAlign > MaxAlign)
1628 MaxAlign = EltAlign;
1629 if (MaxAlign == MaxMaxAlign)
1630 break;
1631 }
1632 }
1633}
1634
1635/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1636/// function arguments in the caller parameter area.
1638 const DataLayout &DL) const {
1639 // 16byte and wider vectors are passed on 16byte boundary.
1640 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1641 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1642 if (Subtarget.hasAltivec())
1643 getMaxByValAlign(Ty, Alignment, Align(16));
1644 return Alignment.value();
1645}
1646
1648 return Subtarget.useSoftFloat();
1649}
1650
1652 return Subtarget.hasSPE();
1653}
1654
1656 return VT.isScalarInteger();
1657}
1658
1660 Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const {
1661 if (!Subtarget.isPPC64() || !Subtarget.hasVSX())
1662 return false;
1663
1664 if (auto *VTy = dyn_cast<VectorType>(VectorTy)) {
1665 if (VTy->getScalarType()->isIntegerTy()) {
1666 // ElemSizeInBits 8/16 can fit in immediate field, not needed here.
1667 if (ElemSizeInBits == 32) {
1668 Index = Subtarget.isLittleEndian() ? 2 : 1;
1669 return true;
1670 }
1671 if (ElemSizeInBits == 64) {
1672 Index = Subtarget.isLittleEndian() ? 1 : 0;
1673 return true;
1674 }
1675 }
1676 }
1677 return false;
1678}
1679
1680const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1681 switch ((PPCISD::NodeType)Opcode) {
1682 case PPCISD::FIRST_NUMBER: break;
1683 case PPCISD::FSEL: return "PPCISD::FSEL";
1684 case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
1685 case PPCISD::XSMINC: return "PPCISD::XSMINC";
1686 case PPCISD::FCFID: return "PPCISD::FCFID";
1687 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1688 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1689 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1690 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1691 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1692 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1693 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1694 case PPCISD::FRE: return "PPCISD::FRE";
1695 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1696 case PPCISD::FTSQRT:
1697 return "PPCISD::FTSQRT";
1698 case PPCISD::FSQRT:
1699 return "PPCISD::FSQRT";
1700 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1701 case PPCISD::VPERM: return "PPCISD::VPERM";
1702 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1704 return "PPCISD::XXSPLTI_SP_TO_DP";
1706 return "PPCISD::XXSPLTI32DX";
1707 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1708 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1709 case PPCISD::XXPERM:
1710 return "PPCISD::XXPERM";
1711 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1712 case PPCISD::CMPB: return "PPCISD::CMPB";
1713 case PPCISD::Hi: return "PPCISD::Hi";
1714 case PPCISD::Lo: return "PPCISD::Lo";
1715 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1716 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1717 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1718 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1719 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1720 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1721 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1722 case PPCISD::SRL: return "PPCISD::SRL";
1723 case PPCISD::SRA: return "PPCISD::SRA";
1724 case PPCISD::SHL: return "PPCISD::SHL";
1725 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1726 case PPCISD::CALL: return "PPCISD::CALL";
1727 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1728 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1729 case PPCISD::CALL_RM:
1730 return "PPCISD::CALL_RM";
1732 return "PPCISD::CALL_NOP_RM";
1734 return "PPCISD::CALL_NOTOC_RM";
1735 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1736 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1737 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1738 case PPCISD::BCTRL_RM:
1739 return "PPCISD::BCTRL_RM";
1741 return "PPCISD::BCTRL_LOAD_TOC_RM";
1742 case PPCISD::RET_GLUE: return "PPCISD::RET_GLUE";
1743 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1744 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1745 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1746 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1747 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1748 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1749 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1750 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1751 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1753 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1755 return "PPCISD::ANDI_rec_1_EQ_BIT";
1757 return "PPCISD::ANDI_rec_1_GT_BIT";
1758 case PPCISD::VCMP: return "PPCISD::VCMP";
1759 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1760 case PPCISD::LBRX: return "PPCISD::LBRX";
1761 case PPCISD::STBRX: return "PPCISD::STBRX";
1762 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1763 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1764 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1765 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1766 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1767 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1768 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1769 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1770 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1772 return "PPCISD::ST_VSR_SCAL_INT";
1773 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1774 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1775 case PPCISD::BDZ: return "PPCISD::BDZ";
1776 case PPCISD::MFFS: return "PPCISD::MFFS";
1777 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1778 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1779 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1780 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1781 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1782 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1783 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1784 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1785 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1786 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1787 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1788 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1789 case PPCISD::GET_TLS_MOD_AIX: return "PPCISD::GET_TLS_MOD_AIX";
1790 case PPCISD::GET_TPOINTER: return "PPCISD::GET_TPOINTER";
1791 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1792 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1793 case PPCISD::TLSLD_AIX: return "PPCISD::TLSLD_AIX";
1794 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1795 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1796 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1797 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1798 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1799 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1801 return "PPCISD::PADDI_DTPREL";
1802 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1803 case PPCISD::SC: return "PPCISD::SC";
1804 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1805 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1806 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1807 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1808 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1809 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1810 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1811 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1812 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1813 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1814 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1815 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1817 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1819 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1820 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1821 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1822 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1823 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1824 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1825 case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
1826 case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
1827 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1829 return "PPCISD::STRICT_FADDRTZ";
1831 return "PPCISD::STRICT_FCTIDZ";
1833 return "PPCISD::STRICT_FCTIWZ";
1835 return "PPCISD::STRICT_FCTIDUZ";
1837 return "PPCISD::STRICT_FCTIWUZ";
1839 return "PPCISD::STRICT_FCFID";
1841 return "PPCISD::STRICT_FCFIDU";
1843 return "PPCISD::STRICT_FCFIDS";
1845 return "PPCISD::STRICT_FCFIDUS";
1846 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1847 case PPCISD::STORE_COND:
1848 return "PPCISD::STORE_COND";
1849 }
1850 return nullptr;
1851}
1852
1854 EVT VT) const {
1855 if (!VT.isVector())
1856 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1857
1859}
1860
1862 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1863 return true;
1864}
1865
1866//===----------------------------------------------------------------------===//
1867// Node matching predicates, for use by the tblgen matching code.
1868//===----------------------------------------------------------------------===//
1869
1870/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1872 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1873 return CFP->getValueAPF().isZero();
1874 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1875 // Maybe this has already been legalized into the constant pool?
1876 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1877 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1878 return CFP->getValueAPF().isZero();
1879 }
1880 return false;
1881}
1882
1883/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1884/// true if Op is undef or if it matches the specified value.
1885static bool isConstantOrUndef(int Op, int Val) {
1886 return Op < 0 || Op == Val;
1887}
1888
1889/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1890/// VPKUHUM instruction.
1891/// The ShuffleKind distinguishes between big-endian operations with
1892/// two different inputs (0), either-endian operations with two identical
1893/// inputs (1), and little-endian operations with two different inputs (2).
1894/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1896 SelectionDAG &DAG) {
1897 bool IsLE = DAG.getDataLayout().isLittleEndian();
1898 if (ShuffleKind == 0) {
1899 if (IsLE)
1900 return false;
1901 for (unsigned i = 0; i != 16; ++i)
1902 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1903 return false;
1904 } else if (ShuffleKind == 2) {
1905 if (!IsLE)
1906 return false;
1907 for (unsigned i = 0; i != 16; ++i)
1908 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1909 return false;
1910 } else if (ShuffleKind == 1) {
1911 unsigned j = IsLE ? 0 : 1;
1912 for (unsigned i = 0; i != 8; ++i)
1913 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1914 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1915 return false;
1916 }
1917 return true;
1918}
1919
1920/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1921/// VPKUWUM instruction.
1922/// The ShuffleKind distinguishes between big-endian operations with
1923/// two different inputs (0), either-endian operations with two identical
1924/// inputs (1), and little-endian operations with two different inputs (2).
1925/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1927 SelectionDAG &DAG) {
1928 bool IsLE = DAG.getDataLayout().isLittleEndian();
1929 if (ShuffleKind == 0) {
1930 if (IsLE)
1931 return false;
1932 for (unsigned i = 0; i != 16; i += 2)
1933 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1934 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1935 return false;
1936 } else if (ShuffleKind == 2) {
1937 if (!IsLE)
1938 return false;
1939 for (unsigned i = 0; i != 16; i += 2)
1940 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1941 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1942 return false;
1943 } else if (ShuffleKind == 1) {
1944 unsigned j = IsLE ? 0 : 2;
1945 for (unsigned i = 0; i != 8; i += 2)
1946 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1947 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1948 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1949 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1950 return false;
1951 }
1952 return true;
1953}
1954
1955/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1956/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1957/// current subtarget.
1958///
1959/// The ShuffleKind distinguishes between big-endian operations with
1960/// two different inputs (0), either-endian operations with two identical
1961/// inputs (1), and little-endian operations with two different inputs (2).
1962/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1964 SelectionDAG &DAG) {
1965 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>();
1966 if (!Subtarget.hasP8Vector())
1967 return false;
1968
1969 bool IsLE = DAG.getDataLayout().isLittleEndian();
1970 if (ShuffleKind == 0) {
1971 if (IsLE)
1972 return false;
1973 for (unsigned i = 0; i != 16; i += 4)
1974 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1975 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1976 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1977 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1978 return false;
1979 } else if (ShuffleKind == 2) {
1980 if (!IsLE)
1981 return false;
1982 for (unsigned i = 0; i != 16; i += 4)
1983 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1984 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1985 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1986 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1987 return false;
1988 } else if (ShuffleKind == 1) {
1989 unsigned j = IsLE ? 0 : 4;
1990 for (unsigned i = 0; i != 8; i += 4)
1991 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1992 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1993 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1994 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1995 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1996 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1997 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1998 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1999 return false;
2000 }
2001 return true;
2002}
2003
2004/// isVMerge - Common function, used to match vmrg* shuffles.
2005///
2006static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
2007 unsigned LHSStart, unsigned RHSStart) {
2008 if (N->getValueType(0) != MVT::v16i8)
2009 return false;
2010 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
2011 "Unsupported merge size!");
2012
2013 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
2014 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
2015 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
2016 LHSStart+j+i*UnitSize) ||
2017 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
2018 RHSStart+j+i*UnitSize))
2019 return false;
2020 }
2021 return true;
2022}
2023
2024/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
2025/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
2026/// The ShuffleKind distinguishes between big-endian merges with two
2027/// different inputs (0), either-endian merges with two identical inputs (1),
2028/// and little-endian merges with two different inputs (2). For the latter,
2029/// the input operands are swapped (see PPCInstrAltivec.td).
2031 unsigned ShuffleKind, SelectionDAG &DAG) {
2032 if (DAG.getDataLayout().isLittleEndian()) {
2033 if (ShuffleKind == 1) // unary
2034 return isVMerge(N, UnitSize, 0, 0);
2035 else if (ShuffleKind == 2) // swapped
2036 return isVMerge(N, UnitSize, 0, 16);
2037 else
2038 return false;
2039 } else {
2040 if (ShuffleKind == 1) // unary
2041 return isVMerge(N, UnitSize, 8, 8);
2042 else if (ShuffleKind == 0) // normal
2043 return isVMerge(N, UnitSize, 8, 24);
2044 else
2045 return false;
2046 }
2047}
2048
2049/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
2050/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
2051/// The ShuffleKind distinguishes between big-endian merges with two
2052/// different inputs (0), either-endian merges with two identical inputs (1),
2053/// and little-endian merges with two different inputs (2). For the latter,
2054/// the input operands are swapped (see PPCInstrAltivec.td).
2056 unsigned ShuffleKind, SelectionDAG &DAG) {
2057 if (DAG.getDataLayout().isLittleEndian()) {
2058 if (ShuffleKind == 1) // unary
2059 return isVMerge(N, UnitSize, 8, 8);
2060 else if (ShuffleKind == 2) // swapped
2061 return isVMerge(N, UnitSize, 8, 24);
2062 else
2063 return false;
2064 } else {
2065 if (ShuffleKind == 1) // unary
2066 return isVMerge(N, UnitSize, 0, 0);
2067 else if (ShuffleKind == 0) // normal
2068 return isVMerge(N, UnitSize, 0, 16);
2069 else
2070 return false;
2071 }
2072}
2073
2074/**
2075 * Common function used to match vmrgew and vmrgow shuffles
2076 *
2077 * The indexOffset determines whether to look for even or odd words in
2078 * the shuffle mask. This is based on the of the endianness of the target
2079 * machine.
2080 * - Little Endian:
2081 * - Use offset of 0 to check for odd elements
2082 * - Use offset of 4 to check for even elements
2083 * - Big Endian:
2084 * - Use offset of 0 to check for even elements
2085 * - Use offset of 4 to check for odd elements
2086 * A detailed description of the vector element ordering for little endian and
2087 * big endian can be found at
2088 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
2089 * Targeting your applications - what little endian and big endian IBM XL C/C++
2090 * compiler differences mean to you
2091 *
2092 * The mask to the shuffle vector instruction specifies the indices of the
2093 * elements from the two input vectors to place in the result. The elements are
2094 * numbered in array-access order, starting with the first vector. These vectors
2095 * are always of type v16i8, thus each vector will contain 16 elements of size
2096 * 8. More info on the shuffle vector can be found in the
2097 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
2098 * Language Reference.
2099 *
2100 * The RHSStartValue indicates whether the same input vectors are used (unary)
2101 * or two different input vectors are used, based on the following:
2102 * - If the instruction uses the same vector for both inputs, the range of the
2103 * indices will be 0 to 15. In this case, the RHSStart value passed should
2104 * be 0.
2105 * - If the instruction has two different vectors then the range of the
2106 * indices will be 0 to 31. In this case, the RHSStart value passed should
2107 * be 16 (indices 0-15 specify elements in the first vector while indices 16
2108 * to 31 specify elements in the second vector).
2109 *
2110 * \param[in] N The shuffle vector SD Node to analyze
2111 * \param[in] IndexOffset Specifies whether to look for even or odd elements
2112 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2113 * vector to the shuffle_vector instruction
2114 * \return true iff this shuffle vector represents an even or odd word merge
2115 */
2116static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2117 unsigned RHSStartValue) {
2118 if (N->getValueType(0) != MVT::v16i8)
2119 return false;
2120
2121 for (unsigned i = 0; i < 2; ++i)
2122 for (unsigned j = 0; j < 4; ++j)
2123 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2124 i*RHSStartValue+j+IndexOffset) ||
2125 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2126 i*RHSStartValue+j+IndexOffset+8))
2127 return false;
2128 return true;
2129}
2130
2131/**
2132 * Determine if the specified shuffle mask is suitable for the vmrgew or
2133 * vmrgow instructions.
2134 *
2135 * \param[in] N The shuffle vector SD Node to analyze
2136 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2137 * \param[in] ShuffleKind Identify the type of merge:
2138 * - 0 = big-endian merge with two different inputs;
2139 * - 1 = either-endian merge with two identical inputs;
2140 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2141 * little-endian merges).
2142 * \param[in] DAG The current SelectionDAG
2143 * \return true iff this shuffle mask
2144 */
2146 unsigned ShuffleKind, SelectionDAG &DAG) {
2147 if (DAG.getDataLayout().isLittleEndian()) {
2148 unsigned indexOffset = CheckEven ? 4 : 0;
2149 if (ShuffleKind == 1) // Unary
2150 return isVMerge(N, indexOffset, 0);
2151 else if (ShuffleKind == 2) // swapped
2152 return isVMerge(N, indexOffset, 16);
2153 else
2154 return false;
2155 }
2156 else {
2157 unsigned indexOffset = CheckEven ? 0 : 4;
2158 if (ShuffleKind == 1) // Unary
2159 return isVMerge(N, indexOffset, 0);
2160 else if (ShuffleKind == 0) // Normal
2161 return isVMerge(N, indexOffset, 16);
2162 else
2163 return false;
2164 }
2165 return false;
2166}
2167
2168/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2169/// amount, otherwise return -1.
2170/// The ShuffleKind distinguishes between big-endian operations with two
2171/// different inputs (0), either-endian operations with two identical inputs
2172/// (1), and little-endian operations with two different inputs (2). For the
2173/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2174int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2175 SelectionDAG &DAG) {
2176 if (N->getValueType(0) != MVT::v16i8)
2177 return -1;
2178
2179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2180
2181 // Find the first non-undef value in the shuffle mask.
2182 unsigned i;
2183 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2184 /*search*/;
2185
2186 if (i == 16) return -1; // all undef.
2187
2188 // Otherwise, check to see if the rest of the elements are consecutively
2189 // numbered from this value.
2190 unsigned ShiftAmt = SVOp->getMaskElt(i);
2191 if (ShiftAmt < i) return -1;
2192
2193 ShiftAmt -= i;
2194 bool isLE = DAG.getDataLayout().isLittleEndian();
2195
2196 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2197 // Check the rest of the elements to see if they are consecutive.
2198 for (++i; i != 16; ++i)
2199 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2200 return -1;
2201 } else if (ShuffleKind == 1) {
2202 // Check the rest of the elements to see if they are consecutive.
2203 for (++i; i != 16; ++i)
2204 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2205 return -1;
2206 } else
2207 return -1;
2208
2209 if (isLE)
2210 ShiftAmt = 16 - ShiftAmt;
2211
2212 return ShiftAmt;
2213}
2214
2215/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2216/// specifies a splat of a single element that is suitable for input to
2217/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2219 EVT VT = N->getValueType(0);
2220 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2221 return EltSize == 8 && N->getMaskElt(0) == N->getMaskElt(1);
2222
2223 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) &&
2224 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes");
2225
2226 // The consecutive indices need to specify an element, not part of two
2227 // different elements. So abandon ship early if this isn't the case.
2228 if (N->getMaskElt(0) % EltSize != 0)
2229 return false;
2230
2231 // This is a splat operation if each element of the permute is the same, and
2232 // if the value doesn't reference the second vector.
2233 unsigned ElementBase = N->getMaskElt(0);
2234
2235 // FIXME: Handle UNDEF elements too!
2236 if (ElementBase >= 16)
2237 return false;
2238
2239 // Check that the indices are consecutive, in the case of a multi-byte element
2240 // splatted with a v16i8 mask.
2241 for (unsigned i = 1; i != EltSize; ++i)
2242 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2243 return false;
2244
2245 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2246 if (N->getMaskElt(i) < 0) continue;
2247 for (unsigned j = 0; j != EltSize; ++j)
2248 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2249 return false;
2250 }
2251 return true;
2252}
2253
2254/// Check that the mask is shuffling N byte elements. Within each N byte
2255/// element of the mask, the indices could be either in increasing or
2256/// decreasing order as long as they are consecutive.
2257/// \param[in] N the shuffle vector SD Node to analyze
2258/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2259/// Word/DoubleWord/QuadWord).
2260/// \param[in] StepLen the delta indices number among the N byte element, if
2261/// the mask is in increasing/decreasing order then it is 1/-1.
2262/// \return true iff the mask is shuffling N byte elements.
2263static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2264 int StepLen) {
2265 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
2266 "Unexpected element width.");
2267 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
2268
2269 unsigned NumOfElem = 16 / Width;
2270 unsigned MaskVal[16]; // Width is never greater than 16
2271 for (unsigned i = 0; i < NumOfElem; ++i) {
2272 MaskVal[0] = N->getMaskElt(i * Width);
2273 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2274 return false;
2275 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2276 return false;
2277 }
2278
2279 for (unsigned int j = 1; j < Width; ++j) {
2280 MaskVal[j] = N->getMaskElt(i * Width + j);
2281 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2282 return false;
2283 }
2284 }
2285 }
2286
2287 return true;
2288}
2289
2290bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2291 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2292 if (!isNByteElemShuffleMask(N, 4, 1))
2293 return false;
2294
2295 // Now we look at mask elements 0,4,8,12
2296 unsigned M0 = N->getMaskElt(0) / 4;
2297 unsigned M1 = N->getMaskElt(4) / 4;
2298 unsigned M2 = N->getMaskElt(8) / 4;
2299 unsigned M3 = N->getMaskElt(12) / 4;
2300 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2301 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2302
2303 // Below, let H and L be arbitrary elements of the shuffle mask
2304 // where H is in the range [4,7] and L is in the range [0,3].
2305 // H, 1, 2, 3 or L, 5, 6, 7
2306 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2307 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2308 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2309 InsertAtByte = IsLE ? 12 : 0;
2310 Swap = M0 < 4;
2311 return true;
2312 }
2313 // 0, H, 2, 3 or 4, L, 6, 7
2314 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2315 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2316 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2317 InsertAtByte = IsLE ? 8 : 4;
2318 Swap = M1 < 4;
2319 return true;
2320 }
2321 // 0, 1, H, 3 or 4, 5, L, 7
2322 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2323 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2324 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2325 InsertAtByte = IsLE ? 4 : 8;
2326 Swap = M2 < 4;
2327 return true;
2328 }
2329 // 0, 1, 2, H or 4, 5, 6, L
2330 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2331 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2332 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2333 InsertAtByte = IsLE ? 0 : 12;
2334 Swap = M3 < 4;
2335 return true;
2336 }
2337
2338 // If both vector operands for the shuffle are the same vector, the mask will
2339 // contain only elements from the first one and the second one will be undef.
2340 if (N->getOperand(1).isUndef()) {
2341 ShiftElts = 0;
2342 Swap = true;
2343 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2344 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2345 InsertAtByte = IsLE ? 12 : 0;
2346 return true;
2347 }
2348 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2349 InsertAtByte = IsLE ? 8 : 4;
2350 return true;
2351 }
2352 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2353 InsertAtByte = IsLE ? 4 : 8;
2354 return true;
2355 }
2356 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2357 InsertAtByte = IsLE ? 0 : 12;
2358 return true;
2359 }
2360 }
2361
2362 return false;
2363}
2364
2366 bool &Swap, bool IsLE) {
2367 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2368 // Ensure each byte index of the word is consecutive.
2369 if (!isNByteElemShuffleMask(N, 4, 1))
2370 return false;
2371
2372 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2373 unsigned M0 = N->getMaskElt(0) / 4;
2374 unsigned M1 = N->getMaskElt(4) / 4;
2375 unsigned M2 = N->getMaskElt(8) / 4;
2376 unsigned M3 = N->getMaskElt(12) / 4;
2377
2378 // If both vector operands for the shuffle are the same vector, the mask will
2379 // contain only elements from the first one and the second one will be undef.
2380 if (N->getOperand(1).isUndef()) {
2381 assert(M0 < 4 && "Indexing into an undef vector?");
2382 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2383 return false;
2384
2385 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2386 Swap = false;
2387 return true;
2388 }
2389
2390 // Ensure each word index of the ShuffleVector Mask is consecutive.
2391 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2392 return false;
2393
2394 if (IsLE) {
2395 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2396 // Input vectors don't need to be swapped if the leading element
2397 // of the result is one of the 3 left elements of the second vector
2398 // (or if there is no shift to be done at all).
2399 Swap = false;
2400 ShiftElts = (8 - M0) % 8;
2401 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2402 // Input vectors need to be swapped if the leading element
2403 // of the result is one of the 3 left elements of the first vector
2404 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2405 Swap = true;
2406 ShiftElts = (4 - M0) % 4;
2407 }
2408
2409 return true;
2410 } else { // BE
2411 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
2412 // Input vectors don't need to be swapped if the leading element
2413 // of the result is one of the 4 elements of the first vector.
2414 Swap = false;
2415 ShiftElts = M0;
2416 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
2417 // Input vectors need to be swapped if the leading element
2418 // of the result is one of the 4 elements of the right vector.
2419 Swap = true;
2420 ShiftElts = M0 - 4;
2421 }
2422
2423 return true;
2424 }
2425}
2426
2428 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2429
2430 if (!isNByteElemShuffleMask(N, Width, -1))
2431 return false;
2432
2433 for (int i = 0; i < 16; i += Width)
2434 if (N->getMaskElt(i) != i + Width - 1)
2435 return false;
2436
2437 return true;
2438}
2439
2441 return isXXBRShuffleMaskHelper(N, 2);
2442}
2443
2445 return isXXBRShuffleMaskHelper(N, 4);
2446}
2447
2449 return isXXBRShuffleMaskHelper(N, 8);
2450}
2451
2453 return isXXBRShuffleMaskHelper(N, 16);
2454}
2455
2456/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2457/// if the inputs to the instruction should be swapped and set \p DM to the
2458/// value for the immediate.
2459/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2460/// AND element 0 of the result comes from the first input (LE) or second input
2461/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2462/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2463/// mask.
2465 bool &Swap, bool IsLE) {
2466 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2467
2468 // Ensure each byte index of the double word is consecutive.
2469 if (!isNByteElemShuffleMask(N, 8, 1))
2470 return false;
2471
2472 unsigned M0 = N->getMaskElt(0) / 8;
2473 unsigned M1 = N->getMaskElt(8) / 8;
2474 assert(((M0 | M1) < 4) && "A mask element out of bounds?");
2475
2476 // If both vector operands for the shuffle are the same vector, the mask will
2477 // contain only elements from the first one and the second one will be undef.
2478 if (N->getOperand(1).isUndef()) {
2479 if ((M0 | M1) < 2) {
2480 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2481 Swap = false;
2482 return true;
2483 } else
2484 return false;
2485 }
2486
2487 if (IsLE) {
2488 if (M0 > 1 && M1 < 2) {
2489 Swap = false;
2490 } else if (M0 < 2 && M1 > 1) {
2491 M0 = (M0 + 2) % 4;
2492 M1 = (M1 + 2) % 4;
2493 Swap = true;
2494 } else
2495 return false;
2496
2497 // Note: if control flow comes here that means Swap is already set above
2498 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2499 return true;
2500 } else { // BE
2501 if (M0 < 2 && M1 > 1) {
2502 Swap = false;
2503 } else if (M0 > 1 && M1 < 2) {
2504 M0 = (M0 + 2) % 4;
2505 M1 = (M1 + 2) % 4;
2506 Swap = true;
2507 } else
2508 return false;
2509
2510 // Note: if control flow comes here that means Swap is already set above
2511 DM = (M0 << 1) + (M1 & 1);
2512 return true;
2513 }
2514}
2515
2516
2517/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2518/// appropriate for PPC mnemonics (which have a big endian bias - namely
2519/// elements are counted from the left of the vector register).
2520unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2521 SelectionDAG &DAG) {
2522 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2523 assert(isSplatShuffleMask(SVOp, EltSize));
2524 EVT VT = SVOp->getValueType(0);
2525
2526 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2527 return DAG.getDataLayout().isLittleEndian() ? 1 - SVOp->getMaskElt(0)
2528 : SVOp->getMaskElt(0);
2529
2530 if (DAG.getDataLayout().isLittleEndian())
2531 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2532 else
2533 return SVOp->getMaskElt(0) / EltSize;
2534}
2535
2536/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2537/// by using a vspltis[bhw] instruction of the specified element size, return
2538/// the constant being splatted. The ByteSize field indicates the number of
2539/// bytes of each element [124] -> [bhw].
2541 SDValue OpVal;
2542
2543 // If ByteSize of the splat is bigger than the element size of the
2544 // build_vector, then we have a case where we are checking for a splat where
2545 // multiple elements of the buildvector are folded together into a single
2546 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2547 unsigned EltSize = 16/N->getNumOperands();
2548 if (EltSize < ByteSize) {
2549 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2550 SDValue UniquedVals[4];
2551 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
2552
2553 // See if all of the elements in the buildvector agree across.
2554 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2555 if (N->getOperand(i).isUndef()) continue;
2556 // If the element isn't a constant, bail fully out.
2557 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2558
2559 if (!UniquedVals[i&(Multiple-1)].getNode())
2560 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2561 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2562 return SDValue(); // no match.
2563 }
2564
2565 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2566 // either constant or undef values that are identical for each chunk. See
2567 // if these chunks can form into a larger vspltis*.
2568
2569 // Check to see if all of the leading entries are either 0 or -1. If
2570 // neither, then this won't fit into the immediate field.
2571 bool LeadingZero = true;
2572 bool LeadingOnes = true;
2573 for (unsigned i = 0; i != Multiple-1; ++i) {
2574 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2575
2576 LeadingZero &= isNullConstant(UniquedVals[i]);
2577 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2578 }
2579 // Finally, check the least significant entry.
2580 if (LeadingZero) {
2581 if (!UniquedVals[Multiple-1].getNode())
2582 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2583 int Val = UniquedVals[Multiple - 1]->getAsZExtVal();
2584 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2585 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2586 }
2587 if (LeadingOnes) {
2588 if (!UniquedVals[Multiple-1].getNode())
2589 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2590 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2591 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2592 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2593 }
2594
2595 return SDValue();
2596 }
2597
2598 // Check to see if this buildvec has a single non-undef value in its elements.
2599 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2600 if (N->getOperand(i).isUndef()) continue;
2601 if (!OpVal.getNode())
2602 OpVal = N->getOperand(i);
2603 else if (OpVal != N->getOperand(i))
2604 return SDValue();
2605 }
2606
2607 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2608
2609 unsigned ValSizeInBytes = EltSize;
2610 uint64_t Value = 0;
2611 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2612 Value = CN->getZExtValue();
2613 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2614 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
2615 Value = llvm::bit_cast<uint32_t>(CN->getValueAPF().convertToFloat());
2616 }
2617
2618 // If the splat value is larger than the element value, then we can never do
2619 // this splat. The only case that we could fit the replicated bits into our
2620 // immediate field for would be zero, and we prefer to use vxor for it.
2621 if (ValSizeInBytes < ByteSize) return SDValue();
2622
2623 // If the element value is larger than the splat value, check if it consists
2624 // of a repeated bit pattern of size ByteSize.
2625 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2626 return SDValue();
2627
2628 // Properly sign extend the value.
2629 int MaskVal = SignExtend32(Value, ByteSize * 8);
2630
2631 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2632 if (MaskVal == 0) return SDValue();
2633
2634 // Finally, if this value fits in a 5 bit sext field, return it
2635 if (SignExtend32<5>(MaskVal) == MaskVal)
2636 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2637 return SDValue();
2638}
2639
2640//===----------------------------------------------------------------------===//
2641// Addressing Mode Selection
2642//===----------------------------------------------------------------------===//
2643
2644/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2645/// or 64-bit immediate, and if the value can be accurately represented as a
2646/// sign extension from a 16-bit value. If so, this returns true and the
2647/// immediate.
2648bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2649 if (!isa<ConstantSDNode>(N))
2650 return false;
2651
2652 Imm = (int16_t)N->getAsZExtVal();
2653 if (N->getValueType(0) == MVT::i32)
2654 return Imm == (int32_t)N->getAsZExtVal();
2655 else
2656 return Imm == (int64_t)N->getAsZExtVal();
2657}
2659 return isIntS16Immediate(Op.getNode(), Imm);
2660}
2661
2662/// Used when computing address flags for selecting loads and stores.
2663/// If we have an OR, check if the LHS and RHS are provably disjoint.
2664/// An OR of two provably disjoint values is equivalent to an ADD.
2665/// Most PPC load/store instructions compute the effective address as a sum,
2666/// so doing this conversion is useful.
2667static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2668 if (N.getOpcode() != ISD::OR)
2669 return false;
2670 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2671 if (!LHSKnown.Zero.getBoolValue())
2672 return false;
2673 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2674 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2675}
2676
2677/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2678/// be represented as an indexed [r+r] operation.
2680 SDValue &Index,
2681 SelectionDAG &DAG) const {
2682 for (SDNode *U : N->uses()) {
2683 if (MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2684 if (Memop->getMemoryVT() == MVT::f64) {
2685 Base = N.getOperand(0);
2686 Index = N.getOperand(1);
2687 return true;
2688 }
2689 }
2690 }
2691 return false;
2692}
2693
2694/// isIntS34Immediate - This method tests if value of node given can be
2695/// accurately represented as a sign extension from a 34-bit value. If so,
2696/// this returns true and the immediate.
2697bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2698 if (!isa<ConstantSDNode>(N))
2699 return false;
2700
2701 Imm = (int64_t)N->getAsZExtVal();
2702 return isInt<34>(Imm);
2703}
2705 return isIntS34Immediate(Op.getNode(), Imm);
2706}
2707
2708/// SelectAddressRegReg - Given the specified addressed, check to see if it
2709/// can be represented as an indexed [r+r] operation. Returns false if it
2710/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2711/// non-zero and N can be represented by a base register plus a signed 16-bit
2712/// displacement, make a more precise judgement by checking (displacement % \p
2713/// EncodingAlignment).
2716 MaybeAlign EncodingAlignment) const {
2717 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2718 // a [pc+imm].
2720 return false;
2721
2722 int16_t Imm = 0;
2723 if (N.getOpcode() == ISD::ADD) {
2724 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2725 // SPE load/store can only handle 8-bit offsets.
2726 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2727 return true;
2728 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2729 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2730 return false; // r+i
2731 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2732 return false; // r+i
2733
2734 Base = N.getOperand(0);
2735 Index = N.getOperand(1);
2736 return true;
2737 } else if (N.getOpcode() == ISD::OR) {
2738 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2739 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2740 return false; // r+i can fold it if we can.
2741
2742 // If this is an or of disjoint bitfields, we can codegen this as an add
2743 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2744 // disjoint.
2745 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2746
2747 if (LHSKnown.Zero.getBoolValue()) {
2748 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2749 // If all of the bits are known zero on the LHS or RHS, the add won't
2750 // carry.
2751 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2752 Base = N.getOperand(0);
2753 Index = N.getOperand(1);
2754 return true;
2755 }
2756 }
2757 }
2758
2759 return false;
2760}
2761
2762// If we happen to be doing an i64 load or store into a stack slot that has
2763// less than a 4-byte alignment, then the frame-index elimination may need to
2764// use an indexed load or store instruction (because the offset may not be a
2765// multiple of 4). The extra register needed to hold the offset comes from the
2766// register scavenger, and it is possible that the scavenger will need to use
2767// an emergency spill slot. As a result, we need to make sure that a spill slot
2768// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2769// stack slot.
2770static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2771 // FIXME: This does not handle the LWA case.
2772 if (VT != MVT::i64)
2773 return;
2774
2775 // NOTE: We'll exclude negative FIs here, which come from argument
2776 // lowering, because there are no known test cases triggering this problem
2777 // using packed structures (or similar). We can remove this exclusion if
2778 // we find such a test case. The reason why this is so test-case driven is
2779 // because this entire 'fixup' is only to prevent crashes (from the
2780 // register scavenger) on not-really-valid inputs. For example, if we have:
2781 // %a = alloca i1
2782 // %b = bitcast i1* %a to i64*
2783 // store i64* a, i64 b
2784 // then the store should really be marked as 'align 1', but is not. If it
2785 // were marked as 'align 1' then the indexed form would have been
2786 // instruction-selected initially, and the problem this 'fixup' is preventing
2787 // won't happen regardless.
2788 if (FrameIdx < 0)
2789 return;
2790
2792 MachineFrameInfo &MFI = MF.getFrameInfo();
2793
2794 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2795 return;
2796
2797 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2798 FuncInfo->setHasNonRISpills();
2799}
2800
2801/// Returns true if the address N can be represented by a base register plus
2802/// a signed 16-bit displacement [r+imm], and if it is not better
2803/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2804/// displacements that are multiples of that value.
2806 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2807 MaybeAlign EncodingAlignment) const {
2808 // FIXME dl should come from parent load or store, not from address
2809 SDLoc dl(N);
2810
2811 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2812 // a [pc+imm].
2814 return false;
2815
2816 // If this can be more profitably realized as r+r, fail.
2817 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2818 return false;
2819
2820 if (N.getOpcode() == ISD::ADD) {
2821 int16_t imm = 0;
2822 if (isIntS16Immediate(N.getOperand(1), imm) &&
2823 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2824 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2825 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2826 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2827 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2828 } else {
2829 Base = N.getOperand(0);
2830 }
2831 return true; // [r+i]
2832 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2833 // Match LOAD (ADD (X, Lo(G))).
2834 assert(!N.getOperand(1).getConstantOperandVal(1) &&
2835 "Cannot handle constant offsets yet!");
2836 Disp = N.getOperand(1).getOperand(0); // The global address.
2841 Base = N.getOperand(0);
2842 return true; // [&g+r]
2843 }
2844 } else if (N.getOpcode() == ISD::OR) {
2845 int16_t imm = 0;
2846 if (isIntS16Immediate(N.getOperand(1), imm) &&
2847 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2848 // If this is an or of disjoint bitfields, we can codegen this as an add
2849 // (for better address arithmetic) if the LHS and RHS of the OR are
2850 // provably disjoint.
2851 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2852
2853 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2854 // If all of the bits are known zero on the LHS or RHS, the add won't
2855 // carry.
2856 if (FrameIndexSDNode *FI =
2857 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2858 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2859 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2860 } else {
2861 Base = N.getOperand(0);
2862 }
2863 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2864 return true;
2865 }
2866 }
2867 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2868 // Loading from a constant address.
2869
2870 // If this address fits entirely in a 16-bit sext immediate field, codegen
2871 // this as "d, 0"
2872 int16_t Imm;
2873 if (isIntS16Immediate(CN, Imm) &&
2874 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2875 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2876 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2877 CN->getValueType(0));
2878 return true;
2879 }
2880
2881 // Handle 32-bit sext immediates with LIS + addr mode.
2882 if ((CN->getValueType(0) == MVT::i32 ||
2883 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2884 (!EncodingAlignment ||
2885 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2886 int Addr = (int)CN->getZExtValue();
2887
2888 // Otherwise, break this down into an LIS + disp.
2889 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2890
2891 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2892 MVT::i32);
2893 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2894 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2895 return true;
2896 }
2897 }
2898
2899 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2900 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2901 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2902 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2903 } else
2904 Base = N;
2905 return true; // [r+0]
2906}
2907
2908/// Similar to the 16-bit case but for instructions that take a 34-bit
2909/// displacement field (prefixed loads/stores).
2911 SDValue &Base,
2912 SelectionDAG &DAG) const {
2913 // Only on 64-bit targets.
2914 if (N.getValueType() != MVT::i64)
2915 return false;
2916
2917 SDLoc dl(N);
2918 int64_t Imm = 0;
2919
2920 if (N.getOpcode() == ISD::ADD) {
2921 if (!isIntS34Immediate(N.getOperand(1), Imm))
2922 return false;
2923 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2924 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2925 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2926 else
2927 Base = N.getOperand(0);
2928 return true;
2929 }
2930
2931 if (N.getOpcode() == ISD::OR) {
2932 if (!isIntS34Immediate(N.getOperand(1), Imm))
2933 return false;
2934 // If this is an or of disjoint bitfields, we can codegen this as an add
2935 // (for better address arithmetic) if the LHS and RHS of the OR are
2936 // provably disjoint.
2937 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2938 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2939 return false;
2940 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2941 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2942 else
2943 Base = N.getOperand(0);
2944 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2945 return true;
2946 }
2947
2948 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2949 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2950 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2951 return true;
2952 }
2953
2954 return false;
2955}
2956
2957/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2958/// represented as an indexed [r+r] operation.
2960 SDValue &Index,
2961 SelectionDAG &DAG) const {
2962 // Check to see if we can easily represent this as an [r+r] address. This
2963 // will fail if it thinks that the address is more profitably represented as
2964 // reg+imm, e.g. where imm = 0.
2965 if (SelectAddressRegReg(N, Base, Index, DAG))
2966 return true;
2967
2968 // If the address is the result of an add, we will utilize the fact that the
2969 // address calculation includes an implicit add. However, we can reduce
2970 // register pressure if we do not materialize a constant just for use as the
2971 // index register. We only get rid of the add if it is not an add of a
2972 // value and a 16-bit signed constant and both have a single use.
2973 int16_t imm = 0;
2974 if (N.getOpcode() == ISD::ADD &&
2975 (!isIntS16Immediate(N.getOperand(1), imm) ||
2976 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2977 Base = N.getOperand(0);
2978 Index = N.getOperand(1);
2979 return true;
2980 }
2981
2982 // Otherwise, do it the hard way, using R0 as the base register.
2983 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2984 N.getValueType());
2985 Index = N;
2986 return true;
2987}
2988
2989template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2990 Ty *PCRelCand = dyn_cast<Ty>(N);
2991 return PCRelCand && (PPCInstrInfo::hasPCRelFlag(PCRelCand->getTargetFlags()));
2992}
2993
2994/// Returns true if this address is a PC Relative address.
2995/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2996/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2998 // This is a materialize PC Relative node. Always select this as PC Relative.
2999 Base = N;
3000 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
3001 return true;
3002 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
3003 isValidPCRelNode<GlobalAddressSDNode>(N) ||
3004 isValidPCRelNode<JumpTableSDNode>(N) ||
3005 isValidPCRelNode<BlockAddressSDNode>(N))
3006 return true;
3007 return false;
3008}
3009
3010/// Returns true if we should use a direct load into vector instruction
3011/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
3012static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
3013
3014 // If there are any other uses other than scalar to vector, then we should
3015 // keep it as a scalar load -> direct move pattern to prevent multiple
3016 // loads.
3017 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
3018 if (!LD)
3019 return false;
3020
3021 EVT MemVT = LD->getMemoryVT();
3022 if (!MemVT.isSimple())
3023 return false;
3024 switch(MemVT.getSimpleVT().SimpleTy) {
3025 case MVT::i64:
3026 break;
3027 case MVT::i32:
3028 if (!ST.hasP8Vector())
3029 return false;
3030 break;
3031 case MVT::i16:
3032 case MVT::i8:
3033 if (!ST.hasP9Vector())
3034 return false;
3035 break;
3036 default:
3037 return false;
3038 }
3039
3040 SDValue LoadedVal(N, 0);
3041 if (!LoadedVal.hasOneUse())
3042 return false;
3043
3044 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
3045 UI != UE; ++UI)
3046 if (UI.getUse().get().getResNo() == 0 &&
3047 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
3048 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
3049 return false;
3050
3051 return true;
3052}
3053
3054/// getPreIndexedAddressParts - returns true by value, base pointer and
3055/// offset pointer and addressing mode by reference if the node's address
3056/// can be legally represented as pre-indexed load / store address.
3058 SDValue &Offset,
3060 SelectionDAG &DAG) const {
3061 if (DisablePPCPreinc) return false;
3062
3063 bool isLoad = true;
3064 SDValue Ptr;
3065 EVT VT;
3066 Align Alignment;
3067 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3068 Ptr = LD->getBasePtr();
3069 VT = LD->getMemoryVT();
3070 Alignment = LD->getAlign();
3071 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3072 Ptr = ST->getBasePtr();
3073 VT = ST->getMemoryVT();
3074 Alignment = ST->getAlign();
3075 isLoad = false;
3076 } else
3077 return false;
3078
3079 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
3080 // instructions because we can fold these into a more efficient instruction
3081 // instead, (such as LXSD).
3082 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
3083 return false;
3084 }
3085
3086 // PowerPC doesn't have preinc load/store instructions for vectors
3087 if (VT.isVector())
3088 return false;
3089
3090 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
3091 // Common code will reject creating a pre-inc form if the base pointer
3092 // is a frame index, or if N is a store and the base pointer is either
3093 // the same as or a predecessor of the value being stored. Check for
3094 // those situations here, and try with swapped Base/Offset instead.
3095 bool Swap = false;
3096
3097 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
3098 Swap = true;
3099 else if (!isLoad) {
3100 SDValue Val = cast<StoreSDNode>(N)->getValue();
3101 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
3102 Swap = true;
3103 }
3104
3105 if (Swap)
3107
3108 AM = ISD::PRE_INC;
3109 return true;
3110 }
3111
3112 // LDU/STU can only handle immediates that are a multiple of 4.
3113 if (VT != MVT::i64) {
3114 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, std::nullopt))
3115 return false;
3116 } else {
3117 // LDU/STU need an address with at least 4-byte alignment.
3118 if (Alignment < Align(4))
3119 return false;
3120
3121 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3122 return false;
3123 }
3124
3125 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3126 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3127 // sext i32 to i64 when addr mode is r+i.
3128 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3129 LD->getExtensionType() == ISD::SEXTLOAD &&
3130 isa<ConstantSDNode>(Offset))
3131 return false;
3132 }
3133
3134 AM = ISD::PRE_INC;
3135 return true;
3136}
3137
3138//===----------------------------------------------------------------------===//
3139// LowerOperation implementation
3140//===----------------------------------------------------------------------===//
3141
3142/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3143/// and LoOpFlags to the target MO flags.
3144static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3145 unsigned &HiOpFlags, unsigned &LoOpFlags,
3146 const GlobalValue *GV = nullptr) {
3147 HiOpFlags = PPCII::MO_HA;
3148 LoOpFlags = PPCII::MO_LO;
3149
3150 // Don't use the pic base if not in PIC relocation model.
3151 if (IsPIC) {
3152 HiOpFlags = PPCII::MO_PIC_HA_FLAG;
3153 LoOpFlags = PPCII::MO_PIC_LO_FLAG;
3154 }
3155}
3156
3157static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3158 SelectionDAG &DAG) {
3159 SDLoc DL(HiPart);
3160 EVT PtrVT = HiPart.getValueType();
3161 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3162
3163 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3164 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3165
3166 // With PIC, the first instruction is actually "GR+hi(&G)".
3167 if (isPIC)
3168 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3169 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3170
3171 // Generate non-pic code that has direct accesses to the constant pool.
3172 // The address of the global is just (hi(&g)+lo(&g)).
3173 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3174}
3175
3177 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3178 FuncInfo->setUsesTOCBasePtr();
3179}
3180
3183}
3184
3185SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3186 SDValue GA) const {
3187 const bool Is64Bit = Subtarget.isPPC64();
3188 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3189 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3190 : Subtarget.isAIXABI()
3191 ? DAG.getRegister(PPC::R2, VT)
3192 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3193 SDValue Ops[] = { GA, Reg };
3194 return DAG.getMemIntrinsicNode(
3195 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3198}
3199
3200SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3201 SelectionDAG &DAG) const {
3202 EVT PtrVT = Op.getValueType();
3203 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3204 const Constant *C = CP->getConstVal();
3205
3206 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3207 // The actual address of the GlobalValue is stored in the TOC.
3208 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3209 if (Subtarget.isUsingPCRelativeCalls()) {
3210 SDLoc DL(CP);
3211 EVT Ty = getPointerTy(DAG.getDataLayout());
3212 SDValue ConstPool = DAG.getTargetConstantPool(
3213 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3214 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3215 }
3216 setUsesTOCBasePtr(DAG);
3217 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3218 return getTOCEntry(DAG, SDLoc(CP), GA);
3219 }
3220
3221 unsigned MOHiFlag, MOLoFlag;
3222 bool IsPIC = isPositionIndependent();
3223 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3224
3225 if (IsPIC && Subtarget.isSVR4ABI()) {
3226 SDValue GA =
3227 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3228 return getTOCEntry(DAG, SDLoc(CP), GA);
3229 }
3230
3231 SDValue CPIHi =
3232 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3233 SDValue CPILo =
3234 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3235 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3236}
3237
3238// For 64-bit PowerPC, prefer the more compact relative encodings.
3239// This trades 32 bits per jump table entry for one or two instructions
3240// on the jump site.
3242 if (isJumpTableRelative())
3244
3246}
3247
3250 return false;
3251 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3252 return true;
3254}
3255
3257 SelectionDAG &DAG) const {
3258 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3260
3261 switch (getTargetMachine().getCodeModel()) {
3262 case CodeModel::Small:
3263 case CodeModel::Medium:
3265 default:
3266 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3268 }
3269}
3270
3271const MCExpr *
3273 unsigned JTI,
3274 MCContext &Ctx) const {
3275 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3277
3278 switch (getTargetMachine().getCodeModel()) {
3279 case CodeModel::Small:
3280 case CodeModel::Medium:
3282 default:
3283 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3284 }
3285}
3286
3287SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3288 EVT PtrVT = Op.getValueType();
3289 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3290
3291 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3292 if (Subtarget.isUsingPCRelativeCalls()) {
3293 SDLoc DL(JT);
3294 EVT Ty = getPointerTy(DAG.getDataLayout());
3295 SDValue GA =
3296 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3297 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3298 return MatAddr;
3299 }
3300
3301 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3302 // The actual address of the GlobalValue is stored in the TOC.
3303 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3304 setUsesTOCBasePtr(DAG);
3305 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3306 return getTOCEntry(DAG, SDLoc(JT), GA);
3307 }
3308
3309 unsigned MOHiFlag, MOLoFlag;
3310 bool IsPIC = isPositionIndependent();
3311 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3312
3313 if (IsPIC && Subtarget.isSVR4ABI()) {
3314 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3316 return getTOCEntry(DAG, SDLoc(GA), GA);
3317 }
3318
3319 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3320 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3321 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3322}
3323
3324SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3325 SelectionDAG &DAG) const {
3326 EVT PtrVT = Op.getValueType();
3327 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3328 const BlockAddress *BA = BASDN->getBlockAddress();
3329
3330 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3331 if (Subtarget.isUsingPCRelativeCalls()) {
3332 SDLoc DL(BASDN);
3333 EVT Ty = getPointerTy(DAG.getDataLayout());
3334 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3336 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3337 return MatAddr;
3338 }
3339
3340 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3341 // The actual BlockAddress is stored in the TOC.
3342 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3343 setUsesTOCBasePtr(DAG);
3344 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3345 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3346 }
3347
3348 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3349 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3350 return getTOCEntry(
3351 DAG, SDLoc(BASDN),
3352 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3353
3354 unsigned MOHiFlag, MOLoFlag;
3355 bool IsPIC = isPositionIndependent();
3356 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3357 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3358 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3359 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3360}
3361
3362SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3363 SelectionDAG &DAG) const {
3364 if (Subtarget.isAIXABI())
3365 return LowerGlobalTLSAddressAIX(Op, DAG);
3366
3367 return LowerGlobalTLSAddressLinux(Op, DAG);
3368}
3369
3370/// updateForAIXShLibTLSModelOpt - Helper to initialize TLS model opt settings,
3371/// and then apply the update.
3373 SelectionDAG &DAG,
3374 const TargetMachine &TM) {
3375 // Initialize TLS model opt setting lazily:
3376 // (1) Use initial-exec for single TLS var references within current function.
3377 // (2) Use local-dynamic for multiple TLS var references within current
3378 // function.
3379 PPCFunctionInfo *FuncInfo =
3381 if (!FuncInfo->isAIXFuncTLSModelOptInitDone()) {
3383 // Iterate over all instructions within current function, collect all TLS
3384 // global variables (global variables taken as the first parameter to
3385 // Intrinsic::threadlocal_address).
3386 const Function &Func = DAG.getMachineFunction().getFunction();
3387 for (Function::const_iterator BI = Func.begin(), BE = Func.end(); BI != BE;
3388 ++BI)
3389 for (BasicBlock::const_iterator II = BI->begin(), IE = BI->end();
3390 II != IE; ++II)
3391 if (II->getOpcode() == Instruction::Call)
3392 if (const CallInst *CI = dyn_cast<const CallInst>(&*II))
3393 if (Function *CF = CI->getCalledFunction())
3394 if (CF->isDeclaration() &&
3395 CF->getIntrinsicID() == Intrinsic::threadlocal_address)
3396 if (const GlobalValue *GV =
3397 dyn_cast<GlobalValue>(II->getOperand(0))) {
3398 TLSModel::Model GVModel = TM.getTLSModel(GV);
3399 if (GVModel == TLSModel::LocalDynamic)
3400 TLSGV.insert(GV);
3401 }
3402
3403 unsigned TLSGVCnt = TLSGV.size();
3404 LLVM_DEBUG(dbgs() << format("LocalDynamic TLSGV count:%d\n", TLSGVCnt));
3405 if (TLSGVCnt <= PPCAIXTLSModelOptUseIEForLDLimit)
3406 FuncInfo->setAIXFuncUseTLSIEForLD();
3408 }
3409
3410 if (FuncInfo->isAIXFuncUseTLSIEForLD()) {
3411 LLVM_DEBUG(
3412 dbgs() << DAG.getMachineFunction().getName()
3413 << " function is using the TLS-IE model for TLS-LD access.\n");
3414 Model = TLSModel::InitialExec;
3415 }
3416}
3417
3418SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3419 SelectionDAG &DAG) const {
3420 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3421
3422 if (DAG.getTarget().useEmulatedTLS())
3423 report_fatal_error("Emulated TLS is not yet supported on AIX");
3424
3425 SDLoc dl(GA);
3426 const GlobalValue *GV = GA->getGlobal();
3427 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3428 bool Is64Bit = Subtarget.isPPC64();
3430
3431 // Apply update to the TLS model.
3432 if (Subtarget.hasAIXShLibTLSModelOpt())
3434
3435 bool IsTLSLocalExecModel = Model == TLSModel::LocalExec;
3436
3437 if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) {
3438 bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
3439 bool HasAIXSmallTLSGlobalAttr = false;
3440 SDValue VariableOffsetTGA =
3441 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TPREL_FLAG);
3442 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3443 SDValue TLSReg;
3444
3445 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
3446 if (GVar->hasAttribute("aix-small-tls"))
3447 HasAIXSmallTLSGlobalAttr = true;
3448
3449 if (Is64Bit) {
3450 // For local-exec and initial-exec on AIX (64-bit), the sequence generated
3451 // involves a load of the variable offset (from the TOC), followed by an
3452 // add of the loaded variable offset to R13 (the thread pointer).
3453 // This code sequence looks like:
3454 // ld reg1,var[TC](2)
3455 // add reg2, reg1, r13 // r13 contains the thread pointer
3456 TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3457
3458 // With the -maix-small-local-exec-tls option, or with the "aix-small-tls"
3459 // global variable attribute, produce a faster access sequence for
3460 // local-exec TLS variables where the offset from the TLS base is encoded
3461 // as an immediate operand.
3462 //
3463 // We only utilize the faster local-exec access sequence when the TLS
3464 // variable has a size within the policy limit. We treat types that are
3465 // not sized or are empty as being over the policy size limit.
3466 if ((HasAIXSmallLocalExecTLS || HasAIXSmallTLSGlobalAttr) &&
3467 IsTLSLocalExecModel) {
3468 Type *GVType = GV->getValueType();
3469 if (GVType->isSized() && !GVType->isEmptyTy() &&
3470 GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
3472 return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA, TLSReg);
3473 }
3474 } else {
3475 // For local-exec and initial-exec on AIX (32-bit), the sequence generated
3476 // involves loading the variable offset from the TOC, generating a call to
3477 // .__get_tpointer to get the thread pointer (which will be in R3), and
3478 // adding the two together:
3479 // lwz reg1,var[TC](2)
3480 // bla .__get_tpointer
3481 // add reg2, reg1, r3
3482 TLSReg = DAG.getNode(PPCISD::GET_TPOINTER, dl, PtrVT);
3483
3484 // We do not implement the 32-bit version of the faster access sequence
3485 // for local-exec that is controlled by the -maix-small-local-exec-tls
3486 // option, or the "aix-small-tls" global variable attribute.
3487 if (HasAIXSmallLocalExecTLS || HasAIXSmallTLSGlobalAttr)
3488 report_fatal_error("The small-local-exec TLS access sequence is "
3489 "currently only supported on AIX (64-bit mode).");
3490 }
3491 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
3492 }
3493
3494 if (Model == TLSModel::LocalDynamic) {
3495 bool HasAIXSmallLocalDynamicTLS = Subtarget.hasAIXSmallLocalDynamicTLS();
3496
3497 // We do not implement the 32-bit version of the faster access sequence
3498 // for local-dynamic that is controlled by -maix-small-local-dynamic-tls.
3499 if (!Is64Bit && HasAIXSmallLocalDynamicTLS)
3500 report_fatal_error("The small-local-dynamic TLS access sequence is "
3501 "currently only supported on AIX (64-bit mode).");
3502
3503 // For local-dynamic on AIX, we need to generate one TOC entry for each
3504 // variable offset, and a single module-handle TOC entry for the entire
3505 // file.
3506
3507 SDValue VariableOffsetTGA =
3508 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSLD_FLAG);
3509 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3510
3512 GlobalVariable *TLSGV =
3513 dyn_cast_or_null<GlobalVariable>(M->getOrInsertGlobal(
3514 StringRef("_$TLSML"), PointerType::getUnqual(*DAG.getContext())));
3516 assert(TLSGV && "Not able to create GV for _$TLSML.");
3517 SDValue ModuleHandleTGA =
3518 DAG.getTargetGlobalAddress(TLSGV, dl, PtrVT, 0, PPCII::MO_TLSLDM_FLAG);
3519 SDValue ModuleHandleTOC = getTOCEntry(DAG, dl, ModuleHandleTGA);
3520 SDValue ModuleHandle =
3521 DAG.getNode(PPCISD::TLSLD_AIX, dl, PtrVT, ModuleHandleTOC);
3522
3523 // With the -maix-small-local-dynamic-tls option, produce a faster access
3524 // sequence for local-dynamic TLS variables where the offset from the
3525 // module-handle is encoded as an immediate operand.
3526 //
3527 // We only utilize the faster local-dynamic access sequence when the TLS
3528 // variable has a size within the policy limit. We treat types that are
3529 // not sized or are empty as being over the policy size limit.
3530 if (HasAIXSmallLocalDynamicTLS) {
3531 Type *GVType = GV->getValueType();
3532 if (GVType->isSized() && !GVType->isEmptyTy() &&
3533 GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
3535 return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA,
3536 ModuleHandle);
3537 }
3538
3539 return DAG.getNode(ISD::ADD, dl, PtrVT, ModuleHandle, VariableOffset);
3540 }
3541
3542 // If Local- or Initial-exec or Local-dynamic is not possible or specified,
3543 // all GlobalTLSAddress nodes are lowered using the general-dynamic model. We
3544 // need to generate two TOC entries, one for the variable offset, one for the
3545 // region handle. The global address for the TOC entry of the region handle is
3546 // created with the MO_TLSGDM_FLAG flag and the global address for the TOC
3547 // entry of the variable offset is created with MO_TLSGD_FLAG.
3548 SDValue VariableOffsetTGA =
3549 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3550 SDValue RegionHandleTGA =
3551 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3552 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3553 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3554 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3555 RegionHandle);
3556}
3557
3558SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3559 SelectionDAG &DAG) const {
3560 // FIXME: TLS addresses currently use medium model code sequences,
3561 // which is the most useful form. Eventually support for small and
3562 // large models could be added if users need it, at the cost of
3563 // additional complexity.
3564 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3565 if (DAG.getTarget().useEmulatedTLS())
3566 return LowerToTLSEmulatedModel(GA, DAG);
3567
3568 SDLoc dl(GA);
3569 const GlobalValue *GV = GA->getGlobal();
3570 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3571 bool is64bit = Subtarget.isPPC64();
3572 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3573 PICLevel::Level picLevel = M->getPICLevel();
3574
3576 TLSModel::Model Model = TM.getTLSModel(GV);
3577
3578 if (Model == TLSModel::LocalExec) {
3579 if (Subtarget.isUsingPCRelativeCalls()) {
3580 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3581 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3583 SDValue MatAddr =
3584 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3585 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3586 }
3587
3588 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3590 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3592 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3593 : DAG.getRegister(PPC::R2, MVT::i32);
3594
3595 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3596 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3597 }
3598
3599 if (Model == TLSModel::InitialExec) {
3600 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3602 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3603 SDValue TGATLS = DAG.getTargetGlobalAddress(
3604 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_TLS_PCREL_FLAG : PPCII::MO_TLS);
3605 SDValue TPOffset;
3606 if (IsPCRel) {
3607 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3608 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3610 } else {
3611 SDValue GOTPtr;
3612 if (is64bit) {
3613 setUsesTOCBasePtr(DAG);
3614 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3615 GOTPtr =
3616 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3617 } else {
3618 if (!TM.isPositionIndependent())
3619 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3620 else if (picLevel == PICLevel::SmallPIC)
3621 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3622 else
3623 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3624 }
3625 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3626 }
3627 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3628 }
3629
3630 if (Model == TLSModel::GeneralDynamic) {
3631 if (Subtarget.isUsingPCRelativeCalls()) {
3632 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3634 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3635 }
3636
3637 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3638 SDValue GOTPtr;
3639 if (is64bit) {
3640 setUsesTOCBasePtr(DAG);
3641 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3642 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3643 GOTReg, TGA);
3644 } else {
3645 if (picLevel == PICLevel::SmallPIC)
3646 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3647 else
3648 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3649 }
3650 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3651 GOTPtr, TGA, TGA);
3652 }
3653
3654 if (Model == TLSModel::LocalDynamic) {
3655 if (Subtarget.isUsingPCRelativeCalls()) {
3656 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3658 SDValue MatPCRel =
3659 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3660 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3661 }
3662
3663 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3664 SDValue GOTPtr;
3665 if (is64bit) {
3666 setUsesTOCBasePtr(DAG);
3667 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3668 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3669 GOTReg, TGA);
3670 } else {
3671 if (picLevel == PICLevel::SmallPIC)
3672 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3673 else
3674 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3675 }
3676 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3677 PtrVT, GOTPtr, TGA, TGA);
3678 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3679 PtrVT, TLSAddr, TGA);
3680 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3681 }
3682
3683 llvm_unreachable("Unknown TLS model!");
3684}
3685
3686SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3687 SelectionDAG &DAG) const {
3688 EVT PtrVT = Op.getValueType();
3689 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3690 SDLoc DL(GSDN);
3691 const GlobalValue *GV = GSDN->