LLVM 17.0.0git
PPCISelLowering.cpp
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1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/ADT/StringRef.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
85#include "llvm/Support/Debug.h"
87#include "llvm/Support/Format.h"
93#include <algorithm>
94#include <cassert>
95#include <cstdint>
96#include <iterator>
97#include <list>
98#include <optional>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
125 "ppc-quadword-atomics",
126 cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
127 cl::Hidden);
128
129static cl::opt<bool>
130 DisablePerfectShuffle("ppc-disable-perfect-shuffle",
131 cl::desc("disable vector permute decomposition"),
132 cl::init(true), cl::Hidden);
133
135 "disable-auto-paired-vec-st",
136 cl::desc("disable automatically generated 32byte paired vector stores"),
137 cl::init(true), cl::Hidden);
138
139STATISTIC(NumTailCalls, "Number of tail calls");
140STATISTIC(NumSiblingCalls, "Number of sibling calls");
141STATISTIC(ShufflesHandledWithVPERM,
142 "Number of shuffles lowered to a VPERM or XXPERM");
143STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
144
145static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
146
147static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
148
149static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
150
151// FIXME: Remove this once the bug has been fixed!
153
155 const PPCSubtarget &STI)
156 : TargetLowering(TM), Subtarget(STI) {
157 // Initialize map that relates the PPC addressing modes to the computed flags
158 // of a load/store instruction. The map is used to determine the optimal
159 // addressing mode when selecting load and stores.
160 initializeAddrModeMap();
161 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
162 // arguments are at least 4/8 bytes aligned.
163 bool isPPC64 = Subtarget.isPPC64();
164 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
165
166 // Set up the register classes.
167 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
168 if (!useSoftFloat()) {
169 if (hasSPE()) {
170 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
171 // EFPU2 APU only supports f32
172 if (!Subtarget.hasEFPU2())
173 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
174 } else {
175 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
176 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
177 }
178 }
179
180 // Match BITREVERSE to customized fast code sequence in the td file.
183
184 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
186
187 // Custom lower inline assembly to check for special registers.
190
191 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
192 for (MVT VT : MVT::integer_valuetypes()) {
195 }
196
197 if (Subtarget.isISA3_0()) {
198 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
199 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
200 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
201 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
202 } else {
203 // No extending loads from f16 or HW conversions back and forth.
204 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
207 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
210 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
211 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
212 }
213
214 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
215
216 // PowerPC has pre-inc load and store's.
227 if (!Subtarget.hasSPE()) {
232 }
233
234 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
235 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
236 for (MVT VT : ScalarIntVTs) {
241 }
242
243 if (Subtarget.useCRBits()) {
245
246 if (isPPC64 || Subtarget.hasFPCVT()) {
249 isPPC64 ? MVT::i64 : MVT::i32);
252 isPPC64 ? MVT::i64 : MVT::i32);
253
256 isPPC64 ? MVT::i64 : MVT::i32);
259 isPPC64 ? MVT::i64 : MVT::i32);
260
263 isPPC64 ? MVT::i64 : MVT::i32);
266 isPPC64 ? MVT::i64 : MVT::i32);
267
270 isPPC64 ? MVT::i64 : MVT::i32);
273 isPPC64 ? MVT::i64 : MVT::i32);
274 } else {
279 }
280
281 // PowerPC does not support direct load/store of condition registers.
284
285 // FIXME: Remove this once the ANDI glue bug is fixed:
286 if (ANDIGlueBug)
288
289 for (MVT VT : MVT::integer_valuetypes()) {
292 setTruncStoreAction(VT, MVT::i1, Expand);
293 }
294
295 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
296 }
297
298 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
299 // PPC (the libcall is not available).
304
305 // We do not currently implement these libm ops for PowerPC.
306 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
307 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
309 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
311 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
312
313 // PowerPC has no SREM/UREM instructions unless we are on P9
314 // On P9 we may use a hardware instruction to compute the remainder.
315 // When the result of both the remainder and the division is required it is
316 // more efficient to compute the remainder from the result of the division
317 // rather than use the remainder instruction. The instructions are legalized
318 // directly because the DivRemPairsPass performs the transformation at the IR
319 // level.
320 if (Subtarget.isISA3_0()) {
325 } else {
330 }
331
332 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
341
342 // Handle constrained floating-point operations of scalar.
343 // TODO: Handle SPE specific operation.
349
354
355 if (!Subtarget.hasSPE()) {
358 }
359
360 if (Subtarget.hasVSX()) {
363 }
364
365 if (Subtarget.hasFSQRT()) {
368 }
369
370 if (Subtarget.hasFPRND()) {
375
380 }
381
382 // We don't support sin/cos/sqrt/fmod/pow
393
394 // MASS transformation for LLVM intrinsics with replicating fast-math flag
395 // to be consistent to PPCGenScalarMASSEntries pass
396 if (TM.getOptLevel() == CodeGenOpt::Aggressive) {
409 }
410
411 if (Subtarget.hasSPE()) {
414 } else {
415 setOperationAction(ISD::FMA , MVT::f64, Legal);
416 setOperationAction(ISD::FMA , MVT::f32, Legal);
417 }
418
419 if (Subtarget.hasSPE())
420 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
421
423
424 // If we're enabling GP optimizations, use hardware square root
425 if (!Subtarget.hasFSQRT() &&
426 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
427 Subtarget.hasFRE()))
429
430 if (!Subtarget.hasFSQRT() &&
431 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
432 Subtarget.hasFRES()))
434
435 if (Subtarget.hasFCPSGN()) {
438 } else {
441 }
442
443 if (Subtarget.hasFPRND()) {
448
453 }
454
455 // Prior to P10, PowerPC does not have BSWAP, but we can use vector BSWAP
456 // instruction xxbrd to speed up scalar BSWAP64.
457 if (Subtarget.isISA3_1()) {
460 } else {
463 ISD::BSWAP, MVT::i64,
464 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
465 }
466
467 // CTPOP or CTTZ were introduced in P8/P9 respectively
468 if (Subtarget.isISA3_0()) {
469 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
470 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
471 } else {
472 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
473 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
474 }
475
476 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
479 } else {
482 }
483
484 // PowerPC does not have ROTR
487
488 if (!Subtarget.useCRBits()) {
489 // PowerPC does not have Select
494 }
495
496 // PowerPC wants to turn select_cc of FP into fsel when possible.
499
500 // PowerPC wants to optimize integer setcc a bit
501 if (!Subtarget.useCRBits())
503
504 if (Subtarget.hasFPU()) {
508
512 }
513
514 // PowerPC does not have BRCOND which requires SetCC
515 if (!Subtarget.useCRBits())
517
519
520 if (Subtarget.hasSPE()) {
521 // SPE has built-in conversions
528
529 // SPE supports signaling compare of f32/f64.
532 } else {
533 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
536
537 // PowerPC does not have [U|S]INT_TO_FP
542 }
543
544 if (Subtarget.hasDirectMove() && isPPC64) {
549 if (TM.Options.UnsafeFPMath) {
558 }
559 } else {
564 }
565
566 // We cannot sextinreg(i1). Expand to shifts.
568
569 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
570 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
571 // support continuation, user-level threading, and etc.. As a result, no
572 // other SjLj exception interfaces are implemented and please don't build
573 // your own exception handling based on them.
574 // LLVM/Clang supports zero-cost DWARF exception handling.
577
578 // We want to legalize GlobalAddress and ConstantPool nodes into the
579 // appropriate instructions to materialize the address.
590
591 // TRAP is legal.
592 setOperationAction(ISD::TRAP, MVT::Other, Legal);
593
594 // TRAMPOLINE is custom lowered.
597
598 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
600
601 if (Subtarget.is64BitELFABI()) {
602 // VAARG always uses double-word chunks, so promote anything smaller.
604 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
606 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
608 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
610 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
612 } else if (Subtarget.is32BitELFABI()) {
613 // VAARG is custom lowered with the 32-bit SVR4 ABI.
616 } else
618
619 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
620 if (Subtarget.is32BitELFABI())
622 else
624
625 // Use the default implementation.
626 setOperationAction(ISD::VAEND , MVT::Other, Expand);
635
636 // We want to custom lower some of our intrinsics.
642
643 // To handle counter-based loop conditions.
645
650
651 // Comparisons that require checking two conditions.
652 if (Subtarget.hasSPE()) {
657 }
670
673
674 if (Subtarget.has64BitSupport()) {
675 // They also have instructions for converting between i64 and fp.
684 // This is just the low 32 bits of a (signed) fp->i64 conversion.
685 // We cannot do this with Promote because i64 is not a legal type.
688
689 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
692 }
693 } else {
694 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
695 if (Subtarget.hasSPE()) {
698 } else {
701 }
702 }
703
704 // With the instructions enabled under FPCVT, we can do everything.
705 if (Subtarget.hasFPCVT()) {
706 if (Subtarget.has64BitSupport()) {
715 }
716
725 }
726
727 if (Subtarget.use64BitRegs()) {
728 // 64-bit PowerPC implementations can support i64 types directly
729 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
730 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
732 // 64-bit PowerPC wants to expand i128 shifts itself.
736 } else {
737 // 32-bit PowerPC wants to expand i64 shifts itself.
741 }
742
743 // PowerPC has better expansions for funnel shifts than the generic
744 // TargetLowering::expandFunnelShift.
745 if (Subtarget.has64BitSupport()) {
748 }
751
752 if (Subtarget.hasVSX()) {
757 }
758
759 if (Subtarget.hasAltivec()) {
760 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
765 }
766 // First set operation action for all vector types to expand. Then we
767 // will selectively turn on ones that can be effectively codegen'd.
769 // add/sub are legal for all supported vector VT's.
772
773 // For v2i64, these are only valid with P8Vector. This is corrected after
774 // the loop.
775 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
780 }
781 else {
786 }
787
788 if (Subtarget.hasVSX()) {
791 }
792
793 // Vector instructions introduced in P8
794 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
797 }
798 else {
801 }
802
803 // Vector instructions introduced in P9
804 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
806 else
808
809 // We promote all shuffles to v16i8.
811 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
812
813 // We promote all non-typed operations to v4i32.
815 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
817 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
819 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
821 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
823 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
826 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
828 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
829
830 // No other operations are legal.
869
870 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
871 setTruncStoreAction(VT, InnerVT, Expand);
874 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
875 }
876 }
878 if (!Subtarget.hasP8Vector()) {
879 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
880 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
881 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
882 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
883 }
884
885 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
886 // with merges, splats, etc.
888
889 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
890 // are cheap, so handle them before they get expanded to scalar.
896
897 setOperationAction(ISD::AND , MVT::v4i32, Legal);
898 setOperationAction(ISD::OR , MVT::v4i32, Legal);
899 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
900 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
902 Subtarget.useCRBits() ? Legal : Expand);
903 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
913 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
916
917 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
918 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
919 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
920 if (Subtarget.hasAltivec())
921 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
923 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
924 if (Subtarget.hasP8Altivec())
925 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
926
927 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
928 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
929 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
930 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
931
932 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
934
935 if (Subtarget.hasVSX()) {
936 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
939 }
940
941 if (Subtarget.hasP8Altivec())
942 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
943 else
944 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
945
946 if (Subtarget.isISA3_1()) {
947 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
948 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
949 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
950 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
951 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
952 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
953 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
954 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
955 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
956 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
957 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
958 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
959 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
960 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
961 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
962 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
963 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
964 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
965 }
966
967 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
968 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
969
972
977
978 // Altivec does not contain unordered floating-point compare instructions
979 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
981 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
983
984 if (Subtarget.hasVSX()) {
987 if (Subtarget.hasP8Vector()) {
990 }
991 if (Subtarget.hasDirectMove() && isPPC64) {
1000 }
1002
1003 // The nearbyint variants are not allowed to raise the inexact exception
1004 // so we can only code-gen them with unsafe math.
1005 if (TM.Options.UnsafeFPMath) {
1008 }
1009
1010 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1011 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1012 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1014 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1015 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
1018
1020 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1021 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1024
1025 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1026 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1027
1028 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1029 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1030
1031 // Share the Altivec comparison restrictions.
1032 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
1033 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
1034 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
1035 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
1036
1037 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1038 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1039
1041
1042 if (Subtarget.hasP8Vector())
1043 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1044
1045 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1046
1047 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1048 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1049 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1050
1051 if (Subtarget.hasP8Altivec()) {
1052 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1053 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1054 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1055
1056 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1057 // SRL, but not for SRA because of the instructions available:
1058 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1059 // doing
1060 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1061 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1062 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1063
1064 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1065 }
1066 else {
1067 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1068 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1069 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1070
1071 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1072
1073 // VSX v2i64 only supports non-arithmetic operations.
1074 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1075 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1076 }
1077
1078 if (Subtarget.isISA3_1())
1079 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1080 else
1081 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1082
1083 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1084 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1086 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1087
1089
1098
1099 // Custom handling for partial vectors of integers converted to
1100 // floating point. We already have optimal handling for v2i32 through
1101 // the DAG combine, so those aren't necessary.
1118
1119 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1120 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1121 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1122 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1125
1128
1129 // Handle constrained floating-point operations of vector.
1130 // The predictor is `hasVSX` because altivec instruction has
1131 // no exception but VSX vector instruction has.
1145
1159
1160 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1161 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1162
1163 for (MVT FPT : MVT::fp_valuetypes())
1164 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1165
1166 // Expand the SELECT to SELECT_CC
1168
1169 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1170 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1171
1172 // No implementation for these ops for PowerPC.
1173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1174 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1175 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1177 setOperationAction(ISD::FREM, MVT::f128, Expand);
1178 }
1179
1180 if (Subtarget.hasP8Altivec()) {
1181 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1182 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1183 }
1184
1185 if (Subtarget.hasP9Vector()) {
1188
1189 // Test data class instructions store results in CR bits.
1190 if (Subtarget.useCRBits()) {
1194 }
1195
1196 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1197 // SRL, but not for SRA because of the instructions available:
1198 // VS{RL} and VS{RL}O.
1199 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1200 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1201 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1202
1203 setOperationAction(ISD::FADD, MVT::f128, Legal);
1204 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1205 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1206 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1208
1209 setOperationAction(ISD::FMA, MVT::f128, Legal);
1216
1218 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1220 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1223
1227
1228 // Handle constrained floating-point operations of fp128
1245 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1246 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1247 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1248 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1249 } else if (Subtarget.hasVSX()) {
1252
1253 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1254 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1255
1256 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1257 // fp_to_uint and int_to_fp.
1260
1261 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1262 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1263 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1264 setOperationAction(ISD::FABS, MVT::f128, Expand);
1266 setOperationAction(ISD::FMA, MVT::f128, Expand);
1268
1269 // Expand the fp_extend if the target type is fp128.
1272
1273 // Expand the fp_round if the source type is fp128.
1274 for (MVT VT : {MVT::f32, MVT::f64}) {
1277 }
1278
1283
1284 // Lower following f128 select_cc pattern:
1285 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1287
1288 // We need to handle f128 SELECT_CC with integer result type.
1290 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1291 }
1292
1293 if (Subtarget.hasP9Altivec()) {
1294 if (Subtarget.isISA3_1()) {
1299 } else {
1302 }
1310
1311 setOperationAction(ISD::ABDU, MVT::v16i8, Legal);
1312 setOperationAction(ISD::ABDU, MVT::v8i16, Legal);
1313 setOperationAction(ISD::ABDU, MVT::v4i32, Legal);
1314 setOperationAction(ISD::ABDS, MVT::v4i32, Legal);
1315 }
1316
1317 if (Subtarget.hasP10Vector()) {
1319 }
1320 }
1321
1322 if (Subtarget.pairedVectorMemops()) {
1323 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1324 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1325 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1326 }
1327 if (Subtarget.hasMMA()) {
1328 if (Subtarget.isISAFuture())
1329 addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass);
1330 else
1331 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1332 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1333 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1335 }
1336
1337 if (Subtarget.has64BitSupport())
1339
1340 if (Subtarget.isISA3_1())
1341 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1342
1343 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1344
1345 if (!isPPC64) {
1348 }
1349
1354 }
1355
1357
1358 if (Subtarget.hasAltivec()) {
1359 // Altivec instructions set fields to all zeros or all ones.
1361 }
1362
1363 setLibcallName(RTLIB::MULO_I128, nullptr);
1364 if (!isPPC64) {
1365 // These libcalls are not available in 32-bit.
1366 setLibcallName(RTLIB::SHL_I128, nullptr);
1367 setLibcallName(RTLIB::SRL_I128, nullptr);
1368 setLibcallName(RTLIB::SRA_I128, nullptr);
1369 setLibcallName(RTLIB::MUL_I128, nullptr);
1370 setLibcallName(RTLIB::MULO_I64, nullptr);
1371 }
1372
1373 if (!isPPC64)
1375 else if (shouldInlineQuadwordAtomics())
1377 else
1379
1380 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1381
1382 // We have target-specific dag combine patterns for the following nodes:
1385 if (Subtarget.hasFPCVT())
1388 if (Subtarget.useCRBits())
1392
1394
1396
1397 if (Subtarget.useCRBits()) {
1399 }
1400
1401 setLibcallName(RTLIB::LOG_F128, "logf128");
1402 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1403 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1404 setLibcallName(RTLIB::EXP_F128, "expf128");
1405 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1406 setLibcallName(RTLIB::SIN_F128, "sinf128");
1407 setLibcallName(RTLIB::COS_F128, "cosf128");
1408 setLibcallName(RTLIB::POW_F128, "powf128");
1409 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1410 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1411 setLibcallName(RTLIB::REM_F128, "fmodf128");
1412 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1413 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1414 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1415 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1416 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1417 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1418 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1419 setLibcallName(RTLIB::RINT_F128, "rintf128");
1420 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1421 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1422 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1423 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1424
1425 if (Subtarget.isAIXABI()) {
1426 setLibcallName(RTLIB::MEMCPY, isPPC64 ? "___memmove64" : "___memmove");
1427 setLibcallName(RTLIB::MEMMOVE, isPPC64 ? "___memmove64" : "___memmove");
1428 setLibcallName(RTLIB::MEMSET, isPPC64 ? "___memset64" : "___memset");
1429 setLibcallName(RTLIB::BZERO, isPPC64 ? "___bzero64" : "___bzero");
1430 }
1431
1432 // With 32 condition bits, we don't need to sink (and duplicate) compares
1433 // aggressively in CodeGenPrep.
1434 if (Subtarget.useCRBits()) {
1437 }
1438
1440
1441 switch (Subtarget.getCPUDirective()) {
1442 default: break;
1443 case PPC::DIR_970:
1444 case PPC::DIR_A2:
1445 case PPC::DIR_E500:
1446 case PPC::DIR_E500mc:
1447 case PPC::DIR_E5500:
1448 case PPC::DIR_PWR4:
1449 case PPC::DIR_PWR5:
1450 case PPC::DIR_PWR5X:
1451 case PPC::DIR_PWR6:
1452 case PPC::DIR_PWR6X:
1453 case PPC::DIR_PWR7:
1454 case PPC::DIR_PWR8:
1455 case PPC::DIR_PWR9:
1456 case PPC::DIR_PWR10:
1460 break;
1461 }
1462
1463 if (Subtarget.enableMachineScheduler())
1465 else
1467
1469
1470 // The Freescale cores do better with aggressive inlining of memcpy and
1471 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1472 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1473 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1474 MaxStoresPerMemset = 32;
1476 MaxStoresPerMemcpy = 32;
1480 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1481 // The A2 also benefits from (very) aggressive inlining of memcpy and
1482 // friends. The overhead of a the function call, even when warm, can be
1483 // over one hundred cycles.
1484 MaxStoresPerMemset = 128;
1485 MaxStoresPerMemcpy = 128;
1486 MaxStoresPerMemmove = 128;
1487 MaxLoadsPerMemcmp = 128;
1488 } else {
1491 }
1492
1493 IsStrictFPEnabled = true;
1494
1495 // Let the subtarget (CPU) decide if a predictable select is more expensive
1496 // than the corresponding branch. This information is used in CGP to decide
1497 // when to convert selects into branches.
1499}
1500
1501// *********************************** NOTE ************************************
1502// For selecting load and store instructions, the addressing modes are defined
1503// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1504// patterns to match the load the store instructions.
1505//
1506// The TD definitions for the addressing modes correspond to their respective
1507// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1508// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1509// address mode flags of a particular node. Afterwards, the computed address
1510// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1511// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1512// accordingly, based on the preferred addressing mode.
1513//
1514// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1515// MemOpFlags contains all the possible flags that can be used to compute the
1516// optimal addressing mode for load and store instructions.
1517// AddrMode contains all the possible load and store addressing modes available
1518// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1519//
1520// When adding new load and store instructions, it is possible that new address
1521// flags may need to be added into MemOpFlags, and a new addressing mode will
1522// need to be added to AddrMode. An entry of the new addressing mode (consisting
1523// of the minimal and main distinguishing address flags for the new load/store
1524// instructions) will need to be added into initializeAddrModeMap() below.
1525// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1526// need to be updated to account for selecting the optimal addressing mode.
1527// *****************************************************************************
1528/// Initialize the map that relates the different addressing modes of the load
1529/// and store instructions to a set of flags. This ensures the load/store
1530/// instruction is correctly matched during instruction selection.
1531void PPCTargetLowering::initializeAddrModeMap() {
1532 AddrModesMap[PPC::AM_DForm] = {
1533 // LWZ, STW
1538 // LBZ, LHZ, STB, STH
1543 // LHA
1548 // LFS, LFD, STFS, STFD
1553 };
1554 AddrModesMap[PPC::AM_DSForm] = {
1555 // LWA
1559 // LD, STD
1563 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1567 };
1568 AddrModesMap[PPC::AM_DQForm] = {
1569 // LXV, STXV
1573 };
1574 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1576 // TODO: Add mapping for quadword load/store.
1577}
1578
1579/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1580/// the desired ByVal argument alignment.
1581static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1582 if (MaxAlign == MaxMaxAlign)
1583 return;
1584 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1585 if (MaxMaxAlign >= 32 &&
1586 VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
1587 MaxAlign = Align(32);
1588 else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
1589 MaxAlign < 16)
1590 MaxAlign = Align(16);
1591 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1592 Align EltAlign;
1593 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1594 if (EltAlign > MaxAlign)
1595 MaxAlign = EltAlign;
1596 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1597 for (auto *EltTy : STy->elements()) {
1598 Align EltAlign;
1599 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1600 if (EltAlign > MaxAlign)
1601 MaxAlign = EltAlign;
1602 if (MaxAlign == MaxMaxAlign)
1603 break;
1604 }
1605 }
1606}
1607
1608/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1609/// function arguments in the caller parameter area.
1611 const DataLayout &DL) const {
1612 // 16byte and wider vectors are passed on 16byte boundary.
1613 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1614 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1615 if (Subtarget.hasAltivec())
1616 getMaxByValAlign(Ty, Alignment, Align(16));
1617 return Alignment.value();
1618}
1619
1621 return Subtarget.useSoftFloat();
1622}
1623
1625 return Subtarget.hasSPE();
1626}
1627
1629 return VT.isScalarInteger();
1630}
1631
1632const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1633 switch ((PPCISD::NodeType)Opcode) {
1634 case PPCISD::FIRST_NUMBER: break;
1635 case PPCISD::FSEL: return "PPCISD::FSEL";
1636 case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
1637 case PPCISD::XSMINC: return "PPCISD::XSMINC";
1638 case PPCISD::FCFID: return "PPCISD::FCFID";
1639 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1640 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1641 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1642 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1643 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1644 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1645 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1646 case PPCISD::FRE: return "PPCISD::FRE";
1647 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1648 case PPCISD::FTSQRT:
1649 return "PPCISD::FTSQRT";
1650 case PPCISD::FSQRT:
1651 return "PPCISD::FSQRT";
1652 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1653 case PPCISD::VPERM: return "PPCISD::VPERM";
1654 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1656 return "PPCISD::XXSPLTI_SP_TO_DP";
1658 return "PPCISD::XXSPLTI32DX";
1659 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1660 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1661 case PPCISD::XXPERM:
1662 return "PPCISD::XXPERM";
1663 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1664 case PPCISD::CMPB: return "PPCISD::CMPB";
1665 case PPCISD::Hi: return "PPCISD::Hi";
1666 case PPCISD::Lo: return "PPCISD::Lo";
1667 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1668 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1669 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1670 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1671 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1672 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1673 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1674 case PPCISD::SRL: return "PPCISD::SRL";
1675 case PPCISD::SRA: return "PPCISD::SRA";
1676 case PPCISD::SHL: return "PPCISD::SHL";
1677 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1678 case PPCISD::CALL: return "PPCISD::CALL";
1679 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1680 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1681 case PPCISD::CALL_RM:
1682 return "PPCISD::CALL_RM";
1684 return "PPCISD::CALL_NOP_RM";
1686 return "PPCISD::CALL_NOTOC_RM";
1687 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1688 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1689 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1690 case PPCISD::BCTRL_RM:
1691 return "PPCISD::BCTRL_RM";
1693 return "PPCISD::BCTRL_LOAD_TOC_RM";
1694 case PPCISD::RET_GLUE: return "PPCISD::RET_GLUE";
1695 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1696 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1697 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1698 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1699 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1700 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1701 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1702 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1703 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1705 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1707 return "PPCISD::ANDI_rec_1_EQ_BIT";
1709 return "PPCISD::ANDI_rec_1_GT_BIT";
1710 case PPCISD::VCMP: return "PPCISD::VCMP";
1711 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1712 case PPCISD::LBRX: return "PPCISD::LBRX";
1713 case PPCISD::STBRX: return "PPCISD::STBRX";
1714 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1715 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1716 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1717 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1718 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1719 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1720 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1721 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1722 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1724 return "PPCISD::ST_VSR_SCAL_INT";
1725 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1726 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1727 case PPCISD::BDZ: return "PPCISD::BDZ";
1728 case PPCISD::MFFS: return "PPCISD::MFFS";
1729 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1730 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1731 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1732 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1733 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1734 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1735 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1736 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1737 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1738 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1739 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1740 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1741 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1742 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1743 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1744 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1745 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1746 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1747 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1748 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1750 return "PPCISD::PADDI_DTPREL";
1751 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1752 case PPCISD::SC: return "PPCISD::SC";
1753 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1754 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1755 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1756 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1757 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1758 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1759 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1760 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1761 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1762 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1763 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1764 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1766 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1768 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1769 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1770 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1771 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1772 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1773 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1774 case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
1775 case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
1776 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1778 return "PPCISD::STRICT_FADDRTZ";
1780 return "PPCISD::STRICT_FCTIDZ";
1782 return "PPCISD::STRICT_FCTIWZ";
1784 return "PPCISD::STRICT_FCTIDUZ";
1786 return "PPCISD::STRICT_FCTIWUZ";
1788 return "PPCISD::STRICT_FCFID";
1790 return "PPCISD::STRICT_FCFIDU";
1792 return "PPCISD::STRICT_FCFIDS";
1794 return "PPCISD::STRICT_FCFIDUS";
1795 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1796 case PPCISD::STORE_COND:
1797 return "PPCISD::STORE_COND";
1798 }
1799 return nullptr;
1800}
1801
1803 EVT VT) const {
1804 if (!VT.isVector())
1805 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1806
1808}
1809
1811 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1812 return true;
1813}
1814
1815//===----------------------------------------------------------------------===//
1816// Node matching predicates, for use by the tblgen matching code.
1817//===----------------------------------------------------------------------===//
1818
1819/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1821 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1822 return CFP->getValueAPF().isZero();
1823 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1824 // Maybe this has already been legalized into the constant pool?
1825 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1826 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1827 return CFP->getValueAPF().isZero();
1828 }
1829 return false;
1830}
1831
1832/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1833/// true if Op is undef or if it matches the specified value.
1834static bool isConstantOrUndef(int Op, int Val) {
1835 return Op < 0 || Op == Val;
1836}
1837
1838/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1839/// VPKUHUM instruction.
1840/// The ShuffleKind distinguishes between big-endian operations with
1841/// two different inputs (0), either-endian operations with two identical
1842/// inputs (1), and little-endian operations with two different inputs (2).
1843/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1845 SelectionDAG &DAG) {
1846 bool IsLE = DAG.getDataLayout().isLittleEndian();
1847 if (ShuffleKind == 0) {
1848 if (IsLE)
1849 return false;
1850 for (unsigned i = 0; i != 16; ++i)
1851 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1852 return false;
1853 } else if (ShuffleKind == 2) {
1854 if (!IsLE)
1855 return false;
1856 for (unsigned i = 0; i != 16; ++i)
1857 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1858 return false;
1859 } else if (ShuffleKind == 1) {
1860 unsigned j = IsLE ? 0 : 1;
1861 for (unsigned i = 0; i != 8; ++i)
1862 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1863 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1864 return false;
1865 }
1866 return true;
1867}
1868
1869/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1870/// VPKUWUM instruction.
1871/// The ShuffleKind distinguishes between big-endian operations with
1872/// two different inputs (0), either-endian operations with two identical
1873/// inputs (1), and little-endian operations with two different inputs (2).
1874/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1876 SelectionDAG &DAG) {
1877 bool IsLE = DAG.getDataLayout().isLittleEndian();
1878 if (ShuffleKind == 0) {
1879 if (IsLE)
1880 return false;
1881 for (unsigned i = 0; i != 16; i += 2)
1882 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1883 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1884 return false;
1885 } else if (ShuffleKind == 2) {
1886 if (!IsLE)
1887 return false;
1888 for (unsigned i = 0; i != 16; i += 2)
1889 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1890 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1891 return false;
1892 } else if (ShuffleKind == 1) {
1893 unsigned j = IsLE ? 0 : 2;
1894 for (unsigned i = 0; i != 8; i += 2)
1895 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1896 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1897 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1898 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1899 return false;
1900 }
1901 return true;
1902}
1903
1904/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1905/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1906/// current subtarget.
1907///
1908/// The ShuffleKind distinguishes between big-endian operations with
1909/// two different inputs (0), either-endian operations with two identical
1910/// inputs (1), and little-endian operations with two different inputs (2).
1911/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1913 SelectionDAG &DAG) {
1914 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>();
1915 if (!Subtarget.hasP8Vector())
1916 return false;
1917
1918 bool IsLE = DAG.getDataLayout().isLittleEndian();
1919 if (ShuffleKind == 0) {
1920 if (IsLE)
1921 return false;
1922 for (unsigned i = 0; i != 16; i += 4)
1923 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1924 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1925 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1926 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1927 return false;
1928 } else if (ShuffleKind == 2) {
1929 if (!IsLE)
1930 return false;
1931 for (unsigned i = 0; i != 16; i += 4)
1932 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1933 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1934 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1935 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1936 return false;
1937 } else if (ShuffleKind == 1) {
1938 unsigned j = IsLE ? 0 : 4;
1939 for (unsigned i = 0; i != 8; i += 4)
1940 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1941 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1942 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1943 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1944 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1945 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1946 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1947 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1948 return false;
1949 }
1950 return true;
1951}
1952
1953/// isVMerge - Common function, used to match vmrg* shuffles.
1954///
1955static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1956 unsigned LHSStart, unsigned RHSStart) {
1957 if (N->getValueType(0) != MVT::v16i8)
1958 return false;
1959 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1960 "Unsupported merge size!");
1961
1962 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1963 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1964 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1965 LHSStart+j+i*UnitSize) ||
1966 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1967 RHSStart+j+i*UnitSize))
1968 return false;
1969 }
1970 return true;
1971}
1972
1973/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1974/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1975/// The ShuffleKind distinguishes between big-endian merges with two
1976/// different inputs (0), either-endian merges with two identical inputs (1),
1977/// and little-endian merges with two different inputs (2). For the latter,
1978/// the input operands are swapped (see PPCInstrAltivec.td).
1980 unsigned ShuffleKind, SelectionDAG &DAG) {
1981 if (DAG.getDataLayout().isLittleEndian()) {
1982 if (ShuffleKind == 1) // unary
1983 return isVMerge(N, UnitSize, 0, 0);
1984 else if (ShuffleKind == 2) // swapped
1985 return isVMerge(N, UnitSize, 0, 16);
1986 else
1987 return false;
1988 } else {
1989 if (ShuffleKind == 1) // unary
1990 return isVMerge(N, UnitSize, 8, 8);
1991 else if (ShuffleKind == 0) // normal
1992 return isVMerge(N, UnitSize, 8, 24);
1993 else
1994 return false;
1995 }
1996}
1997
1998/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1999/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
2000/// The ShuffleKind distinguishes between big-endian merges with two
2001/// different inputs (0), either-endian merges with two identical inputs (1),
2002/// and little-endian merges with two different inputs (2). For the latter,
2003/// the input operands are swapped (see PPCInstrAltivec.td).
2005 unsigned ShuffleKind, SelectionDAG &DAG) {
2006 if (DAG.getDataLayout().isLittleEndian()) {
2007 if (ShuffleKind == 1) // unary
2008 return isVMerge(N, UnitSize, 8, 8);
2009 else if (ShuffleKind == 2) // swapped
2010 return isVMerge(N, UnitSize, 8, 24);
2011 else
2012 return false;
2013 } else {
2014 if (ShuffleKind == 1) // unary
2015 return isVMerge(N, UnitSize, 0, 0);
2016 else if (ShuffleKind == 0) // normal
2017 return isVMerge(N, UnitSize, 0, 16);
2018 else
2019 return false;
2020 }
2021}
2022
2023/**
2024 * Common function used to match vmrgew and vmrgow shuffles
2025 *
2026 * The indexOffset determines whether to look for even or odd words in
2027 * the shuffle mask. This is based on the of the endianness of the target
2028 * machine.
2029 * - Little Endian:
2030 * - Use offset of 0 to check for odd elements
2031 * - Use offset of 4 to check for even elements
2032 * - Big Endian:
2033 * - Use offset of 0 to check for even elements
2034 * - Use offset of 4 to check for odd elements
2035 * A detailed description of the vector element ordering for little endian and
2036 * big endian can be found at
2037 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
2038 * Targeting your applications - what little endian and big endian IBM XL C/C++
2039 * compiler differences mean to you
2040 *
2041 * The mask to the shuffle vector instruction specifies the indices of the
2042 * elements from the two input vectors to place in the result. The elements are
2043 * numbered in array-access order, starting with the first vector. These vectors
2044 * are always of type v16i8, thus each vector will contain 16 elements of size
2045 * 8. More info on the shuffle vector can be found in the
2046 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
2047 * Language Reference.
2048 *
2049 * The RHSStartValue indicates whether the same input vectors are used (unary)
2050 * or two different input vectors are used, based on the following:
2051 * - If the instruction uses the same vector for both inputs, the range of the
2052 * indices will be 0 to 15. In this case, the RHSStart value passed should
2053 * be 0.
2054 * - If the instruction has two different vectors then the range of the
2055 * indices will be 0 to 31. In this case, the RHSStart value passed should
2056 * be 16 (indices 0-15 specify elements in the first vector while indices 16
2057 * to 31 specify elements in the second vector).
2058 *
2059 * \param[in] N The shuffle vector SD Node to analyze
2060 * \param[in] IndexOffset Specifies whether to look for even or odd elements
2061 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2062 * vector to the shuffle_vector instruction
2063 * \return true iff this shuffle vector represents an even or odd word merge
2064 */
2065static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2066 unsigned RHSStartValue) {
2067 if (N->getValueType(0) != MVT::v16i8)
2068 return false;
2069
2070 for (unsigned i = 0; i < 2; ++i)
2071 for (unsigned j = 0; j < 4; ++j)
2072 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2073 i*RHSStartValue+j+IndexOffset) ||
2074 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2075 i*RHSStartValue+j+IndexOffset+8))
2076 return false;
2077 return true;
2078}
2079
2080/**
2081 * Determine if the specified shuffle mask is suitable for the vmrgew or
2082 * vmrgow instructions.
2083 *
2084 * \param[in] N The shuffle vector SD Node to analyze
2085 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2086 * \param[in] ShuffleKind Identify the type of merge:
2087 * - 0 = big-endian merge with two different inputs;
2088 * - 1 = either-endian merge with two identical inputs;
2089 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2090 * little-endian merges).
2091 * \param[in] DAG The current SelectionDAG
2092 * \return true iff this shuffle mask
2093 */
2095 unsigned ShuffleKind, SelectionDAG &DAG) {
2096 if (DAG.getDataLayout().isLittleEndian()) {
2097 unsigned indexOffset = CheckEven ? 4 : 0;
2098 if (ShuffleKind == 1) // Unary
2099 return isVMerge(N, indexOffset, 0);
2100 else if (ShuffleKind == 2) // swapped
2101 return isVMerge(N, indexOffset, 16);
2102 else
2103 return false;
2104 }
2105 else {
2106 unsigned indexOffset = CheckEven ? 0 : 4;
2107 if (ShuffleKind == 1) // Unary
2108 return isVMerge(N, indexOffset, 0);
2109 else if (ShuffleKind == 0) // Normal
2110 return isVMerge(N, indexOffset, 16);
2111 else
2112 return false;
2113 }
2114 return false;
2115}
2116
2117/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2118/// amount, otherwise return -1.
2119/// The ShuffleKind distinguishes between big-endian operations with two
2120/// different inputs (0), either-endian operations with two identical inputs
2121/// (1), and little-endian operations with two different inputs (2). For the
2122/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2123int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2124 SelectionDAG &DAG) {
2125 if (N->getValueType(0) != MVT::v16i8)
2126 return -1;
2127
2128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2129
2130 // Find the first non-undef value in the shuffle mask.
2131 unsigned i;
2132 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2133 /*search*/;
2134
2135 if (i == 16) return -1; // all undef.
2136
2137 // Otherwise, check to see if the rest of the elements are consecutively
2138 // numbered from this value.
2139 unsigned ShiftAmt = SVOp->getMaskElt(i);
2140 if (ShiftAmt < i) return -1;
2141
2142 ShiftAmt -= i;
2143 bool isLE = DAG.getDataLayout().isLittleEndian();
2144
2145 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2146 // Check the rest of the elements to see if they are consecutive.
2147 for (++i; i != 16; ++i)
2148 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2149 return -1;
2150 } else if (ShuffleKind == 1) {
2151 // Check the rest of the elements to see if they are consecutive.
2152 for (++i; i != 16; ++i)
2153 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2154 return -1;
2155 } else
2156 return -1;
2157
2158 if (isLE)
2159 ShiftAmt = 16 - ShiftAmt;
2160
2161 return ShiftAmt;
2162}
2163
2164/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2165/// specifies a splat of a single element that is suitable for input to
2166/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2168 EVT VT = N->getValueType(0);
2169 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2170 return EltSize == 8 && N->getMaskElt(0) == N->getMaskElt(1);
2171
2172 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) &&
2173 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes");
2174
2175 // The consecutive indices need to specify an element, not part of two
2176 // different elements. So abandon ship early if this isn't the case.
2177 if (N->getMaskElt(0) % EltSize != 0)
2178 return false;
2179
2180 // This is a splat operation if each element of the permute is the same, and
2181 // if the value doesn't reference the second vector.
2182 unsigned ElementBase = N->getMaskElt(0);
2183
2184 // FIXME: Handle UNDEF elements too!
2185 if (ElementBase >= 16)
2186 return false;
2187
2188 // Check that the indices are consecutive, in the case of a multi-byte element
2189 // splatted with a v16i8 mask.
2190 for (unsigned i = 1; i != EltSize; ++i)
2191 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2192 return false;
2193
2194 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2195 if (N->getMaskElt(i) < 0) continue;
2196 for (unsigned j = 0; j != EltSize; ++j)
2197 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2198 return false;
2199 }
2200 return true;
2201}
2202
2203/// Check that the mask is shuffling N byte elements. Within each N byte
2204/// element of the mask, the indices could be either in increasing or
2205/// decreasing order as long as they are consecutive.
2206/// \param[in] N the shuffle vector SD Node to analyze
2207/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2208/// Word/DoubleWord/QuadWord).
2209/// \param[in] StepLen the delta indices number among the N byte element, if
2210/// the mask is in increasing/decreasing order then it is 1/-1.
2211/// \return true iff the mask is shuffling N byte elements.
2212static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2213 int StepLen) {
2214 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
2215 "Unexpected element width.");
2216 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
2217
2218 unsigned NumOfElem = 16 / Width;
2219 unsigned MaskVal[16]; // Width is never greater than 16
2220 for (unsigned i = 0; i < NumOfElem; ++i) {
2221 MaskVal[0] = N->getMaskElt(i * Width);
2222 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2223 return false;
2224 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2225 return false;
2226 }
2227
2228 for (unsigned int j = 1; j < Width; ++j) {
2229 MaskVal[j] = N->getMaskElt(i * Width + j);
2230 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2231 return false;
2232 }
2233 }
2234 }
2235
2236 return true;
2237}
2238
2239bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2240 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2241 if (!isNByteElemShuffleMask(N, 4, 1))
2242 return false;
2243
2244 // Now we look at mask elements 0,4,8,12
2245 unsigned M0 = N->getMaskElt(0) / 4;
2246 unsigned M1 = N->getMaskElt(4) / 4;
2247 unsigned M2 = N->getMaskElt(8) / 4;
2248 unsigned M3 = N->getMaskElt(12) / 4;
2249 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2250 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2251
2252 // Below, let H and L be arbitrary elements of the shuffle mask
2253 // where H is in the range [4,7] and L is in the range [0,3].
2254 // H, 1, 2, 3 or L, 5, 6, 7
2255 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2256 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2257 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2258 InsertAtByte = IsLE ? 12 : 0;
2259 Swap = M0 < 4;
2260 return true;
2261 }
2262 // 0, H, 2, 3 or 4, L, 6, 7
2263 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2264 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2265 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2266 InsertAtByte = IsLE ? 8 : 4;
2267 Swap = M1 < 4;
2268 return true;
2269 }
2270 // 0, 1, H, 3 or 4, 5, L, 7
2271 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2272 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2273 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2274 InsertAtByte = IsLE ? 4 : 8;
2275 Swap = M2 < 4;
2276 return true;
2277 }
2278 // 0, 1, 2, H or 4, 5, 6, L
2279 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2280 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2281 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2282 InsertAtByte = IsLE ? 0 : 12;
2283 Swap = M3 < 4;
2284 return true;
2285 }
2286
2287 // If both vector operands for the shuffle are the same vector, the mask will
2288 // contain only elements from the first one and the second one will be undef.
2289 if (N->getOperand(1).isUndef()) {
2290 ShiftElts = 0;
2291 Swap = true;
2292 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2293 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2294 InsertAtByte = IsLE ? 12 : 0;
2295 return true;
2296 }
2297 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2298 InsertAtByte = IsLE ? 8 : 4;
2299 return true;
2300 }
2301 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2302 InsertAtByte = IsLE ? 4 : 8;
2303 return true;
2304 }
2305 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2306 InsertAtByte = IsLE ? 0 : 12;
2307 return true;
2308 }
2309 }
2310
2311 return false;
2312}
2313
2315 bool &Swap, bool IsLE) {
2316 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2317 // Ensure each byte index of the word is consecutive.
2318 if (!isNByteElemShuffleMask(N, 4, 1))
2319 return false;
2320
2321 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2322 unsigned M0 = N->getMaskElt(0) / 4;
2323 unsigned M1 = N->getMaskElt(4) / 4;
2324 unsigned M2 = N->getMaskElt(8) / 4;
2325 unsigned M3 = N->getMaskElt(12) / 4;
2326
2327 // If both vector operands for the shuffle are the same vector, the mask will
2328 // contain only elements from the first one and the second one will be undef.
2329 if (N->getOperand(1).isUndef()) {
2330 assert(M0 < 4 && "Indexing into an undef vector?");
2331 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2332 return false;
2333
2334 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2335 Swap = false;
2336 return true;
2337 }
2338
2339 // Ensure each word index of the ShuffleVector Mask is consecutive.
2340 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2341 return false;
2342
2343 if (IsLE) {
2344 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2345 // Input vectors don't need to be swapped if the leading element
2346 // of the result is one of the 3 left elements of the second vector
2347 // (or if there is no shift to be done at all).
2348 Swap = false;
2349 ShiftElts = (8 - M0) % 8;
2350 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2351 // Input vectors need to be swapped if the leading element
2352 // of the result is one of the 3 left elements of the first vector
2353 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2354 Swap = true;
2355 ShiftElts = (4 - M0) % 4;
2356 }
2357
2358 return true;
2359 } else { // BE
2360 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
2361 // Input vectors don't need to be swapped if the leading element
2362 // of the result is one of the 4 elements of the first vector.
2363 Swap = false;
2364 ShiftElts = M0;
2365 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
2366 // Input vectors need to be swapped if the leading element
2367 // of the result is one of the 4 elements of the right vector.
2368 Swap = true;
2369 ShiftElts = M0 - 4;
2370 }
2371
2372 return true;
2373 }
2374}
2375
2377 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2378
2379 if (!isNByteElemShuffleMask(N, Width, -1))
2380 return false;
2381
2382 for (int i = 0; i < 16; i += Width)
2383 if (N->getMaskElt(i) != i + Width - 1)
2384 return false;
2385
2386 return true;
2387}
2388
2390 return isXXBRShuffleMaskHelper(N, 2);
2391}
2392
2394 return isXXBRShuffleMaskHelper(N, 4);
2395}
2396
2398 return isXXBRShuffleMaskHelper(N, 8);
2399}
2400
2402 return isXXBRShuffleMaskHelper(N, 16);
2403}
2404
2405/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2406/// if the inputs to the instruction should be swapped and set \p DM to the
2407/// value for the immediate.
2408/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2409/// AND element 0 of the result comes from the first input (LE) or second input
2410/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2411/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2412/// mask.
2414 bool &Swap, bool IsLE) {
2415 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2416
2417 // Ensure each byte index of the double word is consecutive.
2418 if (!isNByteElemShuffleMask(N, 8, 1))
2419 return false;
2420
2421 unsigned M0 = N->getMaskElt(0) / 8;
2422 unsigned M1 = N->getMaskElt(8) / 8;
2423 assert(((M0 | M1) < 4) && "A mask element out of bounds?");
2424
2425 // If both vector operands for the shuffle are the same vector, the mask will
2426 // contain only elements from the first one and the second one will be undef.
2427 if (N->getOperand(1).isUndef()) {
2428 if ((M0 | M1) < 2) {
2429 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2430 Swap = false;
2431 return true;
2432 } else
2433 return false;
2434 }
2435
2436 if (IsLE) {
2437 if (M0 > 1 && M1 < 2) {
2438 Swap = false;
2439 } else if (M0 < 2 && M1 > 1) {
2440 M0 = (M0 + 2) % 4;
2441 M1 = (M1 + 2) % 4;
2442 Swap = true;
2443 } else
2444 return false;
2445
2446 // Note: if control flow comes here that means Swap is already set above
2447 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2448 return true;
2449 } else { // BE
2450 if (M0 < 2 && M1 > 1) {
2451 Swap = false;
2452 } else if (M0 > 1 && M1 < 2) {
2453 M0 = (M0 + 2) % 4;
2454 M1 = (M1 + 2) % 4;
2455 Swap = true;
2456 } else
2457 return false;
2458
2459 // Note: if control flow comes here that means Swap is already set above
2460 DM = (M0 << 1) + (M1 & 1);
2461 return true;
2462 }
2463}
2464
2465
2466/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2467/// appropriate for PPC mnemonics (which have a big endian bias - namely
2468/// elements are counted from the left of the vector register).
2469unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2470 SelectionDAG &DAG) {
2471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2472 assert(isSplatShuffleMask(SVOp, EltSize));
2473 EVT VT = SVOp->getValueType(0);
2474
2475 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2476 return DAG.getDataLayout().isLittleEndian() ? 1 - SVOp->getMaskElt(0)
2477 : SVOp->getMaskElt(0);
2478
2479 if (DAG.getDataLayout().isLittleEndian())
2480 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2481 else
2482 return SVOp->getMaskElt(0) / EltSize;
2483}
2484
2485/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2486/// by using a vspltis[bhw] instruction of the specified element size, return
2487/// the constant being splatted. The ByteSize field indicates the number of
2488/// bytes of each element [124] -> [bhw].
2490 SDValue OpVal;
2491
2492 // If ByteSize of the splat is bigger than the element size of the
2493 // build_vector, then we have a case where we are checking for a splat where
2494 // multiple elements of the buildvector are folded together into a single
2495 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2496 unsigned EltSize = 16/N->getNumOperands();
2497 if (EltSize < ByteSize) {
2498 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2499 SDValue UniquedVals[4];
2500 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
2501
2502 // See if all of the elements in the buildvector agree across.
2503 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2504 if (N->getOperand(i).isUndef()) continue;
2505 // If the element isn't a constant, bail fully out.
2506 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2507
2508 if (!UniquedVals[i&(Multiple-1)].getNode())
2509 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2510 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2511 return SDValue(); // no match.
2512 }
2513
2514 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2515 // either constant or undef values that are identical for each chunk. See
2516 // if these chunks can form into a larger vspltis*.
2517
2518 // Check to see if all of the leading entries are either 0 or -1. If
2519 // neither, then this won't fit into the immediate field.
2520 bool LeadingZero = true;
2521 bool LeadingOnes = true;
2522 for (unsigned i = 0; i != Multiple-1; ++i) {
2523 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2524
2525 LeadingZero &= isNullConstant(UniquedVals[i]);
2526 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2527 }
2528 // Finally, check the least significant entry.
2529 if (LeadingZero) {
2530 if (!UniquedVals[Multiple-1].getNode())
2531 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2532 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2533 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2534 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2535 }
2536 if (LeadingOnes) {
2537 if (!UniquedVals[Multiple-1].getNode())
2538 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2539 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2540 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2541 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2542 }
2543
2544 return SDValue();
2545 }
2546
2547 // Check to see if this buildvec has a single non-undef value in its elements.
2548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2549 if (N->getOperand(i).isUndef()) continue;
2550 if (!OpVal.getNode())
2551 OpVal = N->getOperand(i);
2552 else if (OpVal != N->getOperand(i))
2553 return SDValue();
2554 }
2555
2556 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2557
2558 unsigned ValSizeInBytes = EltSize;
2559 uint64_t Value = 0;
2560 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2561 Value = CN->getZExtValue();
2562 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2563 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
2564 Value = llvm::bit_cast<uint32_t>(CN->getValueAPF().convertToFloat());
2565 }
2566
2567 // If the splat value is larger than the element value, then we can never do
2568 // this splat. The only case that we could fit the replicated bits into our
2569 // immediate field for would be zero, and we prefer to use vxor for it.
2570 if (ValSizeInBytes < ByteSize) return SDValue();
2571
2572 // If the element value is larger than the splat value, check if it consists
2573 // of a repeated bit pattern of size ByteSize.
2574 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2575 return SDValue();
2576
2577 // Properly sign extend the value.
2578 int MaskVal = SignExtend32(Value, ByteSize * 8);
2579
2580 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2581 if (MaskVal == 0) return SDValue();
2582
2583 // Finally, if this value fits in a 5 bit sext field, return it
2584 if (SignExtend32<5>(MaskVal) == MaskVal)
2585 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2586 return SDValue();
2587}
2588
2589//===----------------------------------------------------------------------===//
2590// Addressing Mode Selection
2591//===----------------------------------------------------------------------===//
2592
2593/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2594/// or 64-bit immediate, and if the value can be accurately represented as a
2595/// sign extension from a 16-bit value. If so, this returns true and the
2596/// immediate.
2597bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2598 if (!isa<ConstantSDNode>(N))
2599 return false;
2600
2601 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2602 if (N->getValueType(0) == MVT::i32)
2603 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2604 else
2605 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2606}
2607bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2608 return isIntS16Immediate(Op.getNode(), Imm);
2609}
2610
2611/// Used when computing address flags for selecting loads and stores.
2612/// If we have an OR, check if the LHS and RHS are provably disjoint.
2613/// An OR of two provably disjoint values is equivalent to an ADD.
2614/// Most PPC load/store instructions compute the effective address as a sum,
2615/// so doing this conversion is useful.
2616static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2617 if (N.getOpcode() != ISD::OR)
2618 return false;
2619 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2620 if (!LHSKnown.Zero.getBoolValue())
2621 return false;
2622 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2623 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2624}
2625
2626/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2627/// be represented as an indexed [r+r] operation.
2629 SDValue &Index,
2630 SelectionDAG &DAG) const {
2631 for (SDNode *U : N->uses()) {
2632 if (MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2633 if (Memop->getMemoryVT() == MVT::f64) {
2634 Base = N.getOperand(0);
2635 Index = N.getOperand(1);
2636 return true;
2637 }
2638 }
2639 }
2640 return false;
2641}
2642
2643/// isIntS34Immediate - This method tests if value of node given can be
2644/// accurately represented as a sign extension from a 34-bit value. If so,
2645/// this returns true and the immediate.
2646bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2647 if (!isa<ConstantSDNode>(N))
2648 return false;
2649
2650 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2651 return isInt<34>(Imm);
2652}
2653bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2654 return isIntS34Immediate(Op.getNode(), Imm);
2655}
2656
2657/// SelectAddressRegReg - Given the specified addressed, check to see if it
2658/// can be represented as an indexed [r+r] operation. Returns false if it
2659/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2660/// non-zero and N can be represented by a base register plus a signed 16-bit
2661/// displacement, make a more precise judgement by checking (displacement % \p
2662/// EncodingAlignment).
2665 MaybeAlign EncodingAlignment) const {
2666 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2667 // a [pc+imm].
2669 return false;
2670
2671 int16_t Imm = 0;
2672 if (N.getOpcode() == ISD::ADD) {
2673 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2674 // SPE load/store can only handle 8-bit offsets.
2675 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2676 return true;
2677 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2678 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2679 return false; // r+i
2680 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2681 return false; // r+i
2682
2683 Base = N.getOperand(0);
2684 Index = N.getOperand(1);
2685 return true;
2686 } else if (N.getOpcode() == ISD::OR) {
2687 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2688 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2689 return false; // r+i can fold it if we can.
2690
2691 // If this is an or of disjoint bitfields, we can codegen this as an add
2692 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2693 // disjoint.
2694 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2695
2696 if (LHSKnown.Zero.getBoolValue()) {
2697 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2698 // If all of the bits are known zero on the LHS or RHS, the add won't
2699 // carry.
2700 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2701 Base = N.getOperand(0);
2702 Index = N.getOperand(1);
2703 return true;
2704 }
2705 }
2706 }
2707
2708 return false;
2709}
2710
2711// If we happen to be doing an i64 load or store into a stack slot that has
2712// less than a 4-byte alignment, then the frame-index elimination may need to
2713// use an indexed load or store instruction (because the offset may not be a
2714// multiple of 4). The extra register needed to hold the offset comes from the
2715// register scavenger, and it is possible that the scavenger will need to use
2716// an emergency spill slot. As a result, we need to make sure that a spill slot
2717// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2718// stack slot.
2719static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2720 // FIXME: This does not handle the LWA case.
2721 if (VT != MVT::i64)
2722 return;
2723
2724 // NOTE: We'll exclude negative FIs here, which come from argument
2725 // lowering, because there are no known test cases triggering this problem
2726 // using packed structures (or similar). We can remove this exclusion if
2727 // we find such a test case. The reason why this is so test-case driven is
2728 // because this entire 'fixup' is only to prevent crashes (from the
2729 // register scavenger) on not-really-valid inputs. For example, if we have:
2730 // %a = alloca i1
2731 // %b = bitcast i1* %a to i64*
2732 // store i64* a, i64 b
2733 // then the store should really be marked as 'align 1', but is not. If it
2734 // were marked as 'align 1' then the indexed form would have been
2735 // instruction-selected initially, and the problem this 'fixup' is preventing
2736 // won't happen regardless.
2737 if (FrameIdx < 0)
2738 return;
2739
2741 MachineFrameInfo &MFI = MF.getFrameInfo();
2742
2743 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2744 return;
2745
2748}
2749
2750/// Returns true if the address N can be represented by a base register plus
2751/// a signed 16-bit displacement [r+imm], and if it is not better
2752/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2753/// displacements that are multiples of that value.
2755 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2756 MaybeAlign EncodingAlignment) const {
2757 // FIXME dl should come from parent load or store, not from address
2758 SDLoc dl(N);
2759
2760 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2761 // a [pc+imm].
2763 return false;
2764
2765 // If this can be more profitably realized as r+r, fail.
2766 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2767 return false;
2768
2769 if (N.getOpcode() == ISD::ADD) {
2770 int16_t imm = 0;
2771 if (isIntS16Immediate(N.getOperand(1), imm) &&
2772 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2773 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2774 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2775 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2776 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2777 } else {
2778 Base = N.getOperand(0);
2779 }
2780 return true; // [r+i]
2781 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2782 // Match LOAD (ADD (X, Lo(G))).
2783 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
2784 && "Cannot handle constant offsets yet!");
2785 Disp = N.getOperand(1).getOperand(0); // The global address.
2790 Base = N.getOperand(0);
2791 return true; // [&g+r]
2792 }
2793 } else if (N.getOpcode() == ISD::OR) {
2794 int16_t imm = 0;
2795 if (isIntS16Immediate(N.getOperand(1), imm) &&
2796 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2797 // If this is an or of disjoint bitfields, we can codegen this as an add
2798 // (for better address arithmetic) if the LHS and RHS of the OR are
2799 // provably disjoint.
2800 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2801
2802 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2803 // If all of the bits are known zero on the LHS or RHS, the add won't
2804 // carry.
2805 if (FrameIndexSDNode *FI =
2806 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2807 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2808 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2809 } else {
2810 Base = N.getOperand(0);
2811 }
2812 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2813 return true;
2814 }
2815 }
2816 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2817 // Loading from a constant address.
2818
2819 // If this address fits entirely in a 16-bit sext immediate field, codegen
2820 // this as "d, 0"
2821 int16_t Imm;
2822 if (isIntS16Immediate(CN, Imm) &&
2823 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2824 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2825 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2826 CN->getValueType(0));
2827 return true;
2828 }
2829
2830 // Handle 32-bit sext immediates with LIS + addr mode.
2831 if ((CN->getValueType(0) == MVT::i32 ||
2832 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2833 (!EncodingAlignment ||
2834 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2835 int Addr = (int)CN->getZExtValue();
2836
2837 // Otherwise, break this down into an LIS + disp.
2838 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2839
2840 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2841 MVT::i32);
2842 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2843 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2844 return true;
2845 }
2846 }
2847
2848 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2849 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2850 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2851 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2852 } else
2853 Base = N;
2854 return true; // [r+0]
2855}
2856
2857/// Similar to the 16-bit case but for instructions that take a 34-bit
2858/// displacement field (prefixed loads/stores).
2860 SDValue &Base,
2861 SelectionDAG &DAG) const {
2862 // Only on 64-bit targets.
2863 if (N.getValueType() != MVT::i64)
2864 return false;
2865
2866 SDLoc dl(N);
2867 int64_t Imm = 0;
2868
2869 if (N.getOpcode() == ISD::ADD) {
2870 if (!isIntS34Immediate(N.getOperand(1), Imm))
2871 return false;
2872 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2873 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2874 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2875 else
2876 Base = N.getOperand(0);
2877 return true;
2878 }
2879
2880 if (N.getOpcode() == ISD::OR) {
2881 if (!isIntS34Immediate(N.getOperand(1), Imm))
2882 return false;
2883 // If this is an or of disjoint bitfields, we can codegen this as an add
2884 // (for better address arithmetic) if the LHS and RHS of the OR are
2885 // provably disjoint.
2886 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2887 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2888 return false;
2889 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2890 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2891 else
2892 Base = N.getOperand(0);
2893 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2894 return true;
2895 }
2896
2897 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2898 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2899 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2900 return true;
2901 }
2902
2903 return false;
2904}
2905
2906/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2907/// represented as an indexed [r+r] operation.
2909 SDValue &Index,
2910 SelectionDAG &DAG) const {
2911 // Check to see if we can easily represent this as an [r+r] address. This
2912 // will fail if it thinks that the address is more profitably represented as
2913 // reg+imm, e.g. where imm = 0.
2914 if (SelectAddressRegReg(N, Base, Index, DAG))
2915 return true;
2916
2917 // If the address is the result of an add, we will utilize the fact that the
2918 // address calculation includes an implicit add. However, we can reduce
2919 // register pressure if we do not materialize a constant just for use as the
2920 // index register. We only get rid of the add if it is not an add of a
2921 // value and a 16-bit signed constant and both have a single use.
2922 int16_t imm = 0;
2923 if (N.getOpcode() == ISD::ADD &&
2924 (!isIntS16Immediate(N.getOperand(1), imm) ||
2925 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2926 Base = N.getOperand(0);
2927 Index = N.getOperand(1);
2928 return true;
2929 }
2930
2931 // Otherwise, do it the hard way, using R0 as the base register.
2932 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2933 N.getValueType());
2934 Index = N;
2935 return true;
2936}
2937
2938template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2939 Ty *PCRelCand = dyn_cast<Ty>(N);
2940 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2941}
2942
2943/// Returns true if this address is a PC Relative address.
2944/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2945/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2947 // This is a materialize PC Relative node. Always select this as PC Relative.
2948 Base = N;
2949 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2950 return true;
2951 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2952 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2953 isValidPCRelNode<JumpTableSDNode>(N) ||
2954 isValidPCRelNode<BlockAddressSDNode>(N))
2955 return true;
2956 return false;
2957}
2958
2959/// Returns true if we should use a direct load into vector instruction
2960/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2961static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2962
2963 // If there are any other uses other than scalar to vector, then we should
2964 // keep it as a scalar load -> direct move pattern to prevent multiple
2965 // loads.
2966 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2967 if (!LD)
2968 return false;
2969
2970 EVT MemVT = LD->getMemoryVT();
2971 if (!MemVT.isSimple())
2972 return false;
2973 switch(MemVT.getSimpleVT().SimpleTy) {
2974 case MVT::i64:
2975 break;
2976 case MVT::i32:
2977 if (!ST.hasP8Vector())
2978 return false;
2979 break;
2980 case MVT::i16:
2981 case MVT::i8:
2982 if (!ST.hasP9Vector())
2983 return false;
2984 break;
2985 default:
2986 return false;
2987 }
2988
2989 SDValue LoadedVal(N, 0);
2990 if (!LoadedVal.hasOneUse())
2991 return false;
2992
2993 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2994 UI != UE; ++UI)
2995 if (UI.getUse().get().getResNo() == 0 &&
2996 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2997 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2998 return false;
2999
3000 return true;
3001}
3002
3003/// getPreIndexedAddressParts - returns true by value, base pointer and
3004/// offset pointer and addressing mode by reference if the node's address
3005/// can be legally represented as pre-indexed load / store address.
3007 SDValue &Offset,
3009 SelectionDAG &DAG) const {
3010 if (DisablePPCPreinc) return false;
3011
3012 bool isLoad = true;
3013 SDValue Ptr;
3014 EVT VT;
3015 Align Alignment;
3016 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3017 Ptr = LD->getBasePtr();
3018 VT = LD->getMemoryVT();
3019 Alignment = LD->getAlign();
3020 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3021 Ptr = ST->getBasePtr();
3022 VT = ST->getMemoryVT();
3023 Alignment = ST->getAlign();
3024 isLoad = false;
3025 } else
3026 return false;
3027
3028 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
3029 // instructions because we can fold these into a more efficient instruction
3030 // instead, (such as LXSD).
3031 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
3032 return false;
3033 }
3034
3035 // PowerPC doesn't have preinc load/store instructions for vectors
3036 if (VT.isVector())
3037 return false;
3038
3039 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
3040 // Common code will reject creating a pre-inc form if the base pointer
3041 // is a frame index, or if N is a store and the base pointer is either
3042 // the same as or a predecessor of the value being stored. Check for
3043 // those situations here, and try with swapped Base/Offset instead.
3044 bool Swap = false;
3045
3046 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
3047 Swap = true;
3048 else if (!isLoad) {
3049 SDValue Val = cast<StoreSDNode>(N)->getValue();
3050 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
3051 Swap = true;
3052 }
3053
3054 if (Swap)
3056
3057 AM = ISD::PRE_INC;
3058 return true;
3059 }
3060
3061 // LDU/STU can only handle immediates that are a multiple of 4.
3062 if (VT != MVT::i64) {
3063 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, std::nullopt))
3064 return false;
3065 } else {
3066 // LDU/STU need an address with at least 4-byte alignment.
3067 if (Alignment < Align(4))
3068 return false;
3069
3070 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3071 return false;
3072 }
3073
3074 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3075 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3076 // sext i32 to i64 when addr mode is r+i.
3077 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3078 LD->getExtensionType() == ISD::SEXTLOAD &&
3079 isa<ConstantSDNode>(Offset))
3080 return false;
3081 }
3082
3083 AM = ISD::PRE_INC;
3084 return true;
3085}
3086
3087//===----------------------------------------------------------------------===//
3088// LowerOperation implementation
3089//===----------------------------------------------------------------------===//
3090
3091/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3092/// and LoOpFlags to the target MO flags.
3093static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3094 unsigned &HiOpFlags, unsigned &LoOpFlags,
3095 const GlobalValue *GV = nullptr) {
3096 HiOpFlags = PPCII::MO_HA;
3097 LoOpFlags = PPCII::MO_LO;
3098
3099 // Don't use the pic base if not in PIC relocation model.
3100 if (IsPIC) {
3101 HiOpFlags |= PPCII::MO_PIC_FLAG;
3102 LoOpFlags |= PPCII::MO_PIC_FLAG;
3103 }
3104}
3105
3106static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3107 SelectionDAG &DAG) {
3108 SDLoc DL(HiPart);
3109 EVT PtrVT = HiPart.getValueType();
3110 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3111
3112 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3113 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3114
3115 // With PIC, the first instruction is actually "GR+hi(&G)".
3116 if (isPIC)
3117 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3118 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3119
3120 // Generate non-pic code that has direct accesses to the constant pool.
3121 // The address of the global is just (hi(&g)+lo(&g)).
3122 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3123}
3124
3128}
3129
3132}
3133
3134SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3135 SDValue GA) const {
3136 const bool Is64Bit = Subtarget.isPPC64();
3137 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3138 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3139 : Subtarget.isAIXABI()
3140 ? DAG.getRegister(PPC::R2, VT)
3141 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3142 SDValue Ops[] = { GA, Reg };
3143 return DAG.getMemIntrinsicNode(
3144 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3147}
3148
3149SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3150 SelectionDAG &DAG) const {
3151 EVT PtrVT = Op.getValueType();
3152 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3153 const Constant *C = CP->getConstVal();
3154
3155 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3156 // The actual address of the GlobalValue is stored in the TOC.
3157 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3158 if (Subtarget.isUsingPCRelativeCalls()) {
3159 SDLoc DL(CP);
3160 EVT Ty = getPointerTy(DAG.getDataLayout());
3161 SDValue ConstPool = DAG.getTargetConstantPool(
3162 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3163 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3164 }
3165 setUsesTOCBasePtr(DAG);
3166 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3167 return getTOCEntry(DAG, SDLoc(CP), GA);
3168 }
3169
3170 unsigned MOHiFlag, MOLoFlag;
3171 bool IsPIC = isPositionIndependent();
3172 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3173
3174 if (IsPIC && Subtarget.isSVR4ABI()) {
3175 SDValue GA =
3176 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3177 return getTOCEntry(DAG, SDLoc(CP), GA);
3178 }
3179
3180 SDValue CPIHi =
3181 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3182 SDValue CPILo =
3183 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3184 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3185}
3186
3187// For 64-bit PowerPC, prefer the more compact relative encodings.
3188// This trades 32 bits per jump table entry for one or two instructions
3189// on the jump site.
3191 if (isJumpTableRelative())
3193
3195}
3196
3199 return false;
3200 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3201 return true;
3203}
3204
3206 SelectionDAG &DAG) const {
3207 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3209
3210 switch (getTargetMachine().getCodeModel()) {
3211 case CodeModel::Small:
3212 case CodeModel::Medium:
3214 default:
3215 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3217 }
3218}
3219
3220const MCExpr *
3222 unsigned JTI,
3223 MCContext &Ctx) const {
3224 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3226
3227 switch (getTargetMachine().getCodeModel()) {
3228 case CodeModel::Small:
3229 case CodeModel::Medium:
3231 default:
3232 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3233 }
3234}
3235
3236SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3237 EVT PtrVT = Op.getValueType();
3238 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3239
3240 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3241 if (Subtarget.isUsingPCRelativeCalls()) {
3242 SDLoc DL(JT);
3243 EVT Ty = getPointerTy(DAG.getDataLayout());
3244 SDValue GA =
3245 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3246 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3247 return MatAddr;
3248 }
3249
3250 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3251 // The actual address of the GlobalValue is stored in the TOC.
3252 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3253 setUsesTOCBasePtr(DAG);
3254 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3255 return getTOCEntry(DAG, SDLoc(JT), GA);
3256 }
3257
3258 unsigned MOHiFlag, MOLoFlag;
3259 bool IsPIC = isPositionIndependent();
3260 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3261
3262 if (IsPIC && Subtarget.isSVR4ABI()) {
3263 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3265 return getTOCEntry(DAG, SDLoc(GA), GA);
3266 }
3267
3268 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3269 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3270 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3271}
3272
3273SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3274 SelectionDAG &DAG) const {
3275 EVT PtrVT = Op.getValueType();
3276 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3277 const BlockAddress *BA = BASDN->getBlockAddress();
3278
3279 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3280 if (Subtarget.isUsingPCRelativeCalls()) {
3281 SDLoc DL(BASDN);
3282 EVT Ty = getPointerTy(DAG.getDataLayout());
3283 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3285 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3286 return MatAddr;
3287 }
3288
3289 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3290 // The actual BlockAddress is stored in the TOC.
3291 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3292 setUsesTOCBasePtr(DAG);
3293 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3294 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3295 }
3296
3297 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3298 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3299 return getTOCEntry(
3300 DAG, SDLoc(BASDN),
3301 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3302
3303 unsigned MOHiFlag, MOLoFlag;
3304 bool IsPIC = isPositionIndependent();
3305 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3306 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3307 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3308 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3309}
3310
3311SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3312 SelectionDAG &DAG) const {
3313 if (Subtarget.isAIXABI())
3314 return LowerGlobalTLSAddressAIX(Op, DAG);
3315
3316 return LowerGlobalTLSAddressLinux(Op, DAG);
3317}
3318
3319SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3320 SelectionDAG &DAG) const {
3321 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3322
3323 if (DAG.getTarget().useEmulatedTLS())
3324 report_fatal_error("Emulated TLS is not yet supported on AIX");
3325
3326 SDLoc dl(GA);
3327 const GlobalValue *GV = GA->getGlobal();
3328 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3329
3330 // The general-dynamic model is the only access model supported for now, so
3331 // all the GlobalTLSAddress nodes are lowered with this model.
3332 // We need to generate two TOC entries, one for the variable offset, one for
3333 // the region handle. The global address for the TOC entry of the region
3334 // handle is created with the MO_TLSGDM_FLAG flag and the global address
3335 // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
3336 SDValue VariableOffsetTGA =
3337 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3338 SDValue RegionHandleTGA =
3339 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3340 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3341 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3342 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3343 RegionHandle);
3344}
3345
3346SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3347 SelectionDAG &DAG) const {
3348 // FIXME: TLS addresses currently use medium model code sequences,
3349 // which is the most useful form. Eventually support for small and
3350 // large models could be added if users need it, at the cost of
3351 // additional complexity.
3352 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3353 if (DAG.getTarget().useEmulatedTLS())
3354 return LowerToTLSEmulatedModel(GA, DAG);
3355
3356 SDLoc dl(GA);
3357 const GlobalValue *GV = GA->getGlobal();
3358 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3359 bool is64bit = Subtarget.isPPC64();
3360 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3361 PICLevel::Level picLevel = M->getPICLevel();
3362
3364 TLSModel::Model Model = TM.getTLSModel(GV);
3365
3366 if (Model == TLSModel::LocalExec) {
3367 if (Subtarget.isUsingPCRelativeCalls()) {
3368 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3370 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3371 SDValue MatAddr =
3372 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3373 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3374 }
3375
3376 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3378 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3380 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3381 : DAG.getRegister(PPC::R2, MVT::i32);
3382
3383 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3384 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3385 }
3386
3387 if (Model == TLSModel::InitialExec) {
3388 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3390 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3391 SDValue TGATLS = DAG.getTargetGlobalAddress(
3392 GV, dl, PtrVT, 0,
3394 SDValue TPOffset;
3395 if (IsPCRel) {
3396 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3397 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3399 } else {
3400 SDValue GOTPtr;
3401 if (is64bit) {
3402 setUsesTOCBasePtr(DAG);
3403 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3404 GOTPtr =
3405 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3406 } else {
3407 if (!TM.isPositionIndependent())
3408 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3409 else if (picLevel == PICLevel::SmallPIC)
3410 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3411 else
3412 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3413 }
3414 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3415 }
3416 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3417 }
3418
3419 if (Model == TLSModel::GeneralDynamic) {
3420 if (Subtarget.isUsingPCRelativeCalls()) {
3421 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3423 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3424 }
3425
3426 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3427 SDValue GOTPtr;
3428 if (is64bit) {
3429 setUsesTOCBasePtr(DAG);
3430 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3431 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3432 GOTReg, TGA);
3433 } else {
3434 if (picLevel == PICLevel::SmallPIC)
3435 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3436 else
3437 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3438 }
3439 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3440 GOTPtr, TGA, TGA);
3441 }
3442
3443 if (Model == TLSModel::LocalDynamic) {
3444 if (Subtarget.isUsingPCRelativeCalls()) {
3445 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3447 SDValue MatPCRel =
3448 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3449 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3450 }
3451
3452 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3453 SDValue GOTPtr;
3454 if (is64bit) {
3455 setUsesTOCBasePtr(DAG);
3456 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3457 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3458 GOTReg, TGA);
3459 } else {
3460 if (picLevel == PICLevel::SmallPIC)
3461 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3462 else
3463 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3464 }
3465 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3466 PtrVT, GOTPtr, TGA, TGA);
3467 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3468 PtrVT, TLSAddr, TGA);
3469 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3470 }
3471
3472 llvm_unreachable("Unknown TLS model!");
3473}
3474
3475SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3476 SelectionDAG &DAG) const {
3477 EVT PtrVT = Op.getValueType();
3478 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3479 SDLoc DL(GSDN);
3480 const GlobalValue *GV = GSDN->getGlobal();
3481
3482 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3483 // The actual address of the GlobalValue is stored in the TOC.
3484 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3485 if (Subtarget.isUsingPCRelativeCalls()) {
3486 EVT Ty = getPointerTy(DAG.getDataLayout());
3487 if (isAccessedAsGotIndirect(Op)) {
3488 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3491 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3492 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3494 return Load;
3495 } else {
3496 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3498 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3499 }
3500 }
3501 setUsesTOCBasePtr(DAG);
3502 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3503 return getTOCEntry(DAG, DL, GA);
3504 }
3505
3506 unsigned MOHiFlag, MOLoFlag;
3507 bool IsPIC = isPositionIndependent();
3508 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3509
3510 if (IsPIC && Subtarget.isSVR4ABI()) {
3511 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3512 GSDN->getOffset(),
3514 return getTOCEntry(DAG, DL, GA);
3515 }
3516
3517 SDValue GAHi =
3518 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3519 SDValue GALo =
3520 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3521
3522 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3523}
3524
3525SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3526 bool IsStrict = Op->isStrictFPOpcode();
3528 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3529 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3530 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3531 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3532 EVT LHSVT = LHS.getValueType();
3533 SDLoc dl(Op);
3534
3535 // Soften the setcc with libcall if it is fp128.
3536 if (LHSVT == MVT::f128) {
3537 assert(!Subtarget.hasP9Vector() &&
3538 "SETCC for f128 is already legal under Power9!");
3539 softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
3540 Op->getOpcode() == ISD::STRICT_FSETCCS);
3541 if (RHS.getNode())
3542 LHS = DAG.getNode(ISD::SETCC, dl, Op.getValueType(), LHS, RHS,
3543 DAG.getCondCode(CC));
3544 if (IsStrict)
3545 return DAG.getMergeValues({LHS, Chain}, dl);
3546 return LHS;
3547 }
3548
3549 assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!");
3550
3551 if (Op.getValueType() == MVT::v2i64) {
3552 // When the operands themselves are v2i64 values, we need to do something
3553 // special because VSX has no underlying comparison operations for these.
3554 if (LHS.getValueType() == MVT::v2i64) {
3555 // Equality can be handled by casting to the legal type for Altivec
3556 // comparisons, everything else needs to be expanded.
3557 if (CC != ISD::SETEQ && CC != ISD::SETNE)
3558 return SDValue();
3559 SDValue SetCC32 = DAG.getSetCC(
3560 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS),
3561 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC);
3562 int ShuffV[] = {1, 0, 3, 2};
3563 SDValue Shuff =
3564 DAG.getVectorShuffle(MVT::v4i32, dl, SetCC32, SetCC32, ShuffV);
3565 return DAG.getBitcast(MVT::v2i64,
3567 dl, MVT::v4i32, Shuff, SetCC32));
3568 }
3569
3570 // We handle most of these in the usual way.
3571 return Op;
3572 }
3573
3574 // If we're comparing for equality to zero, expose the fact that this is
3575 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3576 // fold the new nodes.
3577 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3578 return V;
3579
3580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
3581 // Leave comparisons against 0 and -1 alone for now, since they're usually
3582 // optimized. FIXME: revisit this when we can custom lower all setcc
3583 // optimizations.
3584 if (C->isAllOnes() || C->isZero())
3585 return SDValue();
3586 }
3587
3588 // If we have an integer seteq/setne, turn it into a compare against zero
3589 // by xor'ing the rhs with the lhs, which is faster than setting a
3590 // condition register, reading it back out, and masking the correct bit. The
3591 // normal approach here uses sub to do this instead of xor. Using xor exposes
3592 // the result to other bit-twiddling opportunities.
3593 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3594 EVT VT = Op.getValueType();
3595 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, LHS, RHS);
3596 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3597 }
3598 return SDValue();
3599}
3600
3601SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3602 SDNode *Node = Op.getNode();
3603 EVT VT = Node->getValueType(0);
3604 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3605 SDValue InChain = Node->getOperand(0);
3606 SDValue VAListPtr = Node->getOperand(1);
3607 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3608 SDLoc dl(Node);
3609
3610 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
3611
3612 // gpr_index
3613 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3614 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3615 InChain = GprIndex.getValue(1);
3616
3617 if (VT == MVT::i64) {
3618 // Check if GprIndex is even
3619 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3620 DAG.getConstant(1, dl, MVT::i32));
3621 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3622 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3623 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3624 DAG.getConstant(1, dl, MVT::i32));
3625 // Align GprIndex to be even if it isn't
3626 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3627 GprIndex);
3628 }
3629
3630 // fpr index is 1 byte after gpr
3631 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3632 DAG.getConstant(1, dl, MVT::i32));
3633
3634 // fpr
3635 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3636 FprPtr, MachinePointerInfo(SV), MVT::i8);
3637 InChain = FprIndex.getValue(1);
3638
3639 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3640 DAG.getConstant(8, dl, MVT::i32));
3641
3642 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3643 DAG.getConstant(4, dl, MVT::i32));
3644
3645 // areas
3646 SDValue OverflowArea =
3647 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3648 InChain = OverflowArea.getValue(1);
3649
3650 SDValue RegSaveArea =
3651 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3652 InChain = RegSaveArea.getValue(1);
3653
3654 // select overflow_area if index > 8
3655 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3656 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3657
3658 // adjustment constant gpr_index * 4/8
3659 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3660 VT.isInteger() ? GprIndex : FprIndex,
3661 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3662 MVT::i32));
3663
3664 // OurReg = RegSaveArea + RegConstant
3665 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3666 RegConstant);
3667
3668 // Floating types are 32 bytes into RegSaveArea
3669 if (VT.isFloatingPoint())
3670 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3671 DAG.getConstant(32, dl, MVT::i32));
3672
3673 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3674 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3675 VT.isInteger() ? GprIndex : FprIndex,
3676 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3677 MVT::i32));
3678
3679 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3680 VT.