LLVM 18.0.0git
PPCISelLowering.cpp
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1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/APSInt.h"
28#include "llvm/ADT/ArrayRef.h"
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallSet.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
59#include "llvm/IR/CallingConv.h"
60#include "llvm/IR/Constant.h"
61#include "llvm/IR/Constants.h"
62#include "llvm/IR/DataLayout.h"
63#include "llvm/IR/DebugLoc.h"
65#include "llvm/IR/Function.h"
66#include "llvm/IR/GlobalValue.h"
67#include "llvm/IR/IRBuilder.h"
69#include "llvm/IR/Intrinsics.h"
70#include "llvm/IR/IntrinsicsPowerPC.h"
71#include "llvm/IR/Module.h"
72#include "llvm/IR/Type.h"
73#include "llvm/IR/Use.h"
74#include "llvm/IR/Value.h"
75#include "llvm/MC/MCContext.h"
76#include "llvm/MC/MCExpr.h"
86#include "llvm/Support/Debug.h"
88#include "llvm/Support/Format.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <optional>
100#include <utility>
101#include <vector>
102
103using namespace llvm;
104
105#define DEBUG_TYPE "ppc-lowering"
106
107static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
108cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
109
110static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
111cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
112
113static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
114cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
115
116static cl::opt<bool> DisableSCO("disable-ppc-sco",
117cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
118
119static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
120cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
121
122static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
123cl::desc("use absolute jump tables on ppc"), cl::Hidden);
124
125static cl::opt<bool>
126 DisablePerfectShuffle("ppc-disable-perfect-shuffle",
127 cl::desc("disable vector permute decomposition"),
128 cl::init(true), cl::Hidden);
129
131 "disable-auto-paired-vec-st",
132 cl::desc("disable automatically generated 32byte paired vector stores"),
133 cl::init(true), cl::Hidden);
134
136 "ppc-min-jump-table-entries", cl::init(64), cl::Hidden,
137 cl::desc("Set minimum number of entries to use a jump table on PPC"));
138
139STATISTIC(NumTailCalls, "Number of tail calls");
140STATISTIC(NumSiblingCalls, "Number of sibling calls");
141STATISTIC(ShufflesHandledWithVPERM,
142 "Number of shuffles lowered to a VPERM or XXPERM");
143STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
144
145static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
146
147static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
148
149static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
150
151// A faster local-exec TLS access sequence (enabled with the
152// -maix-small-local-exec-tls option) can be produced for TLS variables;
153// consistent with the IBM XL compiler, we apply a max size of slightly under
154// 32KB.
156
157// FIXME: Remove this once the bug has been fixed!
159
161 const PPCSubtarget &STI)
162 : TargetLowering(TM), Subtarget(STI) {
163 // Initialize map that relates the PPC addressing modes to the computed flags
164 // of a load/store instruction. The map is used to determine the optimal
165 // addressing mode when selecting load and stores.
166 initializeAddrModeMap();
167 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
168 // arguments are at least 4/8 bytes aligned.
169 bool isPPC64 = Subtarget.isPPC64();
170 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
171
172 // Set up the register classes.
173 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
174 if (!useSoftFloat()) {
175 if (hasSPE()) {
176 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
177 // EFPU2 APU only supports f32
178 if (!Subtarget.hasEFPU2())
179 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
180 } else {
181 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
182 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
183 }
184 }
185
186 // Match BITREVERSE to customized fast code sequence in the td file.
189
190 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
192
193 // Custom lower inline assembly to check for special registers.
196
197 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
198 for (MVT VT : MVT::integer_valuetypes()) {
201 }
202
203 if (Subtarget.isISA3_0()) {
204 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
205 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
206 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
207 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
208 } else {
209 // No extending loads from f16 or HW conversions back and forth.
210 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
213 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
216 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
217 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
218 }
219
220 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
221
222 // PowerPC has pre-inc load and store's.
233 if (!Subtarget.hasSPE()) {
238 }
239
240 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
241 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
242 for (MVT VT : ScalarIntVTs) {
247 }
248
249 if (Subtarget.useCRBits()) {
251
252 if (isPPC64 || Subtarget.hasFPCVT()) {
255 isPPC64 ? MVT::i64 : MVT::i32);
258 isPPC64 ? MVT::i64 : MVT::i32);
259
262 isPPC64 ? MVT::i64 : MVT::i32);
265 isPPC64 ? MVT::i64 : MVT::i32);
266
269 isPPC64 ? MVT::i64 : MVT::i32);
272 isPPC64 ? MVT::i64 : MVT::i32);
273
276 isPPC64 ? MVT::i64 : MVT::i32);
279 isPPC64 ? MVT::i64 : MVT::i32);
280 } else {
285 }
286
287 // PowerPC does not support direct load/store of condition registers.
290
291 // FIXME: Remove this once the ANDI glue bug is fixed:
292 if (ANDIGlueBug)
294
295 for (MVT VT : MVT::integer_valuetypes()) {
298 setTruncStoreAction(VT, MVT::i1, Expand);
299 }
300
301 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
302 }
303
304 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
305 // PPC (the libcall is not available).
310
311 // We do not currently implement these libm ops for PowerPC.
312 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
313 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
314 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
315 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
317 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
318
319 // PowerPC has no SREM/UREM instructions unless we are on P9
320 // On P9 we may use a hardware instruction to compute the remainder.
321 // When the result of both the remainder and the division is required it is
322 // more efficient to compute the remainder from the result of the division
323 // rather than use the remainder instruction. The instructions are legalized
324 // directly because the DivRemPairsPass performs the transformation at the IR
325 // level.
326 if (Subtarget.isISA3_0()) {
331 } else {
336 }
337
338 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
347
348 // Handle constrained floating-point operations of scalar.
349 // TODO: Handle SPE specific operation.
355
360
361 if (!Subtarget.hasSPE()) {
364 }
365
366 if (Subtarget.hasVSX()) {
369 }
370
371 if (Subtarget.hasFSQRT()) {
374 }
375
376 if (Subtarget.hasFPRND()) {
381
386 }
387
388 // We don't support sin/cos/sqrt/fmod/pow
399
400 // MASS transformation for LLVM intrinsics with replicating fast-math flag
401 // to be consistent to PPCGenScalarMASSEntries pass
402 if (TM.getOptLevel() == CodeGenOptLevel::Aggressive) {
415 }
416
417 if (Subtarget.hasSPE()) {
420 } else {
421 setOperationAction(ISD::FMA , MVT::f64, Legal);
422 setOperationAction(ISD::FMA , MVT::f32, Legal);
423 }
424
425 if (Subtarget.hasSPE())
426 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
427
429
430 // If we're enabling GP optimizations, use hardware square root
431 if (!Subtarget.hasFSQRT() &&
432 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
433 Subtarget.hasFRE()))
435
436 if (!Subtarget.hasFSQRT() &&
437 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
438 Subtarget.hasFRES()))
440
441 if (Subtarget.hasFCPSGN()) {
444 } else {
447 }
448
449 if (Subtarget.hasFPRND()) {
454
459 }
460
461 // Prior to P10, PowerPC does not have BSWAP, but we can use vector BSWAP
462 // instruction xxbrd to speed up scalar BSWAP64.
463 if (Subtarget.isISA3_1()) {
466 } else {
469 ISD::BSWAP, MVT::i64,
470 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
471 }
472
473 // CTPOP or CTTZ were introduced in P8/P9 respectively
474 if (Subtarget.isISA3_0()) {
475 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
476 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
477 } else {
478 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
479 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
480 }
481
482 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
485 } else {
488 }
489
490 // PowerPC does not have ROTR
493
494 if (!Subtarget.useCRBits()) {
495 // PowerPC does not have Select
500 }
501
502 // PowerPC wants to turn select_cc of FP into fsel when possible.
505
506 // PowerPC wants to optimize integer setcc a bit
507 if (!Subtarget.useCRBits())
509
510 if (Subtarget.hasFPU()) {
514
518 }
519
520 // PowerPC does not have BRCOND which requires SetCC
521 if (!Subtarget.useCRBits())
523
525
526 if (Subtarget.hasSPE()) {
527 // SPE has built-in conversions
534
535 // SPE supports signaling compare of f32/f64.
538 } else {
539 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
542
543 // PowerPC does not have [U|S]INT_TO_FP
548 }
549
550 if (Subtarget.hasDirectMove() && isPPC64) {
555 if (TM.Options.UnsafeFPMath) {
564 }
565 } else {
570 }
571
572 // We cannot sextinreg(i1). Expand to shifts.
574
575 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
576 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
577 // support continuation, user-level threading, and etc.. As a result, no
578 // other SjLj exception interfaces are implemented and please don't build
579 // your own exception handling based on them.
580 // LLVM/Clang supports zero-cost DWARF exception handling.
583
584 // We want to legalize GlobalAddress and ConstantPool nodes into the
585 // appropriate instructions to materialize the address.
596
597 // TRAP is legal.
598 setOperationAction(ISD::TRAP, MVT::Other, Legal);
599
600 // TRAMPOLINE is custom lowered.
603
604 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
606
607 if (Subtarget.is64BitELFABI()) {
608 // VAARG always uses double-word chunks, so promote anything smaller.
610 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
612 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
614 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
616 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
618 } else if (Subtarget.is32BitELFABI()) {
619 // VAARG is custom lowered with the 32-bit SVR4 ABI.
622 } else
624
625 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
626 if (Subtarget.is32BitELFABI())
628 else
630
631 // Use the default implementation.
632 setOperationAction(ISD::VAEND , MVT::Other, Expand);
641
642 // We want to custom lower some of our intrinsics.
648
649 // To handle counter-based loop conditions.
651
656
657 // Comparisons that require checking two conditions.
658 if (Subtarget.hasSPE()) {
663 }
676
679
680 if (Subtarget.has64BitSupport()) {
681 // They also have instructions for converting between i64 and fp.
690 // This is just the low 32 bits of a (signed) fp->i64 conversion.
691 // We cannot do this with Promote because i64 is not a legal type.
694
695 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
698 }
699 } else {
700 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
701 if (Subtarget.hasSPE()) {
704 } else {
707 }
708 }
709
710 // With the instructions enabled under FPCVT, we can do everything.
711 if (Subtarget.hasFPCVT()) {
712 if (Subtarget.has64BitSupport()) {
721 }
722
731 }
732
733 if (Subtarget.use64BitRegs()) {
734 // 64-bit PowerPC implementations can support i64 types directly
735 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
736 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
738 // 64-bit PowerPC wants to expand i128 shifts itself.
742 } else {
743 // 32-bit PowerPC wants to expand i64 shifts itself.
747 }
748
749 // PowerPC has better expansions for funnel shifts than the generic
750 // TargetLowering::expandFunnelShift.
751 if (Subtarget.has64BitSupport()) {
754 }
757
758 if (Subtarget.hasVSX()) {
763 }
764
765 if (Subtarget.hasAltivec()) {
766 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
771 }
772 // First set operation action for all vector types to expand. Then we
773 // will selectively turn on ones that can be effectively codegen'd.
775 // add/sub are legal for all supported vector VT's.
778
779 // For v2i64, these are only valid with P8Vector. This is corrected after
780 // the loop.
781 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
786 }
787 else {
792 }
793
794 if (Subtarget.hasVSX()) {
797 }
798
799 // Vector instructions introduced in P8
800 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
803 }
804 else {
807 }
808
809 // Vector instructions introduced in P9
810 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
812 else
814
815 // We promote all shuffles to v16i8.
817 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
818
819 // We promote all non-typed operations to v4i32.
821 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
823 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
825 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
827 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
829 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
832 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
834 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
835
836 // No other operations are legal.
875
876 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
877 setTruncStoreAction(VT, InnerVT, Expand);
880 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
881 }
882 }
884 if (!Subtarget.hasP8Vector()) {
885 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
886 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
887 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
888 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
889 }
890
891 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
892 // with merges, splats, etc.
894
895 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
896 // are cheap, so handle them before they get expanded to scalar.
902
903 setOperationAction(ISD::AND , MVT::v4i32, Legal);
904 setOperationAction(ISD::OR , MVT::v4i32, Legal);
905 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
906 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
908 Subtarget.useCRBits() ? Legal : Expand);
909 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
919 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
922
923 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
924 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
925 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
926 if (Subtarget.hasAltivec())
927 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
929 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
930 if (Subtarget.hasP8Altivec())
931 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
932
933 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
934 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
935 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
936 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
937
938 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
939 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
940
941 if (Subtarget.hasVSX()) {
942 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
945 }
946
947 if (Subtarget.hasP8Altivec())
948 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 else
950 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
951
952 if (Subtarget.isISA3_1()) {
953 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
954 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
955 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
956 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
957 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
958 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
959 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
960 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
961 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
962 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
963 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
964 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
965 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
966 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
967 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
968 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
969 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
970 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
971 }
972
973 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
974 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
975
978
983
984 // Altivec does not contain unordered floating-point compare instructions
985 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
987 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
989
990 if (Subtarget.hasVSX()) {
993 if (Subtarget.hasP8Vector()) {
996 }
997 if (Subtarget.hasDirectMove() && isPPC64) {
1006 }
1008
1009 // The nearbyint variants are not allowed to raise the inexact exception
1010 // so we can only code-gen them with unsafe math.
1011 if (TM.Options.UnsafeFPMath) {
1014 }
1015
1016 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1017 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1018 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1020 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1021 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
1024
1026 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1027 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1030
1031 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1032 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1033
1034 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1035 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1036
1037 // Share the Altivec comparison restrictions.
1038 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
1039 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
1040 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
1041 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
1042
1043 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1044 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1045
1047
1048 if (Subtarget.hasP8Vector())
1049 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1050
1051 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1052
1053 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1054 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1055 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1056
1057 if (Subtarget.hasP8Altivec()) {
1058 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1059 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1060 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1061
1062 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1063 // SRL, but not for SRA because of the instructions available:
1064 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1065 // doing
1066 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1067 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1068 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1069
1070 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1071 }
1072 else {
1073 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1074 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1075 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1076
1077 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1078
1079 // VSX v2i64 only supports non-arithmetic operations.
1080 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1081 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1082 }
1083
1084 if (Subtarget.isISA3_1())
1085 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1086 else
1087 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1088
1089 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1090 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1092 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1093
1095
1104
1105 // Custom handling for partial vectors of integers converted to
1106 // floating point. We already have optimal handling for v2i32 through
1107 // the DAG combine, so those aren't necessary.
1124
1125 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1126 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1127 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1128 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1131
1134
1135 // Handle constrained floating-point operations of vector.
1136 // The predictor is `hasVSX` because altivec instruction has
1137 // no exception but VSX vector instruction has.
1151
1165
1166 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1167 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1168
1169 for (MVT FPT : MVT::fp_valuetypes())
1170 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1171
1172 // Expand the SELECT to SELECT_CC
1174
1175 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1176 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1177
1178 // No implementation for these ops for PowerPC.
1179 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1180 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1181 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1183 setOperationAction(ISD::FREM, MVT::f128, Expand);
1184 }
1185
1186 if (Subtarget.hasP8Altivec()) {
1187 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1188 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1189 }
1190
1191 if (Subtarget.hasP9Vector()) {
1194
1195 // Test data class instructions store results in CR bits.
1196 if (Subtarget.useCRBits()) {
1200 }
1201
1202 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1203 // SRL, but not for SRA because of the instructions available:
1204 // VS{RL} and VS{RL}O.
1205 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1206 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1207 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1208
1209 setOperationAction(ISD::FADD, MVT::f128, Legal);
1210 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1211 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1212 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1214
1215 setOperationAction(ISD::FMA, MVT::f128, Legal);
1222
1224 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1226 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1229
1233
1234 // Handle constrained floating-point operations of fp128
1251 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1252 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1253 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1254 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1255 } else if (Subtarget.hasVSX()) {
1258
1259 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1260 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1261
1262 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1263 // fp_to_uint and int_to_fp.
1266
1267 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1268 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1269 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1270 setOperationAction(ISD::FABS, MVT::f128, Expand);
1272 setOperationAction(ISD::FMA, MVT::f128, Expand);
1274
1275 // Expand the fp_extend if the target type is fp128.
1278
1279 // Expand the fp_round if the source type is fp128.
1280 for (MVT VT : {MVT::f32, MVT::f64}) {
1283 }
1284
1289
1290 // Lower following f128 select_cc pattern:
1291 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1293
1294 // We need to handle f128 SELECT_CC with integer result type.
1296 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1297 }
1298
1299 if (Subtarget.hasP9Altivec()) {
1300 if (Subtarget.isISA3_1()) {
1305 } else {
1308 }
1316
1317 setOperationAction(ISD::ABDU, MVT::v16i8, Legal);
1318 setOperationAction(ISD::ABDU, MVT::v8i16, Legal);
1319 setOperationAction(ISD::ABDU, MVT::v4i32, Legal);
1320 setOperationAction(ISD::ABDS, MVT::v4i32, Legal);
1321 }
1322
1323 if (Subtarget.hasP10Vector()) {
1325 }
1326 }
1327
1328 if (Subtarget.pairedVectorMemops()) {
1329 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1330 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1331 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1332 }
1333 if (Subtarget.hasMMA()) {
1334 if (Subtarget.isISAFuture())
1335 addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass);
1336 else
1337 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1338 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1339 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1341 }
1342
1343 if (Subtarget.has64BitSupport())
1345
1346 if (Subtarget.isISA3_1())
1347 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1348
1349 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1350
1351 if (!isPPC64) {
1354 }
1355
1360 }
1361
1363
1364 if (Subtarget.hasAltivec()) {
1365 // Altivec instructions set fields to all zeros or all ones.
1367 }
1368
1369 setLibcallName(RTLIB::MULO_I128, nullptr);
1370 if (!isPPC64) {
1371 // These libcalls are not available in 32-bit.
1372 setLibcallName(RTLIB::SHL_I128, nullptr);
1373 setLibcallName(RTLIB::SRL_I128, nullptr);
1374 setLibcallName(RTLIB::SRA_I128, nullptr);
1375 setLibcallName(RTLIB::MUL_I128, nullptr);
1376 setLibcallName(RTLIB::MULO_I64, nullptr);
1377 }
1378
1381 else if (isPPC64)
1383 else
1385
1386 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1387
1388 // We have target-specific dag combine patterns for the following nodes:
1391 if (Subtarget.hasFPCVT())
1394 if (Subtarget.useCRBits())
1398
1400
1402
1403 if (Subtarget.useCRBits()) {
1405 }
1406
1407 setLibcallName(RTLIB::LOG_F128, "logf128");
1408 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1409 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1410 setLibcallName(RTLIB::EXP_F128, "expf128");
1411 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1412 setLibcallName(RTLIB::SIN_F128, "sinf128");
1413 setLibcallName(RTLIB::COS_F128, "cosf128");
1414 setLibcallName(RTLIB::POW_F128, "powf128");
1415 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1416 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1417 setLibcallName(RTLIB::REM_F128, "fmodf128");
1418 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1419 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1420 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1421 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1422 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1423 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1424 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1425 setLibcallName(RTLIB::RINT_F128, "rintf128");
1426 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1427 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1428 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1429 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1430 setLibcallName(RTLIB::FREXP_F128, "frexpf128");
1431
1432 if (Subtarget.isAIXABI()) {
1433 setLibcallName(RTLIB::MEMCPY, isPPC64 ? "___memmove64" : "___memmove");
1434 setLibcallName(RTLIB::MEMMOVE, isPPC64 ? "___memmove64" : "___memmove");
1435 setLibcallName(RTLIB::MEMSET, isPPC64 ? "___memset64" : "___memset");
1436 setLibcallName(RTLIB::BZERO, isPPC64 ? "___bzero64" : "___bzero");
1437 }
1438
1439 // With 32 condition bits, we don't need to sink (and duplicate) compares
1440 // aggressively in CodeGenPrep.
1441 if (Subtarget.useCRBits()) {
1444 }
1445
1446 // TODO: The default entry number is set to 64. This stops most jump table
1447 // generation on PPC. But it is good for current PPC HWs because the indirect
1448 // branch instruction mtctr to the jump table may lead to bad branch predict.
1449 // Re-evaluate this value on future HWs that can do better with mtctr.
1451
1453
1454 switch (Subtarget.getCPUDirective()) {
1455 default: break;
1456 case PPC::DIR_970:
1457 case PPC::DIR_A2:
1458 case PPC::DIR_E500:
1459 case PPC::DIR_E500mc:
1460 case PPC::DIR_E5500:
1461 case PPC::DIR_PWR4:
1462 case PPC::DIR_PWR5:
1463 case PPC::DIR_PWR5X:
1464 case PPC::DIR_PWR6:
1465 case PPC::DIR_PWR6X:
1466 case PPC::DIR_PWR7:
1467 case PPC::DIR_PWR8:
1468 case PPC::DIR_PWR9:
1469 case PPC::DIR_PWR10:
1473 break;
1474 }
1475
1476 if (Subtarget.enableMachineScheduler())
1478 else
1480
1482
1483 // The Freescale cores do better with aggressive inlining of memcpy and
1484 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1485 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1486 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1487 MaxStoresPerMemset = 32;
1489 MaxStoresPerMemcpy = 32;
1493 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1494 // The A2 also benefits from (very) aggressive inlining of memcpy and
1495 // friends. The overhead of a the function call, even when warm, can be
1496 // over one hundred cycles.
1497 MaxStoresPerMemset = 128;
1498 MaxStoresPerMemcpy = 128;
1499 MaxStoresPerMemmove = 128;
1500 MaxLoadsPerMemcmp = 128;
1501 } else {
1504 }
1505
1506 IsStrictFPEnabled = true;
1507
1508 // Let the subtarget (CPU) decide if a predictable select is more expensive
1509 // than the corresponding branch. This information is used in CGP to decide
1510 // when to convert selects into branches.
1512}
1513
1514// *********************************** NOTE ************************************
1515// For selecting load and store instructions, the addressing modes are defined
1516// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1517// patterns to match the load the store instructions.
1518//
1519// The TD definitions for the addressing modes correspond to their respective
1520// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1521// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1522// address mode flags of a particular node. Afterwards, the computed address
1523// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1524// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1525// accordingly, based on the preferred addressing mode.
1526//
1527// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1528// MemOpFlags contains all the possible flags that can be used to compute the
1529// optimal addressing mode for load and store instructions.
1530// AddrMode contains all the possible load and store addressing modes available
1531// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1532//
1533// When adding new load and store instructions, it is possible that new address
1534// flags may need to be added into MemOpFlags, and a new addressing mode will
1535// need to be added to AddrMode. An entry of the new addressing mode (consisting
1536// of the minimal and main distinguishing address flags for the new load/store
1537// instructions) will need to be added into initializeAddrModeMap() below.
1538// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1539// need to be updated to account for selecting the optimal addressing mode.
1540// *****************************************************************************
1541/// Initialize the map that relates the different addressing modes of the load
1542/// and store instructions to a set of flags. This ensures the load/store
1543/// instruction is correctly matched during instruction selection.
1544void PPCTargetLowering::initializeAddrModeMap() {
1545 AddrModesMap[PPC::AM_DForm] = {
1546 // LWZ, STW
1551 // LBZ, LHZ, STB, STH
1556 // LHA
1561 // LFS, LFD, STFS, STFD
1566 };
1567 AddrModesMap[PPC::AM_DSForm] = {
1568 // LWA
1572 // LD, STD
1576 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1580 };
1581 AddrModesMap[PPC::AM_DQForm] = {
1582 // LXV, STXV
1586 };
1587 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1589 // TODO: Add mapping for quadword load/store.
1590}
1591
1592/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1593/// the desired ByVal argument alignment.
1594static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1595 if (MaxAlign == MaxMaxAlign)
1596 return;
1597 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1598 if (MaxMaxAlign >= 32 &&
1599 VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
1600 MaxAlign = Align(32);
1601 else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
1602 MaxAlign < 16)
1603 MaxAlign = Align(16);
1604 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1605 Align EltAlign;
1606 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1607 if (EltAlign > MaxAlign)
1608 MaxAlign = EltAlign;
1609 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1610 for (auto *EltTy : STy->elements()) {
1611 Align EltAlign;
1612 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1613 if (EltAlign > MaxAlign)
1614 MaxAlign = EltAlign;
1615 if (MaxAlign == MaxMaxAlign)
1616 break;
1617 }
1618 }
1619}
1620
1621/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1622/// function arguments in the caller parameter area.
1624 const DataLayout &DL) const {
1625 // 16byte and wider vectors are passed on 16byte boundary.
1626 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1627 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1628 if (Subtarget.hasAltivec())
1629 getMaxByValAlign(Ty, Alignment, Align(16));
1630 return Alignment.value();
1631}
1632
1634 return Subtarget.useSoftFloat();
1635}
1636
1638 return Subtarget.hasSPE();
1639}
1640
1642 return VT.isScalarInteger();
1643}
1644
1646 Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const {
1647 if (!Subtarget.isPPC64() || !Subtarget.hasVSX())
1648 return false;
1649
1650 if (auto *VTy = dyn_cast<VectorType>(VectorTy)) {
1651 if (VTy->getScalarType()->isIntegerTy()) {
1652 // ElemSizeInBits 8/16 can fit in immediate field, not needed here.
1653 if (ElemSizeInBits == 32) {
1654 Index = Subtarget.isLittleEndian() ? 2 : 1;
1655 return true;
1656 }
1657 if (ElemSizeInBits == 64) {
1658 Index = Subtarget.isLittleEndian() ? 1 : 0;
1659 return true;
1660 }
1661 }
1662 }
1663 return false;
1664}
1665
1667 switch ((PPCISD::NodeType)Opcode) {
1668 case PPCISD::FIRST_NUMBER: break;
1669 case PPCISD::FSEL: return "PPCISD::FSEL";
1670 case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
1671 case PPCISD::XSMINC: return "PPCISD::XSMINC";
1672 case PPCISD::FCFID: return "PPCISD::FCFID";
1673 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1674 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1675 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1676 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1677 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1678 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1679 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1680 case PPCISD::FRE: return "PPCISD::FRE";
1681 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1682 case PPCISD::FTSQRT:
1683 return "PPCISD::FTSQRT";
1684 case PPCISD::FSQRT:
1685 return "PPCISD::FSQRT";
1686 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1687 case PPCISD::VPERM: return "PPCISD::VPERM";
1688 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1690 return "PPCISD::XXSPLTI_SP_TO_DP";
1692 return "PPCISD::XXSPLTI32DX";
1693 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1694 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1695 case PPCISD::XXPERM:
1696 return "PPCISD::XXPERM";
1697 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1698 case PPCISD::CMPB: return "PPCISD::CMPB";
1699 case PPCISD::Hi: return "PPCISD::Hi";
1700 case PPCISD::Lo: return "PPCISD::Lo";
1701 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1702 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1703 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1704 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1705 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1706 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1707 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1708 case PPCISD::SRL: return "PPCISD::SRL";
1709 case PPCISD::SRA: return "PPCISD::SRA";
1710 case PPCISD::SHL: return "PPCISD::SHL";
1711 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1712 case PPCISD::CALL: return "PPCISD::CALL";
1713 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1714 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1715 case PPCISD::CALL_RM:
1716 return "PPCISD::CALL_RM";
1718 return "PPCISD::CALL_NOP_RM";
1720 return "PPCISD::CALL_NOTOC_RM";
1721 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1722 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1723 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1724 case PPCISD::BCTRL_RM:
1725 return "PPCISD::BCTRL_RM";
1727 return "PPCISD::BCTRL_LOAD_TOC_RM";
1728 case PPCISD::RET_GLUE: return "PPCISD::RET_GLUE";
1729 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1730 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1731 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1732 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1733 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1734 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1735 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1736 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1737 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1739 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1741 return "PPCISD::ANDI_rec_1_EQ_BIT";
1743 return "PPCISD::ANDI_rec_1_GT_BIT";
1744 case PPCISD::VCMP: return "PPCISD::VCMP";
1745 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1746 case PPCISD::LBRX: return "PPCISD::LBRX";
1747 case PPCISD::STBRX: return "PPCISD::STBRX";
1748 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1749 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1750 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1751 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1752 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1753 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1754 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1755 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1756 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1758 return "PPCISD::ST_VSR_SCAL_INT";
1759 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1760 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1761 case PPCISD::BDZ: return "PPCISD::BDZ";
1762 case PPCISD::MFFS: return "PPCISD::MFFS";
1763 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1764 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1765 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1766 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1767 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1768 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1769 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1770 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1771 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1772 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1773 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1774 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1775 case PPCISD::GET_TPOINTER: return "PPCISD::GET_TPOINTER";
1776 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1777 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1778 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1779 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1780 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1781 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1782 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1783 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1785 return "PPCISD::PADDI_DTPREL";
1786 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1787 case PPCISD::SC: return "PPCISD::SC";
1788 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1789 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1790 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1791 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1792 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1793 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1794 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1795 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1796 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1797 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1798 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1799 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1801 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1803 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1804 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1805 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1806 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1807 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1808 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1809 case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
1810 case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
1811 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1813 return "PPCISD::STRICT_FADDRTZ";
1815 return "PPCISD::STRICT_FCTIDZ";
1817 return "PPCISD::STRICT_FCTIWZ";
1819 return "PPCISD::STRICT_FCTIDUZ";
1821 return "PPCISD::STRICT_FCTIWUZ";
1823 return "PPCISD::STRICT_FCFID";
1825 return "PPCISD::STRICT_FCFIDU";
1827 return "PPCISD::STRICT_FCFIDS";
1829 return "PPCISD::STRICT_FCFIDUS";
1830 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1831 case PPCISD::STORE_COND:
1832 return "PPCISD::STORE_COND";
1833 }
1834 return nullptr;
1835}
1836
1838 EVT VT) const {
1839 if (!VT.isVector())
1840 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1841
1843}
1844
1846 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1847 return true;
1848}
1849
1850//===----------------------------------------------------------------------===//
1851// Node matching predicates, for use by the tblgen matching code.
1852//===----------------------------------------------------------------------===//
1853
1854/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1856 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1857 return CFP->getValueAPF().isZero();
1858 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1859 // Maybe this has already been legalized into the constant pool?
1860 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1861 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1862 return CFP->getValueAPF().isZero();
1863 }
1864 return false;
1865}
1866
1867/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1868/// true if Op is undef or if it matches the specified value.
1869static bool isConstantOrUndef(int Op, int Val) {
1870 return Op < 0 || Op == Val;
1871}
1872
1873/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1874/// VPKUHUM instruction.
1875/// The ShuffleKind distinguishes between big-endian operations with
1876/// two different inputs (0), either-endian operations with two identical
1877/// inputs (1), and little-endian operations with two different inputs (2).
1878/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1880 SelectionDAG &DAG) {
1881 bool IsLE = DAG.getDataLayout().isLittleEndian();
1882 if (ShuffleKind == 0) {
1883 if (IsLE)
1884 return false;
1885 for (unsigned i = 0; i != 16; ++i)
1886 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1887 return false;
1888 } else if (ShuffleKind == 2) {
1889 if (!IsLE)
1890 return false;
1891 for (unsigned i = 0; i != 16; ++i)
1892 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1893 return false;
1894 } else if (ShuffleKind == 1) {
1895 unsigned j = IsLE ? 0 : 1;
1896 for (unsigned i = 0; i != 8; ++i)
1897 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1898 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1899 return false;
1900 }
1901 return true;
1902}
1903
1904/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1905/// VPKUWUM instruction.
1906/// The ShuffleKind distinguishes between big-endian operations with
1907/// two different inputs (0), either-endian operations with two identical
1908/// inputs (1), and little-endian operations with two different inputs (2).
1909/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1911 SelectionDAG &DAG) {
1912 bool IsLE = DAG.getDataLayout().isLittleEndian();
1913 if (ShuffleKind == 0) {
1914 if (IsLE)
1915 return false;
1916 for (unsigned i = 0; i != 16; i += 2)
1917 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1918 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1919 return false;
1920 } else if (ShuffleKind == 2) {
1921 if (!IsLE)
1922 return false;
1923 for (unsigned i = 0; i != 16; i += 2)
1924 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1925 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1926 return false;
1927 } else if (ShuffleKind == 1) {
1928 unsigned j = IsLE ? 0 : 2;
1929 for (unsigned i = 0; i != 8; i += 2)
1930 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1931 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1932 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1933 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1934 return false;
1935 }
1936 return true;
1937}
1938
1939/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1940/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1941/// current subtarget.
1942///
1943/// The ShuffleKind distinguishes between big-endian operations with
1944/// two different inputs (0), either-endian operations with two identical
1945/// inputs (1), and little-endian operations with two different inputs (2).
1946/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1948 SelectionDAG &DAG) {
1949 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>();
1950 if (!Subtarget.hasP8Vector())
1951 return false;
1952
1953 bool IsLE = DAG.getDataLayout().isLittleEndian();
1954 if (ShuffleKind == 0) {
1955 if (IsLE)
1956 return false;
1957 for (unsigned i = 0; i != 16; i += 4)
1958 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1959 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1960 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1961 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1962 return false;
1963 } else if (ShuffleKind == 2) {
1964 if (!IsLE)
1965 return false;
1966 for (unsigned i = 0; i != 16; i += 4)
1967 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1968 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1969 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1970 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1971 return false;
1972 } else if (ShuffleKind == 1) {
1973 unsigned j = IsLE ? 0 : 4;
1974 for (unsigned i = 0; i != 8; i += 4)
1975 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1976 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1977 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1978 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1979 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1980 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1981 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1982 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1983 return false;
1984 }
1985 return true;
1986}
1987
1988/// isVMerge - Common function, used to match vmrg* shuffles.
1989///
1990static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1991 unsigned LHSStart, unsigned RHSStart) {
1992 if (N->getValueType(0) != MVT::v16i8)
1993 return false;
1994 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1995 "Unsupported merge size!");
1996
1997 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1998 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1999 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
2000 LHSStart+j+i*UnitSize) ||
2001 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
2002 RHSStart+j+i*UnitSize))
2003 return false;
2004 }
2005 return true;
2006}
2007
2008/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
2009/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
2010/// The ShuffleKind distinguishes between big-endian merges with two
2011/// different inputs (0), either-endian merges with two identical inputs (1),
2012/// and little-endian merges with two different inputs (2). For the latter,
2013/// the input operands are swapped (see PPCInstrAltivec.td).
2015 unsigned ShuffleKind, SelectionDAG &DAG) {
2016 if (DAG.getDataLayout().isLittleEndian()) {
2017 if (ShuffleKind == 1) // unary
2018 return isVMerge(N, UnitSize, 0, 0);
2019 else if (ShuffleKind == 2) // swapped
2020 return isVMerge(N, UnitSize, 0, 16);
2021 else
2022 return false;
2023 } else {
2024 if (ShuffleKind == 1) // unary
2025 return isVMerge(N, UnitSize, 8, 8);
2026 else if (ShuffleKind == 0) // normal
2027 return isVMerge(N, UnitSize, 8, 24);
2028 else
2029 return false;
2030 }
2031}
2032
2033/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
2034/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
2035/// The ShuffleKind distinguishes between big-endian merges with two
2036/// different inputs (0), either-endian merges with two identical inputs (1),
2037/// and little-endian merges with two different inputs (2). For the latter,
2038/// the input operands are swapped (see PPCInstrAltivec.td).
2040 unsigned ShuffleKind, SelectionDAG &DAG) {
2041 if (DAG.getDataLayout().isLittleEndian()) {
2042 if (ShuffleKind == 1) // unary
2043 return isVMerge(N, UnitSize, 8, 8);
2044 else if (ShuffleKind == 2) // swapped
2045 return isVMerge(N, UnitSize, 8, 24);
2046 else
2047 return false;
2048 } else {
2049 if (ShuffleKind == 1) // unary
2050 return isVMerge(N, UnitSize, 0, 0);
2051 else if (ShuffleKind == 0) // normal
2052 return isVMerge(N, UnitSize, 0, 16);
2053 else
2054 return false;
2055 }
2056}
2057
2058/**
2059 * Common function used to match vmrgew and vmrgow shuffles
2060 *
2061 * The indexOffset determines whether to look for even or odd words in
2062 * the shuffle mask. This is based on the of the endianness of the target
2063 * machine.
2064 * - Little Endian:
2065 * - Use offset of 0 to check for odd elements
2066 * - Use offset of 4 to check for even elements
2067 * - Big Endian:
2068 * - Use offset of 0 to check for even elements
2069 * - Use offset of 4 to check for odd elements
2070 * A detailed description of the vector element ordering for little endian and
2071 * big endian can be found at
2072 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
2073 * Targeting your applications - what little endian and big endian IBM XL C/C++
2074 * compiler differences mean to you
2075 *
2076 * The mask to the shuffle vector instruction specifies the indices of the
2077 * elements from the two input vectors to place in the result. The elements are
2078 * numbered in array-access order, starting with the first vector. These vectors
2079 * are always of type v16i8, thus each vector will contain 16 elements of size
2080 * 8. More info on the shuffle vector can be found in the
2081 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
2082 * Language Reference.
2083 *
2084 * The RHSStartValue indicates whether the same input vectors are used (unary)
2085 * or two different input vectors are used, based on the following:
2086 * - If the instruction uses the same vector for both inputs, the range of the
2087 * indices will be 0 to 15. In this case, the RHSStart value passed should
2088 * be 0.
2089 * - If the instruction has two different vectors then the range of the
2090 * indices will be 0 to 31. In this case, the RHSStart value passed should
2091 * be 16 (indices 0-15 specify elements in the first vector while indices 16
2092 * to 31 specify elements in the second vector).
2093 *
2094 * \param[in] N The shuffle vector SD Node to analyze
2095 * \param[in] IndexOffset Specifies whether to look for even or odd elements
2096 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2097 * vector to the shuffle_vector instruction
2098 * \return true iff this shuffle vector represents an even or odd word merge
2099 */
2100static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2101 unsigned RHSStartValue) {
2102 if (N->getValueType(0) != MVT::v16i8)
2103 return false;
2104
2105 for (unsigned i = 0; i < 2; ++i)
2106 for (unsigned j = 0; j < 4; ++j)
2107 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2108 i*RHSStartValue+j+IndexOffset) ||
2109 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2110 i*RHSStartValue+j+IndexOffset+8))
2111 return false;
2112 return true;
2113}
2114
2115/**
2116 * Determine if the specified shuffle mask is suitable for the vmrgew or
2117 * vmrgow instructions.
2118 *
2119 * \param[in] N The shuffle vector SD Node to analyze
2120 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2121 * \param[in] ShuffleKind Identify the type of merge:
2122 * - 0 = big-endian merge with two different inputs;
2123 * - 1 = either-endian merge with two identical inputs;
2124 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2125 * little-endian merges).
2126 * \param[in] DAG The current SelectionDAG
2127 * \return true iff this shuffle mask
2128 */
2130 unsigned ShuffleKind, SelectionDAG &DAG) {
2131 if (DAG.getDataLayout().isLittleEndian()) {
2132 unsigned indexOffset = CheckEven ? 4 : 0;
2133 if (ShuffleKind == 1) // Unary
2134 return isVMerge(N, indexOffset, 0);
2135 else if (ShuffleKind == 2) // swapped
2136 return isVMerge(N, indexOffset, 16);
2137 else
2138 return false;
2139 }
2140 else {
2141 unsigned indexOffset = CheckEven ? 0 : 4;
2142 if (ShuffleKind == 1) // Unary
2143 return isVMerge(N, indexOffset, 0);
2144 else if (ShuffleKind == 0) // Normal
2145 return isVMerge(N, indexOffset, 16);
2146 else
2147 return false;
2148 }
2149 return false;
2150}
2151
2152/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2153/// amount, otherwise return -1.
2154/// The ShuffleKind distinguishes between big-endian operations with two
2155/// different inputs (0), either-endian operations with two identical inputs
2156/// (1), and little-endian operations with two different inputs (2). For the
2157/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2158int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2159 SelectionDAG &DAG) {
2160 if (N->getValueType(0) != MVT::v16i8)
2161 return -1;
2162
2163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2164
2165 // Find the first non-undef value in the shuffle mask.
2166 unsigned i;
2167 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2168 /*search*/;
2169
2170 if (i == 16) return -1; // all undef.
2171
2172 // Otherwise, check to see if the rest of the elements are consecutively
2173 // numbered from this value.
2174 unsigned ShiftAmt = SVOp->getMaskElt(i);
2175 if (ShiftAmt < i) return -1;
2176
2177 ShiftAmt -= i;
2178 bool isLE = DAG.getDataLayout().isLittleEndian();
2179
2180 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2181 // Check the rest of the elements to see if they are consecutive.
2182 for (++i; i != 16; ++i)
2183 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2184 return -1;
2185 } else if (ShuffleKind == 1) {
2186 // Check the rest of the elements to see if they are consecutive.
2187 for (++i; i != 16; ++i)
2188 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2189 return -1;
2190 } else
2191 return -1;
2192
2193 if (isLE)
2194 ShiftAmt = 16 - ShiftAmt;
2195
2196 return ShiftAmt;
2197}
2198
2199/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2200/// specifies a splat of a single element that is suitable for input to
2201/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2203 EVT VT = N->getValueType(0);
2204 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2205 return EltSize == 8 && N->getMaskElt(0) == N->getMaskElt(1);
2206
2207 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) &&
2208 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes");
2209
2210 // The consecutive indices need to specify an element, not part of two
2211 // different elements. So abandon ship early if this isn't the case.
2212 if (N->getMaskElt(0) % EltSize != 0)
2213 return false;
2214
2215 // This is a splat operation if each element of the permute is the same, and
2216 // if the value doesn't reference the second vector.
2217 unsigned ElementBase = N->getMaskElt(0);
2218
2219 // FIXME: Handle UNDEF elements too!
2220 if (ElementBase >= 16)
2221 return false;
2222
2223 // Check that the indices are consecutive, in the case of a multi-byte element
2224 // splatted with a v16i8 mask.
2225 for (unsigned i = 1; i != EltSize; ++i)
2226 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2227 return false;
2228
2229 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2230 if (N->getMaskElt(i) < 0) continue;
2231 for (unsigned j = 0; j != EltSize; ++j)
2232 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2233 return false;
2234 }
2235 return true;
2236}
2237
2238/// Check that the mask is shuffling N byte elements. Within each N byte
2239/// element of the mask, the indices could be either in increasing or
2240/// decreasing order as long as they are consecutive.
2241/// \param[in] N the shuffle vector SD Node to analyze
2242/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2243/// Word/DoubleWord/QuadWord).
2244/// \param[in] StepLen the delta indices number among the N byte element, if
2245/// the mask is in increasing/decreasing order then it is 1/-1.
2246/// \return true iff the mask is shuffling N byte elements.
2247static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2248 int StepLen) {
2249 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
2250 "Unexpected element width.");
2251 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
2252
2253 unsigned NumOfElem = 16 / Width;
2254 unsigned MaskVal[16]; // Width is never greater than 16
2255 for (unsigned i = 0; i < NumOfElem; ++i) {
2256 MaskVal[0] = N->getMaskElt(i * Width);
2257 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2258 return false;
2259 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2260 return false;
2261 }
2262
2263 for (unsigned int j = 1; j < Width; ++j) {
2264 MaskVal[j] = N->getMaskElt(i * Width + j);
2265 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2266 return false;
2267 }
2268 }
2269 }
2270
2271 return true;
2272}
2273
2274bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2275 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2276 if (!isNByteElemShuffleMask(N, 4, 1))
2277 return false;
2278
2279 // Now we look at mask elements 0,4,8,12
2280 unsigned M0 = N->getMaskElt(0) / 4;
2281 unsigned M1 = N->getMaskElt(4) / 4;
2282 unsigned M2 = N->getMaskElt(8) / 4;
2283 unsigned M3 = N->getMaskElt(12) / 4;
2284 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2285 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2286
2287 // Below, let H and L be arbitrary elements of the shuffle mask
2288 // where H is in the range [4,7] and L is in the range [0,3].
2289 // H, 1, 2, 3 or L, 5, 6, 7
2290 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2291 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2292 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2293 InsertAtByte = IsLE ? 12 : 0;
2294 Swap = M0 < 4;
2295 return true;
2296 }
2297 // 0, H, 2, 3 or 4, L, 6, 7
2298 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2299 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2300 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2301 InsertAtByte = IsLE ? 8 : 4;
2302 Swap = M1 < 4;
2303 return true;
2304 }
2305 // 0, 1, H, 3 or 4, 5, L, 7
2306 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2307 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2308 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2309 InsertAtByte = IsLE ? 4 : 8;
2310 Swap = M2 < 4;
2311 return true;
2312 }
2313 // 0, 1, 2, H or 4, 5, 6, L
2314 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2315 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2316 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2317 InsertAtByte = IsLE ? 0 : 12;
2318 Swap = M3 < 4;
2319 return true;
2320 }
2321
2322 // If both vector operands for the shuffle are the same vector, the mask will
2323 // contain only elements from the first one and the second one will be undef.
2324 if (N->getOperand(1).isUndef()) {
2325 ShiftElts = 0;
2326 Swap = true;
2327 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2328 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2329 InsertAtByte = IsLE ? 12 : 0;
2330 return true;
2331 }
2332 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2333 InsertAtByte = IsLE ? 8 : 4;
2334 return true;
2335 }
2336 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2337 InsertAtByte = IsLE ? 4 : 8;
2338 return true;
2339 }
2340 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2341 InsertAtByte = IsLE ? 0 : 12;
2342 return true;
2343 }
2344 }
2345
2346 return false;
2347}
2348
2350 bool &Swap, bool IsLE) {
2351 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2352 // Ensure each byte index of the word is consecutive.
2353 if (!isNByteElemShuffleMask(N, 4, 1))
2354 return false;
2355
2356 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2357 unsigned M0 = N->getMaskElt(0) / 4;
2358 unsigned M1 = N->getMaskElt(4) / 4;
2359 unsigned M2 = N->getMaskElt(8) / 4;
2360 unsigned M3 = N->getMaskElt(12) / 4;
2361
2362 // If both vector operands for the shuffle are the same vector, the mask will
2363 // contain only elements from the first one and the second one will be undef.
2364 if (N->getOperand(1).isUndef()) {
2365 assert(M0 < 4 && "Indexing into an undef vector?");
2366 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2367 return false;
2368
2369 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2370 Swap = false;
2371 return true;
2372 }
2373
2374 // Ensure each word index of the ShuffleVector Mask is consecutive.
2375 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2376 return false;
2377
2378 if (IsLE) {
2379 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2380 // Input vectors don't need to be swapped if the leading element
2381 // of the result is one of the 3 left elements of the second vector
2382 // (or if there is no shift to be done at all).
2383 Swap = false;
2384 ShiftElts = (8 - M0) % 8;
2385 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2386 // Input vectors need to be swapped if the leading element
2387 // of the result is one of the 3 left elements of the first vector
2388 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2389 Swap = true;
2390 ShiftElts = (4 - M0) % 4;
2391 }
2392
2393 return true;
2394 } else { // BE
2395 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
2396 // Input vectors don't need to be swapped if the leading element
2397 // of the result is one of the 4 elements of the first vector.
2398 Swap = false;
2399 ShiftElts = M0;
2400 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
2401 // Input vectors need to be swapped if the leading element
2402 // of the result is one of the 4 elements of the right vector.
2403 Swap = true;
2404 ShiftElts = M0 - 4;
2405 }
2406
2407 return true;
2408 }
2409}
2410
2412 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2413
2414 if (!isNByteElemShuffleMask(N, Width, -1))
2415 return false;
2416
2417 for (int i = 0; i < 16; i += Width)
2418 if (N->getMaskElt(i) != i + Width - 1)
2419 return false;
2420
2421 return true;
2422}
2423
2425 return isXXBRShuffleMaskHelper(N, 2);
2426}
2427
2429 return isXXBRShuffleMaskHelper(N, 4);
2430}
2431
2433 return isXXBRShuffleMaskHelper(N, 8);
2434}
2435
2437 return isXXBRShuffleMaskHelper(N, 16);
2438}
2439
2440/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2441/// if the inputs to the instruction should be swapped and set \p DM to the
2442/// value for the immediate.
2443/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2444/// AND element 0 of the result comes from the first input (LE) or second input
2445/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2446/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2447/// mask.
2449 bool &Swap, bool IsLE) {
2450 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2451
2452 // Ensure each byte index of the double word is consecutive.
2453 if (!isNByteElemShuffleMask(N, 8, 1))
2454 return false;
2455
2456 unsigned M0 = N->getMaskElt(0) / 8;
2457 unsigned M1 = N->getMaskElt(8) / 8;
2458 assert(((M0 | M1) < 4) && "A mask element out of bounds?");
2459
2460 // If both vector operands for the shuffle are the same vector, the mask will
2461 // contain only elements from the first one and the second one will be undef.
2462 if (N->getOperand(1).isUndef()) {
2463 if ((M0 | M1) < 2) {
2464 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2465 Swap = false;
2466 return true;
2467 } else
2468 return false;
2469 }
2470
2471 if (IsLE) {
2472 if (M0 > 1 && M1 < 2) {
2473 Swap = false;
2474 } else if (M0 < 2 && M1 > 1) {
2475 M0 = (M0 + 2) % 4;
2476 M1 = (M1 + 2) % 4;
2477 Swap = true;
2478 } else
2479 return false;
2480
2481 // Note: if control flow comes here that means Swap is already set above
2482 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2483 return true;
2484 } else { // BE
2485 if (M0 < 2 && M1 > 1) {
2486 Swap = false;
2487 } else if (M0 > 1 && M1 < 2) {
2488 M0 = (M0 + 2) % 4;
2489 M1 = (M1 + 2) % 4;
2490 Swap = true;
2491 } else
2492 return false;
2493
2494 // Note: if control flow comes here that means Swap is already set above
2495 DM = (M0 << 1) + (M1 & 1);
2496 return true;
2497 }
2498}
2499
2500
2501/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2502/// appropriate for PPC mnemonics (which have a big endian bias - namely
2503/// elements are counted from the left of the vector register).
2504unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2505 SelectionDAG &DAG) {
2506 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2507 assert(isSplatShuffleMask(SVOp, EltSize));
2508 EVT VT = SVOp->getValueType(0);
2509
2510 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2511 return DAG.getDataLayout().isLittleEndian() ? 1 - SVOp->getMaskElt(0)
2512 : SVOp->getMaskElt(0);
2513
2514 if (DAG.getDataLayout().isLittleEndian())
2515 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2516 else
2517 return SVOp->getMaskElt(0) / EltSize;
2518}
2519
2520/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2521/// by using a vspltis[bhw] instruction of the specified element size, return
2522/// the constant being splatted. The ByteSize field indicates the number of
2523/// bytes of each element [124] -> [bhw].
2525 SDValue OpVal;
2526
2527 // If ByteSize of the splat is bigger than the element size of the
2528 // build_vector, then we have a case where we are checking for a splat where
2529 // multiple elements of the buildvector are folded together into a single
2530 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2531 unsigned EltSize = 16/N->getNumOperands();
2532 if (EltSize < ByteSize) {
2533 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2534 SDValue UniquedVals[4];
2535 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
2536
2537 // See if all of the elements in the buildvector agree across.
2538 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2539 if (N->getOperand(i).isUndef()) continue;
2540 // If the element isn't a constant, bail fully out.
2541 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2542
2543 if (!UniquedVals[i&(Multiple-1)].getNode())
2544 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2545 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2546 return SDValue(); // no match.
2547 }
2548
2549 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2550 // either constant or undef values that are identical for each chunk. See
2551 // if these chunks can form into a larger vspltis*.
2552
2553 // Check to see if all of the leading entries are either 0 or -1. If
2554 // neither, then this won't fit into the immediate field.
2555 bool LeadingZero = true;
2556 bool LeadingOnes = true;
2557 for (unsigned i = 0; i != Multiple-1; ++i) {
2558 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2559
2560 LeadingZero &= isNullConstant(UniquedVals[i]);
2561 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2562 }
2563 // Finally, check the least significant entry.
2564 if (LeadingZero) {
2565 if (!UniquedVals[Multiple-1].getNode())
2566 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2567 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2568 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2569 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2570 }
2571 if (LeadingOnes) {
2572 if (!UniquedVals[Multiple-1].getNode())
2573 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2574 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2575 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2576 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2577 }
2578
2579 return SDValue();
2580 }
2581
2582 // Check to see if this buildvec has a single non-undef value in its elements.
2583 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2584 if (N->getOperand(i).isUndef()) continue;
2585 if (!OpVal.getNode())
2586 OpVal = N->getOperand(i);
2587 else if (OpVal != N->getOperand(i))
2588 return SDValue();
2589 }
2590
2591 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2592
2593 unsigned ValSizeInBytes = EltSize;
2594 uint64_t Value = 0;
2595 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2596 Value = CN->getZExtValue();
2597 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2598 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
2599 Value = llvm::bit_cast<uint32_t>(CN->getValueAPF().convertToFloat());
2600 }
2601
2602 // If the splat value is larger than the element value, then we can never do
2603 // this splat. The only case that we could fit the replicated bits into our
2604 // immediate field for would be zero, and we prefer to use vxor for it.
2605 if (ValSizeInBytes < ByteSize) return SDValue();
2606
2607 // If the element value is larger than the splat value, check if it consists
2608 // of a repeated bit pattern of size ByteSize.
2609 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2610 return SDValue();
2611
2612 // Properly sign extend the value.
2613 int MaskVal = SignExtend32(Value, ByteSize * 8);
2614
2615 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2616 if (MaskVal == 0) return SDValue();
2617
2618 // Finally, if this value fits in a 5 bit sext field, return it
2619 if (SignExtend32<5>(MaskVal) == MaskVal)
2620 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2621 return SDValue();
2622}
2623
2624//===----------------------------------------------------------------------===//
2625// Addressing Mode Selection
2626//===----------------------------------------------------------------------===//
2627
2628/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2629/// or 64-bit immediate, and if the value can be accurately represented as a
2630/// sign extension from a 16-bit value. If so, this returns true and the
2631/// immediate.
2632bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2633 if (!isa<ConstantSDNode>(N))
2634 return false;
2635
2636 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2637 if (N->getValueType(0) == MVT::i32)
2638 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2639 else
2640 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2641}
2643 return isIntS16Immediate(Op.getNode(), Imm);
2644}
2645
2646/// Used when computing address flags for selecting loads and stores.
2647/// If we have an OR, check if the LHS and RHS are provably disjoint.
2648/// An OR of two provably disjoint values is equivalent to an ADD.
2649/// Most PPC load/store instructions compute the effective address as a sum,
2650/// so doing this conversion is useful.
2651static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2652 if (N.getOpcode() != ISD::OR)
2653 return false;
2654 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2655 if (!LHSKnown.Zero.getBoolValue())
2656 return false;
2657 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2658 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2659}
2660
2661/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2662/// be represented as an indexed [r+r] operation.
2664 SDValue &Index,
2665 SelectionDAG &DAG) const {
2666 for (SDNode *U : N->uses()) {
2667 if (MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2668 if (Memop->getMemoryVT() == MVT::f64) {
2669 Base = N.getOperand(0);
2670 Index = N.getOperand(1);
2671 return true;
2672 }
2673 }
2674 }
2675 return false;
2676}
2677
2678/// isIntS34Immediate - This method tests if value of node given can be
2679/// accurately represented as a sign extension from a 34-bit value. If so,
2680/// this returns true and the immediate.
2681bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2682 if (!isa<ConstantSDNode>(N))
2683 return false;
2684
2685 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2686 return isInt<34>(Imm);
2687}
2689 return isIntS34Immediate(Op.getNode(), Imm);
2690}
2691
2692/// SelectAddressRegReg - Given the specified addressed, check to see if it
2693/// can be represented as an indexed [r+r] operation. Returns false if it
2694/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2695/// non-zero and N can be represented by a base register plus a signed 16-bit
2696/// displacement, make a more precise judgement by checking (displacement % \p
2697/// EncodingAlignment).
2700 MaybeAlign EncodingAlignment) const {
2701 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2702 // a [pc+imm].
2704 return false;
2705
2706 int16_t Imm = 0;
2707 if (N.getOpcode() == ISD::ADD) {
2708 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2709 // SPE load/store can only handle 8-bit offsets.
2710 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2711 return true;
2712 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2713 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2714 return false; // r+i
2715 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2716 return false; // r+i
2717
2718 Base = N.getOperand(0);
2719 Index = N.getOperand(1);
2720 return true;
2721 } else if (N.getOpcode() == ISD::OR) {
2722 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2723 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2724 return false; // r+i can fold it if we can.
2725
2726 // If this is an or of disjoint bitfields, we can codegen this as an add
2727 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2728 // disjoint.
2729 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2730
2731 if (LHSKnown.Zero.getBoolValue()) {
2732 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2733 // If all of the bits are known zero on the LHS or RHS, the add won't
2734 // carry.
2735 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2736 Base = N.getOperand(0);
2737 Index = N.getOperand(1);
2738 return true;
2739 }
2740 }
2741 }
2742
2743 return false;
2744}
2745
2746// If we happen to be doing an i64 load or store into a stack slot that has
2747// less than a 4-byte alignment, then the frame-index elimination may need to
2748// use an indexed load or store instruction (because the offset may not be a
2749// multiple of 4). The extra register needed to hold the offset comes from the
2750// register scavenger, and it is possible that the scavenger will need to use
2751// an emergency spill slot. As a result, we need to make sure that a spill slot
2752// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2753// stack slot.
2754static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2755 // FIXME: This does not handle the LWA case.
2756 if (VT != MVT::i64)
2757 return;
2758
2759 // NOTE: We'll exclude negative FIs here, which come from argument
2760 // lowering, because there are no known test cases triggering this problem
2761 // using packed structures (or similar). We can remove this exclusion if
2762 // we find such a test case. The reason why this is so test-case driven is
2763 // because this entire 'fixup' is only to prevent crashes (from the
2764 // register scavenger) on not-really-valid inputs. For example, if we have:
2765 // %a = alloca i1
2766 // %b = bitcast i1* %a to i64*
2767 // store i64* a, i64 b
2768 // then the store should really be marked as 'align 1', but is not. If it
2769 // were marked as 'align 1' then the indexed form would have been
2770 // instruction-selected initially, and the problem this 'fixup' is preventing
2771 // won't happen regardless.
2772 if (FrameIdx < 0)
2773 return;
2774
2776 MachineFrameInfo &MFI = MF.getFrameInfo();
2777
2778 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2779 return;
2780
2781 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2782 FuncInfo->setHasNonRISpills();
2783}
2784
2785/// Returns true if the address N can be represented by a base register plus
2786/// a signed 16-bit displacement [r+imm], and if it is not better
2787/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2788/// displacements that are multiples of that value.
2790 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2791 MaybeAlign EncodingAlignment) const {
2792 // FIXME dl should come from parent load or store, not from address
2793 SDLoc dl(N);
2794
2795 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2796 // a [pc+imm].
2798 return false;
2799
2800 // If this can be more profitably realized as r+r, fail.
2801 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2802 return false;
2803
2804 if (N.getOpcode() == ISD::ADD) {
2805 int16_t imm = 0;
2806 if (isIntS16Immediate(N.getOperand(1), imm) &&
2807 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2808 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2809 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2810 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2811 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2812 } else {
2813 Base = N.getOperand(0);
2814 }
2815 return true; // [r+i]
2816 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2817 // Match LOAD (ADD (X, Lo(G))).
2818 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
2819 && "Cannot handle constant offsets yet!");
2820 Disp = N.getOperand(1).getOperand(0); // The global address.
2825 Base = N.getOperand(0);
2826 return true; // [&g+r]
2827 }
2828 } else if (N.getOpcode() == ISD::OR) {
2829 int16_t imm = 0;
2830 if (isIntS16Immediate(N.getOperand(1), imm) &&
2831 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2832 // If this is an or of disjoint bitfields, we can codegen this as an add
2833 // (for better address arithmetic) if the LHS and RHS of the OR are
2834 // provably disjoint.
2835 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2836
2837 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2838 // If all of the bits are known zero on the LHS or RHS, the add won't
2839 // carry.
2840 if (FrameIndexSDNode *FI =
2841 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2842 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2843 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2844 } else {
2845 Base = N.getOperand(0);
2846 }
2847 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2848 return true;
2849 }
2850 }
2851 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2852 // Loading from a constant address.
2853
2854 // If this address fits entirely in a 16-bit sext immediate field, codegen
2855 // this as "d, 0"
2856 int16_t Imm;
2857 if (isIntS16Immediate(CN, Imm) &&
2858 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2859 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2860 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2861 CN->getValueType(0));
2862 return true;
2863 }
2864
2865 // Handle 32-bit sext immediates with LIS + addr mode.
2866 if ((CN->getValueType(0) == MVT::i32 ||
2867 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2868 (!EncodingAlignment ||
2869 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2870 int Addr = (int)CN->getZExtValue();
2871
2872 // Otherwise, break this down into an LIS + disp.
2873 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2874
2875 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2876 MVT::i32);
2877 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2878 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2879 return true;
2880 }
2881 }
2882
2883 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2884 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2885 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2886 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2887 } else
2888 Base = N;
2889 return true; // [r+0]
2890}
2891
2892/// Similar to the 16-bit case but for instructions that take a 34-bit
2893/// displacement field (prefixed loads/stores).
2895 SDValue &Base,
2896 SelectionDAG &DAG) const {
2897 // Only on 64-bit targets.
2898 if (N.getValueType() != MVT::i64)
2899 return false;
2900
2901 SDLoc dl(N);
2902 int64_t Imm = 0;
2903
2904 if (N.getOpcode() == ISD::ADD) {
2905 if (!isIntS34Immediate(N.getOperand(1), Imm))
2906 return false;
2907 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2908 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2909 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2910 else
2911 Base = N.getOperand(0);
2912 return true;
2913 }
2914
2915 if (N.getOpcode() == ISD::OR) {
2916 if (!isIntS34Immediate(N.getOperand(1), Imm))
2917 return false;
2918 // If this is an or of disjoint bitfields, we can codegen this as an add
2919 // (for better address arithmetic) if the LHS and RHS of the OR are
2920 // provably disjoint.
2921 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2922 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2923 return false;
2924 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2925 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2926 else
2927 Base = N.getOperand(0);
2928 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2929 return true;
2930 }
2931
2932 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2933 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2934 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2935 return true;
2936 }
2937
2938 return false;
2939}
2940
2941/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2942/// represented as an indexed [r+r] operation.
2944 SDValue &Index,
2945 SelectionDAG &DAG) const {
2946 // Check to see if we can easily represent this as an [r+r] address. This
2947 // will fail if it thinks that the address is more profitably represented as
2948 // reg+imm, e.g. where imm = 0.
2949 if (SelectAddressRegReg(N, Base, Index, DAG))
2950 return true;
2951
2952 // If the address is the result of an add, we will utilize the fact that the
2953 // address calculation includes an implicit add. However, we can reduce
2954 // register pressure if we do not materialize a constant just for use as the
2955 // index register. We only get rid of the add if it is not an add of a
2956 // value and a 16-bit signed constant and both have a single use.
2957 int16_t imm = 0;
2958 if (N.getOpcode() == ISD::ADD &&
2959 (!isIntS16Immediate(N.getOperand(1), imm) ||
2960 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2961 Base = N.getOperand(0);
2962 Index = N.getOperand(1);
2963 return true;
2964 }
2965
2966 // Otherwise, do it the hard way, using R0 as the base register.
2967 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2968 N.getValueType());
2969 Index = N;
2970 return true;
2971}
2972
2973template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2974 Ty *PCRelCand = dyn_cast<Ty>(N);
2975 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2976}
2977
2978/// Returns true if this address is a PC Relative address.
2979/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2980/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2982 // This is a materialize PC Relative node. Always select this as PC Relative.
2983 Base = N;
2984 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2985 return true;
2986 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2987 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2988 isValidPCRelNode<JumpTableSDNode>(N) ||
2989 isValidPCRelNode<BlockAddressSDNode>(N))
2990 return true;
2991 return false;
2992}
2993
2994/// Returns true if we should use a direct load into vector instruction
2995/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2996static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2997
2998 // If there are any other uses other than scalar to vector, then we should
2999 // keep it as a scalar load -> direct move pattern to prevent multiple
3000 // loads.
3001 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
3002 if (!LD)
3003 return false;
3004
3005 EVT MemVT = LD->getMemoryVT();
3006 if (!MemVT.isSimple())
3007 return false;
3008 switch(MemVT.getSimpleVT().SimpleTy) {
3009 case MVT::i64:
3010 break;
3011 case MVT::i32:
3012 if (!ST.hasP8Vector())
3013 return false;
3014 break;
3015 case MVT::i16:
3016 case MVT::i8:
3017 if (!ST.hasP9Vector())
3018 return false;
3019 break;
3020 default:
3021 return false;
3022 }
3023
3024 SDValue LoadedVal(N, 0);
3025 if (!LoadedVal.hasOneUse())
3026 return false;
3027
3028 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
3029 UI != UE; ++UI)
3030 if (UI.getUse().get().getResNo() == 0 &&
3031 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
3032 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
3033 return false;
3034
3035 return true;
3036}
3037
3038/// getPreIndexedAddressParts - returns true by value, base pointer and
3039/// offset pointer and addressing mode by reference if the node's address
3040/// can be legally represented as pre-indexed load / store address.
3042 SDValue &Offset,
3044 SelectionDAG &DAG) const {
3045 if (DisablePPCPreinc) return false;
3046
3047 bool isLoad = true;
3048 SDValue Ptr;
3049 EVT VT;
3050 Align Alignment;
3051 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3052 Ptr = LD->getBasePtr();
3053 VT = LD->getMemoryVT();
3054 Alignment = LD->getAlign();
3055 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3056 Ptr = ST->getBasePtr();
3057 VT = ST->getMemoryVT();
3058 Alignment = ST->getAlign();
3059 isLoad = false;
3060 } else
3061 return false;
3062
3063 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
3064 // instructions because we can fold these into a more efficient instruction
3065 // instead, (such as LXSD).
3066 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
3067 return false;
3068 }
3069
3070 // PowerPC doesn't have preinc load/store instructions for vectors
3071 if (VT.isVector())
3072 return false;
3073
3074 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
3075 // Common code will reject creating a pre-inc form if the base pointer
3076 // is a frame index, or if N is a store and the base pointer is either
3077 // the same as or a predecessor of the value being stored. Check for
3078 // those situations here, and try with swapped Base/Offset instead.
3079 bool Swap = false;
3080
3081 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
3082 Swap = true;
3083 else if (!isLoad) {
3084 SDValue Val = cast<StoreSDNode>(N)->getValue();
3085 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
3086 Swap = true;
3087 }
3088
3089 if (Swap)
3091
3092 AM = ISD::PRE_INC;
3093 return true;
3094 }
3095
3096 // LDU/STU can only handle immediates that are a multiple of 4.
3097 if (VT != MVT::i64) {
3098 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, std::nullopt))
3099 return false;
3100 } else {
3101 // LDU/STU need an address with at least 4-byte alignment.
3102 if (Alignment < Align(4))
3103 return false;
3104
3105 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3106 return false;
3107 }
3108
3109 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3110 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3111 // sext i32 to i64 when addr mode is r+i.
3112 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3113 LD->getExtensionType() == ISD::SEXTLOAD &&
3114 isa<ConstantSDNode>(Offset))
3115 return false;
3116 }
3117
3118 AM = ISD::PRE_INC;
3119 return true;
3120}
3121
3122//===----------------------------------------------------------------------===//
3123// LowerOperation implementation
3124//===----------------------------------------------------------------------===//
3125
3126/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3127/// and LoOpFlags to the target MO flags.
3128static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3129 unsigned &HiOpFlags, unsigned &LoOpFlags,
3130 const GlobalValue *GV = nullptr) {
3131 HiOpFlags = PPCII::MO_HA;
3132 LoOpFlags = PPCII::MO_LO;
3133
3134 // Don't use the pic base if not in PIC relocation model.
3135 if (IsPIC) {
3136 HiOpFlags |= PPCII::MO_PIC_FLAG;
3137 LoOpFlags |= PPCII::MO_PIC_FLAG;
3138 }
3139}
3140
3141static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3142 SelectionDAG &DAG) {
3143 SDLoc DL(HiPart);
3144 EVT PtrVT = HiPart.getValueType();
3145 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3146
3147 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3148 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3149
3150 // With PIC, the first instruction is actually "GR+hi(&G)".
3151 if (isPIC)
3152 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3153 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3154
3155 // Generate non-pic code that has direct accesses to the constant pool.
3156 // The address of the global is just (hi(&g)+lo(&g)).
3157 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3158}
3159
3161 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3162 FuncInfo->setUsesTOCBasePtr();
3163}
3164
3167}
3168
3169SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3170 SDValue GA) const {
3171 const bool Is64Bit = Subtarget.isPPC64();
3172 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3173 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3174 : Subtarget.isAIXABI()
3175 ? DAG.getRegister(PPC::R2, VT)
3176 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3177 SDValue Ops[] = { GA, Reg };
3178 return DAG.getMemIntrinsicNode(
3179 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3182}
3183
3184SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3185 SelectionDAG &DAG) const {
3186 EVT PtrVT = Op.getValueType();
3187 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3188 const Constant *C = CP->getConstVal();
3189
3190 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3191 // The actual address of the GlobalValue is stored in the TOC.
3192 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3193 if (Subtarget.isUsingPCRelativeCalls()) {
3194 SDLoc DL(CP);
3195 EVT Ty = getPointerTy(DAG.getDataLayout());
3196 SDValue ConstPool = DAG.getTargetConstantPool(
3197 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3198 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3199 }
3200 setUsesTOCBasePtr(DAG);
3201 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3202 return getTOCEntry(DAG, SDLoc(CP), GA);
3203 }
3204
3205 unsigned MOHiFlag, MOLoFlag;
3206 bool IsPIC = isPositionIndependent();
3207 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3208
3209 if (IsPIC && Subtarget.isSVR4ABI()) {
3210 SDValue GA =
3211 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3212 return getTOCEntry(DAG, SDLoc(CP), GA);
3213 }
3214
3215 SDValue CPIHi =
3216 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3217 SDValue CPILo =
3218 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3219 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3220}
3221
3222// For 64-bit PowerPC, prefer the more compact relative encodings.
3223// This trades 32 bits per jump table entry for one or two instructions
3224// on the jump site.
3226 if (isJumpTableRelative())
3228
3230}
3231
3234 return false;
3235 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3236 return true;
3238}
3239
3241 SelectionDAG &DAG) const {
3242 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3244
3245 switch (getTargetMachine().getCodeModel()) {
3246 case CodeModel::Small:
3247 case CodeModel::Medium:
3249 default:
3250 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3252 }
3253}
3254
3255const MCExpr *
3257 unsigned JTI,
3258 MCContext &Ctx) const {
3259 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3261
3262 switch (getTargetMachine().getCodeModel()) {
3263 case CodeModel::Small:
3264 case CodeModel::Medium:
3266 default:
3267 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3268 }
3269}
3270
3271SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3272 EVT PtrVT = Op.getValueType();
3273 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3274
3275 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3276 if (Subtarget.isUsingPCRelativeCalls()) {
3277 SDLoc DL(JT);
3278 EVT Ty = getPointerTy(DAG.getDataLayout());
3279 SDValue GA =
3280 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3281 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3282 return MatAddr;
3283 }
3284
3285 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3286 // The actual address of the GlobalValue is stored in the TOC.
3287 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3288 setUsesTOCBasePtr(DAG);
3289 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3290 return getTOCEntry(DAG, SDLoc(JT), GA);
3291 }
3292
3293 unsigned MOHiFlag, MOLoFlag;
3294 bool IsPIC = isPositionIndependent();
3295 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3296
3297 if (IsPIC && Subtarget.isSVR4ABI()) {
3298 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3300 return getTOCEntry(DAG, SDLoc(GA), GA);
3301 }
3302
3303 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3304 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3305 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3306}
3307
3308SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3309 SelectionDAG &DAG) const {
3310 EVT PtrVT = Op.getValueType();
3311 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3312 const BlockAddress *BA = BASDN->getBlockAddress();
3313
3314 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3315 if (Subtarget.isUsingPCRelativeCalls()) {
3316 SDLoc DL(BASDN);
3317 EVT Ty = getPointerTy(DAG.getDataLayout());
3318 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3320 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3321 return MatAddr;
3322 }
3323
3324 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3325 // The actual BlockAddress is stored in the TOC.
3326 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3327 setUsesTOCBasePtr(DAG);
3328 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3329 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3330 }
3331
3332 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3333 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3334 return getTOCEntry(
3335 DAG, SDLoc(BASDN),
3336 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3337
3338 unsigned MOHiFlag, MOLoFlag;
3339 bool IsPIC = isPositionIndependent();
3340 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3341 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3342 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3343 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3344}
3345
3346SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3347 SelectionDAG &DAG) const {
3348 if (Subtarget.isAIXABI())
3349 return LowerGlobalTLSAddressAIX(Op, DAG);
3350
3351 return LowerGlobalTLSAddressLinux(Op, DAG);
3352}
3353
3354SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3355 SelectionDAG &DAG) const {
3356 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3357
3358 if (DAG.getTarget().useEmulatedTLS())
3359 report_fatal_error("Emulated TLS is not yet supported on AIX");
3360
3361 SDLoc dl(GA);
3362 const GlobalValue *GV = GA->getGlobal();
3363 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3364 bool Is64Bit = Subtarget.isPPC64();
3365 bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
3367 bool IsTLSLocalExecModel = Model == TLSModel::LocalExec;
3368
3369 if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) {
3370 SDValue VariableOffsetTGA =
3371 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TPREL_FLAG);
3372 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3373 SDValue TLSReg;
3374 if (Is64Bit) {
3375 // For local-exec and initial-exec on AIX (64-bit), the sequence generated
3376 // involves a load of the variable offset (from the TOC), followed by an
3377 // add of the loaded variable offset to R13 (the thread pointer).
3378 // This code sequence looks like:
3379 // ld reg1,var[TC](2)
3380 // add reg2, reg1, r13 // r13 contains the thread pointer
3381 TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3382
3383 // With the -maix-small-local-exec-tls option, produce a faster access
3384 // sequence for local-exec TLS variables where the offset from the TLS
3385 // base is encoded as an immediate operand.
3386 //
3387 // We only utilize the faster local-exec access sequence when the TLS
3388 // variable has a size within the policy limit. We treat types that are
3389 // not sized or are empty as being over the policy size limit.
3390 if (HasAIXSmallLocalExecTLS && IsTLSLocalExecModel) {
3391 Type *GVType = GV->getValueType();
3392 if (GVType->isSized() && !GVType->isEmptyTy() &&
3393 GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
3395 return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA, TLSReg);
3396 }
3397 } else {
3398 // For local-exec and initial-exec on AIX (32-bit), the sequence generated
3399 // involves loading the variable offset from the TOC, generating a call to
3400 // .__get_tpointer to get the thread pointer (which will be in R3), and
3401 // adding the two together:
3402 // lwz reg1,var[TC](2)
3403 // bla .__get_tpointer
3404 // add reg2, reg1, r3
3405 TLSReg = DAG.getNode(PPCISD::GET_TPOINTER, dl, PtrVT);
3406
3407 // We do not implement the 32-bit version of the faster access sequence
3408 // for local-exec that is controlled by -maix-small-local-exec-tls.
3409 if (HasAIXSmallLocalExecTLS)
3410 report_fatal_error("The small-local-exec TLS access sequence is "
3411 "currently only supported on AIX (64-bit mode).");
3412 }
3413 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
3414 }
3415
3416 // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
3417 // supported models. If Local- or Initial-exec are not possible or specified,
3418 // all GlobalTLSAddress nodes are lowered using the general-dynamic model.
3419 // We need to generate two TOC entries, one for the variable offset, one for
3420 // the region handle. The global address for the TOC entry of the region
3421 // handle is created with the MO_TLSGDM_FLAG flag and the global address
3422 // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
3423 SDValue VariableOffsetTGA =
3424 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3425 SDValue RegionHandleTGA =
3426 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3427 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3428 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3429 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3430 RegionHandle);
3431}
3432
3433SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3434 SelectionDAG &DAG) const {
3435 // FIXME: TLS addresses currently use medium model code sequences,
3436 // which is the most useful form. Eventually support for small and
3437 // large models could be added if users need it, at the cost of
3438 // additional complexity.
3439 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3440 if (DAG.getTarget().useEmulatedTLS())
3441 return LowerToTLSEmulatedModel(GA, DAG);
3442
3443 SDLoc dl(GA);
3444 const GlobalValue *GV = GA->getGlobal();
3445 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3446 bool is64bit = Subtarget.isPPC64();
3447 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3448 PICLevel::Level picLevel = M->getPICLevel();
3449
3451 TLSModel::Model Model = TM.getTLSModel(GV);
3452
3453 if (Model == TLSModel::LocalExec) {
3454 if (Subtarget.isUsingPCRelativeCalls()) {
3455 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3457 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3458 SDValue MatAddr =
3459 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3460 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3461 }
3462
3463 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3465 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3467 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3468 : DAG.getRegister(PPC::R2, MVT::i32);
3469
3470 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3471 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3472 }
3473
3474 if (Model == TLSModel::InitialExec) {
3475 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3477 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3478 SDValue TGATLS = DAG.getTargetGlobalAddress(
3479 GV, dl, PtrVT, 0,
3481 SDValue TPOffset;
3482 if (IsPCRel) {
3483 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3484 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3486 } else {
3487 SDValue GOTPtr;
3488 if (is64bit) {
3489 setUsesTOCBasePtr(DAG);
3490 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3491 GOTPtr =
3492 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3493 } else {
3494 if (!TM.isPositionIndependent())
3495 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3496 else if (picLevel == PICLevel::SmallPIC)
3497 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3498 else
3499 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3500 }
3501 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3502 }
3503 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3504 }
3505
3506 if (Model == TLSModel::GeneralDynamic) {
3507 if (Subtarget.isUsingPCRelativeCalls()) {
3508 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3510 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3511 }
3512
3513 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3514 SDValue GOTPtr;
3515 if (is64bit) {
3516 setUsesTOCBasePtr(DAG);
3517 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3518 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3519 GOTReg, TGA);
3520 } else {
3521 if (picLevel == PICLevel::SmallPIC)
3522 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3523 else
3524 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3525 }
3526 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3527 GOTPtr, TGA, TGA);
3528 }
3529
3530 if (Model == TLSModel::LocalDynamic) {
3531 if (Subtarget.isUsingPCRelativeCalls()) {
3532 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3534 SDValue MatPCRel =
3535 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3536 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3537 }
3538
3539 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3540 SDValue GOTPtr;
3541 if (is64bit) {
3542 setUsesTOCBasePtr(DAG);
3543 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3544 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3545 GOTReg, TGA);
3546 } else {
3547 if (picLevel == PICLevel::SmallPIC)
3548 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3549 else
3550 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3551 }
3552 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3553 PtrVT, GOTPtr, TGA, TGA);
3554 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3555 PtrVT, TLSAddr, TGA);
3556 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3557 }
3558
3559 llvm_unreachable("Unknown TLS model!");
3560}
3561
3562SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3563 SelectionDAG &DAG) const {
3564 EVT PtrVT = Op.getValueType();
3565 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3566 SDLoc DL(GSDN);
3567 const GlobalValue *GV = GSDN->getGlobal();
3568
3569 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3570 // The actual address of the GlobalValue is stored in the TOC.
3571 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3572 if (Subtarget.isUsingPCRelativeCalls()) {
3573 EVT Ty = getPointerTy(DAG.getDataLayout());
3575 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3578 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3579 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3581 return Load;
3582 } else {
3583 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3585 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3586 }
3587 }
3588 setUsesTOCBasePtr(DAG);
3589 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3590 return getTOCEntry(DAG, DL, GA);
3591 }
3592
3593 unsigned MOHiFlag, MOLoFlag;
3594 bool IsPIC = isPositionIndependent();
3595 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3596
3597 if (IsPIC && Subtarget.isSVR4ABI()) {
3598 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3599 GSDN->getOffset(),
3601 return getTOCEntry(DAG, DL, GA);
3602 }
3603
3604 SDValue GAHi =
3605 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3606 SDValue GALo =
3607 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3608
3609 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3610}
3611
3612SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3613 bool IsStrict = Op->isStrictFPOpcode();
3615 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3616 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3617 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3618 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3619 EVT LHSVT = LHS.getValueType();
3620 SDLoc dl(Op);
3621
3622 // Soften the setcc with libcall if it is fp128.
3623 if (LHSVT == MVT::f128) {
3624 assert(!Subtarget.hasP9Vector() &&
3625 "SETCC for f128 is already legal under Power9!");
3626 softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
3627 Op->getOpcode() == ISD::STRICT_FSETCCS);
3628 if (RHS.getNode())
3629 LHS = DAG.getNode(ISD::SETCC, dl, Op.getValueType(), LHS, RHS,
3630 DAG.getCondCode(CC));
3631 if (IsStrict)
3632 return DAG.getMergeValues({LHS, Chain}, dl);
3633 return LHS;
3634 }
3635
3636 assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!");
3637
3638 if (Op.getValueType() == MVT::v2i64) {
3639 // When the operands themselves are v2i64 values, we need to do something
3640 // special because VSX has no underlying comparison operations for these.
3641 if (LHS.getValueType() == MVT::v2i64) {
3642 // Equality can be handled by casting to the legal type for Altivec
3643 // comparisons, everything else needs to be expanded.
3644 if (CC != ISD::SETEQ && CC != ISD::SETNE)
3645 return SDValue();
3646 SDValue SetCC32 = DAG.getSetCC(
3647 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS),
3648 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC);
3649 int ShuffV[] = {1, 0, 3, 2};
3650 SDValue Shuff =
3651 DAG.getVectorShuffle(MVT::v4i32, dl, SetCC32, SetCC32, ShuffV);
3652 return DAG.getBitcast(MVT::v2i64,
3654 dl, MVT::v4i32, Shuff, SetCC32));
3655 }
3656
3657 // We handle most of these in the usual way.
3658 return Op;
3659 }
3660
3661 // If we're comparing for equality to zero, expose the fact that this is
3662 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3663 // fold the new nodes.
3664 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3665 return V;
3666
3667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
3668 // Leave comparisons against 0 and -1 alone for now, since they're usually
3669 // optimized. FIXME: revisit this when we can custom lower all setcc
3670 // optimizations.
3671 if (C->isAllOnes() || C->isZero())
3672 return SDValue();
3673 }
3674
3675 // If we have an integer seteq/setne, turn it into a compare against zero
3676 // by xor'ing the rhs with the lhs, which is faster than setting a
3677 // condition register, reading it back out, and masking the correct bit. The
3678 // normal approach here uses sub to do this instead of xor. Using xor exposes
3679 // the result to other bit-twiddling opportunities.
3680 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3681 EVT VT = Op.getValueType();</