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9 #ifndef LLVM_LIB_CODEGEN_BRANCHFOLDING_H
10 #define LLVM_LIB_CODEGEN_BRANCHFOLDING_H
22 class MachineBranchProbabilityInfo;
23 class MachineFunction;
24 class MachineLoopInfo;
25 class MachineRegisterInfo;
27 class ProfileSummaryInfo;
28 class TargetInstrInfo;
29 class TargetRegisterInfo;
33 explicit BranchFolder(
bool DefaultEnableTailMerge,
bool CommonHoist,
39 unsigned MinTailLength = 0);
47 bool AfterPlacement =
false);
50 class MergePotentialsElt {
56 : Hash(
h), Block(
b) {}
58 unsigned getHash()
const {
return Hash; }
65 bool operator<(
const MergePotentialsElt &)
const;
68 using MPIterator = std::vector<MergePotentialsElt>::iterator;
70 std::vector<MergePotentialsElt> MergePotentials;
80 : MPIter(mp), TailStartPos(tsp) {}
82 MPIterator getMPIter()
const {
86 MergePotentialsElt &getMergePotentialsElt()
const {
94 unsigned getHash()
const {
95 return getMergePotentialsElt().getHash();
99 return getMergePotentialsElt().getBlock();
102 bool tailIsWholeBlock()
const {
103 return TailStartPos == getBlock()->begin();
107 getMergePotentialsElt().setBlock(
MBB);
114 std::vector<SameTailElt> SameTails;
116 bool AfterBlockPlacement;
117 bool EnableTailMerge;
118 bool EnableHoistCommonCode;
120 unsigned MinCommonTailLength;
135 unsigned MinCommonTailLength);
159 unsigned ComputeSameTails(
unsigned CurHash,
unsigned minCommonTailLength,
172 unsigned maxCommonTailLength,
173 unsigned &commonTailIndex);
177 void mergeCommonTails(
unsigned commonTailIndex);
200 #endif // LLVM_LIB_CODEGEN_BRANCHFOLDING_H
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A set of physical registers with utility functions to track liveness when walking backward/forward th...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
unsigned const TargetRegisterInfo * TRI
LLVM Basic Block Representation.
TargetInstrInfo - Interface to description of machine instruction set.
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
const HexagonInstrInfo * TII
Analysis providing profile information.
bool operator<(int64_t V1, const APSInt &V2)
@ BasicBlock
Various leaf nodes.
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
unsigned const MachineRegisterInfo * MRI
the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin h
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB