LLVM 19.0.0git
CodeGenPassBuilder.h
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1//===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// Interfaces for producing common pass manager configurations.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_PASSES_CODEGENPASSBUILDER_H
15#define LLVM_PASSES_CODEGENPASSBUILDER_H
16
18#include "llvm/ADT/StringRef.h"
53#include "llvm/IR/PassManager.h"
54#include "llvm/IR/Verifier.h"
56#include "llvm/MC/MCAsmInfo.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/Error.h"
74#include <cassert>
75#include <type_traits>
76#include <utility>
77
78namespace llvm {
79
80// FIXME: Dummy target independent passes definitions that have not yet been
81// ported to new pass manager. Once they do, remove these.
82#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) \
83 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
84 template <typename... Ts> PASS_NAME(Ts &&...) {} \
85 PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
86 return PreservedAnalyses::all(); \
87 } \
88 };
89#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \
90 struct PASS_NAME : public MachinePassInfoMixin<PASS_NAME> { \
91 template <typename... Ts> PASS_NAME(Ts &&...) {} \
92 PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
93 return PreservedAnalyses::all(); \
94 } \
95 };
96#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \
97 struct PASS_NAME : public MachinePassInfoMixin<PASS_NAME> { \
98 template <typename... Ts> PASS_NAME(Ts &&...) {} \
99 PreservedAnalyses run(MachineFunction &, \
100 MachineFunctionAnalysisManager &) { \
101 return PreservedAnalyses::all(); \
102 } \
103 };
104#include "llvm/Passes/MachinePassRegistry.def"
105
106/// This class provides access to building LLVM's passes.
107///
108/// Its members provide the baseline state available to passes during their
109/// construction. The \c MachinePassRegistry.def file specifies how to construct
110/// all of the built-in passes, and those may reference these members during
111/// construction.
112template <typename DerivedT> class CodeGenPassBuilder {
113public:
115 const CGPassBuilderOption &Opts,
117 : TM(TM), Opt(Opts), PIC(PIC) {
118 // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
119 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
120
121 // Target should override TM.Options.EnableIPRA in their target-specific
122 // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
123 if (Opt.EnableIPRA)
125
128
131 }
132
134 raw_pwrite_stream *DwoOut,
135 CodeGenFileType FileType) const;
136
138 return PIC;
139 }
140
141protected:
142 template <typename PassT>
143 using is_module_pass_t = decltype(std::declval<PassT &>().run(
144 std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
145
146 template <typename PassT>
147 using is_function_pass_t = decltype(std::declval<PassT &>().run(
148 std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
149
150 template <typename PassT>
151 using is_machine_function_pass_t = decltype(std::declval<PassT &>().run(
152 std::declval<MachineFunction &>(),
153 std::declval<MachineFunctionAnalysisManager &>()));
154
155 // Function object to maintain state while adding codegen IR passes.
156 // TODO: add a Function -> MachineFunction adaptor and merge
157 // AddIRPass/AddMachinePass so we can have a function pipeline that runs both
158 // function passes and machine function passes.
159 class AddIRPass {
160 public:
161 AddIRPass(ModulePassManager &MPM, const DerivedT &PB) : MPM(MPM), PB(PB) {}
163 if (!FPM.isEmpty())
164 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
165 }
166
167 template <typename PassT>
168 void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
171 "Only module pass and function pass are supported.");
172
173 if (!PB.runBeforeAdding(Name))
174 return;
175
176 // Add Function Pass
178 FPM.addPass(std::forward<PassT>(Pass));
179
180 for (auto &C : PB.AfterCallbacks)
181 C(Name);
182 } else {
183 // Add Module Pass
184 if (!FPM.isEmpty()) {
185 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
186 FPM = FunctionPassManager();
187 }
188
189 MPM.addPass(std::forward<PassT>(Pass));
190
191 for (auto &C : PB.AfterCallbacks)
192 C(Name);
193 }
194 }
195
196 private:
199 const DerivedT &PB;
200 };
201
202 // Function object to maintain state while adding codegen machine passes.
204 public:
205 AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
206 : MPM(MPM), PB(PB) {}
208 if (!MFPM.isEmpty())
210 }
211
212 template <typename PassT>
213 void operator()(PassT &&Pass, bool Force = false,
214 StringRef Name = PassT::name()) {
217 "Only module pass and function pass are supported.");
218
219 if (!Force && !PB.runBeforeAdding(Name))
220 return;
221
222 // Add Function Pass
224 MFPM.addPass(std::forward<PassT>(Pass));
225
226 for (auto &C : PB.AfterCallbacks)
227 C(Name);
228 } else {
229 // Add Module Pass
230 if (!MFPM.isEmpty()) {
231 MPM.addPass(
234 }
235
236 MPM.addPass(std::forward<PassT>(Pass));
237
238 for (auto &C : PB.AfterCallbacks)
239 C(Name);
240 }
241 }
242
243 private:
246 const DerivedT &PB;
247 };
248
252
253 template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
255
256 /// Check whether or not GlobalISel should abort on error.
257 /// When this is disabled, GlobalISel will fall back on SDISel instead of
258 /// erroring out.
261 }
262
263 /// Check whether or not a diagnostic should be emitted when GlobalISel
264 /// uses the fallback path. In other words, it will emit a diagnostic
265 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
268 }
269
270 /// addInstSelector - This method should install an instruction selector pass,
271 /// which converts from LLVM code to machine instructions.
273 return make_error<StringError>("addInstSelector is not overridden",
275 }
276
277 /// Target can override this to add GlobalMergePass before all IR passes.
279
280 /// Add passes that optimize instruction level parallelism for out-of-order
281 /// targets. These passes are run while the machine code is still in SSA
282 /// form, so they can use MachineTraceMetrics to control their heuristics.
283 ///
284 /// All passes added here should preserve the MachineDominatorTree,
285 /// MachineLoopInfo, and MachineTraceMetrics analyses.
286 void addILPOpts(AddMachinePass &) const {}
287
288 /// This method may be implemented by targets that want to run passes
289 /// immediately before register allocation.
291
292 /// addPreRewrite - Add passes to the optimized register allocation pipeline
293 /// after register allocation is complete, but before virtual registers are
294 /// rewritten to physical registers.
295 ///
296 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
297 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
298 /// When these passes run, VirtRegMap contains legal physreg assignments for
299 /// all virtual registers.
300 ///
301 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
302 /// be honored. This is also not generally used for the fast variant,
303 /// where the allocation and rewriting are done in one pass.
305
306 /// Add passes to be run immediately after virtual registers are rewritten
307 /// to physical registers.
309
310 /// This method may be implemented by targets that want to run passes after
311 /// register allocation pass pipeline but before prolog-epilog insertion.
313
314 /// This method may be implemented by targets that want to run passes after
315 /// prolog-epilog insertion and before the second instruction scheduling pass.
317
318 /// This pass may be implemented by targets that want to run passes
319 /// immediately before machine code is emitted.
321
322 /// Targets may add passes immediately before machine code is emitted in this
323 /// callback. This is called even later than `addPreEmitPass`.
324 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
325 // position and remove the `2` suffix here as this callback is what
326 // `addPreEmitPass` *should* be but in reality isn't.
328
329 /// {{@ For GlobalISel
330 ///
331
332 /// addPreISel - This method should add any "last minute" LLVM->LLVM
333 /// passes (which are run just before instruction selector).
334 void addPreISel(AddIRPass &) const {
335 llvm_unreachable("addPreISel is not overridden");
336 }
337
338 /// This method should install an IR translator pass, which converts from
339 /// LLVM code to machine instructions with possibly generic opcodes.
341 return make_error<StringError>("addIRTranslator is not overridden",
343 }
344
345 /// This method may be implemented by targets that want to run passes
346 /// immediately before legalization.
348
349 /// This method should install a legalize pass, which converts the instruction
350 /// sequence into one that can be selected by the target.
352 return make_error<StringError>("addLegalizeMachineIR is not overridden",
354 }
355
356 /// This method may be implemented by targets that want to run passes
357 /// immediately before the register bank selection.
359
360 /// This method should install a register bank selector pass, which
361 /// assigns register banks to virtual registers without a register
362 /// class or register banks.
364 return make_error<StringError>("addRegBankSelect is not overridden",
366 }
367
368 /// This method may be implemented by targets that want to run passes
369 /// immediately before the (global) instruction selection.
371
372 /// This method should install a (global) instruction selector pass, which
373 /// converts possibly generic instructions to fully target-specific
374 /// instructions, thereby constraining all generic virtual registers to
375 /// register classes.
377 return make_error<StringError>(
378 "addGlobalInstructionSelect is not overridden",
380 }
381 /// @}}
382
383 /// High level function that adds all passes necessary to go from llvm IR
384 /// representation to the MI representation.
385 /// Adds IR based lowering and target specific optimization passes and finally
386 /// the core instruction selection passes.
387 void addISelPasses(AddIRPass &) const;
388
389 /// Add the actual instruction selection passes. This does not include
390 /// preparation passes on IR.
391 Error addCoreISelPasses(AddMachinePass &) const;
392
393 /// Add the complete, standard set of LLVM CodeGen passes.
394 /// Fully developed targets will not generally override this.
395 Error addMachinePasses(AddMachinePass &) const;
396
397 /// Add passes to lower exception handling for the code generator.
398 void addPassesToHandleExceptions(AddIRPass &) const;
399
400 /// Add common target configurable passes that perform LLVM IR to IR
401 /// transforms following machine independent optimization.
402 void addIRPasses(AddIRPass &) const;
403
404 /// Add pass to prepare the LLVM IR for code generation. This should be done
405 /// before exception handling preparation passes.
406 void addCodeGenPrepare(AddIRPass &) const;
407
408 /// Add common passes that perform LLVM IR to IR transforms in preparation for
409 /// instruction selection.
410 void addISelPrepare(AddIRPass &) const;
411
412 /// Methods with trivial inline returns are convenient points in the common
413 /// codegen pass pipeline where targets may insert passes. Methods with
414 /// out-of-line standard implementations are major CodeGen stages called by
415 /// addMachinePasses. Some targets may override major stages when inserting
416 /// passes is insufficient, but maintaining overriden stages is more work.
417 ///
418
419 /// addMachineSSAOptimization - Add standard passes that optimize machine
420 /// instructions in SSA form.
421 void addMachineSSAOptimization(AddMachinePass &) const;
422
423 /// addFastRegAlloc - Add the minimum set of target-independent passes that
424 /// are required for fast register allocation.
425 Error addFastRegAlloc(AddMachinePass &) const;
426
427 /// addOptimizedRegAlloc - Add passes related to register allocation.
428 /// LLVMTargetMachine provides standard regalloc passes for most targets.
429 void addOptimizedRegAlloc(AddMachinePass &) const;
430
431 /// Add passes that optimize machine instructions after register allocation.
432 void addMachineLateOptimization(AddMachinePass &) const;
433
434 /// addGCPasses - Add late codegen passes that analyze code for garbage
435 /// collection. This should return true if GC info should be printed after
436 /// these passes.
438
439 /// Add standard basic block placement passes.
440 void addBlockPlacement(AddMachinePass &) const;
441
443 std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
445 llvm_unreachable("addAsmPrinter is not overridden");
446 }
447
448 /// Utilities for targets to add passes to the pass manager.
449 ///
450
451 /// createTargetRegisterAllocator - Create the register allocator pass for
452 /// this target at the current optimization level.
453 void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
454
455 /// addMachinePasses helper to create the target-selected or overriden
456 /// regalloc pass.
457 void addRegAllocPass(AddMachinePass &, bool Optimized) const;
458
459 /// Add core register alloator passes which do the actual register assignment
460 /// and rewriting. \returns true if any passes were added.
461 Error addRegAssignmentFast(AddMachinePass &) const;
462 Error addRegAssignmentOptimized(AddMachinePass &) const;
463
464private:
465 DerivedT &derived() { return static_cast<DerivedT &>(*this); }
466 const DerivedT &derived() const {
467 return static_cast<const DerivedT &>(*this);
468 }
469
470 bool runBeforeAdding(StringRef Name) const {
471 bool ShouldAdd = true;
472 for (auto &C : BeforeCallbacks)
473 ShouldAdd &= C(Name);
474 return ShouldAdd;
475 }
476
477 void setStartStopPasses(const TargetPassConfig::StartStopInfo &Info) const;
478
479 Error verifyStartStop(const TargetPassConfig::StartStopInfo &Info) const;
480
481 mutable SmallVector<llvm::unique_function<bool(StringRef)>, 4>
482 BeforeCallbacks;
483 mutable SmallVector<llvm::unique_function<void(StringRef)>, 4> AfterCallbacks;
484
485 /// Helper variable for `-start-before/-start-after/-stop-before/-stop-after`
486 mutable bool Started = true;
487 mutable bool Stopped = true;
488};
489
490template <typename Derived>
493 CodeGenFileType FileType) const {
494 auto StartStopInfo = TargetPassConfig::getStartStopInfo(*PIC);
495 if (!StartStopInfo)
496 return StartStopInfo.takeError();
497 setStartStopPasses(*StartStopInfo);
498
500 bool PrintMIR = !PrintAsm && FileType != CodeGenFileType::Null;
501
502 {
503 AddIRPass addIRPass(MPM, derived());
506 addISelPasses(addIRPass);
507 }
508
509 AddMachinePass addPass(MPM, derived());
510
511 if (PrintMIR)
512 addPass(PrintMIRPreparePass(Out), /*Force=*/true);
513
514 if (auto Err = addCoreISelPasses(addPass))
515 return std::move(Err);
516
517 if (auto Err = derived().addMachinePasses(addPass))
518 return std::move(Err);
519
520 if (PrintAsm) {
521 derived().addAsmPrinter(
522 addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
523 return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
524 });
525 }
526
527 if (PrintMIR)
528 addPass(PrintMIRPass(Out), /*Force=*/true);
529
530 addPass(FreeMachineFunctionPass());
531 return verifyStartStop(*StartStopInfo);
532}
533
534template <typename Derived>
537 if (!Info.StartPass.empty()) {
538 Started = false;
539 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StartAfter,
540 Count = 0u](StringRef ClassName) mutable {
541 if (Count == Info.StartInstanceNum) {
542 if (AfterFlag) {
543 AfterFlag = false;
544 Started = true;
545 }
546 return Started;
547 }
548
549 auto PassName = PIC->getPassNameForClassName(ClassName);
550 if (Info.StartPass == PassName && ++Count == Info.StartInstanceNum)
551 Started = !Info.StartAfter;
552
553 return Started;
554 });
555 }
556
557 if (!Info.StopPass.empty()) {
558 Stopped = false;
559 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StopAfter,
560 Count = 0u](StringRef ClassName) mutable {
561 if (Count == Info.StopInstanceNum) {
562 if (AfterFlag) {
563 AfterFlag = false;
564 Stopped = true;
565 }
566 return !Stopped;
567 }
568
569 auto PassName = PIC->getPassNameForClassName(ClassName);
570 if (Info.StopPass == PassName && ++Count == Info.StopInstanceNum)
571 Stopped = !Info.StopAfter;
572 return !Stopped;
573 });
574 }
575}
576
577template <typename Derived>
578Error CodeGenPassBuilder<Derived>::verifyStartStop(
579 const TargetPassConfig::StartStopInfo &Info) const {
580 if (Started && Stopped)
581 return Error::success();
582
583 if (!Started)
584 return make_error<StringError>(
585 "Can't find start pass \"" +
586 PIC->getPassNameForClassName(Info.StartPass) + "\".",
587 std::make_error_code(std::errc::invalid_argument));
588 if (!Stopped)
589 return make_error<StringError>(
590 "Can't find stop pass \"" +
591 PIC->getPassNameForClassName(Info.StopPass) + "\".",
592 std::make_error_code(std::errc::invalid_argument));
593 return Error::success();
594}
595
596template <typename Derived>
598 derived().addGlobalMergePass(addPass);
599 if (TM.useEmulatedTLS())
600 addPass(LowerEmuTLSPass());
601
603
604 derived().addIRPasses(addPass);
605 derived().addCodeGenPrepare(addPass);
606 addPassesToHandleExceptions(addPass);
607 derived().addISelPrepare(addPass);
608}
609
610/// Add common target configurable passes that perform LLVM IR to IR transforms
611/// following machine independent optimization.
612template <typename Derived>
614 // Before running any passes, run the verifier to determine if the input
615 // coming from the front-end and/or optimizer is valid.
616 if (!Opt.DisableVerify)
617 addPass(VerifierPass());
618
619 // Run loop strength reduction before anything else.
620 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) {
622 /*UseMemorySSA=*/true));
623 // FIXME: use -stop-after so we could remove PrintLSR
624 if (Opt.PrintLSR)
625 addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
626 }
627
628 if (getOptLevel() != CodeGenOptLevel::None) {
629 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
630 // loads and compares. ExpandMemCmpPass then tries to expand those calls
631 // into optimally-sized loads and compares. The transforms are enabled by a
632 // target lowering hook.
633 if (!Opt.DisableMergeICmps)
634 addPass(MergeICmpsPass());
635 addPass(ExpandMemCmpPass(&TM));
636 }
637
638 // Run GC lowering passes for builtin collectors
639 // TODO: add a pass insertion point here
640 addPass(GCLoweringPass());
641 addPass(ShadowStackGCLoweringPass());
643
644 // Make sure that no unreachable blocks are instruction selected.
645 addPass(UnreachableBlockElimPass());
646
647 // Prepare expensive constants for SelectionDAG.
648 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableConstantHoisting)
649 addPass(ConstantHoistingPass());
650
651 // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
652 // operands with calls to the corresponding functions in a vector library.
653 if (getOptLevel() != CodeGenOptLevel::None)
654 addPass(ReplaceWithVeclib());
655
656 if (getOptLevel() != CodeGenOptLevel::None &&
659
660 // Instrument function entry and exit, e.g. with calls to mcount().
661 addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
662
663 // Add scalarization of target's unsupported masked memory intrinsics pass.
664 // the unsupported intrinsic will be replaced with a chain of basic blocks,
665 // that stores/loads element one-by-one if the appropriate mask bit is set.
667
668 // Expand reduction intrinsics into shuffle sequences if the target wants to.
669 addPass(ExpandReductionsPass());
670
671 // Convert conditional moves to conditional jumps when profitable.
672 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize)
673 addPass(SelectOptimizePass(&TM));
674}
675
676/// Turn exception handling constructs into something the code generators can
677/// handle.
678template <typename Derived>
680 AddIRPass &addPass) const {
681 const MCAsmInfo *MCAI = TM.getMCAsmInfo();
682 assert(MCAI && "No MCAsmInfo");
683 switch (MCAI->getExceptionHandlingType()) {
684 case ExceptionHandling::SjLj:
685 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
686 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
687 // catch info can get misplaced when a selector ends up more than one block
688 // removed from the parent invoke(s). This could happen when a landing
689 // pad is shared by multiple invokes and is also a target of a normal
690 // edge from elsewhere.
691 addPass(SjLjEHPreparePass(&TM));
692 [[fallthrough]];
693 case ExceptionHandling::DwarfCFI:
694 case ExceptionHandling::ARM:
695 case ExceptionHandling::AIX:
696 case ExceptionHandling::ZOS:
697 addPass(DwarfEHPreparePass(&TM));
698 break;
699 case ExceptionHandling::WinEH:
700 // We support using both GCC-style and MSVC-style exceptions on Windows, so
701 // add both preparation passes. Each pass will only actually run if it
702 // recognizes the personality function.
703 addPass(WinEHPreparePass());
704 addPass(DwarfEHPreparePass(&TM));
705 break;
706 case ExceptionHandling::Wasm:
707 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
708 // on catchpads and cleanuppads because it does not outline them into
709 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
710 // should remove PHIs there.
711 addPass(WinEHPreparePass(/*DemoteCatchSwitchPHIOnly=*/false));
712 addPass(WasmEHPreparePass());
713 break;
714 case ExceptionHandling::None:
715 addPass(LowerInvokePass());
716
717 // The lower invoke pass may create unreachable code. Remove it.
718 addPass(UnreachableBlockElimPass());
719 break;
720 }
721}
722
723/// Add pass to prepare the LLVM IR for code generation. This should be done
724/// before exception handling preparation passes.
725template <typename Derived>
727 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableCGP)
728 addPass(CodeGenPreparePass(&TM));
729 // TODO: Default ctor'd RewriteSymbolPass is no-op.
730 // addPass(RewriteSymbolPass());
731}
732
733/// Add common passes that perform LLVM IR to IR transforms in preparation for
734/// instruction selection.
735template <typename Derived>
737 derived().addPreISel(addPass);
738
739 addPass(CallBrPreparePass());
740 // Add both the safe stack and the stack protection passes: each of them will
741 // only protect functions that have corresponding attributes.
742 addPass(SafeStackPass(&TM));
743 addPass(StackProtectorPass(&TM));
744
745 if (Opt.PrintISelInput)
746 addPass(PrintFunctionPass(dbgs(),
747 "\n\n*** Final LLVM Code input to ISel ***\n"));
748
749 // All passes which modify the LLVM IR are now complete; run the verifier
750 // to ensure that the IR is valid.
751 if (!Opt.DisableVerify)
752 addPass(VerifierPass());
753}
754
755template <typename Derived>
757 AddMachinePass &addPass) const {
758 // Enable FastISel with -fast-isel, but allow that to be overridden.
759 TM.setO0WantsFastISel(Opt.EnableFastISelOption.value_or(true));
760
761 // Determine an instruction selector.
762 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
763 SelectorType Selector;
764
765 if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
766 Selector = SelectorType::FastISel;
767 else if ((Opt.EnableGlobalISelOption &&
768 *Opt.EnableGlobalISelOption == true) ||
769 (TM.Options.EnableGlobalISel &&
771 *Opt.EnableGlobalISelOption == false)))
772 Selector = SelectorType::GlobalISel;
773 else if (TM.getOptLevel() == CodeGenOptLevel::None && TM.getO0WantsFastISel())
774 Selector = SelectorType::FastISel;
775 else
776 Selector = SelectorType::SelectionDAG;
777
778 // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
779 if (Selector == SelectorType::FastISel) {
780 TM.setFastISel(true);
781 TM.setGlobalISel(false);
782 } else if (Selector == SelectorType::GlobalISel) {
783 TM.setFastISel(false);
784 TM.setGlobalISel(true);
785 }
786
787 // Add instruction selector passes.
788 if (Selector == SelectorType::GlobalISel) {
789 if (auto Err = derived().addIRTranslator(addPass))
790 return std::move(Err);
791
792 derived().addPreLegalizeMachineIR(addPass);
793
794 if (auto Err = derived().addLegalizeMachineIR(addPass))
795 return std::move(Err);
796
797 // Before running the register bank selector, ask the target if it
798 // wants to run some passes.
799 derived().addPreRegBankSelect(addPass);
800
801 if (auto Err = derived().addRegBankSelect(addPass))
802 return std::move(Err);
803
804 derived().addPreGlobalInstructionSelect(addPass);
805
806 if (auto Err = derived().addGlobalInstructionSelect(addPass))
807 return std::move(Err);
808
809 // Pass to reset the MachineFunction if the ISel failed.
810 addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
811 isGlobalISelAbortEnabled()));
812
813 // Provide a fallback path when we do not want to abort on
814 // not-yet-supported input.
815 if (!isGlobalISelAbortEnabled())
816 if (auto Err = derived().addInstSelector(addPass))
817 return std::move(Err);
818
819 } else if (auto Err = derived().addInstSelector(addPass))
820 return std::move(Err);
821
822 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
823 // FinalizeISel.
824 addPass(FinalizeISelPass());
825
826 // // Print the instruction selected machine code...
827 // printAndVerify("After Instruction Selection");
828
829 return Error::success();
830}
831
832/// Add the complete set of target-independent postISel code generator passes.
833///
834/// This can be read as the standard order of major LLVM CodeGen stages. Stages
835/// with nontrivial configuration or multiple passes are broken out below in
836/// add%Stage routines.
837///
838/// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the
839/// Target. The addPre/Post methods with empty header implementations allow
840/// injecting target-specific fixups just before or after major stages.
841/// Additionally, targets have the flexibility to change pass order within a
842/// stage by overriding default implementation of add%Stage routines below. Each
843/// technique has maintainability tradeoffs because alternate pass orders are
844/// not well supported. addPre/Post works better if the target pass is easily
845/// tied to a common pass. But if it has subtle dependencies on multiple passes,
846/// the target should override the stage instead.
847template <typename Derived>
849 AddMachinePass &addPass) const {
850 // Add passes that optimize machine instructions in SSA form.
851 if (getOptLevel() != CodeGenOptLevel::None) {
852 derived().addMachineSSAOptimization(addPass);
853 } else {
854 // If the target requests it, assign local variables to stack slots relative
855 // to one another and simplify frame index references where possible.
856 addPass(LocalStackSlotPass());
857 }
858
859 if (TM.Options.EnableIPRA)
860 addPass(RegUsageInfoPropagationPass());
861
862 // Run pre-ra passes.
863 derived().addPreRegAlloc(addPass);
864
865 // Run register allocation and passes that are tightly coupled with it,
866 // including phi elimination and scheduling.
867 if (*Opt.OptimizeRegAlloc) {
868 derived().addOptimizedRegAlloc(addPass);
869 } else {
870 if (auto Err = derived().addFastRegAlloc(addPass))
871 return Err;
872 }
873
874 // Run post-ra passes.
875 derived().addPostRegAlloc(addPass);
876
877 addPass(RemoveRedundantDebugValuesPass());
878
879 // Insert prolog/epilog code. Eliminate abstract frame index references...
880 if (getOptLevel() != CodeGenOptLevel::None) {
881 addPass(PostRAMachineSinkingPass());
882 addPass(ShrinkWrapPass());
883 }
884
885 addPass(PrologEpilogInserterPass());
886
887 /// Add passes that optimize machine instructions after register allocation.
888 if (getOptLevel() != CodeGenOptLevel::None)
889 derived().addMachineLateOptimization(addPass);
890
891 // Expand pseudo instructions before second scheduling pass.
892 addPass(ExpandPostRAPseudosPass());
893
894 // Run pre-sched2 passes.
895 derived().addPreSched2(addPass);
896
898 addPass(ImplicitNullChecksPass());
899
900 // Second pass scheduler.
901 // Let Target optionally insert this pass by itself at some other
902 // point.
903 if (getOptLevel() != CodeGenOptLevel::None &&
904 !TM.targetSchedulesPostRAScheduling()) {
905 if (Opt.MISchedPostRA)
906 addPass(PostMachineSchedulerPass());
907 else
908 addPass(PostRASchedulerPass());
909 }
910
911 // GC
912 derived().addGCPasses(addPass);
913
914 // Basic block placement.
915 if (getOptLevel() != CodeGenOptLevel::None)
916 derived().addBlockPlacement(addPass);
917
918 // Insert before XRay Instrumentation.
919 addPass(FEntryInserterPass());
920
921 addPass(XRayInstrumentationPass());
922 addPass(PatchableFunctionPass());
923
924 derived().addPreEmitPass(addPass);
925
926 if (TM.Options.EnableIPRA)
927 // Collect register usage information and produce a register mask of
928 // clobbered registers, to be used to optimize call sites.
929 addPass(RegUsageInfoCollectorPass());
930
931 addPass(FuncletLayoutPass());
932
933 addPass(StackMapLivenessPass());
934 addPass(LiveDebugValuesPass());
935 addPass(MachineSanitizerBinaryMetadata());
936
937 if (TM.Options.EnableMachineOutliner &&
938 getOptLevel() != CodeGenOptLevel::None &&
939 Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
940 bool RunOnAllFunctions =
941 (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
942 bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
943 if (AddOutliner)
944 addPass(MachineOutlinerPass(RunOnAllFunctions));
945 }
946
947 // Add passes that directly emit MI after all other MI passes.
948 derived().addPreEmitPass2(addPass);
949
950 return Error::success();
951}
952
953/// Add passes that optimize machine instructions in SSA form.
954template <typename Derived>
956 AddMachinePass &addPass) const {
957 // Pre-ra tail duplication.
958 addPass(EarlyTailDuplicatePass());
959
960 // Optimize PHIs before DCE: removing dead PHI cycles may make more
961 // instructions dead.
962 addPass(OptimizePHIsPass());
963
964 // This pass merges large allocas. StackSlotColoring is a different pass
965 // which merges spill slots.
966 addPass(StackColoringPass());
967
968 // If the target requests it, assign local variables to stack slots relative
969 // to one another and simplify frame index references where possible.
970 addPass(LocalStackSlotPass());
971
972 // With optimization, dead code should already be eliminated. However
973 // there is one known exception: lowered code for arguments that are only
974 // used by tail calls, where the tail calls reuse the incoming stack
975 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
977
978 // Allow targets to insert passes that improve instruction level parallelism,
979 // like if-conversion. Such passes will typically need dominator trees and
980 // loop info, just like LICM and CSE below.
981 derived().addILPOpts(addPass);
982
983 addPass(EarlyMachineLICMPass());
984 addPass(MachineCSEPass());
985
986 addPass(MachineSinkingPass());
987
988 addPass(PeepholeOptimizerPass());
989 // Clean-up the dead code that may have been generated by peephole
990 // rewriting.
992}
993
994//===---------------------------------------------------------------------===//
995/// Register Allocation Pass Configuration
996//===---------------------------------------------------------------------===//
997
998/// Instantiate the default register allocator pass for this target for either
999/// the optimized or unoptimized allocation path. This will be added to the pass
1000/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1001/// in the optimized case.
1002///
1003/// A target that uses the standard regalloc pass order for fast or optimized
1004/// allocation may still override this for per-target regalloc
1005/// selection. But -regalloc=... always takes precedence.
1006template <typename Derived>
1008 AddMachinePass &addPass, bool Optimized) const {
1009 if (Optimized)
1010 addPass(RAGreedyPass());
1011 else
1012 addPass(RAFastPass());
1013}
1014
1015/// Find and instantiate the register allocation pass requested by this target
1016/// at the current optimization level. Different register allocators are
1017/// defined as separate passes because they may require different analysis.
1018template <typename Derived>
1020 bool Optimized) const {
1021 // TODO: Parse Opt.RegAlloc to add register allocator.
1022}
1023
1024template <typename Derived>
1026 AddMachinePass &addPass) const {
1027 // TODO: Ensure allocator is default or fast.
1028 addRegAllocPass(addPass, false);
1029 return Error::success();
1030}
1031
1032template <typename Derived>
1034 AddMachinePass &addPass) const {
1035 // Add the selected register allocation pass.
1036 addRegAllocPass(addPass, true);
1037
1038 // Allow targets to change the register assignments before rewriting.
1039 derived().addPreRewrite(addPass);
1040
1041 // Finally rewrite virtual registers.
1042 addPass(VirtRegRewriterPass());
1043 // Perform stack slot coloring and post-ra machine LICM.
1044 //
1045 // FIXME: Re-enable coloring with register when it's capable of adding
1046 // kill markers.
1047 addPass(StackSlotColoringPass());
1048
1049 return Error::success();
1050}
1051
1052/// Add the minimum set of target-independent passes that are required for
1053/// register allocation. No coalescing or scheduling.
1054template <typename Derived>
1056 AddMachinePass &addPass) const {
1057 addPass(PHIEliminationPass());
1058 addPass(TwoAddressInstructionPass());
1059 return derived().addRegAssignmentFast(addPass);
1060}
1061
1062/// Add standard target-independent passes that are tightly coupled with
1063/// optimized register allocation, including coalescing, machine instruction
1064/// scheduling, and register allocation itself.
1065template <typename Derived>
1067 AddMachinePass &addPass) const {
1068 addPass(DetectDeadLanesPass());
1069
1070 addPass(InitUndefPass());
1071
1072 addPass(ProcessImplicitDefsPass());
1073
1074 // Edge splitting is smarter with machine loop info.
1075 addPass(PHIEliminationPass());
1076
1077 // Eventually, we want to run LiveIntervals before PHI elimination.
1078 if (Opt.EarlyLiveIntervals)
1079 addPass(LiveIntervalsPass());
1080
1081 addPass(TwoAddressInstructionPass());
1082 addPass(RegisterCoalescerPass());
1083
1084 // The machine scheduler may accidentally create disconnected components
1085 // when moving subregister definitions around, avoid this by splitting them to
1086 // separate vregs before. Splitting can also improve reg. allocation quality.
1087 addPass(RenameIndependentSubregsPass());
1088
1089 // PreRA instruction scheduling.
1090 addPass(MachineSchedulerPass());
1091
1092 if (derived().addRegAssignmentOptimized(addPass)) {
1093 // Allow targets to expand pseudo instructions depending on the choice of
1094 // registers before MachineCopyPropagation.
1095 derived().addPostRewrite(addPass);
1096
1097 // Copy propagate to forward register uses and try to eliminate COPYs that
1098 // were not coalesced.
1099 addPass(MachineCopyPropagationPass());
1100
1101 // Run post-ra machine LICM to hoist reloads / remats.
1102 //
1103 // FIXME: can this move into MachineLateOptimization?
1104 addPass(MachineLICMPass());
1105 }
1106}
1107
1108//===---------------------------------------------------------------------===//
1109/// Post RegAlloc Pass Configuration
1110//===---------------------------------------------------------------------===//
1111
1112/// Add passes that optimize machine instructions after register allocation.
1113template <typename Derived>
1115 AddMachinePass &addPass) const {
1116 // Branch folding must be run after regalloc and prolog/epilog insertion.
1117 addPass(BranchFolderPass());
1118
1119 // Tail duplication.
1120 // Note that duplicating tail just increases code size and degrades
1121 // performance for targets that require Structured Control Flow.
1122 // In addition it can also make CFG irreducible. Thus we disable it.
1123 if (!TM.requiresStructuredCFG())
1124 addPass(TailDuplicatePass());
1125
1126 // Cleanup of redundant (identical) address/immediate loads.
1127 addPass(MachineLateInstrsCleanupPass());
1128
1129 // Copy propagation.
1130 addPass(MachineCopyPropagationPass());
1131}
1132
1133/// Add standard basic block placement passes.
1134template <typename Derived>
1136 AddMachinePass &addPass) const {
1137 addPass(MachineBlockPlacementPass());
1138 // Run a separate pass to collect block placement statistics.
1140 addPass(MachineBlockPlacementStatsPass());
1141}
1142
1143} // namespace llvm
1144
1145#endif // LLVM_PASSES_CODEGENPASSBUILDER_H
This is the interface for LLVM's primary stateless and local alias analysis.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Defines an IR pass for CodeGen Prepare.
std::string Name
This file defines passes to print out IR in various granularities.
This file contains the declaration of the InterleavedAccessPass class, its corresponding pass name is...
This header provides classes for managing a pipeline of passes over loops in LLVM IR.
The header file for the LowerConstantIntrinsics pass as used by the new pass manager.
if(VerifyEach)
ModulePassManager MPM
const char LLVMTargetMachineRef TM
PassInstrumentationCallbacks PIC
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
This header defines various interfaces for pass management in LLVM.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This is the interface for a metadata-based scoped no-alias analysis.
This file contains the declaration of the SelectOptimizePass class, its corresponding pass name is se...
This file defines the SmallVector class.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
This is the interface for a metadata-based TBAA.
static const char PassName[]
AddIRPass(ModulePassManager &MPM, const DerivedT &PB)
void operator()(PassT &&Pass, StringRef Name=PassT::name())
AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
void operator()(PassT &&Pass, bool Force=false, StringRef Name=PassT::name())
This class provides access to building LLVM's passes.
Error addLegalizeMachineIR(AddMachinePass &) const
This method should install a legalize pass, which converts the instruction sequence into one that can...
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const
void addISelPasses(AddIRPass &) const
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Error addInstSelector(AddMachinePass &) const
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
PassInstrumentationCallbacks * getPassInstrumentationCallbacks() const
void addPreEmitPass(AddMachinePass &) const
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Error addIRTranslator(AddMachinePass &) const
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Error addGlobalInstructionSelect(AddMachinePass &) const
This method should install a (global) instruction selector pass, which converts possibly generic inst...
void addPostRewrite(AddMachinePass &) const
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Error addRegBankSelect(AddMachinePass &) const
This method should install a register bank selector pass, which assigns register banks to virtual reg...
void addPreSched2(AddMachinePass &) const
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
CodeGenPassBuilder(LLVMTargetMachine &TM, const CGPassBuilderOption &Opts, PassInstrumentationCallbacks *PIC)
void addPreLegalizeMachineIR(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before legalization.
Error buildPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const
void addOptimizedRegAlloc(AddMachinePass &) const
addOptimizedRegAlloc - Add passes related to register allocation.
decltype(std::declval< PassT & >().run(std::declval< Function & >(), std::declval< FunctionAnalysisManager & >())) is_function_pass_t
void addGCPasses(AddMachinePass &) const
addGCPasses - Add late codegen passes that analyze code for garbage collection.
void addMachineSSAOptimization(AddMachinePass &) const
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Error addRegAssignmentOptimized(AddMachinePass &) const
Error addCoreISelPasses(AddMachinePass &) const
Add the actual instruction selection passes.
PassInstrumentationCallbacks * PIC
void addPassesToHandleExceptions(AddIRPass &) const
Add passes to lower exception handling for the code generator.
void addPreGlobalInstructionSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the (global) ins...
void addMachineLateOptimization(AddMachinePass &) const
Add passes that optimize machine instructions after register allocation.
void addISelPrepare(AddIRPass &) const
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
void addPostRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addGlobalMergePass(AddIRPass &) const
Target can override this to add GlobalMergePass before all IR passes.
void addCodeGenPrepare(AddIRPass &) const
Add pass to prepare the LLVM IR for code generation.
bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
void addPreISel(AddIRPass &) const
{{@ For GlobalISel
void addPreRegBankSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the register ban...
decltype(std::declval< PassT & >().run(std::declval< Module & >(), std::declval< ModuleAnalysisManager & >())) is_module_pass_t
void addBlockPlacement(AddMachinePass &) const
Add standard basic block placement passes.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
CodeGenOptLevel getOptLevel() const
void addPreEmitPass2(AddMachinePass &) const
Targets may add passes immediately before machine code is emitted in this callback.
std::function< Expected< std::unique_ptr< MCStreamer > >(MCContext &)> CreateMCStreamer
void addIRPasses(AddIRPass &) const
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
decltype(std::declval< PassT & >().run(std::declval< MachineFunction & >(), std::declval< MachineFunctionAnalysisManager & >())) is_machine_function_pass_t
void addRegAllocPass(AddMachinePass &, bool Optimized) const
addMachinePasses helper to create the target-selected or overriden regalloc pass.
void addILPOpts(AddMachinePass &) const
Add passes that optimize instruction level parallelism for out-of-order targets.
Error addRegAssignmentFast(AddMachinePass &) const
Add core register alloator passes which do the actual register assignment and rewriting.
void addPreRewrite(AddMachinePass &) const
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Error addMachinePasses(AddMachinePass &) const
Add the complete, standard set of LLVM CodeGen passes.
void addPreRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before register allocat...
void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const
Utilities for targets to add passes to the pass manager.
Error addFastRegAlloc(AddMachinePass &) const
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
LowerIntrinsics - This pass rewrites calls to the llvm.gcread or llvm.gcwrite intrinsics,...
Definition: GCMetadata.h:195
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Expected< std::unique_ptr< MCStreamer > > createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, MCContext &Ctx)
Performs Loop Strength Reduce Pass.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:787
Context object for machine code objects.
Definition: MCContext.h:76
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
StringRef getPassNameForClassName(StringRef ClassName)
Get the pass name for a given pass class name.
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:273
bool isEmpty() const
Returns if the pass manager contains any passes.
Definition: PassManager.h:296
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
Pass (for the new pass manager) for printing a Function as LLVM's text IR assembly.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetOptions Options
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
static Expected< StartStopInfo > getStartStopInfo(PassInstrumentationCallbacks &PIC)
Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Create a verifier pass.
Definition: Verifier.h:132
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:444
unique_function is a type-erasing functor similar to std::function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PassManager< Function > FunctionPassManager
Convenience typedef for a pass manager over functions.
Definition: PassManager.h:315
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:943
std::error_code inconvertibleErrorCode()
The value returned by this function can be returned from convertToErrorCode for Error values where no...
Definition: Error.cpp:90
PassManager< MachineFunction > MachineFunctionPassManager
Convenience typedef for a pass manager over functions.
typename detail::detector< void, Op, Args... >::value_t is_detected
Detects if a given trait holds for some set of arguments 'Args'.
Definition: STLExtras.h:79
CodeGenFileType
These enums are meant to be passed into addPassesToEmitFile to indicate what type of file to emit,...
Definition: CodeGen.h:83
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
ModuleToMachineFunctionPassAdaptor createModuleToMachineFunctionPassAdaptor(MachineFunctionPassT &&Pass)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1135
std::enable_if_t< is_detected< HasRunOnLoopT, LoopPassT >::value, FunctionToLoopPassAdaptor > createFunctionToLoopPassAdaptor(LoopPassT &&Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool UseBranchProbabilityInfo=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
std::optional< bool > EnableGlobalISelOption
std::optional< bool > EnableIPRA
std::optional< bool > OptimizeRegAlloc
std::optional< bool > EnableFastISelOption
std::optional< GlobalISelAbortMode > EnableGlobalISelAbort
A utility pass template to force an analysis result to be available.
Definition: PassManager.h:969