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FastISel.h
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1 //===- FastISel.h - Definition of the FastISel class ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the FastISel class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
16 
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/DebugLoc.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/InstrTypes.h"
27 #include "llvm/IR/IntrinsicInst.h"
29 #include <algorithm>
30 #include <cstdint>
31 #include <utility>
32 
33 namespace llvm {
34 
35 class AllocaInst;
36 class BasicBlock;
37 class CallInst;
38 class Constant;
39 class ConstantFP;
40 class DataLayout;
41 class FunctionLoweringInfo;
42 class LoadInst;
43 class MachineConstantPool;
44 class MachineFrameInfo;
45 class MachineFunction;
46 class MachineInstr;
47 class MachineMemOperand;
48 class MachineOperand;
49 class MachineRegisterInfo;
50 class MCContext;
51 class MCInstrDesc;
52 class MCSymbol;
53 class TargetInstrInfo;
54 class TargetLibraryInfo;
55 class TargetMachine;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
58 class Type;
59 class User;
60 class Value;
61 
62 /// This is a fast-path instruction selection class that generates poor
63 /// code and doesn't support illegal types or non-trivial lowering, but runs
64 /// quickly.
65 class FastISel {
66 public:
70  Type *RetTy = nullptr;
71  bool RetSExt : 1;
72  bool RetZExt : 1;
73  bool IsVarArg : 1;
74  bool IsInReg : 1;
75  bool DoesNotReturn : 1;
77  bool IsPatchPoint : 1;
78 
79  // IsTailCall Should be modified by implementations of FastLowerCall
80  // that perform tail call conversions.
81  bool IsTailCall = false;
82 
83  unsigned NumFixedArgs = -1;
85  const Value *Callee = nullptr;
86  MCSymbol *Symbol = nullptr;
88  const CallBase *CB = nullptr;
89  MachineInstr *Call = nullptr;
91  unsigned NumResultRegs = 0;
92 
98 
102 
104  const Value *Target, ArgListTy &&ArgsList,
105  const CallBase &Call) {
106  RetTy = ResultTy;
107  Callee = Target;
108 
109  IsInReg = Call.hasRetAttr(Attribute::InReg);
110  DoesNotReturn = Call.doesNotReturn();
111  IsVarArg = FuncTy->isVarArg();
112  IsReturnValueUsed = !Call.use_empty();
113  RetSExt = Call.hasRetAttr(Attribute::SExt);
114  RetZExt = Call.hasRetAttr(Attribute::ZExt);
115 
116  CallConv = Call.getCallingConv();
117  Args = std::move(ArgsList);
118  NumFixedArgs = FuncTy->getNumParams();
119 
120  CB = &Call;
121 
122  return *this;
123  }
124 
126  MCSymbol *Target, ArgListTy &&ArgsList,
127  const CallBase &Call,
128  unsigned FixedArgs = ~0U) {
129  RetTy = ResultTy;
130  Callee = Call.getCalledOperand();
131  Symbol = Target;
132 
133  IsInReg = Call.hasRetAttr(Attribute::InReg);
134  DoesNotReturn = Call.doesNotReturn();
135  IsVarArg = FuncTy->isVarArg();
136  IsReturnValueUsed = !Call.use_empty();
137  RetSExt = Call.hasRetAttr(Attribute::SExt);
138  RetZExt = Call.hasRetAttr(Attribute::ZExt);
139 
140  CallConv = Call.getCallingConv();
141  Args = std::move(ArgsList);
142  NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
143 
144  CB = &Call;
145 
146  return *this;
147  }
148 
150  const Value *Target, ArgListTy &&ArgsList,
151  unsigned FixedArgs = ~0U) {
152  RetTy = ResultTy;
153  Callee = Target;
154  CallConv = CC;
155  Args = std::move(ArgsList);
156  NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
157  return *this;
158  }
159 
161  CallingConv::ID CC, Type *ResultTy,
162  StringRef Target, ArgListTy &&ArgsList,
163  unsigned FixedArgs = ~0U);
164 
166  MCSymbol *Target, ArgListTy &&ArgsList,
167  unsigned FixedArgs = ~0U) {
168  RetTy = ResultTy;
169  Symbol = Target;
170  CallConv = CC;
171  Args = std::move(ArgsList);
172  NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
173  return *this;
174  }
175 
177  IsTailCall = Value;
178  return *this;
179  }
180 
183  return *this;
184  }
185 
186  ArgListTy &getArgs() { return Args; }
187 
188  void clearOuts() {
189  OutVals.clear();
190  OutFlags.clear();
191  OutRegs.clear();
192  }
193 
194  void clearIns() {
195  Ins.clear();
196  InRegs.clear();
197  }
198  };
199 
200 protected:
209  const DataLayout &DL;
215 
216  /// The position of the last instruction for materializing constants
217  /// for use in the current block. It resets to EmitStartPt when it makes sense
218  /// (for example, it's usually profitable to avoid function calls between the
219  /// definition and the use)
221 
222  /// The top most instruction in the current block that is allowed for
223  /// emitting local variables. LastLocalValue resets to EmitStartPt when it
224  /// makes sense (for example, on function calls)
226 
227 public:
228  virtual ~FastISel();
229 
230  /// Return the position of the last instruction emitted for
231  /// materializing constants for use in the current block.
233 
234  /// Update the position of the last instruction emitted for
235  /// materializing constants for use in the current block.
237  EmitStartPt = I;
238  LastLocalValue = I;
239  }
240 
241  /// Set the current block to which generated machine instructions will
242  /// be appended.
243  void startNewBlock();
244 
245  /// Flush the local value map.
246  void finishBasicBlock();
247 
248  /// Return current debug location information.
249  DebugLoc getCurDebugLoc() const { return DbgLoc; }
250 
251  /// Do "fast" instruction selection for function arguments and append
252  /// the machine instructions to the current block. Returns true when
253  /// successful.
254  bool lowerArguments();
255 
256  /// Do "fast" instruction selection for the given LLVM IR instruction
257  /// and append the generated machine instructions to the current block.
258  /// Returns true if selection was successful.
259  bool selectInstruction(const Instruction *I);
260 
261  /// Do "fast" instruction selection for the given LLVM IR operator
262  /// (Instruction or ConstantExpr), and append generated machine instructions
263  /// to the current block. Return true if selection was successful.
264  bool selectOperator(const User *I, unsigned Opcode);
265 
266  /// Create a virtual register and arrange for it to be assigned the
267  /// value for the given LLVM value.
268  Register getRegForValue(const Value *V);
269 
270  /// Look up the value to see if its value is already cached in a
271  /// register. It may be defined by instructions across blocks or defined
272  /// locally.
273  Register lookUpRegForValue(const Value *V);
274 
275  /// This is a wrapper around getRegForValue that also takes care of
276  /// truncating or sign-extending the given getelementptr index value.
277  Register getRegForGEPIndex(const Value *Idx);
278 
279  /// We're checking to see if we can fold \p LI into \p FoldInst. Note
280  /// that we could have a sequence where multiple LLVM IR instructions are
281  /// folded into the same machineinstr. For example we could have:
282  ///
283  /// A: x = load i32 *P
284  /// B: y = icmp A, 42
285  /// C: br y, ...
286  ///
287  /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
288  /// (and any other folded instructions) because it is between A and C.
289  ///
290  /// If we succeed folding, return true.
291  bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
292 
293  /// The specified machine instr operand is a vreg, and that vreg is
294  /// being provided by the specified load instruction. If possible, try to
295  /// fold the load as an operand to the instruction, returning true if
296  /// possible.
297  ///
298  /// This method should be implemented by targets.
299  virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
300  const LoadInst * /*LI*/) {
301  return false;
302  }
303 
304  /// Reset InsertPt to prepare for inserting instructions into the
305  /// current block.
306  void recomputeInsertPt();
307 
308  /// Remove all dead instructions between the I and E.
311 
313 
314  /// Prepare InsertPt to begin inserting instructions into the local
315  /// value area and return the old insert position.
317 
318  /// Reset InsertPt to the given old insert position.
319  void leaveLocalValueArea(SavePoint Old);
320 
321 protected:
323  const TargetLibraryInfo *LibInfo,
324  bool SkipTargetIndependentISel = false);
325 
326  /// This method is called by target-independent code when the normal
327  /// FastISel process fails to select an instruction. This gives targets a
328  /// chance to emit code for anything that doesn't fit into FastISel's
329  /// framework. It returns true if it was successful.
330  virtual bool fastSelectInstruction(const Instruction *I) = 0;
331 
332  /// This method is called by target-independent code to do target-
333  /// specific argument lowering. It returns true if it was successful.
334  virtual bool fastLowerArguments();
335 
336  /// This method is called by target-independent code to do target-
337  /// specific call lowering. It returns true if it was successful.
338  virtual bool fastLowerCall(CallLoweringInfo &CLI);
339 
340  /// This method is called by target-independent code to do target-
341  /// specific intrinsic lowering. It returns true if it was successful.
342  virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II);
343 
344  /// This method is called by target-independent code to request that an
345  /// instruction with the given type and opcode be emitted.
346  virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
347 
348  /// This method is called by target-independent code to request that an
349  /// instruction with the given type, opcode, and register operand be emitted.
350  virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0);
351 
352  /// This method is called by target-independent code to request that an
353  /// instruction with the given type, opcode, and register operands be emitted.
354  virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
355  unsigned Op1);
356 
357  /// This method is called by target-independent code to request that an
358  /// instruction with the given type, opcode, and register and immediate
359  /// operands be emitted.
360  virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
361  uint64_t Imm);
362 
363  /// This method is a wrapper of fastEmit_ri.
364  ///
365  /// It first tries to emit an instruction with an immediate operand using
366  /// fastEmit_ri. If that fails, it materializes the immediate into a register
367  /// and try fastEmit_rr instead.
368  Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm,
369  MVT ImmType);
370 
371  /// This method is called by target-independent code to request that an
372  /// instruction with the given type, opcode, and immediate operand be emitted.
373  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
374 
375  /// This method is called by target-independent code to request that an
376  /// instruction with the given type, opcode, and floating-point immediate
377  /// operand be emitted.
378  virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
379  const ConstantFP *FPImm);
380 
381  /// Emit a MachineInstr with no operands and a result register in the
382  /// given register class.
383  Register fastEmitInst_(unsigned MachineInstOpcode,
384  const TargetRegisterClass *RC);
385 
386  /// Emit a MachineInstr with one register operand and a result register
387  /// in the given register class.
388  Register fastEmitInst_r(unsigned MachineInstOpcode,
389  const TargetRegisterClass *RC, unsigned Op0);
390 
391  /// Emit a MachineInstr with two register operands and a result
392  /// register in the given register class.
393  Register fastEmitInst_rr(unsigned MachineInstOpcode,
394  const TargetRegisterClass *RC, unsigned Op0,
395  unsigned Op1);
396 
397  /// Emit a MachineInstr with three register operands and a result
398  /// register in the given register class.
399  Register fastEmitInst_rrr(unsigned MachineInstOpcode,
400  const TargetRegisterClass *RC, unsigned Op0,
401  unsigned Op1, unsigned Op2);
402 
403  /// Emit a MachineInstr with a register operand, an immediate, and a
404  /// result register in the given register class.
405  Register fastEmitInst_ri(unsigned MachineInstOpcode,
406  const TargetRegisterClass *RC, unsigned Op0,
407  uint64_t Imm);
408 
409  /// Emit a MachineInstr with one register operand and two immediate
410  /// operands.
411  Register fastEmitInst_rii(unsigned MachineInstOpcode,
412  const TargetRegisterClass *RC, unsigned Op0,
413  uint64_t Imm1, uint64_t Imm2);
414 
415  /// Emit a MachineInstr with a floating point immediate, and a result
416  /// register in the given register class.
417  Register fastEmitInst_f(unsigned MachineInstOpcode,
418  const TargetRegisterClass *RC,
419  const ConstantFP *FPImm);
420 
421  /// Emit a MachineInstr with two register operands, an immediate, and a
422  /// result register in the given register class.
423  Register fastEmitInst_rri(unsigned MachineInstOpcode,
424  const TargetRegisterClass *RC, unsigned Op0,
425  unsigned Op1, uint64_t Imm);
426 
427  /// Emit a MachineInstr with a single immediate operand, and a result
428  /// register in the given register class.
429  Register fastEmitInst_i(unsigned MachineInstOpcode,
430  const TargetRegisterClass *RC, uint64_t Imm);
431 
432  /// Emit a MachineInstr for an extract_subreg from a specified index of
433  /// a superregister to a specified type.
434  Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx);
435 
436  /// Emit MachineInstrs to compute the value of Op with all but the
437  /// least significant bit set to zero.
438  Register fastEmitZExtFromI1(MVT VT, unsigned Op0);
439 
440  /// Emit an unconditional branch to the given block, unless it is the
441  /// immediate (fall-through) successor, and update the CFG.
442  void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc);
443 
444  /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
445  /// and adds TrueMBB and FalseMBB to the successor list.
446  void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB,
447  MachineBasicBlock *FalseMBB);
448 
449  /// Update the value map to include the new mapping for this
450  /// instruction, or insert an extra copy to get the result in a previous
451  /// determined register.
452  ///
453  /// NOTE: This is only necessary because we might select a block that uses a
454  /// value before we select the block that defines the value. It might be
455  /// possible to fix this by selecting blocks in reverse postorder.
456  void updateValueMap(const Value *I, Register Reg, unsigned NumRegs = 1);
457 
459 
460  /// Try to constrain Op so that it is usable by argument OpNum of the
461  /// provided MCInstrDesc. If this fails, create a new virtual register in the
462  /// correct class and COPY the value there.
464  unsigned OpNum);
465 
466  /// Emit a constant in a register using target-specific logic, such as
467  /// constant pool loads.
468  virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
469 
470  /// Emit an alloca address in a register using target-specific logic.
471  virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
472 
473  /// Emit the floating-point constant +0.0 in a register using target-
474  /// specific logic.
475  virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
476  return 0;
477  }
478 
479  /// Check if \c Add is an add that can be safely folded into \c GEP.
480  ///
481  /// \c Add can be folded into \c GEP if:
482  /// - \c Add is an add,
483  /// - \c Add's size matches \c GEP's,
484  /// - \c Add is in the same basic block as \c GEP, and
485  /// - \c Add has a constant operand.
486  bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
487 
488  /// Create a machine mem operand from the given instruction.
490 
492 
493  bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
494  bool lowerCallTo(const CallInst *CI, const char *SymName,
495  unsigned NumArgs);
496  bool lowerCallTo(CallLoweringInfo &CLI);
497 
498  bool lowerCall(const CallInst *I);
499  /// Select and emit code for a binary operator instruction, which has
500  /// an opcode which directly corresponds to the given ISD opcode.
501  bool selectBinaryOp(const User *I, unsigned ISDOpcode);
502  bool selectFNeg(const User *I, const Value *In);
503  bool selectGetElementPtr(const User *I);
504  bool selectStackmap(const CallInst *I);
505  bool selectPatchpoint(const CallInst *I);
506  bool selectCall(const User *I);
507  bool selectIntrinsicCall(const IntrinsicInst *II);
508  bool selectBitCast(const User *I);
509  bool selectFreeze(const User *I);
510  bool selectCast(const User *I, unsigned Opcode);
511  bool selectExtractValue(const User *U);
512  bool selectXRayCustomEvent(const CallInst *II);
513  bool selectXRayTypedEvent(const CallInst *II);
514 
515  bool shouldOptForSize(const MachineFunction *MF) const {
516  // TODO: Implement PGSO.
517  return MF->getFunction().hasOptSize();
518  }
519 
520 private:
521  /// Handle PHI nodes in successor blocks.
522  ///
523  /// Emit code to ensure constants are copied into registers when needed.
524  /// Remember the virtual registers that need to be added to the Machine PHI
525  /// nodes as input. We cannot just directly add them, because expansion might
526  /// result in multiple MBB's for one BB. As such, the start of the BB might
527  /// correspond to a different MBB than the end.
528  bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
529 
530  /// Helper for materializeRegForValue to materialize a constant in a
531  /// target-independent way.
532  Register materializeConstant(const Value *V, MVT VT);
533 
534  /// Helper for getRegForVale. This function is called when the value
535  /// isn't already available in a register and must be materialized with new
536  /// instructions.
537  Register materializeRegForValue(const Value *V, MVT VT);
538 
539  /// Clears LocalValueMap and moves the area for the new local variables
540  /// to the beginning of the block. It helps to avoid spilling cached variables
541  /// across heavy instructions like calls.
542  void flushLocalValueMap();
543 
544  /// Removes dead local value instructions after SavedLastLocalvalue.
545  void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
546 
547  /// Insertion point before trying to select the current instruction.
548  MachineBasicBlock::iterator SavedInsertPt;
549 
550  /// Add a stackmap or patchpoint intrinsic call's live variable
551  /// operands to a stackmap or patchpoint machine instruction.
552  bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
553  const CallInst *CI, unsigned StartIdx);
554  bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
555  const Value *Callee, bool ForceRetVoidTy,
556  CallLoweringInfo &CLI);
557 };
558 
559 } // end namespace llvm
560 
561 #endif // LLVM_CODEGEN_FASTISEL_H
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::FastISel::LibInfo
const TargetLibraryInfo * LibInfo
Definition: FastISel.h:213
llvm::objcarc::ARCInstKind::User
@ User
could "use" a pointer
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::FastISel::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: FastISel.h:84
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::FastISel::lowerCallTo
bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs)
Definition: FastISel.cpp:968
llvm::FastISel::selectPatchpoint
bool selectPatchpoint(const CallInst *I)
Definition: FastISel.cpp:766
llvm::FastISel::CallLoweringInfo::OutFlags
SmallVector< ISD::ArgFlagsTy, 16 > OutFlags
Definition: FastISel.h:94
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::FastISel::getRegForValue
Register getRegForValue(const Value *V)
Create a virtual register and arrange for it to be assigned the value for the given LLVM value.
Definition: FastISel.cpp:242
llvm::FastISel::~FastISel
virtual ~FastISel()
llvm::FastISel::fastEmit_f
virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1878
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::FastISel::CallLoweringInfo::CallLoweringInfo
CallLoweringInfo()
Definition: FastISel.h:99
IntrinsicInst.h
llvm::FastISel::selectCast
bool selectCast(const User *I, unsigned Opcode)
Definition: FastISel.cpp:1389
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
StringRef.h
llvm::FastISel::CallLoweringInfo::Callee
const Value * Callee
Definition: FastISel.h:85
llvm::FastISel::updateValueMap
void updateValueMap(const Value *I, Register Reg, unsigned NumRegs=1)
Update the value map to include the new mapping for this instruction, or insert an extra copy to get ...
Definition: FastISel.cpp:366
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultTy, MCSymbol *Target, ArgListTy &&ArgsList, unsigned FixedArgs=~0U)
Definition: FastISel.h:165
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::FastISel::fastEmit_ri_
Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm, MVT ImmType)
This method is a wrapper of fastEmit_ri.
Definition: FastISel.cpp:1892
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::FastISel::fastEmitInst_f
Register fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm)
Emit a MachineInstr with a floating point immediate, and a result register in the given register clas...
Definition: FastISel.cpp:2072
llvm::FastISel::CallLoweringInfo::setIsPatchPoint
CallLoweringInfo & setIsPatchPoint(bool Value=true)
Definition: FastISel.h:181
llvm::FastISel::FastISel
FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, bool SkipTargetIndependentISel=false)
Definition: FastISel.cpp:1841
llvm::FastISel::CallLoweringInfo::ResultReg
Register ResultReg
Definition: FastISel.h:90
llvm::FastISel::CallLoweringInfo::InRegs
SmallVector< Register, 4 > InRegs
Definition: FastISel.h:97
llvm::FastISel::finishBasicBlock
void finishBasicBlock()
Flush the local value map.
Definition: FastISel.cpp:138
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, MCSymbol *Target, ArgListTy &&ArgsList, const CallBase &Call, unsigned FixedArgs=~0U)
Definition: FastISel.h:125
llvm::FastISel::lowerArguments
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
Definition: FastISel.cpp:140
llvm::FastISel::fastEmitZExtFromI1
Register fastEmitZExtFromI1(MVT VT, unsigned Op0)
Emit MachineInstrs to compute the value of Op with all but the least significant bit set to zero.
Definition: FastISel.cpp:2146
llvm::FastISel::selectFreeze
bool selectFreeze(const User *I)
Definition: FastISel.cpp:1468
llvm::FastISel::enterLocalValueArea
SavePoint enterLocalValueArea()
Prepare InsertPt to begin inserting instructions into the local value area and return the old insert ...
Definition: FastISel.cpp:439
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::FastISel::CallLoweringInfo::OutVals
SmallVector< Value *, 16 > OutVals
Definition: FastISel.h:93
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
DenseMap.h
llvm::FastISel::fastEmitInst_rii
Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2)
Emit a MachineInstr with one register operand and two immediate operands.
Definition: FastISel.cpp:2048
llvm::FastISel::fastEmit_rr
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1869
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::FastISel::CallLoweringInfo::RetSExt
bool RetSExt
Definition: FastISel.h:71
llvm::FastISel::getLastLocalValue
MachineInstr * getLastLocalValue()
Return the position of the last instruction emitted for materializing constants for use in the curren...
Definition: FastISel.h:232
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:739
llvm::FastISel::TLI
const TargetLowering & TLI
Definition: FastISel.h:211
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
llvm::FastISel::getRegForGEPIndex
Register getRegForGEPIndex(const Value *Idx)
This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the give...
Definition: FastISel.cpp:387
llvm::FastISel::fastSelectInstruction
virtual bool fastSelectInstruction(const Instruction *I)=0
This method is called by target-independent code when the normal FastISel process fails to select an ...
llvm::FastISel::MFI
MachineFrameInfo & MFI
Definition: FastISel.h:205
llvm::FunctionType::isVarArg
bool isVarArg() const
Definition: DerivedTypes.h:123
llvm::FastISel::CallLoweringInfo::RetZExt
bool RetZExt
Definition: FastISel.h:72
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
MachineValueType.h
TargetLowering.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::FastISel::FuncInfo
FunctionLoweringInfo & FuncInfo
Definition: FastISel.h:202
llvm::FastISel::fastMaterializeConstant
virtual unsigned fastMaterializeConstant(const Constant *C)
Emit a constant in a register using target-specific logic, such as constant pool loads.
Definition: FastISel.h:468
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::FastISel::createResultReg
Register createResultReg(const TargetRegisterClass *RC)
Definition: FastISel.cpp:1927
llvm::User
Definition: User.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FastISel::CallLoweringInfo::clearIns
void clearIns()
Definition: FastISel.h:194
InstrTypes.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
llvm::FastISel::CallLoweringInfo::CB
const CallBase * CB
Definition: FastISel.h:88
llvm::FastISel::LastLocalValue
MachineInstr * LastLocalValue
The position of the last instruction for materializing constants for use in the current block.
Definition: FastISel.h:220
llvm::FastISel::leaveLocalValueArea
void leaveLocalValueArea(SavePoint Old)
Reset InsertPt to the given old insert position.
Definition: FastISel.cpp:445
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::FastISel::selectXRayTypedEvent
bool selectXRayTypedEvent(const CallInst *II)
Definition: FastISel.cpp:923
false
Definition: StackSlotColoring.cpp:142
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::FastISel::fastEmit_
virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode)
This method is called by target-independent code to request that an instruction with the given type a...
Definition: FastISel.cpp:1863
llvm::FastISel::MCP
MachineConstantPool & MCP
Definition: FastISel.h:206
llvm::Instruction
Definition: Instruction.h:45
llvm::FastISel::selectStackmap
bool selectStackmap(const CallInst *I)
Definition: FastISel.cpp:654
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::FastISel::fastEmit_ri
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1883
llvm::FastISel::CallLoweringInfo::IsInReg
bool IsInReg
Definition: FastISel.h:74
llvm::FastISel::CallLoweringInfo::clearOuts
void clearOuts()
Definition: FastISel.h:188
DebugLoc.h
llvm::FastISel::MRI
MachineRegisterInfo & MRI
Definition: FastISel.h:204
llvm::FastISel::CallLoweringInfo::Call
MachineInstr * Call
Definition: FastISel.h:89
llvm::FastISel::createMachineMemOperandFor
MachineMemOperand * createMachineMemOperandFor(const Instruction *I) const
Create a machine mem operand from the given instruction.
Definition: FastISel.cpp:2294
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:710
llvm::FastISel::fastLowerIntrinsicCall
virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II)
This method is called by target-independent code to do target- specific intrinsic lowering.
Definition: FastISel.cpp:1859
llvm::FastISel::fastMaterializeAlloca
virtual unsigned fastMaterializeAlloca(const AllocaInst *C)
Emit an alloca address in a register using target-specific logic.
Definition: FastISel.h:471
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::FastISel::CallLoweringInfo::NumResultRegs
unsigned NumResultRegs
Definition: FastISel.h:91
llvm::FastISel::selectInstruction
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
Definition: FastISel.cpp:1508
llvm::FastISel::DbgLoc
DebugLoc DbgLoc
Definition: FastISel.h:207
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::FastISel::tryToFoldLoadIntoMI
virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)
The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...
Definition: FastISel.h:299
llvm::FastISel::fastLowerCall
virtual bool fastLowerCall(CallLoweringInfo &CLI)
This method is called by target-independent code to do target- specific call lowering.
Definition: FastISel.cpp:1857
llvm::FastISel::fastEmit_i
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1874
llvm::FastISel::fastEmitBranch
void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc)
Emit an unconditional branch to the given block, unless it is the immediate (fall-through) successor,...
Definition: FastISel.cpp:1592
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::FastISel::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: FastISel.h:186
llvm::FastISel::selectIntrinsicCall
bool selectIntrinsicCall(const IntrinsicInst *II)
Definition: FastISel.cpp:1205
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::FastISel::fastEmitInst_rri
Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm)
Emit a MachineInstr with two register operands, an immediate, and a result register in the given regi...
Definition: FastISel.cpp:2091
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::FastISel::CallLoweringInfo::Args
ArgListTy Args
Definition: FastISel.h:87
llvm::FastISel::CallLoweringInfo::IsReturnValueUsed
bool IsReturnValueUsed
Definition: FastISel.h:76
llvm::FastISel::CallLoweringInfo
Definition: FastISel.h:69
TemplateParamKind::Type
@ Type
llvm::FastISel::fastEmit_r
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1865
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:274
llvm::FastISel::fastEmitInst_
Register fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC)
Emit a MachineInstr with no operands and a result register in the given register class.
Definition: FastISel.cpp:1948
llvm::FastISel::fastLowerArguments
virtual bool fastLowerArguments()
This method is called by target-independent code to do target- specific argument lowering.
Definition: FastISel.cpp:1855
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
llvm::FastISel::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: FastISel.h:81
llvm::FastISel::ArgListTy
TargetLoweringBase::ArgListTy ArgListTy
Definition: FastISel.h:68
llvm::FastISel::CallLoweringInfo::NumFixedArgs
unsigned NumFixedArgs
Definition: FastISel.h:83
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::FastISel::selectOperator
bool selectOperator(const User *I, unsigned Opcode)
Do "fast" instruction selection for the given LLVM IR operator (Instruction or ConstantExpr),...
Definition: FastISel.cpp:1713
llvm::FastISel::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: FastISel.h:73
llvm::FastISel::LocalValueMap
DenseMap< const Value *, Register > LocalValueMap
Definition: FastISel.h:201
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::FastISel::canFoldAddIntoGEP
bool canFoldAddIntoGEP(const User *GEP, const Value *Add)
Check if Add is an add that can be safely folded into GEP.
Definition: FastISel.cpp:2277
uint32_t
llvm::FastISel::shouldOptForSize
bool shouldOptForSize(const MachineFunction *MF) const
Definition: FastISel.h:515
llvm::FastISel::CallLoweringInfo::Symbol
MCSymbol * Symbol
Definition: FastISel.h:86
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::FastISel::fastEmitInst_ri
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:2026
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:304
llvm::Function::hasOptSize
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:671
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultTy, const Value *Target, ArgListTy &&ArgsList, unsigned FixedArgs=~0U)
Definition: FastISel.h:149
CallingConv.h
Attributes.h
llvm::FastISel::tryToFoldLoad
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
Definition: FastISel.cpp:2221
llvm::FastISel::getCurDebugLoc
DebugLoc getCurDebugLoc() const
Return current debug location information.
Definition: FastISel.h:249
llvm::FastISel::lowerCall
bool lowerCall(const CallInst *I)
Definition: FastISel.cpp:1118
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::FastISel::selectExtractValue
bool selectExtractValue(const User *U)
Definition: FastISel.cpp:1673
llvm::FastISel::CallLoweringInfo::OutRegs
SmallVector< Register, 16 > OutRegs
Definition: FastISel.h:95
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::FastISel::selectFNeg
bool selectFNeg(const User *I, const Value *In)
Emit an FNeg operation.
Definition: FastISel.cpp:1631
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::FastISel::CallLoweringInfo::RetTy
Type * RetTy
Definition: FastISel.h:70
llvm::FastISel::selectXRayCustomEvent
bool selectXRayCustomEvent(const CallInst *II)
Definition: FastISel.cpp:904
llvm::FastISel::SkipTargetIndependentISel
bool SkipTargetIndependentISel
Definition: FastISel.h:214
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::FastISel::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 4 > Ins
Definition: FastISel.h:96
llvm::FastISel::selectGetElementPtr
bool selectGetElementPtr(const User *I)
Definition: FastISel.cpp:541
llvm::FastISel::setLastLocalValue
void setLastLocalValue(MachineInstr *I)
Update the position of the last instruction emitted for materializing constants for use in the curren...
Definition: FastISel.h:236
SmallVector.h
llvm::FastISel::MF
MachineFunction * MF
Definition: FastISel.h:203
llvm::FastISel::fastEmitInst_rrr
Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2)
Emit a MachineInstr with three register operands and a result register in the given register class.
Definition: FastISel.cpp:2000
llvm::FastISel::removeDeadCode
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
Definition: FastISel.cpp:419
llvm::FastISel::CallLoweringInfo::IsPatchPoint
bool IsPatchPoint
Definition: FastISel.h:77
llvm::FastISel::CallLoweringInfo::setTailCall
CallLoweringInfo & setTailCall(bool Value=true)
Definition: FastISel.h:176
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
DerivedTypes.h
llvm::FastISel::CallLoweringInfo::DoesNotReturn
bool DoesNotReturn
Definition: FastISel.h:75
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::FastISel::TRI
const TargetRegisterInfo & TRI
Definition: FastISel.h:212
llvm::FastISel::selectCall
bool selectCall(const User *I)
Definition: FastISel.cpp:1168
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:62
llvm::FastISel::optimizeCmpPredicate
CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const
Definition: FastISel.cpp:2341
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, const Value *Target, ArgListTy &&ArgsList, const CallBase &Call)
Definition: FastISel.h:103
llvm::FastISel::selectBitCast
bool selectBitCast(const User *I)
Definition: FastISel.cpp:1420
llvm::FastISel::TII
const TargetInstrInfo & TII
Definition: FastISel.h:210
llvm::FastISel::fastEmitInst_extractsubreg
Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx)
Emit a MachineInstr for an extract_subreg from a specified index of a superregister to a specified ty...
Definition: FastISel.cpp:2132
llvm::FastISel::fastMaterializeFloatZero
virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF)
Emit the floating-point constant +0.0 in a register using target- specific logic.
Definition: FastISel.h:475
llvm::FastISel::EmitStartPt
MachineInstr * EmitStartPt
The top most instruction in the current block that is allowed for emitting local variables.
Definition: FastISel.h:225
llvm::FastISel::lookUpRegForValue
Register lookUpRegForValue(const Value *V)
Look up the value to see if its value is already cached in a register.
Definition: FastISel.cpp:355
llvm::FastISel::finishCondBranch
void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB)
Emit an unconditional branch to FalseMBB, obtains the branch weight and adds TrueMBB and FalseMBB to ...
Definition: FastISel.cpp:1612
llvm::MachineInstrBundleIterator< MachineInstr >
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1815
llvm::FastISel::fastEmitInst_rr
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Definition: FastISel.cpp:1977
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::FastISel::DL
const DataLayout & DL
Definition: FastISel.h:209
llvm::FastISel::selectBinaryOp
bool selectBinaryOp(const User *I, unsigned ISDOpcode)
Select and emit code for a binary operator instruction, which has an opcode which directly correspond...
Definition: FastISel.cpp:453
llvm::FastISel::recomputeInsertPt
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
Definition: FastISel.cpp:405
llvm::FastISel::startNewBlock
void startNewBlock()
Set the current block to which generated machine instructions will be appended.
Definition: FastISel.cpp:125
llvm::FastISel::TM
const TargetMachine & TM
Definition: FastISel.h:208
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::FastISel::constrainOperandRegClass
Register constrainOperandRegClass(const MCInstrDesc &II, Register Op, unsigned OpNum)
Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc.
Definition: FastISel.cpp:1931
llvm::FastISel::fastEmitInst_r
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
Definition: FastISel.cpp:1957
llvm::FastISel::fastEmitInst_i
Register fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm)
Emit a MachineInstr with a single immediate operand, and a result register in the given register clas...
Definition: FastISel.cpp:2116
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103