LLVM  17.0.0git
HexagonISelDAGToDAG.h
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1 //===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // Hexagon specific code to select Hexagon machine instructions for
9 // SelectionDAG operations.
10 //===----------------------------------------------------------------------===//
11 
12 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
13 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
14 
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/ADT/StringRef.h"
20 #include "llvm/Support/CodeGen.h"
21 
22 #include <vector>
23 
24 namespace llvm {
25 class MachineFunction;
26 class HexagonInstrInfo;
27 class HexagonRegisterInfo;
28 
30  const HexagonSubtarget *HST;
31  const HexagonInstrInfo *HII;
32  const HexagonRegisterInfo *HRI;
33 public:
34  static char ID;
35 
36  HexagonDAGToDAGISel() = delete;
37 
40  : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
41  HRI(nullptr) {}
42 
44  // Reset the subtarget each time through.
46  HII = HST->getInstrInfo();
47  HRI = HST->getRegisterInfo();
49  updateAligna();
50  return true;
51  }
52 
53  bool ComplexPatternFuncMutatesDAG() const override {
54  return true;
55  }
56  void PreprocessISelDAG() override;
57  void emitFunctionEntryCode() override;
58 
59  void Select(SDNode *N) override;
60 
61  // Complex Pattern Selectors.
62  inline bool SelectAddrGA(SDValue &N, SDValue &R);
63  inline bool SelectAddrGP(SDValue &N, SDValue &R);
64  inline bool SelectAnyImm(SDValue &N, SDValue &R);
65  inline bool SelectAnyInt(SDValue &N, SDValue &R);
66  bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment);
67  bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment);
68  bool SelectAddrFI(SDValue &N, SDValue &R);
69  bool DetectUseSxtw(SDValue &N, SDValue &R);
70 
71  inline bool SelectAnyImm0(SDValue &N, SDValue &R);
72  inline bool SelectAnyImm1(SDValue &N, SDValue &R);
73  inline bool SelectAnyImm2(SDValue &N, SDValue &R);
74  inline bool SelectAnyImm3(SDValue &N, SDValue &R);
75 
76  // Generate a machine instruction node corresponding to the circ/brev
77  // load intrinsic.
79  // Given the circ/brev load intrinsic and the already generated machine
80  // instruction, generate the appropriate store (that is a part of the
81  // intrinsic's functionality).
83 
84  void SelectFrameIndex(SDNode *N);
85  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
86  /// inline asm expressions.
88  unsigned ConstraintID,
89  std::vector<SDValue> &OutOps) override;
91  bool SelectBrevLdIntrinsic(SDNode *IntN);
92  bool SelectNewCircIntrinsic(SDNode *IntN);
93  void SelectLoad(SDNode *N);
94  void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
95  void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
96  void SelectStore(SDNode *N);
97  void SelectSHL(SDNode *N);
101  void SelectConstant(SDNode *N);
102  void SelectConstantFP(SDNode *N);
103  void SelectV65Gather(SDNode *N);
106  void SelectAddSubCarry(SDNode *N);
107  void SelectVAlign(SDNode *N);
108  void SelectVAlignAddr(SDNode *N);
109  void SelectTypecast(SDNode *N);
110  void SelectP2D(SDNode *N);
111  void SelectD2P(SDNode *N);
112  void SelectQ2V(SDNode *N);
113  void SelectV2Q(SDNode *N);
114 
115  // Include the declarations autogenerated from the selection patterns.
116  #define GET_DAGISEL_DECL
117  #include "HexagonGenDAGISel.inc"
118 
119 private:
120  // This is really only to get access to ReplaceNode (which is a protected
121  // member). Any other members used by HvxSelector can be moved around to
122  // make them accessible).
123  friend struct HvxSelector;
124 
125  SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
126  SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
127  return SDValue(U, 0);
128  }
129 
130  bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
131  bool isAlignedMemNode(const MemSDNode *N) const;
132  bool isSmallStackStore(const StoreSDNode *N) const;
133  bool isPositiveHalfWord(const SDNode *N) const;
134  bool hasOneUse(const SDNode *N) const;
135 
136  // DAG preprocessing functions.
137  void PreprocessHvxISelDAG();
138  void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
139  void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
140  void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
141  void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
142  void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);
143 
144  void SelectHvxExtractSubvector(SDNode *N);
145  void SelectHvxShuffle(SDNode *N);
146  void SelectHvxRor(SDNode *N);
147  void SelectHvxVAlign(SDNode *N);
148 
149  // Function postprocessing.
150  void updateAligna();
151 
152  SmallDenseMap<SDNode *,int> RootWeights;
153  SmallDenseMap<SDNode *,int> RootHeights;
154  SmallDenseMap<const Value *,int> GAUsesInFunction;
155  int getWeight(SDNode *N);
156  int getHeight(SDNode *N);
157  SDValue getMultiplierForSHL(SDNode *N);
158  SDValue factorOutPowerOf2(SDValue V, unsigned Power);
159  unsigned getUsesInFunction(const Value *V);
160  SDValue balanceSubTree(SDNode *N, bool Factorize = false);
161  void rebalanceAddressTrees();
162 }; // end HexagonDAGToDAGISel
163 }
164 
165 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circular buffer intrinsics.
Definition: HexagonISelDAGToDAG.cpp:364
llvm::HexagonDAGToDAGISel::ComplexPatternFuncMutatesDAG
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
Definition: HexagonISelDAGToDAG.h:53
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::HexagonDAGToDAGISel::PreprocessISelDAG
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
Definition: HexagonISelDAGToDAG.cpp:1263
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::HexagonDAGToDAGISel::SelectD2P
void SelectD2P(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:872
llvm::HexagonDAGToDAGISel::SelectAddrGA
bool SelectAddrGA(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1373
StringRef.h
llvm::HexagonDAGToDAGISel::SelectAnyImmediate
bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)
Definition: HexagonISelDAGToDAG.cpp:1407
llvm::HexagonDAGToDAGISel::SelectAddSubCarry
void SelectAddSubCarry(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:786
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
HexagonSubtarget.h
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2901
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:26
llvm::SmallDenseMap
Definition: DenseMap.h:880
llvm::HexagonDAGToDAGISel::ID
static char ID
Definition: HexagonISelDAGToDAG.h:34
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::HexagonDAGToDAGISel::SelectV2Q
void SelectV2Q(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:881
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2348
llvm::HexagonDAGToDAGISel::HexagonDAGToDAGISel
HexagonDAGToDAGISel()=delete
llvm::MemSDNode
This is an abstract virtual class for memory operations.
Definition: SelectionDAGNodes.h:1275
llvm::HexagonDAGToDAGISel
Definition: HexagonISelDAGToDAG.h:29
HexagonTargetMachine.h
llvm::HexagonDAGToDAGISel::SelectP2D
void SelectP2D(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:865
llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
Definition: HexagonISelDAGToDAG.cpp:221
SelectionDAG.h
llvm::HexagonDAGToDAGISel::SelectVAlignAddr
void SelectVAlignAddr(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:842
llvm::HexagonDAGToDAGISel::SelectSHL
void SelectSHL(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:573
llvm::HexagonDAGToDAGISel::SelectLoad
void SelectLoad(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:450
llvm::SelectionDAGISel::OptLevel
CodeGenOpt::Level OptLevel
Definition: SelectionDAGISel.h:54
llvm::HexagonDAGToDAGISel::SelectVAlign
void SelectVAlign(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:795
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::HvxSelector
Definition: HexagonISelDAGToDAGHVX.cpp:923
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::HexagonDAGToDAGISel::SelectConstantFP
void SelectConstantFP(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:723
llvm::HexagonDAGToDAGISel::SelectV65GatherPred
void SelectV65GatherPred(SDNode *N)
Definition: HexagonISelDAGToDAGHVX.cpp:2857
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::HexagonDAGToDAGISel::SelectAnyImm0
bool SelectAnyImm0(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1385
llvm::HexagonDAGToDAGISel::SelectFrameIndex
void SelectFrameIndex(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:757
llvm::HexagonDAGToDAGISel::HexagonDAGToDAGISel
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel)
Definition: HexagonISelDAGToDAG.h:38
llvm::HexagonDAGToDAGISel::SelectConstant
void SelectConstant(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:744
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2376
llvm::HexagonDAGToDAGISel::SelectAnyInt
bool SelectAnyInt(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1398
llvm::SelectionDAGISel::CurDAG
SelectionDAG * CurDAG
Definition: SelectionDAGISel.h:49
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9916
llvm::HexagonDAGToDAGISel::SelectAnyImm1
bool SelectAnyImm1(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1388
llvm::HexagonDAGToDAGISel::emitFunctionEntryCode
void emitFunctionEntryCode() override
Definition: HexagonISelDAGToDAG.cpp:1323
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::HexagonDAGToDAGISel::SelectQ2V
void SelectQ2V(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:895
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonDAGToDAGISel::SelectIndexedStore
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
Definition: HexagonISelDAGToDAG.cpp:468
SelectionDAGISel.h
llvm::HexagonDAGToDAGISel::SelectTypecast
void SelectTypecast(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:857
llvm::HexagonDAGToDAGISel::SelectIndexedLoad
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
Definition: HexagonISelDAGToDAG.cpp:71
llvm::HexagonDAGToDAGISel::SelectGlobalAddress
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)
Definition: HexagonISelDAGToDAG.cpp:1448
llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
Definition: HexagonISelDAGToDAG.cpp:256
llvm::HexagonDAGToDAGISel::SelectAddrGP
bool SelectAddrGP(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1377
llvm::HexagonDAGToDAGISel::SelectIntrinsicWChain
void SelectIntrinsicWChain(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:630
llvm::SelectionDAGISel::MF
MachineFunction * MF
Definition: SelectionDAGISel.h:47
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:125
llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic
bool SelectBrevLdIntrinsic(SDNode *IntN)
Definition: HexagonISelDAGToDAG.cpp:323
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::HexagonDAGToDAGISel::SelectV65Gather
void SelectV65Gather(SDNode *N)
Definition: HexagonISelDAGToDAGHVX.cpp:2897
llvm::HexagonDAGToDAGISel::SelectAddrFI
bool SelectAddrFI(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1361
llvm::HexagonDAGToDAGISel::SelectAnyImm
bool SelectAnyImm(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1381
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
CodeGen.h
llvm::SelectionDAGISel
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
Definition: SelectionDAGISel.h:41
llvm::HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.
Definition: HexagonISelDAGToDAG.cpp:959
llvm::HexagonDAGToDAGISel::SelectAnyImm3
bool SelectAnyImm3(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1394
N
#define N
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
Definition: HexagonISelDAGToDAG.cpp:190
llvm::HexagonDAGToDAGISel::Select
void Select(SDNode *N) override
Main hook for targets to transform nodes into machine nodes.
Definition: HexagonISelDAGToDAG.cpp:908
llvm::HexagonDAGToDAGISel::SelectAnyImm2
bool SelectAnyImm2(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1391
llvm::HexagonDAGToDAGISel::SelectStore
void SelectStore(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:559
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
llvm::HexagonDAGToDAGISel::SelectExtractSubvector
void SelectExtractSubvector(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:701
llvm::SelectionDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: SelectionDAGISel.cpp:381
hasOneUse
static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS)
Definition: WebAssemblyRegStackify.cpp:283
llvm::HexagonDAGToDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: HexagonISelDAGToDAG.h:43
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain
void SelectIntrinsicWOChain(SDNode *N)
Definition: HexagonISelDAGToDAG.cpp:667
llvm::HexagonDAGToDAGISel::SelectHVXDualOutput
void SelectHVXDualOutput(SDNode *N)
Definition: HexagonISelDAGToDAGHVX.cpp:2935
llvm::HexagonDAGToDAGISel::DetectUseSxtw
bool DetectUseSxtw(SDValue &N, SDValue &R)
Definition: HexagonISelDAGToDAG.cpp:1493