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12 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
13 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
25 class MachineFunction;
26 class HexagonInstrInfo;
27 class HexagonRegisterInfo;
88 unsigned ConstraintID,
89 std::vector<SDValue> &OutOps)
override;
116 #define GET_DAGISEL_DECL
117 #include "HexagonGenDAGISel.inc"
130 bool keepsLowBits(
const SDValue &Val,
unsigned NumBits,
SDValue &Src);
131 bool isAlignedMemNode(
const MemSDNode *
N)
const;
133 bool isPositiveHalfWord(
const SDNode *
N)
const;
137 void PreprocessHvxISelDAG();
138 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
139 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
140 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
141 void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
142 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);
144 void SelectHvxExtractSubvector(
SDNode *
N);
145 void SelectHvxShuffle(
SDNode *
N);
147 void SelectHvxVAlign(
SDNode *
N);
159 unsigned getUsesInFunction(
const Value *V);
161 void rebalanceAddressTrees();
165 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circular buffer intrinsics.
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
This is an optimization pass for GlobalISel generic memory operations.
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void SelectD2P(SDNode *N)
bool SelectAddrGA(SDValue &N, SDValue &R)
bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)
void SelectAddSubCarry(SDNode *N)
An SDNode that represents everything that will be needed to construct a MachineInstr.
Represents one node in the SelectionDAG.
void SelectV2Q(SDNode *N)
This class is used to represent ISD::LOAD nodes.
HexagonDAGToDAGISel()=delete
This is an abstract virtual class for memory operations.
void SelectP2D(SDNode *N)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
void SelectVAlignAddr(SDNode *N)
void SelectSHL(SDNode *N)
void SelectLoad(SDNode *N)
CodeGenOpt::Level OptLevel
void SelectVAlign(SDNode *N)
This struct is a compact representation of a valid (non-zero power of two) alignment.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const HexagonInstrInfo * getInstrInfo() const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void SelectConstantFP(SDNode *N)
void SelectV65GatherPred(SDNode *N)
bool SelectAnyImm0(SDValue &N, SDValue &R)
void SelectFrameIndex(SDNode *N)
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel)
void SelectConstant(SDNode *N)
This class is used to represent ISD::STORE nodes.
bool SelectAnyInt(SDValue &N, SDValue &R)
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
bool SelectAnyImm1(SDValue &N, SDValue &R)
void emitFunctionEntryCode() override
void SelectQ2V(SDNode *N)
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
void SelectTypecast(SDNode *N)
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
bool SelectAddrGP(SDValue &N, SDValue &R)
void SelectIntrinsicWChain(SDNode *N)
const HexagonRegisterInfo * getRegisterInfo() const override
bool SelectBrevLdIntrinsic(SDNode *IntN)
void SelectV65Gather(SDNode *N)
bool SelectAddrFI(SDValue &N, SDValue &R)
bool SelectAnyImm(SDValue &N, SDValue &R)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.
bool SelectAnyImm3(SDValue &N, SDValue &R)
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
void Select(SDNode *N) override
Main hook for targets to transform nodes into machine nodes.
bool SelectAnyImm2(SDValue &N, SDValue &R)
void SelectStore(SDNode *N)
Level
Code generation optimization level.
void SelectExtractSubvector(SDNode *N)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
LLVM Value Representation.
void SelectIntrinsicWOChain(SDNode *N)
void SelectHVXDualOutput(SDNode *N)
bool DetectUseSxtw(SDValue &N, SDValue &R)