38#define DEBUG_TYPE "mips-isel"
39#define PASS_NAME "MIPS DAG->DAG Pattern Instruction Selection"
61 processFunctionAfterISel(
MF);
155bool MipsDAGToDAGISel::selectVSplat(
SDNode *
N,
APInt &Imm,
156 unsigned MinSizeInBits)
const {
161bool MipsDAGToDAGISel::selectVSplatUimm1(
SDValue N,
SDValue &Imm)
const {
166bool MipsDAGToDAGISel::selectVSplatUimm2(
SDValue N,
SDValue &Imm)
const {
171bool MipsDAGToDAGISel::selectVSplatUimm3(
SDValue N,
SDValue &Imm)
const {
176bool MipsDAGToDAGISel::selectVSplatUimm4(
SDValue N,
SDValue &Imm)
const {
181bool MipsDAGToDAGISel::selectVSplatUimm5(
SDValue N,
SDValue &Imm)
const {
186bool MipsDAGToDAGISel::selectVSplatUimm6(
SDValue N,
SDValue &Imm)
const {
191bool MipsDAGToDAGISel::selectVSplatUimm8(
SDValue N,
SDValue &Imm)
const {
196bool MipsDAGToDAGISel::selectVSplatSimm5(
SDValue N,
SDValue &Imm)
const {
201bool MipsDAGToDAGISel::selectVSplatUimmPow2(
SDValue N,
SDValue &Imm)
const {
206bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(
SDValue N,
SDValue &Imm)
const {
211bool MipsDAGToDAGISel::selectVSplatMaskL(
SDValue N,
SDValue &Imm)
const {
216bool MipsDAGToDAGISel::selectVSplatMaskR(
SDValue N,
SDValue &Imm)
const {
224bool MipsDAGToDAGISel::selectVecAddAsVecSubIfProfitable(
SDNode *
Node) {
227 EVT VT =
Node->getValueType(0);
233 auto *BVN = dyn_cast<BuildVectorSDNode>(
C);
237 APInt SplatValue, SplatUndef;
238 unsigned SplatBitSize;
241 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
245 auto IsInlineConstant = [](
const APInt &
Imm) {
return Imm.isIntN(5); };
247 if (IsInlineConstant(SplatValue))
250 APInt NegSplatValue = 0 - SplatValue;
251 if (!IsInlineConstant(NegSplatValue))
258 assert(NegC &&
"Constant-folding failed!");
272 if (
Node->isMachineOpcode()) {
286 if (
Node->getSimpleValueType(0).isVector() &&
287 selectVecAddAsVecSubIfProfitable(
Node))
300 cast<MemSDNode>(
Node)->getAlign() >=
301 cast<MemSDNode>(
Node)->getMemoryVT().getStoreSize()) &&
302 "Unexpected unaligned loads/stores.");
311bool MipsDAGToDAGISel::SelectInlineAsmMemoryOperand(
313 std::vector<SDValue> &OutOps) {
315 switch(ConstraintID) {
321 OutOps.push_back(
Op);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t Opcode
DEMANGLE_DUMP_METHOD void dump() const
Class for arbitrary precision integers.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
This class represents an Operation in the Expression.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
SDNode * getGlobalBaseReg()
getGlobalBaseReg - Output the instructions required to put the GOT address into a register.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetLowering * getTargetLowering() const
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
bool isVector() const
Return true if this is a vector value type.