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24 #define GET_INSTRINFO_CTOR_DTOR
25 #include "NVPTXGenInstrInfo.inc"
28 void NVPTXInstrInfo::anchor() {}
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
44 if (DestRC == &NVPTX::Int1RegsRegClass) {
46 }
else if (DestRC == &NVPTX::Int16RegsRegClass) {
48 }
else if (DestRC == &NVPTX::Int32RegsRegClass) {
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
50 : NVPTX::BITCONVERT_32_F2I);
51 }
else if (DestRC == &NVPTX::Int64RegsRegClass) {
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
53 : NVPTX::BITCONVERT_64_F2I);
54 }
else if (DestRC == &NVPTX::Float16RegsRegClass) {
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr
56 : NVPTX::BITCONVERT_16_I2F);
57 }
else if (DestRC == &NVPTX::Float16x2RegsRegClass) {
59 }
else if (DestRC == &NVPTX::Float32RegsRegClass) {
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
61 : NVPTX::BITCONVERT_32_I2F);
62 }
else if (DestRC == &NVPTX::Float64RegsRegClass) {
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
64 : NVPTX::BITCONVERT_64_I2F);
99 bool AllowModify)
const {
102 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I))
109 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
110 if (LastInst.
getOpcode() == NVPTX::GOTO) {
113 }
else if (LastInst.
getOpcode() == NVPTX::CBranch) {
127 if (
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
131 if (SecondLastInst.
getOpcode() == NVPTX::CBranch &&
141 if (SecondLastInst.
getOpcode() == NVPTX::GOTO &&
146 I->eraseFromParent();
155 int *BytesRemoved)
const {
156 assert(!BytesRemoved &&
"code size not handled");
161 if (
I->getOpcode() != NVPTX::GOTO &&
I->getOpcode() != NVPTX::CBranch)
165 I->eraseFromParent();
172 if (
I->getOpcode() != NVPTX::CBranch)
176 I->eraseFromParent();
185 int *BytesAdded)
const {
186 assert(!BytesAdded &&
"code size not handled");
189 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
191 "NVPTX branch conditions have two components!");
This is an optimization pass for GlobalISel generic memory operations.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineBasicBlock * getMBB() const
SmallVector< MachineOperand, 4 > Cond
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned const MachineRegisterInfo * MRI
Should compile to something r4 addze r3 instead we get
unsigned getKillRegState(bool B)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
Wrapper class representing physical registers. Should be passed by value.