40 return Value & 0xfffc;
44 return Value & 0x3fffffc;
46 return Value & 0xffff;
49 return Value & 0xfffc;
52 return Value & 0x3ffffffff;
103 {
"fixup_ppc_br24abs", 6, 24, 0 },
104 {
"fixup_ppc_brcond14abs", 16, 14, 0 },
105 {
"fixup_ppc_half16", 0, 16, 0 },
106 {
"fixup_ppc_half16ds", 0, 14, 0 },
108 {
"fixup_ppc_imm34", 0, 34, 0 },
109 {
"fixup_ppc_nofixup", 0, 0, 0 }
116 {
"fixup_ppc_br24abs", 2, 24, 0 },
117 {
"fixup_ppc_brcond14abs", 2, 14, 0 },
118 {
"fixup_ppc_half16", 0, 16, 0 },
119 {
"fixup_ppc_half16ds", 2, 14, 0 },
121 {
"fixup_ppc_imm34", 0, 34, 0 },
122 {
"fixup_ppc_nofixup", 0, 0, 0 }
156 for (
unsigned i = 0; i != NumBytes; ++i) {
165 switch ((
unsigned)Kind) {
175 if (
const auto *S = dyn_cast<MCSymbolELF>(&
A->getSymbol())) {
179 unsigned Other = S->getOther() << 2;
182 }
else if (
const auto *S = dyn_cast<MCSymbolXCOFF>(&
A->getSymbol())) {
183 return !
Target.isAbsolute() && S->isExternal() &&
208 for (
uint64_t i = 0; i != NumNops; ++i)
209 support::endian::write<uint32_t>(
OS, 0x60000000, Endian);
222class ELFPPCAsmBackend :
public PPCAsmBackend {
224 ELFPPCAsmBackend(
const Target &
T,
const Triple &TT) : PPCAsmBackend(
T,
TT) {}
226 std::unique_ptr<MCObjectTargetWriter>
227 createObjectTargetWriter()
const override {
229 bool Is64 =
TT.isPPC64();
233 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override;
236class XCOFFPPCAsmBackend :
public PPCAsmBackend {
239 : PPCAsmBackend(
T,
TT) {}
241 std::unique_ptr<MCObjectTargetWriter>
242 createObjectTargetWriter()
const override {
246 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override;
251std::optional<MCFixupKind>
253 if (
TT.isOSBinFormatELF()) {
257#define ELF_RELOC(X, Y) .Case(#X, Y)
258#include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
260 .
Case(
"BFD_RELOC_NONE", ELF::R_PPC64_NONE)
261 .
Case(
"BFD_RELOC_16", ELF::R_PPC64_ADDR16)
262 .
Case(
"BFD_RELOC_32", ELF::R_PPC64_ADDR32)
263 .
Case(
"BFD_RELOC_64", ELF::R_PPC64_ADDR64)
267#define ELF_RELOC(X, Y) .Case(#X, Y)
268#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
270 .
Case(
"BFD_RELOC_NONE", ELF::R_PPC_NONE)
271 .
Case(
"BFD_RELOC_16", ELF::R_PPC_ADDR16)
272 .
Case(
"BFD_RELOC_32", ELF::R_PPC_ADDR32)
281std::optional<MCFixupKind>
293 if (TT.isOSBinFormatXCOFF())
294 return new XCOFFPPCAsmBackend(
T, TT);
296 return new ELFPPCAsmBackend(
T, TT);
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::optional< std::vector< StOtherPiece > > Other
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Generic interface to target specific assembler backends.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target)
Hook to check if a relocation is needed for some target specific reason.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_Data_2
A two-byte fixup.
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...