LLVM 17.0.0git
PPCAsmBackend.cpp
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1//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
14#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCSymbolELF.h"
22#include "llvm/MC/MCValue.h"
25using namespace llvm;
26
27static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
28 switch (Kind) {
29 default:
30 llvm_unreachable("Unknown fixup kind!");
31 case FK_Data_1:
32 case FK_Data_2:
33 case FK_Data_4:
34 case FK_Data_8:
36 return Value;
39 return Value & 0xfffc;
43 return Value & 0x3fffffc;
45 return Value & 0xffff;
48 return Value & 0xfffc;
51 return Value & 0x3ffffffff;
52 }
53}
54
55static unsigned getFixupKindNumBytes(unsigned Kind) {
56 switch (Kind) {
57 default:
58 llvm_unreachable("Unknown fixup kind!");
59 case FK_Data_1:
60 return 1;
61 case FK_Data_2:
65 return 2;
66 case FK_Data_4:
72 return 4;
75 case FK_Data_8:
76 return 8;
78 return 0;
79 }
80}
81
82namespace {
83
84class PPCAsmBackend : public MCAsmBackend {
85protected:
86 Triple TT;
87public:
88 PPCAsmBackend(const Target &T, const Triple &TT)
89 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
90 TT(TT) {}
91
92 unsigned getNumFixupKinds() const override {
94 }
95
96 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
97 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
98 // name offset bits flags
99 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
100 { "fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
101 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
102 { "fixup_ppc_br24abs", 6, 24, 0 },
103 { "fixup_ppc_brcond14abs", 16, 14, 0 },
104 { "fixup_ppc_half16", 0, 16, 0 },
105 { "fixup_ppc_half16ds", 0, 14, 0 },
106 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
107 { "fixup_ppc_imm34", 0, 34, 0 },
108 { "fixup_ppc_nofixup", 0, 0, 0 }
109 };
110 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
111 // name offset bits flags
112 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
113 { "fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_ppc_br24abs", 2, 24, 0 },
116 { "fixup_ppc_brcond14abs", 2, 14, 0 },
117 { "fixup_ppc_half16", 0, 16, 0 },
118 { "fixup_ppc_half16ds", 2, 14, 0 },
119 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
120 { "fixup_ppc_imm34", 0, 34, 0 },
121 { "fixup_ppc_nofixup", 0, 0, 0 }
122 };
123
124 // Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
125 // do not require any extra processing.
126 if (Kind >= FirstLiteralRelocationKind)
128
129 if (Kind < FirstTargetFixupKind)
131
132 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
133 "Invalid kind!");
134 return (Endian == support::little
135 ? InfosLE
136 : InfosBE)[Kind - FirstTargetFixupKind];
137 }
138
139 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
141 uint64_t Value, bool IsResolved,
142 const MCSubtargetInfo *STI) const override {
143 MCFixupKind Kind = Fixup.getKind();
144 if (Kind >= FirstLiteralRelocationKind)
145 return;
147 if (!Value) return; // Doesn't change encoding.
148
149 unsigned Offset = Fixup.getOffset();
150 unsigned NumBytes = getFixupKindNumBytes(Kind);
151
152 // For each byte of the fragment that the fixup touches, mask in the bits
153 // from the fixup value. The Value has been "split up" into the appropriate
154 // bitfields above.
155 for (unsigned i = 0; i != NumBytes; ++i) {
156 unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i);
157 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
158 }
159 }
160
161 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
162 const MCValue &Target) override {
163 MCFixupKind Kind = Fixup.getKind();
164 switch ((unsigned)Kind) {
165 default:
170 // If the target symbol has a local entry point we must not attempt
171 // to resolve the fixup directly. Emit a relocation and leave
172 // resolution of the final target address to the linker.
173 if (const MCSymbolRefExpr *A = Target.getSymA()) {
174 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
175 // The "other" values are stored in the last 6 bits of the second
176 // byte. The traditional defines for STO values assume the full byte
177 // and thus the shift to pack it.
178 unsigned Other = S->getOther() << 2;
179 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0)
180 return true;
181 }
182 }
183 return false;
184 }
185 }
186
189 const MCRelaxableFragment *DF,
190 const MCAsmLayout &Layout) const override {
191 // FIXME.
192 llvm_unreachable("relaxInstruction() unimplemented");
193 }
194
195 void relaxInstruction(MCInst &Inst,
196 const MCSubtargetInfo &STI) const override {
197 // FIXME.
198 llvm_unreachable("relaxInstruction() unimplemented");
199 }
200
201 bool writeNopData(raw_ostream &OS, uint64_t Count,
202 const MCSubtargetInfo *STI) const override {
203 uint64_t NumNops = Count / 4;
204 for (uint64_t i = 0; i != NumNops; ++i)
205 support::endian::write<uint32_t>(OS, 0x60000000, Endian);
206
207 OS.write_zeros(Count % 4);
208
209 return true;
210 }
211};
212} // end anonymous namespace
213
214
215// FIXME: This should be in a separate file.
216namespace {
217
218class ELFPPCAsmBackend : public PPCAsmBackend {
219public:
220 ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {}
221
222 std::unique_ptr<MCObjectTargetWriter>
223 createObjectTargetWriter() const override {
224 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
225 bool Is64 = TT.isPPC64();
226 return createPPCELFObjectWriter(Is64, OSABI);
227 }
228
229 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
230};
231
232class XCOFFPPCAsmBackend : public PPCAsmBackend {
233public:
234 XCOFFPPCAsmBackend(const Target &T, const Triple &TT)
235 : PPCAsmBackend(T, TT) {}
236
237 std::unique_ptr<MCObjectTargetWriter>
238 createObjectTargetWriter() const override {
239 return createPPCXCOFFObjectWriter(TT.isArch64Bit());
240 }
241};
242
243} // end anonymous namespace
244
245std::optional<MCFixupKind>
246ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
247 if (TT.isOSBinFormatELF()) {
248 unsigned Type;
249 if (TT.isPPC64()) {
251#define ELF_RELOC(X, Y) .Case(#X, Y)
252#include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
253#undef ELF_RELOC
254 .Case("BFD_RELOC_NONE", ELF::R_PPC64_NONE)
255 .Case("BFD_RELOC_16", ELF::R_PPC64_ADDR16)
256 .Case("BFD_RELOC_32", ELF::R_PPC64_ADDR32)
257 .Case("BFD_RELOC_64", ELF::R_PPC64_ADDR64)
258 .Default(-1u);
259 } else {
261#define ELF_RELOC(X, Y) .Case(#X, Y)
262#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
263#undef ELF_RELOC
264 .Case("BFD_RELOC_NONE", ELF::R_PPC_NONE)
265 .Case("BFD_RELOC_16", ELF::R_PPC_ADDR16)
266 .Case("BFD_RELOC_32", ELF::R_PPC_ADDR32)
267 .Default(-1u);
268 }
269 if (Type != -1u)
270 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
271 }
272 return std::nullopt;
273}
274
276 const MCSubtargetInfo &STI,
277 const MCRegisterInfo &MRI,
278 const MCTargetOptions &Options) {
279 const Triple &TT = STI.getTargetTriple();
280 if (TT.isOSBinFormatXCOFF())
281 return new XCOFFPPCAsmBackend(T, TT);
282
283 return new ELFPPCAsmBackend(T, TT);
284}
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
std::optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1260
static LVOptions Options
Definition: LVOptions.cpp:25
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:171
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:97
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ STO_PPC64_LOCAL_MASK
Definition: ELF.h:409
@ fixup_ppc_pcrel34
Definition: PPCFixupKinds.h:44
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
Definition: PPCFixupKinds.h:33
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
@ NumTargetFixupKinds
Definition: PPCFixupKinds.h:60
@ fixup_ppc_br24_notoc
Definition: PPCFixupKinds.h:24
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
Definition: PPCFixupKinds.h:27
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:56
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Definition: PPCFixupKinds.h:52
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...