LLVM 18.0.0git
PPCAsmBackend.cpp
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1//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
14#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCSymbolELF.h"
23#include "llvm/MC/MCValue.h"
26using namespace llvm;
27
28static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
29 switch (Kind) {
30 default:
31 llvm_unreachable("Unknown fixup kind!");
32 case FK_Data_1:
33 case FK_Data_2:
34 case FK_Data_4:
35 case FK_Data_8:
37 return Value;
40 return Value & 0xfffc;
44 return Value & 0x3fffffc;
46 return Value & 0xffff;
49 return Value & 0xfffc;
52 return Value & 0x3ffffffff;
53 }
54}
55
56static unsigned getFixupKindNumBytes(unsigned Kind) {
57 switch (Kind) {
58 default:
59 llvm_unreachable("Unknown fixup kind!");
60 case FK_Data_1:
61 return 1;
62 case FK_Data_2:
66 return 2;
67 case FK_Data_4:
73 return 4;
76 case FK_Data_8:
77 return 8;
79 return 0;
80 }
81}
82
83namespace {
84
85class PPCAsmBackend : public MCAsmBackend {
86protected:
87 Triple TT;
88public:
89 PPCAsmBackend(const Target &T, const Triple &TT)
90 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
91 TT(TT) {}
92
93 unsigned getNumFixupKinds() const override {
95 }
96
97 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
98 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
99 // name offset bits flags
100 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
101 { "fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
102 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
103 { "fixup_ppc_br24abs", 6, 24, 0 },
104 { "fixup_ppc_brcond14abs", 16, 14, 0 },
105 { "fixup_ppc_half16", 0, 16, 0 },
106 { "fixup_ppc_half16ds", 0, 14, 0 },
107 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
108 { "fixup_ppc_imm34", 0, 34, 0 },
109 { "fixup_ppc_nofixup", 0, 0, 0 }
110 };
111 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
112 // name offset bits flags
113 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_ppc_br24abs", 2, 24, 0 },
117 { "fixup_ppc_brcond14abs", 2, 14, 0 },
118 { "fixup_ppc_half16", 0, 16, 0 },
119 { "fixup_ppc_half16ds", 2, 14, 0 },
120 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
121 { "fixup_ppc_imm34", 0, 34, 0 },
122 { "fixup_ppc_nofixup", 0, 0, 0 }
123 };
124
125 // Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
126 // do not require any extra processing.
127 if (Kind >= FirstLiteralRelocationKind)
129
130 if (Kind < FirstTargetFixupKind)
132
133 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
134 "Invalid kind!");
135 return (Endian == support::little
136 ? InfosLE
137 : InfosBE)[Kind - FirstTargetFixupKind];
138 }
139
140 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
142 uint64_t Value, bool IsResolved,
143 const MCSubtargetInfo *STI) const override {
144 MCFixupKind Kind = Fixup.getKind();
145 if (Kind >= FirstLiteralRelocationKind)
146 return;
148 if (!Value) return; // Doesn't change encoding.
149
150 unsigned Offset = Fixup.getOffset();
151 unsigned NumBytes = getFixupKindNumBytes(Kind);
152
153 // For each byte of the fragment that the fixup touches, mask in the bits
154 // from the fixup value. The Value has been "split up" into the appropriate
155 // bitfields above.
156 for (unsigned i = 0; i != NumBytes; ++i) {
157 unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i);
158 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
159 }
160 }
161
162 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
163 const MCValue &Target) override {
164 MCFixupKind Kind = Fixup.getKind();
165 switch ((unsigned)Kind) {
166 default:
171 // If the target symbol has a local entry point we must not attempt
172 // to resolve the fixup directly. Emit a relocation and leave
173 // resolution of the final target address to the linker.
174 if (const MCSymbolRefExpr *A = Target.getSymA()) {
175 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
176 // The "other" values are stored in the last 6 bits of the second
177 // byte. The traditional defines for STO values assume the full byte
178 // and thus the shift to pack it.
179 unsigned Other = S->getOther() << 2;
180 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0)
181 return true;
182 } else if (const auto *S = dyn_cast<MCSymbolXCOFF>(&A->getSymbol())) {
183 return !Target.isAbsolute() && S->isExternal() &&
184 S->getStorageClass() == XCOFF::C_WEAKEXT;
185 }
186 }
187 return false;
188 }
189 }
190
193 const MCRelaxableFragment *DF,
194 const MCAsmLayout &Layout) const override {
195 // FIXME.
196 llvm_unreachable("relaxInstruction() unimplemented");
197 }
198
199 void relaxInstruction(MCInst &Inst,
200 const MCSubtargetInfo &STI) const override {
201 // FIXME.
202 llvm_unreachable("relaxInstruction() unimplemented");
203 }
204
205 bool writeNopData(raw_ostream &OS, uint64_t Count,
206 const MCSubtargetInfo *STI) const override {
207 uint64_t NumNops = Count / 4;
208 for (uint64_t i = 0; i != NumNops; ++i)
209 support::endian::write<uint32_t>(OS, 0x60000000, Endian);
210
211 OS.write_zeros(Count % 4);
212
213 return true;
214 }
215};
216} // end anonymous namespace
217
218
219// FIXME: This should be in a separate file.
220namespace {
221
222class ELFPPCAsmBackend : public PPCAsmBackend {
223public:
224 ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {}
225
226 std::unique_ptr<MCObjectTargetWriter>
227 createObjectTargetWriter() const override {
228 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
229 bool Is64 = TT.isPPC64();
230 return createPPCELFObjectWriter(Is64, OSABI);
231 }
232
233 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
234};
235
236class XCOFFPPCAsmBackend : public PPCAsmBackend {
237public:
238 XCOFFPPCAsmBackend(const Target &T, const Triple &TT)
239 : PPCAsmBackend(T, TT) {}
240
241 std::unique_ptr<MCObjectTargetWriter>
242 createObjectTargetWriter() const override {
243 return createPPCXCOFFObjectWriter(TT.isArch64Bit());
244 }
245
246 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
247};
248
249} // end anonymous namespace
250
251std::optional<MCFixupKind>
252ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
253 if (TT.isOSBinFormatELF()) {
254 unsigned Type;
255 if (TT.isPPC64()) {
257#define ELF_RELOC(X, Y) .Case(#X, Y)
258#include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
259#undef ELF_RELOC
260 .Case("BFD_RELOC_NONE", ELF::R_PPC64_NONE)
261 .Case("BFD_RELOC_16", ELF::R_PPC64_ADDR16)
262 .Case("BFD_RELOC_32", ELF::R_PPC64_ADDR32)
263 .Case("BFD_RELOC_64", ELF::R_PPC64_ADDR64)
264 .Default(-1u);
265 } else {
267#define ELF_RELOC(X, Y) .Case(#X, Y)
268#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
269#undef ELF_RELOC
270 .Case("BFD_RELOC_NONE", ELF::R_PPC_NONE)
271 .Case("BFD_RELOC_16", ELF::R_PPC_ADDR16)
272 .Case("BFD_RELOC_32", ELF::R_PPC_ADDR32)
273 .Default(-1u);
274 }
275 if (Type != -1u)
276 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
277 }
278 return std::nullopt;
279}
280
281std::optional<MCFixupKind>
282XCOFFPPCAsmBackend::getFixupKind(StringRef Name) const {
284 .Case("R_REF", (MCFixupKind)PPC::fixup_ppc_nofixup)
285 .Default(std::nullopt);
286}
287
289 const MCSubtargetInfo &STI,
290 const MCRegisterInfo &MRI,
291 const MCTargetOptions &Options) {
292 const Triple &TT = STI.getTargetTriple();
293 if (TT.isOSBinFormatXCOFF())
294 return new XCOFFPPCAsmBackend(T, TT);
295
296 return new ELFPPCAsmBackend(T, TT);
297}
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
@ Default
Definition: DwarfDebug.cpp:87
std::string Name
std::optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1272
static LVOptions Options
Definition: LVOptions.cpp:25
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:184
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:102
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:70
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:274
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ STO_PPC64_LOCAL_MASK
Definition: ELF.h:409
@ fixup_ppc_pcrel34
Definition: PPCFixupKinds.h:44
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
Definition: PPCFixupKinds.h:33
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
@ NumTargetFixupKinds
Definition: PPCFixupKinds.h:61
@ fixup_ppc_br24_notoc
Definition: PPCFixupKinds.h:24
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
Definition: PPCFixupKinds.h:27
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:57
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Definition: PPCFixupKinds.h:53
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
@ C_WEAKEXT
Definition: XCOFF.h:198
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:44
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:49
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...