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27 #define DEBUG_TYPE "asm-printer"
30 #define PRINT_ALIAS_INSTR
31 #include "RISCVGenAsmWriter.inc"
34 #define GEN_UNCOMPRESS_INSTR
35 #include "RISCVGenCompressInstEmitter.inc"
39 cl::desc(
"Disable the emission of assembler pseudo instructions"),
54 if (Opt ==
"no-aliases") {
58 if (Opt ==
"numeric") {
73 Res = uncompressInst(UncompressedMI, *
MI,
MRI, STI);
75 NewMI =
const_cast<MCInst *
>(&UncompressedMI);
87 const char *Modifier) {
88 assert((Modifier ==
nullptr || Modifier[0] == 0) &&
"No modifiers supported");
101 assert(MO.
isExpr() &&
"Unknown operand kind in printOperand");
126 unsigned Imm =
MI->getOperand(OpNo).getImm();
137 unsigned FenceArg =
MI->getOperand(OpNo).getImm();
138 assert (((FenceArg >> 4) == 0) &&
"Invalid immediate in printFenceArg");
164 assert(MO.
isReg() &&
"printZeroOffsetMemOp can only print register operands");
172 unsigned Imm =
MI->getOperand(OpNo).getImm();
189 assert(MO.
isReg() &&
"printVMaskReg can only print register operands");
190 if (MO.
getReg() == RISCV::NoRegister)
199 : RISCV::ABIRegAltName);
This is an optimization pass for GlobalISel generic memory operations.
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Target - Wrapper for Target specific information.
Instances of this class represent a single low-level machine instruction.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
static unsigned getSEW(unsigned VType)
void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
const MCRegisterInfo & MRI
bool hasFeature(unsigned Feature) const
void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
const FeatureBitset & getFeatureBits() const
This class implements an extremely fast bulk output stream that can only output to a stream.
void printRegName(raw_ostream &O, unsigned RegNo) const override
Print the assembler register name.
static cl::opt< bool > NoAliases("riscv-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
initializer< Ty > init(const Ty &Val)
format_object< int64_t > formatHex(int64_t Value) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef - Represent a constant reference to a string, i.e.
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
static StringRef roundingModeToString(RoundingMode RndMode)
void printVType(unsigned VType, raw_ostream &OS)
static RISCVII::VLMUL getVLMUL(unsigned VType)
const SysReg * lookupSysRegByEncoding(uint16_t)
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Instances of this class represent operands of the MCInst class.
static const char * getRegisterName(unsigned RegNo)
Generic base class for all target subtargets.
unsigned getReg() const
Returns the register number.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)