LLVM 17.0.0git
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1//===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9/// This pass is required to take advantage of the interprocedural register
10/// allocation infrastructure.
12/// This pass is simple MachineFunction pass which collects register usage
13/// details by iterating through each physical registers and checking
14/// MRI::isPhysRegUsed() then creates a RegMask based on this details.
15/// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
19#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/Passes.h"
26#include "llvm/IR/Function.h"
27#include "llvm/Support/Debug.h"
30using namespace llvm;
32#define DEBUG_TYPE "ip-regalloc"
35 "Number of functions optimized for callee saved registers");
37namespace {
44 }
46 StringRef getPassName() const override {
47 return "Register Usage Information Collector Pass";
48 }
50 void getAnalysisUsage(AnalysisUsage &AU) const override {
52 AU.setPreservesAll();
54 }
56 bool runOnMachineFunction(MachineFunction &MF) override;
58 // Call getCalleeSaves and then also set the bits for subregs and
59 // fully saved superregs.
60 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
62 static char ID;
65} // end of anonymous namespace
67char RegUsageInfoCollector::ID = 0;
69INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
70 "Register Usage Information Collector", false, false)
72INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
76 return new RegUsageInfoCollector();
79// TODO: Move to hook somwehere?
81// Return true if it is useful to track the used registers for IPRA / no CSR
82// optimizations. This is not useful for entry points, and computing the
83// register usage information is expensive.
84static bool isCallableFunction(const MachineFunction &MF) {
85 switch (MF.getFunction().getCallingConv()) {
94 return false;
95 default:
96 return true;
97 }
100bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
103 const LLVMTargetMachine &TM = MF.getTarget();
105 LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
106 << " -------------------- \nFunction Name : "
107 << MF.getName() << '\n');
109 // Analyzing the register usage may be expensive on some targets.
110 if (!isCallableFunction(MF)) {
111 LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n");
112 return false;
113 }
115 // If there are no callers, there's no point in computing more precise
116 // register usage here.
117 if (MF.getFunction().use_empty()) {
118 LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n");
119 return false;
120 }
122 std::vector<uint32_t> RegMask;
124 // Compute the size of the bit vector to represent all the registers.
125 // The bit vector is broken into 32-bit chunks, thus takes the ceil of
126 // the number of registers divided by 32 for the size.
127 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
128 RegMask.resize(RegMaskSize, ~((uint32_t)0));
130 const Function &F = MF.getFunction();
132 PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
133 PRUI.setTargetMachine(TM);
135 LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
137 BitVector SavedRegs;
138 computeCalleeSavedRegs(SavedRegs, MF);
140 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
141 auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
142 RegMask[Reg / 32] &= ~(1u << Reg % 32);
143 };
145 // Some targets can clobber registers "inside" a call, typically in
146 // linker-generated code.
147 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
148 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
149 SetRegAsDefined(*AI);
151 // Scan all the physical registers. When a register is defined in the current
152 // function set it and all the aliasing registers as defined in the regmask.
153 // FIXME: Rewrite to use regunits.
154 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
155 // Don't count registers that are saved and restored.
156 if (SavedRegs.test(PReg))
157 continue;
158 // If a register is defined by an instruction mark it as defined together
159 // with all it's unsaved aliases.
160 if (!MRI->def_empty(PReg)) {
161 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
162 if (!SavedRegs.test(*AI))
163 SetRegAsDefined(*AI);
164 continue;
165 }
166 // If a register is in the UsedPhysRegsMask set then mark it as defined.
167 // All clobbered aliases will also be in the set, so we can skip setting
168 // as defined all the aliases here.
169 if (UsedPhysRegsMask.test(PReg))
170 SetRegAsDefined(PReg);
171 }
175 ++NumCSROpt;
176 LLVM_DEBUG(dbgs() << MF.getName()
177 << " function optimized for not having CSR.\n");
178 }
181 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
182 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
183 dbgs() << printReg(PReg, TRI) << " ";
184 }
186 dbgs() << " \n----------------------------------------\n";
187 );
189 PRUI.storeUpdateRegUsageInfo(F, RegMask);
191 return false;
194void RegUsageInfoCollector::
195computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
199 // Target will return the set of registers that it saves/restores as needed.
200 SavedRegs.clear();
201 TFI.getCalleeSaves(MF, SavedRegs);
202 if (SavedRegs.none())
203 return;
205 // Insert subregs.
206 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
207 for (unsigned i = 0; CSRegs[i]; ++i) {
208 MCPhysReg Reg = CSRegs[i];
209 if (SavedRegs.test(Reg)) {
210 // Save subregisters
211 for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)
212 SavedRegs.set(*SR);
213 }
214 }
unsigned const MachineRegisterInfo * MRI
#define LLVM_DEBUG(X)
Definition: Debug.h:101
Natural Loop Information
Definition: LoopInfo.cpp:1177
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Register Usage Information Collector
static bool isCallableFunction(const MachineFunction &MF)
This pass is required to take advantage of the interprocedural register allocation infrastructure.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
Definition: Statistic.h:167
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
bool test(unsigned Idx) const
Definition: BitVector.h:461
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:335
BitVector & set()
Definition: BitVector.h:351
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:188
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:237
This class describes a target machine that is implemented with the LLVM target-independent code gener...
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MCSubRegIterator enumerates all sub-registers of Reg.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
void storeUpdateRegUsageInfo(const Function &FP, ArrayRef< uint32_t > RegMask)
To store RegMask for given Function *.
void setTargetMachine(const LLVMTargetMachine &TM)
Set TargetMachine which is used to print analysis.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Information about stack frame layout on the target.
virtual void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
virtual bool isProfitableForNoCSROpt(const Function &F) const
Check if the no-CSR optimisation is profitable for the given function.
static bool isSafeForNoCSROpt(const Function &F)
Check if given function is safe for not having callee saved registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
bool use_empty() const
Definition: Value.h:344
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:194
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:185
Used for AMDGPU code object kernels.
Definition: CallingConv.h:197
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:203
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:188
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:191
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:215
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:210
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void initializeRegUsageInfoCollectorPass(PassRegistry &)