LLVM  15.0.0git
RegUsageInfoCollector.cpp
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1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This pass is required to take advantage of the interprocedural register
10 /// allocation infrastructure.
11 ///
12 /// This pass is simple MachineFunction pass which collects register usage
13 /// details by iterating through each physical registers and checking
14 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
15 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
16 ///
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/Debug.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "ip-regalloc"
33 
34 STATISTIC(NumCSROpt,
35  "Number of functions optimized for callee saved registers");
36 
37 namespace {
38 
40 public:
44  }
45 
46  StringRef getPassName() const override {
47  return "Register Usage Information Collector Pass";
48  }
49 
50  void getAnalysisUsage(AnalysisUsage &AU) const override {
52  AU.setPreservesAll();
54  }
55 
56  bool runOnMachineFunction(MachineFunction &MF) override;
57 
58  // Call getCalleeSaves and then also set the bits for subregs and
59  // fully saved superregs.
60  static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
61 
62  static char ID;
63 };
64 
65 } // end of anonymous namespace
66 
68 
69 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
70  "Register Usage Information Collector", false, false)
74 
76  return new RegUsageInfoCollector();
77 }
78 
79 // TODO: Move to hook somwehere?
80 
81 // Return true if it is useful to track the used registers for IPRA / no CSR
82 // optimizations. This is not useful for entry points, and computing the
83 // register usage information is expensive.
84 static bool isCallableFunction(const MachineFunction &MF) {
85  switch (MF.getFunction().getCallingConv()) {
94  return false;
95  default:
96  return true;
97  }
98 }
99 
100 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
103  const LLVMTargetMachine &TM = MF.getTarget();
104 
105  LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
106  << " -------------------- \nFunction Name : "
107  << MF.getName() << '\n');
108 
109  // Analyzing the register usage may be expensive on some targets.
110  if (!isCallableFunction(MF)) {
111  LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n");
112  return false;
113  }
114 
115  // If there are no callers, there's no point in computing more precise
116  // register usage here.
117  if (MF.getFunction().use_empty()) {
118  LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n");
119  return false;
120  }
121 
122  std::vector<uint32_t> RegMask;
123 
124  // Compute the size of the bit vector to represent all the registers.
125  // The bit vector is broken into 32-bit chunks, thus takes the ceil of
126  // the number of registers divided by 32 for the size.
127  unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
128  RegMask.resize(RegMaskSize, ~((uint32_t)0));
129 
130  const Function &F = MF.getFunction();
131 
132  PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
133  PRUI.setTargetMachine(TM);
134 
135  LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
136 
137  BitVector SavedRegs;
138  computeCalleeSavedRegs(SavedRegs, MF);
139 
140  const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
141  auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
142  RegMask[Reg / 32] &= ~(1u << Reg % 32);
143  };
144 
145  // Some targets can clobber registers "inside" a call, typically in
146  // linker-generated code.
147  for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
148  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
149  SetRegAsDefined(*AI);
150 
151  // Scan all the physical registers. When a register is defined in the current
152  // function set it and all the aliasing registers as defined in the regmask.
153  // FIXME: Rewrite to use regunits.
154  for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
155  // Don't count registers that are saved and restored.
156  if (SavedRegs.test(PReg))
157  continue;
158  // If a register is defined by an instruction mark it as defined together
159  // with all it's unsaved aliases.
160  if (!MRI->def_empty(PReg)) {
161  for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
162  if (!SavedRegs.test(*AI))
163  SetRegAsDefined(*AI);
164  continue;
165  }
166  // If a register is in the UsedPhysRegsMask set then mark it as defined.
167  // All clobbered aliases will also be in the set, so we can skip setting
168  // as defined all the aliases here.
169  if (UsedPhysRegsMask.test(PReg))
170  SetRegAsDefined(PReg);
171  }
172 
175  ++NumCSROpt;
176  LLVM_DEBUG(dbgs() << MF.getName()
177  << " function optimized for not having CSR.\n");
178  }
179 
180  LLVM_DEBUG(
181  for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
182  if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
183  dbgs() << printReg(PReg, TRI) << " ";
184  }
185 
186  dbgs() << " \n----------------------------------------\n";
187  );
188 
189  PRUI.storeUpdateRegUsageInfo(F, RegMask);
190 
191  return false;
192 }
193 
194 void RegUsageInfoCollector::
195 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
198 
199  // Target will return the set of registers that it saves/restores as needed.
200  SavedRegs.clear();
201  TFI.getCalleeSaves(MF, SavedRegs);
202  if (SavedRegs.none())
203  return;
204 
205  // Insert subregs.
206  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
207  for (unsigned i = 0; CSRegs[i]; ++i) {
208  MCPhysReg Reg = CSRegs[i];
209  if (SavedRegs.test(Reg)) {
210  // Save subregisters
211  for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)
212  SavedRegs.set(*SR);
213  }
214  }
215 }
i
i
Definition: README.txt:29
llvm::TargetFrameLowering::getCalleeSaves
virtual void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
Definition: TargetFrameLoweringImpl.cpp:70
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:223
llvm::TargetRegisterInfo::getIntraCallClobberedRegs
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
Definition: TargetRegisterInfo.h:502
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::CallingConv::AMDGPU_VS
@ AMDGPU_VS
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:204
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Function
Definition: Function.h:60
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::BitVector::clear
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:328
llvm::BitVector::none
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:181
Statistic.h
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
Information
Natural Loop Information
Definition: LoopInfo.cpp:1173
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
Collector
Register Usage Information Collector
Definition: RegUsageInfoCollector.cpp:73
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
llvm::TargetFrameLowering::isProfitableForNoCSROpt
virtual bool isProfitableForNoCSROpt(const Function &F) const
Check if the no-CSR optimisation is profitable for the given function.
Definition: TargetFrameLowering.h:451
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:645
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo
void storeUpdateRegUsageInfo(const Function &FP, ArrayRef< uint32_t > RegMask)
To store RegMask for given Function *.
Definition: RegisterUsageInfo.cpp:57
false
Definition: StackSlotColoring.cpp:141
llvm::CallingConv::AMDGPU_ES
@ AMDGPU_ES
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:236
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:207
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::BitVector
Definition: BitVector.h:75
llvm::Value::use_empty
bool use_empty() const
Definition: Value.h:344
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::initializeRegUsageInfoCollectorPass
void initializeRegUsageInfoCollectorPass(PassRegistry &)
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
isCallableFunction
static bool isCallableFunction(const MachineFunction &MF)
Definition: RegUsageInfoCollector.cpp:84
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:565
llvm::TargetFrameLowering::isSafeForNoCSROpt
static bool isSafeForNoCSROpt(const Function &F)
Check if given function is safe for not having callee saved registers.
Definition: TargetFrameLoweringImpl.cpp:154
llvm::PhysicalRegisterUsageInfo
Definition: RegisterUsageInfo.h:34
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
RegUsageInfoCollector
RegUsageInfoCollector
Definition: RegUsageInfoCollector.cpp:72
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
RegisterUsageInfo.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineRegisterInfo::getUsedPhysRegsMask
const BitVector & getUsedPhysRegsMask() const
Definition: MachineRegisterInfo.h:880
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::createRegUsageInfoCollector
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
Definition: RegUsageInfoCollector.cpp:75
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector", "Register Usage Information Collector", false, false) INITIALIZE_PASS_END(RegUsageInfoCollector
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::PhysicalRegisterUsageInfo::setTargetMachine
void setTargetMachine(const LLVMTargetMachine &TM)
Set TargetMachine which is used to print analysis.
Function.h
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:597
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::Registry
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::CallingConv::AMDGPU_LS
@ AMDGPU_LS
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:231
MachineOperand.h
llvm::CallingConv::AMDGPU_CS
@ AMDGPU_CS
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:213
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
raw_ostream.h
Debug.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38