LLVM 17.0.0git
SIFixVGPRCopies.cpp
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1//===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Add implicit use of exec to vector register copies.
11///
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPU.h"
15#include "GCNSubtarget.h"
18
19using namespace llvm;
20
21#define DEBUG_TYPE "si-fix-vgpr-copies"
22
23namespace {
24
25class SIFixVGPRCopies : public MachineFunctionPass {
26public:
27 static char ID;
28
29public:
30 SIFixVGPRCopies() : MachineFunctionPass(ID) {
32 }
33
34 bool runOnMachineFunction(MachineFunction &MF) override;
35
36 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
37};
38
39} // End anonymous namespace.
40
41INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
42
43char SIFixVGPRCopies::ID = 0;
44
45char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
46
47bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
48 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
49 const SIRegisterInfo *TRI = ST.getRegisterInfo();
50 const SIInstrInfo *TII = ST.getInstrInfo();
51 bool Changed = false;
52
53 for (MachineBasicBlock &MBB : MF) {
54 for (MachineInstr &MI : MBB) {
55 switch (MI.getOpcode()) {
56 case AMDGPU::COPY:
57 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
58 MI.addOperand(MF,
59 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
60 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
61 Changed = true;
62 }
63 break;
64 default:
65 break;
66 }
67 }
68 }
69
70 return Changed;
71}
MachineBasicBlock & MBB
Provides AMDGPU specific target descriptions.
#define LLVM_DEBUG(X)
Definition: Debug.h:101
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
#define DEBUG_TYPE
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
Definition: MachineInstr.h:68
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeSIFixVGPRCopiesPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & SIFixVGPRCopiesID