LLVM  14.0.0git
SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "AMDGPUGenRegisterInfo.inc"
19 
20 namespace llvm {
21 
22 class GCNSubtarget;
23 class LiveIntervals;
24 class LivePhysRegs;
25 class RegisterBank;
26 struct SGPRSpillBuilder;
27 
28 class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
29 private:
30  const GCNSubtarget &ST;
31  bool SpillSGPRToVGPR;
32  bool isWave32;
33  BitVector RegPressureIgnoredUnits;
34 
35  /// Sub reg indexes for getRegSplitParts.
36  /// First index represents subreg size from 1 to 16 DWORDs.
37  /// The inner vector is sorted by bit offset.
38  /// Provided a register can be fully split with given subregs,
39  /// all elements of the inner vector combined give a full lane mask.
40  static std::array<std::vector<int16_t>, 16> RegSplitParts;
41 
42  // Table representing sub reg of given width and offset.
43  // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
44  // Second index is 32 different dword offsets.
45  static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
46 
47  void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
48 
49 public:
50  SIRegisterInfo(const GCNSubtarget &ST);
51 
52  /// \returns the sub reg enum value for the given \p Channel
53  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
54  static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
55 
56  bool spillSGPRToVGPR() const {
57  return SpillSGPRToVGPR;
58  }
59 
60  /// Return the end register initially reserved for the scratch buffer in case
61  /// spilling is needed.
63 
64  BitVector getReservedRegs(const MachineFunction &MF) const override;
65 
66  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
67  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
69  CallingConv::ID) const override;
70  const uint32_t *getNoPreservedMask() const override;
71 
72  // Stack access is very expensive. CSRs are also the high registers, and we
73  // want to minimize the number of used registers.
74  unsigned getCSRFirstUseCost() const override {
75  return 100;
76  }
77 
78  Register getFrameRegister(const MachineFunction &MF) const override;
79 
80  bool hasBasePointer(const MachineFunction &MF) const;
81  Register getBaseRegister() const;
82 
83  bool shouldRealignStack(const MachineFunction &MF) const override;
84  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
85 
86  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
88  const MachineFunction &MF) const override;
89  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
90 
91  int64_t getScratchInstrOffset(const MachineInstr *MI) const;
92 
94  int Idx) const override;
95 
96  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
97 
99  int64_t Offset) const override;
100 
101  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
102  int64_t Offset) const override;
103 
104  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
105  int64_t Offset) const override;
106 
108  const MachineFunction &MF, unsigned Kind = 0) const override;
109 
110  /// Returns a legal register class to copy a register in the specified class
111  /// to or from. If it is possible to copy the register directly without using
112  /// a cross register class copy, return the specified RC. Returns NULL if it
113  /// is not possible to copy between two registers of the specified class.
114  const TargetRegisterClass *
115  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
116 
118  bool IsLoad, bool IsKill = true) const;
119 
120  /// If \p OnlyToVGPR is true, this will only succeed if this
122  int FI, RegScavenger *RS,
123  LiveIntervals *LIS = nullptr,
124  bool OnlyToVGPR = false) const;
125 
127  int FI, RegScavenger *RS,
128  LiveIntervals *LIS = nullptr,
129  bool OnlyToVGPR = false) const;
130 
132  unsigned FIOperandNum,
133  RegScavenger *RS) const override;
134 
136  int FI, RegScavenger *RS,
137  LiveIntervals *LIS = nullptr) const;
138 
139  StringRef getRegAsmName(MCRegister Reg) const override;
140 
141  // Pseudo regs are not allowed
142  unsigned getHWRegIndex(MCRegister Reg) const {
143  return getEncodingValue(Reg) & 0xff;
144  }
145 
148 
151 
153  static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
154 
155  /// Return the 'base' register class for this register.
156  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
158 
159  /// \returns true if this class contains only SGPR registers
160  bool isSGPRClass(const TargetRegisterClass *RC) const {
161  return !hasVGPRs(RC) && !hasAGPRs(RC);
162  }
163 
164  /// \returns true if this class ID contains only SGPR registers
165  bool isSGPRClassID(unsigned RCID) const {
166  return isSGPRClass(getRegClass(RCID));
167  }
168 
169  bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
170 
171  /// \returns true if this class contains only VGPR registers
172  bool isVGPRClass(const TargetRegisterClass *RC) const {
173  return hasVGPRs(RC) && !hasAGPRs(RC);
174  }
175 
176  /// \returns true if this class contains only AGPR registers
177  bool isAGPRClass(const TargetRegisterClass *RC) const {
178  return hasAGPRs(RC) && !hasVGPRs(RC);
179  }
180 
181  /// \returns true if this class contains VGPR registers.
182  bool hasVGPRs(const TargetRegisterClass *RC) const;
183 
184  /// \returns true if this class contains AGPR registers.
185  bool hasAGPRs(const TargetRegisterClass *RC) const;
186 
187  /// \returns true if this class contains any vector registers.
188  bool hasVectorRegisters(const TargetRegisterClass *RC) const {
189  return hasVGPRs(RC) || hasAGPRs(RC);
190  }
191 
192  /// \returns A VGPR reg class with the same width as \p SRC
193  const TargetRegisterClass *
195 
196  /// \returns An AGPR reg class with the same width as \p SRC
197  const TargetRegisterClass *
199 
200  /// \returns A SGPR reg class with the same width as \p SRC
201  const TargetRegisterClass *
203 
204  /// \returns The canonical register class that is used for a sub-register of
205  /// \p RC for the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC
206  /// will be returned.
208  unsigned SubIdx) const;
209 
210  /// Returns a register class which is compatible with \p SuperRC, such that a
211  /// subregister exists with class \p SubRC with subregister index \p
212  /// SubIdx. If this is impossible (e.g., an unaligned subregister index within
213  /// a register tuple), return null.
214  const TargetRegisterClass *
216  const TargetRegisterClass *SubRC,
217  unsigned SubIdx) const;
218 
219  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
220  unsigned DefSubReg,
221  const TargetRegisterClass *SrcRC,
222  unsigned SrcSubReg) const override;
223 
224  /// \returns True if operands defined with this operand type can accept
225  /// a literal constant (i.e. any 32-bit immediate).
226  bool opCanUseLiteralConstant(unsigned OpType) const;
227 
228  /// \returns True if operands defined with this operand type can accept
229  /// an inline constant. i.e. An integer value in the range (-16, 64) or
230  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
231  bool opCanUseInlineConstant(unsigned OpType) const;
232 
234  const TargetRegisterClass *RC,
235  const MachineFunction &MF,
236  bool ReserveHighestVGPR = false) const;
237 
239  Register Reg) const;
240  bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
241  bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
243  return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
244  }
245 
246  bool isConstantPhysReg(MCRegister PhysReg) const override;
247 
248  bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
249  return !isSGPRClass(RC);
250  }
251 
253  unsigned EltSize) const;
254 
256  const TargetRegisterClass *SrcRC,
257  unsigned SubReg,
258  const TargetRegisterClass *DstRC,
259  unsigned DstSubReg,
260  const TargetRegisterClass *NewRC,
261  LiveIntervals &LIS) const override;
262 
263  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
264  MachineFunction &MF) const override;
265 
266  unsigned getRegPressureSetLimit(const MachineFunction &MF,
267  unsigned Idx) const override;
268 
269  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
270 
272 
273  const TargetRegisterClass *
275  const RegisterBank &Bank,
276  const MachineRegisterInfo &MRI) const;
277 
278  const TargetRegisterClass *
280  const RegisterBank &Bank,
281  const MachineRegisterInfo &MRI) const {
282  return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
283  }
284 
285  const TargetRegisterClass *
287  const MachineRegisterInfo &MRI) const override;
288 
290  return isWave32 ? &AMDGPU::SReg_32RegClass
291  : &AMDGPU::SReg_64RegClass;
292  }
293 
295  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
296  : &AMDGPU::SReg_64_XEXECRegClass;
297  }
298 
299  // Return the appropriate register class to use for 64-bit VGPRs for the
300  // subtarget.
301  const TargetRegisterClass *getVGPR64Class() const;
302 
303  MCRegister getVCC() const;
304 
305  const TargetRegisterClass *getRegClass(unsigned RCID) const;
306 
307  // Find reaching register definition
309  MachineInstr &Use,
311  LiveIntervals *LIS) const;
312 
313  const uint32_t *getAllVGPRRegMask() const;
314  const uint32_t *getAllAGPRRegMask() const;
315  const uint32_t *getAllVectorRegMask() const;
316  const uint32_t *getAllAllocatableSRegMask() const;
317 
318  // \returns number of 32 bit registers covered by a \p LM
319  static unsigned getNumCoveredRegs(LaneBitmask LM) {
320  // The assumption is that every lo16 subreg is an even bit and every hi16
321  // is an adjacent odd bit or vice versa.
322  uint64_t Mask = LM.getAsInteger();
323  uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;
324  Mask = (Even >> 1) | Mask;
325  uint64_t Odd = Mask & 0x5555555555555555ULL;
326  return countPopulation(Odd);
327  }
328 
329  // \returns a DWORD offset of a \p SubReg
330  unsigned getChannelFromSubReg(unsigned SubReg) const {
331  return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
332  }
333 
334  // \returns a DWORD size of a \p SubReg
335  unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
336  return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
337  }
338 
339  // For a given 16 bit \p Reg \returns a 32 bit register holding it.
340  // \returns \p Reg otherwise.
342 
343  // Returns true if a given register class is properly aligned for
344  // the subtarget.
345  bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
346 
347  /// Return all SGPR128 which satisfy the waves per execution unit requirement
348  /// of the subtarget.
350 
351  /// Return all SGPR64 which satisfy the waves per execution unit requirement
352  /// of the subtarget.
354 
355  /// Return all SGPR32 which satisfy the waves per execution unit requirement
356  /// of the subtarget.
358 
359  // Insert spill or restore instructions.
360  // When lowering spill pseudos, the RegScavenger should be set.
361  // For creating spill instructions during frame lowering, where no scavenger
362  // is available, LiveRegs can be used.
364  MachineBasicBlock::iterator MI, unsigned LoadStoreOp,
365  int Index, Register ValueReg, bool ValueIsKill,
366  MCRegister ScratchOffsetReg, int64_t InstrOffset,
368  LivePhysRegs *LiveRegs = nullptr) const;
369 };
370 
371 } // End namespace llvm
372 
373 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:1991
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:344
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2178
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SIRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:2537
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:666
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2439
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:638
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1452
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2551
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:652
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2383
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:644
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2557
llvm::SIRegisterInfo::isSGPRClassID
bool isSGPRClassID(unsigned RCID) const
Definition: SIRegisterInfo.h:165
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:273
llvm::SIRegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: SIRegisterInfo.h:74
llvm::SIRegisterInfo::getWaveMaskRegClass
const TargetRegisterClass * getWaveMaskRegClass() const
Definition: SIRegisterInfo.h:294
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2186
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:680
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:423
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:632
llvm::SIRegisterInfo::hasAGPRs
bool hasAGPRs(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:2173
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SIRegisterInfo::isAGPRClass
bool isAGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:177
llvm::SIRegisterInfo::getSubRegClass
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
Definition: SIRegisterInfo.cpp:2203
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1303
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:2454
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.h:279
llvm::SIRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
Definition: SIRegisterInfo.cpp:805
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:387
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2392
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2309
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2321
llvm::SIRegisterInfo::getHWRegIndex
unsigned getHWRegIndex(MCRegister Reg) const
Definition: SIRegisterInfo.h:142
llvm::SIRegisterInfo::getChannelFromSubReg
unsigned getChannelFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:330
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:1569
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2350
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:335
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:427
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:28
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:368
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:2428
llvm::BitVector
Definition: BitVector.h:74
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:2432
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SIRegisterInfo::isDivergentRegClass
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
Definition: SIRegisterInfo.h:248
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2267
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:780
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:409
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:411
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2243
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:599
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:1938
uint64_t
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:623
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:402
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1047
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:419
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.cpp:2398
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2159
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2314
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:289
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2293
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:415
llvm::SIRegisterInfo::isSGPRClass
bool isSGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:160
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:383
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:2508
llvm::ArrayRef< int16_t >
llvm::SIRegisterInfo::getNumCoveredRegs
static unsigned getNumCoveredRegs(LaneBitmask LM)
Definition: SIRegisterInfo.h:319
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:2525
llvm::SIRegisterInfo::spillSGPRToVGPR
bool spillSGPRToVGPR() const
Definition: SIRegisterInfo.h:56
uint32_t
llvm::LaneBitmask::getAsInteger
constexpr Type getAsInteger() const
Definition: LaneBitmask.h:74
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:364
llvm::SIRegisterInfo::hasVectorRegisters
bool hasVectorRegisters(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:188
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:731
llvm::SIRegisterInfo::hasVGPRs
bool hasVGPRs(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:2169
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:70
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2369
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2563
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
uint16_t
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1536
AMDGPUGenRegisterInfo
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1336
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:612
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:2418
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2277
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2225
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2051
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2234
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2329
llvm::SIRegisterInfo::isVectorRegister
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.h:242
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2194
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:436
llvm::SIRegisterInfo::isVGPRClass
bool isVGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:172
llvm::SIRegisterInfo::getPhysRegClass
const TargetRegisterClass * getPhysRegClass(MCRegister Reg) const
Return the 'base' register class for this register.
Definition: SIRegisterInfo.cpp:2091
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:443
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:796
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2061
llvm::LLT
Definition: LowLevelTypeImpl.h:40