LLVM  13.0.0git
SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "AMDGPUGenRegisterInfo.inc"
19 
20 namespace llvm {
21 
22 class GCNSubtarget;
23 class LiveIntervals;
24 class LivePhysRegs;
25 class RegisterBank;
26 struct SGPRSpillBuilder;
27 class SIMachineFunctionInfo;
28 
29 class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
30 private:
31  const GCNSubtarget &ST;
32  bool SpillSGPRToVGPR;
33  bool isWave32;
34  BitVector RegPressureIgnoredUnits;
35 
36  /// Sub reg indexes for getRegSplitParts.
37  /// First index represents subreg size from 1 to 16 DWORDs.
38  /// The inner vector is sorted by bit offset.
39  /// Provided a register can be fully split with given subregs,
40  /// all elements of the inner vector combined give a full lane mask.
41  static std::array<std::vector<int16_t>, 16> RegSplitParts;
42 
43  // Table representing sub reg of given width and offset.
44  // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
45  // Second index is 32 different dword offsets.
46  static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
47 
48  void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
49 
50 public:
51  SIRegisterInfo(const GCNSubtarget &ST);
52 
53  /// \returns the sub reg enum value for the given \p Channel
54  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
55  static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
56 
57  bool spillSGPRToVGPR() const {
58  return SpillSGPRToVGPR;
59  }
60 
61  /// Return the end register initially reserved for the scratch buffer in case
62  /// spilling is needed.
64 
65  BitVector getReservedRegs(const MachineFunction &MF) const override;
66 
67  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
68  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
70  CallingConv::ID) const override;
71  const uint32_t *getNoPreservedMask() const override;
72 
73  // Stack access is very expensive. CSRs are also the high registers, and we
74  // want to minimize the number of used registers.
75  unsigned getCSRFirstUseCost() const override {
76  return 100;
77  }
78 
79  Register getFrameRegister(const MachineFunction &MF) const override;
80 
81  bool hasBasePointer(const MachineFunction &MF) const;
82  Register getBaseRegister() const;
83 
84  bool shouldRealignStack(const MachineFunction &MF) const override;
85  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
86 
87  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
89  const MachineFunction &MF) const override;
90  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
91 
92  int64_t getScratchInstrOffset(const MachineInstr *MI) const;
93 
95  int Idx) const override;
96 
97  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
98 
100  int64_t Offset) const override;
101 
102  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
103  int64_t Offset) const override;
104 
105  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
106  int64_t Offset) const override;
107 
109  const MachineFunction &MF, unsigned Kind = 0) const override;
110 
112  bool IsLoad, bool IsKill = true) const;
113 
115  int64_t VGPRLanes) const;
116 
117  /// If \p OnlyToVGPR is true, this will only succeed if this
119  int FI, RegScavenger *RS,
120  bool OnlyToVGPR = false) const;
121 
123  int FI, RegScavenger *RS,
124  bool OnlyToVGPR = false) const;
125 
127  unsigned FIOperandNum,
128  RegScavenger *RS) const override;
129 
131  int FI, RegScavenger *RS) const;
132 
133  StringRef getRegAsmName(MCRegister Reg) const override;
134 
135  // Pseudo regs are not allowed
136  unsigned getHWRegIndex(MCRegister Reg) const {
137  return getEncodingValue(Reg) & 0xff;
138  }
139 
142 
145 
147  static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
148 
149  /// Return the 'base' register class for this register.
150  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
152 
153  /// \returns true if this class contains only SGPR registers
154  bool isSGPRClass(const TargetRegisterClass *RC) const {
155  return !hasVGPRs(RC) && !hasAGPRs(RC);
156  }
157 
158  /// \returns true if this class ID contains only SGPR registers
159  bool isSGPRClassID(unsigned RCID) const {
160  return isSGPRClass(getRegClass(RCID));
161  }
162 
163  bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
164 
165  /// \returns true if this class contains only AGPR registers
166  bool isAGPRClass(const TargetRegisterClass *RC) const {
167  return hasAGPRs(RC) && !hasVGPRs(RC);
168  }
169 
170  /// \returns true if this class contains VGPR registers.
171  bool hasVGPRs(const TargetRegisterClass *RC) const;
172 
173  /// \returns true if this class contains AGPR registers.
174  bool hasAGPRs(const TargetRegisterClass *RC) const;
175 
176  /// \returns true if this class contains any vector registers.
177  bool hasVectorRegisters(const TargetRegisterClass *RC) const {
178  return hasVGPRs(RC) || hasAGPRs(RC);
179  }
180 
181  /// \returns A VGPR reg class with the same width as \p SRC
182  const TargetRegisterClass *
184 
185  /// \returns An AGPR reg class with the same width as \p SRC
186  const TargetRegisterClass *
188 
189  /// \returns A SGPR reg class with the same width as \p SRC
190  const TargetRegisterClass *
192 
193  /// \returns The canonical register class that is used for a sub-register of
194  /// \p RC for the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC
195  /// will be returned.
197  unsigned SubIdx) const;
198 
199  /// Returns a register class which is compatible with \p SuperRC, such that a
200  /// subregister exists with class \p SubRC with subregister index \p
201  /// SubIdx. If this is impossible (e.g., an unaligned subregister index within
202  /// a register tuple), return null.
203  const TargetRegisterClass *
205  const TargetRegisterClass *SubRC,
206  unsigned SubIdx) const;
207 
208  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
209  unsigned DefSubReg,
210  const TargetRegisterClass *SrcRC,
211  unsigned SrcSubReg) const override;
212 
213  /// \returns True if operands defined with this operand type can accept
214  /// a literal constant (i.e. any 32-bit immediate).
215  bool opCanUseLiteralConstant(unsigned OpType) const;
216 
217  /// \returns True if operands defined with this operand type can accept
218  /// an inline constant. i.e. An integer value in the range (-16, 64) or
219  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
220  bool opCanUseInlineConstant(unsigned OpType) const;
221 
223  const TargetRegisterClass *RC,
224  const MachineFunction &MF,
225  bool ReserveHighestVGPR = false) const;
226 
228  Register Reg) const;
229  bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
230  bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232  return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
233  }
234 
235  bool isConstantPhysReg(MCRegister PhysReg) const override;
236 
237  bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
238  return !isSGPRClass(RC);
239  }
240 
242  unsigned EltSize) const;
243 
245  const TargetRegisterClass *SrcRC,
246  unsigned SubReg,
247  const TargetRegisterClass *DstRC,
248  unsigned DstSubReg,
249  const TargetRegisterClass *NewRC,
250  LiveIntervals &LIS) const override;
251 
252  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
253  MachineFunction &MF) const override;
254 
255  unsigned getRegPressureSetLimit(const MachineFunction &MF,
256  unsigned Idx) const override;
257 
258  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
259 
261 
262  const TargetRegisterClass *
264  const RegisterBank &Bank,
265  const MachineRegisterInfo &MRI) const;
266 
267  const TargetRegisterClass *
269  const RegisterBank &Bank,
270  const MachineRegisterInfo &MRI) const {
271  return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
272  }
273 
274  const TargetRegisterClass *
276  const MachineRegisterInfo &MRI) const override;
277 
279  return isWave32 ? &AMDGPU::SReg_32RegClass
280  : &AMDGPU::SReg_64RegClass;
281  }
282 
284  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
285  : &AMDGPU::SReg_64_XEXECRegClass;
286  }
287 
288  // Return the appropriate register class to use for 64-bit VGPRs for the
289  // subtarget.
290  const TargetRegisterClass *getVGPR64Class() const;
291 
292  MCRegister getVCC() const;
293 
294  const TargetRegisterClass *getRegClass(unsigned RCID) const;
295 
296  // Find reaching register definition
298  MachineInstr &Use,
300  LiveIntervals *LIS) const;
301 
302  const uint32_t *getAllVGPRRegMask() const;
303  const uint32_t *getAllAGPRRegMask() const;
304  const uint32_t *getAllVectorRegMask() const;
305  const uint32_t *getAllAllocatableSRegMask() const;
306 
307  // \returns number of 32 bit registers covered by a \p LM
308  static unsigned getNumCoveredRegs(LaneBitmask LM) {
309  // The assumption is that every lo16 subreg is an even bit and every hi16
310  // is an adjacent odd bit or vice versa.
311  uint64_t Mask = LM.getAsInteger();
312  uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;
313  Mask = (Even >> 1) | Mask;
314  uint64_t Odd = Mask & 0x5555555555555555ULL;
315  return countPopulation(Odd);
316  }
317 
318  // \returns a DWORD offset of a \p SubReg
319  unsigned getChannelFromSubReg(unsigned SubReg) const {
320  return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
321  }
322 
323  // \returns a DWORD size of a \p SubReg
324  unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
325  return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
326  }
327 
328  // For a given 16 bit \p Reg \returns a 32 bit register holding it.
329  // \returns \p Reg otherwise.
331 
332  // Returns true if a given register class is properly aligned for
333  // the subtarget.
334  bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
335 
336  /// Return all SGPR128 which satisfy the waves per execution unit requirement
337  /// of the subtarget.
339 
340  /// Return all SGPR64 which satisfy the waves per execution unit requirement
341  /// of the subtarget.
343 
344  /// Return all SGPR32 which satisfy the waves per execution unit requirement
345  /// of the subtarget.
347 
348  // Insert spill or restore instructions.
349  // When lowering spill pseudos, the RegScavenger should be set.
350  // For creating spill instructions during frame lowering, where no scavenger
351  // is available, LiveRegs can be used.
352  void buildSpillLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp,
353  int Index, Register ValueReg, bool ValueIsKill,
354  MCRegister ScratchOffsetReg, int64_t InstrOffset,
356  LivePhysRegs *LiveRegs = nullptr) const;
357 };
358 
359 } // End namespace llvm
360 
361 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:39
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:1918
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:344
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2114
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:212
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SIRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:2473
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:655
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2375
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:627
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2487
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:641
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2319
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:633
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2493
llvm::SIRegisterInfo::isSGPRClassID
bool isSGPRClassID(unsigned RCID) const
Definition: SIRegisterInfo.h:159
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:273
llvm::SIRegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: SIRegisterInfo.h:75
llvm::SIRegisterInfo::getWaveMaskRegClass
const TargetRegisterClass * getWaveMaskRegClass() const
Definition: SIRegisterInfo.h:283
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2122
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:669
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:423
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:621
llvm::SIRegisterInfo::hasAGPRs
bool hasAGPRs(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:2101
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SIRegisterInfo::isAGPRClass
bool isAGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:166
llvm::SIRegisterInfo::getSubRegClass
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
Definition: SIRegisterInfo.cpp:2139
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1275
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:2390
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.h:268
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1406
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:387
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1023
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2328
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2245
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2257
llvm::SIRegisterInfo::getHWRegIndex
unsigned getHWRegIndex(MCRegister Reg) const
Definition: SIRegisterInfo.h:136
llvm::SIRegisterInfo::getChannelFromSubReg
unsigned getChannelFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:319
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:1502
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2286
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1308
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:324
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:427
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:368
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:2364
llvm::BitVector
Definition: BitVector.h:74
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:2368
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SIRegisterInfo::isDivergentRegClass
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
Definition: SIRegisterInfo.h:237
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2203
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:769
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:409
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:411
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2179
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:588
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:1869
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:612
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:402
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:419
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.cpp:2334
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2075
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2250
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:278
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2229
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:415
llvm::SIRegisterInfo::isSGPRClass
bool isSGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:154
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:383
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:2444
llvm::ArrayRef< int16_t >
llvm::SIRegisterInfo::getNumCoveredRegs
static unsigned getNumCoveredRegs(LaneBitmask LM)
Definition: SIRegisterInfo.h:308
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:2461
llvm::SIRegisterInfo::spillSGPRToVGPR
bool spillSGPRToVGPR() const
Definition: SIRegisterInfo.h:57
uint32_t
llvm::LaneBitmask::getAsInteger
constexpr Type getAsInteger() const
Definition: LaneBitmask.h:73
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:364
llvm::SIRegisterInfo::hasVectorRegisters
bool hasVectorRegisters(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:177
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:720
llvm::SIRegisterInfo::hasVGPRs
bool hasVGPRs(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:2087
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:70
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2305
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2499
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
uint16_t
AMDGPUGenRegisterInfo
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1472
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:601
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:2354
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2213
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2161
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:1974
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2170
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2265
llvm::SIRegisterInfo::buildSGPRSpillLoadStore
void buildSGPRSpillLoadStore(SGPRSpillBuilder &SB, int Offset, int64_t VGPRLanes) const
llvm::SIRegisterInfo::isVectorRegister
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.h:231
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2130
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:436
llvm::SIRegisterInfo::getPhysRegClass
const TargetRegisterClass * getPhysRegClass(MCRegister Reg) const
Return the 'base' register class for this register.
Definition: SIRegisterInfo.cpp:2012
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:443
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:785
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:1984
llvm::LLT
Definition: LowLevelTypeImpl.h:40