SIInstrInfo.h File Reference

Interface definition for SIInstrInfo. More...

#include "AMDGPUMIRFormatter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "AMDGPUGenInstrInfo.inc"

Go to the source code of this file.

Classes
struct	llvm::SIInstrWorklist
	Utility to store machine instructions worklist. More...
class	llvm::SIInstrInfo

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::AMDGPU
namespace	llvm::SI
namespace	llvm::SI::KernelInputOffsets

Macros
#define	GET_INSTRINFO_HEADER

Enumerations
enum	llvm::AMDGPU::AsmComments { llvm::AMDGPU::SGPR_SPILL = MachineInstr::TAsmComments }
enum	llvm::SI::KernelInputOffsets::Offsets {   llvm::SI::KernelInputOffsets::NGROUPS_X = 0 , llvm::SI::KernelInputOffsets::NGROUPS_Y = 4 , llvm::SI::KernelInputOffsets::NGROUPS_Z = 8 , llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X = 12 ,   llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y = 16 , llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z = 20 , llvm::SI::KernelInputOffsets::LOCAL_SIZE_X = 24 , llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y = 28 ,   llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z = 32 }
	Offsets in bytes from the start of the input buffer. More...

Functions
bool	llvm::isOfRegClass (const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
	Returns true if a reg:subreg pair P has a TRC class.
TargetInstrInfo::RegSubRegPair	llvm::getRegSubRegPair (const MachineOperand &O)
	Create RegSubRegPair from a register MachineOperand.
TargetInstrInfo::RegSubRegPair	llvm::getRegSequenceSubReg (MachineInstr &MI, unsigned SubReg)
	Return the SubReg component from REG_SEQUENCE.
MachineInstr *	llvm::getVRegSubRegDef (const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
	Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subreg-manipulation pseudos.
bool	llvm::execMayBeModifiedBeforeUse (const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
	Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
bool	llvm::execMayBeModifiedBeforeAnyUse (const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
	Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
LLVM_READONLY int	llvm::AMDGPU::getVOPe64 (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getVOPe32 (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getSDWAOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getDPPOp32 (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getDPPOp64 (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getBasicFromSDWAOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getCommuteRev (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getCommuteOrig (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getAddr64Inst (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getIfAddr64Inst (uint16_t Opcode)
	Check if Opcode is an Addr64 opcode.
LLVM_READONLY int	llvm::AMDGPU::getSOPKOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getGlobalSaddrOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getGlobalVaddrOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getVCMPXNoSDstOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getFlatScratchInstSTfromSS (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getFlatScratchInstSVfromSVS (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getFlatScratchInstSSfromSV (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getFlatScratchInstSVfromSS (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getMFMAEarlyClobberOp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getMFMASrcCVDstAGPROp (uint16_t Opcode)
LLVM_READONLY int	llvm::AMDGPU::getVCMPXOpFromVCMP (uint16_t Opcode)

Variables
constexpr unsigned	llvm::DefaultMemoryClusterDWordsLimit = 8
static const MachineMemOperand::Flags	llvm::MONoClobber
	Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the start of an entry function to this load.
static const MachineMemOperand::Flags	llvm::MOLastUse
	Mark the MMO of a load as the last use.
static const MachineMemOperand::Flags	llvm::MOCooperative
	Mark the MMO of cooperative load/store atomics.
const uint64_t	llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t	llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
const uint64_t	llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
const uint64_t	llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Detailed Description

Interface definition for SIInstrInfo.

Definition in file SIInstrInfo.h.

Macro Definition Documentation

GET_INSTRINFO_HEADER

#define GET_INSTRINFO_HEADER

Definition at line 25 of file SIInstrInfo.h.