#include "Target/AMDGPU/SILowerI1Copies.h"

Public Member Functions
	PhiLoweringHelper (MachineFunction &MF, MachineDominatorTree &DT, MachinePostDominatorTree &PDT)
virtual	~PhiLoweringHelper ()=default
bool	lowerPhis ()
bool	isConstantLaneMask (Register Reg, bool &Val) const
void	mergeIncomingLaneMasks (Register DstReg, MachineBasicBlock &MBB, SmallVectorImpl< Incoming > &Incomings, MachineIDFSSAUpdater &SSAUpdater, LoopFinder &LF, PhiIncomingAnalysis &PIA)
	Merge the `Incomings` lane masks into `DstReg`, the value owned by `MBB`.
MachineBasicBlock::iterator	getSaluInsertionAtEnd (MachineBasicBlock &MBB) const
	Return a point at the end of the given `MBB` to insert SALU instructions for lane mask calculation.
void	initializeLaneMaskRegisterAttributes (Register LaneMask)
void	initializeLaneMaskRegisterAttributes (MachineRegisterInfo::VRegAttrs Attrs)
bool	isLaneMaskReg (Register Reg) const
virtual void	markAsLaneMask (Register DstReg) const =0
virtual void	getCandidatesForLowering (SmallVectorImpl< MachineInstr * > &Vreg1Phis) const =0
virtual void	collectIncomingValuesFromPhi (const MachineInstr *MI, SmallVectorImpl< Incoming > &Incomings) const =0
virtual void	replaceDstReg (Register NewReg, Register OldReg, MachineBasicBlock *MBB)=0
virtual void	buildMergeLaneMasks (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, Register PrevReg, Register CurReg)=0
virtual void	constrainAsLaneMask (Incoming &In)=0

Protected Attributes
bool	IsWave32 = false
MachineFunction &	MF
MachineDominatorTree &	DT
MachinePostDominatorTree &	PDT
MachineRegisterInfo *	MRI = nullptr
const GCNSubtarget *	ST = nullptr
const SIInstrInfo *	TII = nullptr
MachineRegisterInfo::VRegAttrs	LaneMaskRegAttrs
const AMDGPU::LaneMaskConstants *	LMC = nullptr
DenseSet< Register >	PhiRegisters

Detailed Description

Definition at line 42 of file SILowerI1Copies.h.

Constructor & Destructor Documentation

◆ PhiLoweringHelper()

AMDGPU::PhiLoweringHelper::PhiLoweringHelper	(	MachineFunction &	MF,
		MachineDominatorTree &	DT,
		MachinePostDominatorTree &	PDT )

Definition at line 448 of file SILowerI1Copies.cpp.

References DT, llvm::get(), LMC, MF, MRI, PDT, ST, and TII.

◆ ~PhiLoweringHelper()

virtual llvm::AMDGPU::PhiLoweringHelper::~PhiLoweringHelper ( )

virtualdefault

Member Function Documentation

◆ buildMergeLaneMasks()

virtual void llvm::AMDGPU::PhiLoweringHelper::buildMergeLaneMasks	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DstReg,
		Register	PrevReg,
		Register	CurReg )

pure virtual

References DL, llvm::AMDGPU::I, and MBB.

Referenced by mergeIncomingLaneMasks().

◆ collectIncomingValuesFromPhi()

virtual void llvm::AMDGPU::PhiLoweringHelper::collectIncomingValuesFromPhi	(	const MachineInstr *	MI,
		SmallVectorImpl< Incoming > &	Incomings ) const

pure virtual

References MI.

Referenced by lowerPhis().

◆ constrainAsLaneMask()

virtual void llvm::AMDGPU::PhiLoweringHelper::constrainAsLaneMask ( Incoming & In )

pure virtual

Referenced by mergeIncomingLaneMasks().

◆ getCandidatesForLowering()

virtual void llvm::AMDGPU::PhiLoweringHelper::getCandidatesForLowering ( SmallVectorImpl< MachineInstr * > & Vreg1Phis ) const

pure virtual

Referenced by lowerPhis().

◆ getSaluInsertionAtEnd()

MachineBasicBlock::iterator AMDGPU::PhiLoweringHelper::getSaluInsertionAtEnd ( MachineBasicBlock & MBB ) const

Return a point at the end of the given MBB to insert SALU instructions for lane mask calculation.

Take terminators and SCC into account.

Definition at line 714 of file SILowerI1Copies.cpp.

References llvm::AMDGPU::E, llvm::AMDGPU::I, instrDefsUsesSCC(), llvm_unreachable, and MBB.

Referenced by mergeIncomingLaneMasks().

◆ initializeLaneMaskRegisterAttributes() [1/2]

void llvm::AMDGPU::PhiLoweringHelper::initializeLaneMaskRegisterAttributes ( MachineRegisterInfo::VRegAttrs Attrs )

inline

Definition at line 83 of file SILowerI1Copies.h.

References LaneMaskRegAttrs.

◆ initializeLaneMaskRegisterAttributes() [2/2]

void llvm::AMDGPU::PhiLoweringHelper::initializeLaneMaskRegisterAttributes ( Register LaneMask )

inline

Definition at line 78 of file SILowerI1Copies.h.

References LaneMaskRegAttrs, and MRI.

Referenced by lowerPhis().

◆ isConstantLaneMask()

bool AMDGPU::PhiLoweringHelper::isConstantLaneMask	(	Register	Reg,
		bool &	Val ) const

Definition at line 660 of file SILowerI1Copies.cpp.

References llvm::AMDGPU::Imm, isLaneMaskReg(), LMC, MI, and MRI.

◆ isLaneMaskReg()

bool llvm::AMDGPU::PhiLoweringHelper::isLaneMaskReg ( Register Reg ) const

inline

Definition at line 87 of file SILowerI1Copies.h.

References MRI, Reg, ST, and TII.

Referenced by isConstantLaneMask().

◆ lowerPhis()

bool AMDGPU::PhiLoweringHelper::lowerPhis ( )

Definition at line 542 of file SILowerI1Copies.cpp.

References llvm::SmallVectorImpl< T >::clear(), collectIncomingValuesFromPhi(), llvm::dbgs(), DT, llvm::SmallVectorTemplateCommon< T, typename >::empty(), getCandidatesForLowering(), initializeLaneMaskRegisterAttributes(), LLVM_DEBUG, markAsLaneMask(), MBB, mergeIncomingLaneMasks(), MF, MI, PDT, PhiRegisters, replaceDstReg(), and TII.

◆ markAsLaneMask()

virtual void llvm::AMDGPU::PhiLoweringHelper::markAsLaneMask ( Register DstReg ) const

pure virtual

Referenced by lowerPhis().

◆ mergeIncomingLaneMasks()

void AMDGPU::PhiLoweringHelper::mergeIncomingLaneMasks	(	Register	DstReg,
		MachineBasicBlock &	MBB,
		SmallVectorImpl< Incoming > &	Incomings,
		MachineIDFSSAUpdater &	SSAUpdater,
		LoopFinder &	LF,
		PhiIncomingAnalysis &	PIA )

Merge the Incomings lane masks into DstReg, the value owned by MBB.

Builds the per-predecessor merges and leaves SSAUpdater calculated so the caller can query the merged value with getValueInMiddleOfBlock. Incomings is sorted and its UpdatedReg fields are filled in.

Definition at line 458 of file SILowerI1Copies.cpp.

References llvm::AMDGPU::LoopFinder::addLoopEntries(), llvm::AMDGPU::PhiIncomingAnalysis::analyze(), llvm::AMDGPU::Incoming::Block, buildMergeLaneMasks(), constrainAsLaneMask(), llvm::AMDGPU::createLaneMaskReg(), DT, llvm::AMDGPU::LoopFinder::findLoop(), getSaluInsertionAtEnd(), llvm::AMDGPU::LoopFinder::initialize(), insertUndefLaneMask(), llvm::AMDGPU::PhiIncomingAnalysis::isSource(), llvm::Register::isValid(), LaneMaskRegAttrs, MBB, MRI, PDT, llvm::AMDGPU::PhiIncomingAnalysis::predecessors(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::Incoming::Reg, llvm::sort(), and llvm::AMDGPU::Incoming::UpdatedReg.

Referenced by lowerPhis().

◆ replaceDstReg()

virtual void llvm::AMDGPU::PhiLoweringHelper::replaceDstReg	(	Register	NewReg,
		Register	OldReg,
		MachineBasicBlock *	MBB )

pure virtual

References MBB.

Referenced by lowerPhis().

Member Data Documentation

◆ DT

MachineDominatorTree& llvm::AMDGPU::PhiLoweringHelper::DT

protected

Definition at line 51 of file SILowerI1Copies.h.

Referenced by lowerPhis(), mergeIncomingLaneMasks(), and PhiLoweringHelper().

◆ IsWave32

bool llvm::AMDGPU::PhiLoweringHelper::IsWave32 = false

protected

Definition at line 49 of file SILowerI1Copies.h.

◆ LaneMaskRegAttrs

MachineRegisterInfo::VRegAttrs llvm::AMDGPU::PhiLoweringHelper::LaneMaskRegAttrs

protected

Definition at line 56 of file SILowerI1Copies.h.

Referenced by initializeLaneMaskRegisterAttributes(), initializeLaneMaskRegisterAttributes(), and mergeIncomingLaneMasks().

◆ LMC

const AMDGPU::LaneMaskConstants* llvm::AMDGPU::PhiLoweringHelper::LMC = nullptr

protected

Definition at line 57 of file SILowerI1Copies.h.

Referenced by isConstantLaneMask(), and PhiLoweringHelper().

◆ MF

MachineFunction& llvm::AMDGPU::PhiLoweringHelper::MF

protected

Definition at line 50 of file SILowerI1Copies.h.

Referenced by lowerPhis(), and PhiLoweringHelper().

◆ MRI

MachineRegisterInfo* llvm::AMDGPU::PhiLoweringHelper::MRI = nullptr

protected

Definition at line 53 of file SILowerI1Copies.h.

Referenced by initializeLaneMaskRegisterAttributes(), isConstantLaneMask(), isLaneMaskReg(), mergeIncomingLaneMasks(), and PhiLoweringHelper().

◆ PDT

MachinePostDominatorTree& llvm::AMDGPU::PhiLoweringHelper::PDT

protected

Definition at line 52 of file SILowerI1Copies.h.

Referenced by lowerPhis(), mergeIncomingLaneMasks(), and PhiLoweringHelper().

◆ PhiRegisters

DenseSet<Register> llvm::AMDGPU::PhiLoweringHelper::PhiRegisters

protected

Definition at line 60 of file SILowerI1Copies.h.

Referenced by lowerPhis().

◆ ST

const GCNSubtarget* llvm::AMDGPU::PhiLoweringHelper::ST = nullptr

protected

Definition at line 54 of file SILowerI1Copies.h.

Referenced by isLaneMaskReg(), and PhiLoweringHelper().

◆ TII

const SIInstrInfo* llvm::AMDGPU::PhiLoweringHelper::TII = nullptr

protected

Definition at line 55 of file SILowerI1Copies.h.

Referenced by isLaneMaskReg(), lowerPhis(), and PhiLoweringHelper().

The documentation for this class was generated from the following files:

lib/Target/AMDGPU/SILowerI1Copies.h
lib/Target/AMDGPU/SILowerI1Copies.cpp

Public Member Functions

Protected Attributes

Detailed Description

Constructor & Destructor Documentation

◆ PhiLoweringHelper()

◆ ~PhiLoweringHelper()

Member Function Documentation

◆ buildMergeLaneMasks()

◆ collectIncomingValuesFromPhi()

◆ constrainAsLaneMask()

◆ getCandidatesForLowering()

◆ getSaluInsertionAtEnd()

◆ initializeLaneMaskRegisterAttributes() [1/2]

◆ initializeLaneMaskRegisterAttributes() [2/2]

◆ isConstantLaneMask()

◆ isLaneMaskReg()

◆ lowerPhis()

◆ markAsLaneMask()

◆ mergeIncomingLaneMasks()

◆ replaceDstReg()

Member Data Documentation

◆ DT

◆ IsWave32

◆ LaneMaskRegAttrs

◆ LMC

◆ MF

◆ MRI

◆ PDT

◆ PhiRegisters

◆ ST

◆ TII