31 : PointerSize(PointerSize), Bound(0) {}
62 SPIRV::AccessQualifier::AccessQualifier AccessQual,
bool EmitIR) {
72 VRegToTypeMap[&MF][VReg] = SpirvType;
78 MRI.setRegClass(Res, &SPIRV::TYPERegClass);
84 MRI.setRegClass(Res, &SPIRV::TYPERegClass);
89 return MIRBuilder.
buildInstr(SPIRV::OpTypeBool)
96 assert(Width <= 64 &&
"Unsupported integer width!");
99 if (
ST.canUseExtension(
100 SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers)) {
102 .
addImm(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers);
104 .
addImm(SPIRV::Capability::ArbitraryPrecisionIntegersINTEL);
105 }
else if (Width <= 8)
107 else if (Width <= 16)
109 else if (Width <= 32)
111 else if (Width <= 64)
114 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpTypeInt)
117 .
addImm(IsSigned ? 1 : 0);
123 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpTypeFloat)
130 return MIRBuilder.
buildInstr(SPIRV::OpTypeVoid)
139 assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||
140 EleOpc == SPIRV::OpTypeBool) &&
141 "Invalid vector element type");
143 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpTypeVector)
150std::tuple<Register, ConstantInt *, bool>
160 bool NewInstr =
false;
178 return std::make_tuple(Res, CI, NewInstr);
181std::tuple<Register, ConstantFP *, bool, unsigned>
182SPIRVGlobalRegistry::getOrCreateConstFloatReg(
APFloat Val,
SPIRVType *SpvType,
186 const Type *LLVMFloatTy;
196 bool NewInstr =
false;
198 auto *
const CI = ConstantFP::get(Ctx, Val);
215 return std::make_tuple(Res, CI, NewInstr,
BitWidth);
228 getOrCreateConstFloatReg(Val, SpvType,
nullptr, &
I, &
TII);
231 if (!New && (!
I.getOperand(0).isReg() || Res !=
I.getOperand(0).getReg()))
237 MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpConstantNull))
241 MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpConstantF))
250 *ST.getRegisterInfo(), *ST.getRegBankInfo());
262 std::tie(Res, CI, New) =
263 getOrCreateConstIntReg(Val, SpvType,
nullptr, &
I, &
TII);
266 if (!New && (!
I.getOperand(0).isReg() || Res !=
I.getOperand(0).getReg()))
270 if (Val || !ZeroAsNull) {
271 MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpConstantI))
276 MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpConstantNull))
282 *ST.getRegisterInfo(), *ST.getRegBankInfo());
290 auto &MF = MIRBuilder.
getMF();
297 const auto ConstInt =
298 ConstantInt::get(
const_cast<IntegerType *
>(LLVMIntTy), Val);
303 Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
304 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
306 SPIRV::AccessQualifier::ReadWrite, EmitIR);
307 DT.
add(ConstInt, &MIRBuilder.
getMF(), Res);
314 MIB = MIRBuilder.
buildInstr(SPIRV::OpConstantI)
320 MIB = MIRBuilder.
buildInstr(SPIRV::OpConstantNull)
326 *Subtarget.getRegisterInfo(),
327 *Subtarget.getRegBankInfo());
336 auto &MF = MIRBuilder.
getMF();
337 auto &Ctx = MF.getFunction().getContext();
343 const auto ConstFP = ConstantFP::get(Ctx, Val);
346 Res = MF.getRegInfo().createGenericVirtualRegister(
LLT::scalar(32));
347 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
349 DT.
add(ConstFP, &MF, Res);
352 MIB = MIRBuilder.
buildInstr(SPIRV::OpConstantF)
355 addNumImm(ConstFP->getValueAPF().bitcastToAPInt(), MIB);
367 if (SpvType->
getOpcode() == SPIRV::OpTypeVector ||
368 SpvType->
getOpcode() == SPIRV::OpTypeArray) {
372 if (
Type->getOpcode() == SPIRV::OpTypeFloat) {
377 assert(
Type->getOpcode() == SPIRV::OpTypeInt);
383Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
386 unsigned ElemCnt,
bool ZeroAsNull) {
397 SpvScalConst = getOrCreateBaseRegister(Val,
I, SpvType,
TII,
BitWidth);
410 MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpConstantComposite))
413 for (
unsigned i = 0; i < ElemCnt; ++i)
416 MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpConstantNull))
422 *Subtarget.getRegisterInfo(),
423 *Subtarget.getRegBankInfo());
439 auto *ConstVal = ConstantInt::get(LLVMBaseTy, Val);
443 return getOrCreateCompositeOrNull(ConstVal,
I, SpvType,
TII, ConstVec, BW,
458 auto *ConstVal = ConstantFP::get(LLVMBaseTy, Val);
462 return getOrCreateCompositeOrNull(ConstVal,
I, SpvType,
TII, ConstVec, BW,
473 const ArrayType *LLVMArrTy = cast<ArrayType>(LLVMTy);
475 auto *ConstInt = ConstantInt::get(LLVMBaseTy, Val);
480 return getOrCreateCompositeOrNull(ConstInt,
I, SpvType,
TII, ConstArr, BW,
484Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
505 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpConstantComposite)
508 for (
unsigned i = 0; i < ElemCnt; ++i)
529 const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val);
533 return getOrCreateIntCompositeOrNull(Val, MIRBuilder, SpvType, EmitIR,
544 const ArrayType *LLVMArrTy = cast<ArrayType>(LLVMTy);
546 const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val);
551 return getOrCreateIntCompositeOrNull(Val, MIRBuilder, SpvType, EmitIR,
585 MIRBuilder)) ==
nullptr)
592 auto Res = MIRBuilder.
buildInstr(SPIRV::OpConstantSampler)
598 assert(Res->getOperand(0).isReg());
599 return Res->getOperand(0).getReg();
604 const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage,
607 bool IsInstSelector) {
610 GVar = cast<const GlobalVariable>(GV);
615 GVar = M->getGlobalVariable(
Name);
616 if (GVar ==
nullptr) {
632 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpVariable)
643 if (IsInstSelector) {
646 *Subtarget.getRegisterInfo(),
647 *Subtarget.getRegBankInfo());
650 DT.
add(GVar, &MIRBuilder.
getMF(), Reg);
654 assert(
MRI->getType(ResVReg).isPointer() &&
"Pointer type is expected");
655 if (Reg != ResVReg) {
658 MRI->setType(Reg, RegLLTy);
665 if (!DefType || DefType !=
BaseType)
677 if (IsConst && ST.isOpenCLEnv())
682 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Alignment, {Alignment});
689 SPIRV::BuiltIn::BuiltIn BuiltInId;
692 {
static_cast<uint32_t>(BuiltInId)});
702 "Invalid array element type");
705 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpTypeArray)
727 for (
const auto &Elem : Ty->
elements()) {
731 "Invalid struct element type");
736 for (
const auto &Ty : FieldTypes)
745SPIRVType *SPIRVGlobalRegistry::getOrCreateSpecialType(
747 SPIRV::AccessQualifier::AccessQualifier AccQual) {
752SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(
753 SPIRV::StorageClass::StorageClass SC,
SPIRVType *ElemType,
757 return MIRBuilder.
buildInstr(SPIRV::OpTypePointer)
763SPIRVType *SPIRVGlobalRegistry::getOpTypeForwardPointer(
765 return MIRBuilder.
buildInstr(SPIRV::OpTypeForwardPointer)
770SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction(
773 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpTypeFunction)
776 for (
const SPIRVType *ArgType : ArgTypes)
788 SPIRVType *SpirvType = getOpTypeFunction(RetType, ArgTypes, MIRBuilder);
790 return finishCreatingSPIRVType(Ty, SpirvType);
793SPIRVType *SPIRVGlobalRegistry::findSPIRVType(
795 SPIRV::AccessQualifier::AccessQualifier AccQual,
bool EmitIR) {
799 if (ForwardPointerTypes.contains(Ty))
800 return ForwardPointerTypes[Ty];
801 return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, EmitIR);
805 assert(SpirvType &&
"Attempting to get type id for nullptr type.");
806 if (SpirvType->
getOpcode() == SPIRV::OpTypeForwardPointer)
807 return SpirvType->
uses().begin()->getReg();
808 return SpirvType->
defs().begin()->getReg();
811SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
813 SPIRV::AccessQualifier::AccessQualifier AccQual,
bool EmitIR) {
815 return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);
816 auto &TypeToSPIRVTypeMap = DT.
getTypes()->getAllUses();
817 auto t = TypeToSPIRVTypeMap.find(Ty);
818 if (t != TypeToSPIRVTypeMap.end()) {
819 auto tt = t->second.find(&MIRBuilder.
getMF());
820 if (tt != t->second.end())
824 if (
auto IType = dyn_cast<IntegerType>(Ty)) {
825 const unsigned Width = IType->getBitWidth();
826 return Width == 1 ? getOpTypeBool(MIRBuilder)
827 : getOpTypeInt(Width, MIRBuilder,
false);
832 return getOpTypeVoid(MIRBuilder);
835 findSPIRVType(cast<FixedVectorType>(Ty)->getElementType(), MIRBuilder);
836 return getOpTypeVector(cast<FixedVectorType>(Ty)->getNumElements(), El,
843 if (
auto SType = dyn_cast<StructType>(Ty)) {
844 if (SType->isOpaque())
845 return getOpTypeOpaque(SType, MIRBuilder);
846 return getOpTypeStruct(SType, MIRBuilder, EmitIR);
848 if (
auto FType = dyn_cast<FunctionType>(Ty)) {
849 SPIRVType *
RetTy = findSPIRVType(FType->getReturnType(), MIRBuilder);
851 for (
const auto &t : FType->params()) {
852 ParamTypes.
push_back(findSPIRVType(t, MIRBuilder));
854 return getOpTypeFunction(
RetTy, ParamTypes, MIRBuilder);
856 unsigned AddrSpace = 0xFFFF;
857 if (
auto PType = dyn_cast<TypedPointerType>(Ty))
858 AddrSpace = PType->getAddressSpace();
859 else if (
auto PType = dyn_cast<PointerType>(Ty))
860 AddrSpace = PType->getAddressSpace();
865 if (
auto PType = dyn_cast<TypedPointerType>(Ty))
877 if (SpvElementType ==
nullptr) {
878 if (!ForwardPointerTypes.contains(Ty))
879 ForwardPointerTypes[Ty] = getOpTypeForwardPointer(SC, MIRBuilder);
880 return ForwardPointerTypes[Ty];
884 if (ForwardPointerTypes.contains(Ty)) {
886 return getOpTypePointer(SC, SpvElementType, MIRBuilder, Reg);
892SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(
894 SPIRV::AccessQualifier::AccessQualifier AccessQual,
bool EmitIR) {
895 if (TypesInProcessing.count(Ty) && !
isPointerTy(Ty))
897 TypesInProcessing.insert(Ty);
898 SPIRVType *SpirvType = createSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR);
899 TypesInProcessing.erase(Ty);
901 SPIRVToLLVMType[SpirvType] = Ty;
905 if (SpirvType->
getOpcode() != SPIRV::OpTypeForwardPointer && !
Reg.isValid() &&
910 DT.
add(cast<TypedPointerType>(Ty)->getElementType(),
925 auto t = VRegToTypeMap.find(MF ? MF :
CurMF);
926 if (t != VRegToTypeMap.end()) {
927 auto tt = t->second.find(VReg);
928 if (tt != t->second.end())
936 SPIRV::AccessQualifier::AccessQualifier AccessQual,
bool EmitIR) {
941 Reg = DT.
find(cast<TypedPointerType>(Ty)->getElementType(),
950 TypesInProcessing.clear();
951 SPIRVType *STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR);
953 for (
auto &
CU : ForwardPointerTypes) {
954 const Type *Ty2 =
CU.first;
956 if ((Reg = DT.
find(Ty2, &MIRBuilder.
getMF())).isValid())
959 STy2 = restOfCreateSPIRVType(Ty2, MIRBuilder, AccessQual, EmitIR);
963 ForwardPointerTypes.clear();
968 unsigned TypeOpcode)
const {
970 assert(
Type &&
"isScalarOfType VReg has no type assigned");
971 return Type->getOpcode() == TypeOpcode;
975 unsigned TypeOpcode)
const {
977 assert(
Type &&
"isScalarOrVectorOfType VReg has no type assigned");
978 if (
Type->getOpcode() == TypeOpcode)
980 if (
Type->getOpcode() == SPIRV::OpTypeVector) {
983 return ScalarType->
getOpcode() == TypeOpcode;
997 return Type->getOpcode() == SPIRV::OpTypeVector
998 ?
static_cast<unsigned>(
Type->getOperand(2).getImm())
1005 if (
Type->getOpcode() == SPIRV::OpTypeVector) {
1006 auto EleTypeReg =
Type->getOperand(1).getReg();
1009 if (
Type->getOpcode() == SPIRV::OpTypeInt ||
1010 Type->getOpcode() == SPIRV::OpTypeFloat)
1011 return Type->getOperand(1).getImm();
1012 if (
Type->getOpcode() == SPIRV::OpTypeBool)
1014 llvm_unreachable(
"Attempting to get bit width of non-integer/float type.");
1020 unsigned NumElements = 1;
1021 if (
Type->getOpcode() == SPIRV::OpTypeVector) {
1022 NumElements =
static_cast<unsigned>(
Type->getOperand(2).getImm());
1025 return Type->getOpcode() == SPIRV::OpTypeInt ||
1026 Type->getOpcode() == SPIRV::OpTypeFloat
1027 ? NumElements *
Type->getOperand(1).getImm()
1033 if (
Type &&
Type->getOpcode() == SPIRV::OpTypeVector)
1035 return Type &&
Type->getOpcode() == SPIRV::OpTypeInt ?
Type :
nullptr;
1046 PtrType && PtrType->
getOpcode() == SPIRV::OpTypePointer
1049 return ElemType ? ElemType->
getOpcode() : 0;
1054 if (!Type1 || !
Type2)
1060 if (Op1 == SPIRV::OpTypePointer &&
1063 if (Op2 == SPIRV::OpTypePointer &&
1068 return Bits1 > 0 && Bits1 == Bits2;
1071SPIRV::StorageClass::StorageClass
1075 Type->getOperand(1).isImm() &&
"Pointer type is expected");
1076 return static_cast<SPIRV::StorageClass::StorageClass
>(
1077 Type->getOperand(1).getImm());
1083 SPIRV::ImageFormat::ImageFormat ImageFormat,
1084 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1086 Arrayed, Multisampled, Sampled, ImageFormat,
1088 if (
auto *Res = checkSpecialInstr(TD, MIRBuilder))
1091 DT.
add(TD, &MIRBuilder.
getMF(), ResVReg);
1092 return MIRBuilder.
buildInstr(SPIRV::OpTypeImage)
1107 if (
auto *Res = checkSpecialInstr(TD, MIRBuilder))
1110 DT.
add(TD, &MIRBuilder.
getMF(), ResVReg);
1116 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1118 if (
auto *Res = checkSpecialInstr(TD, MIRBuilder))
1121 DT.
add(TD, &MIRBuilder.
getMF(), ResVReg);
1122 return MIRBuilder.
buildInstr(SPIRV::OpTypePipe)
1130 if (
auto *Res = checkSpecialInstr(TD, MIRBuilder))
1133 DT.
add(TD, &MIRBuilder.
getMF(), ResVReg);
1143 if (
auto *Res = checkSpecialInstr(TD, MIRBuilder))
1146 DT.
add(TD, &MIRBuilder.
getMF(), ResVReg);
1147 return MIRBuilder.
buildInstr(SPIRV::OpTypeSampledImage)
1159 DT.
add(Ty, &MIRBuilder.
getMF(), ResVReg);
1175 SPIRV::StorageClass::StorageClass SC,
1176 SPIRV::AccessQualifier::AccessQualifier AQ) {
1177 unsigned VecElts = 0;
1200 TypeStr = TypeStr.
substr(strlen(
"*"));
1207 TypeStr = TypeStr.
substr(0, TypeStr.
find(
']'));
1227SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(
const Type *LLVMTy,
1231 SPIRVToLLVMType[SpirvType] = LLVMTy;
1238 unsigned SPIRVOPcode,
1244 auto MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRVOPcode))
1249 return finishCreatingSPIRVType(LLVMTy, MIB);
1292 auto MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpTypeBool))
1295 return finishCreatingSPIRVType(LLVMTy, MIB);
1315 auto MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpTypeVector))
1320 return finishCreatingSPIRVType(LLVMTy, MIB);
1334 auto MIB =
BuildMI(BB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpTypeArray))
1339 return finishCreatingSPIRVType(LLVMTy, MIB);
1344 SPIRV::StorageClass::StorageClass SC) {
1356 MIRBuilder.
getTII().
get(SPIRV::OpTypePointer))
1361 return finishCreatingSPIRVType(LLVMTy, MIB);
1366 SPIRV::StorageClass::StorageClass SC) {
1389 MIB =
BuildMI(*
I.getParent(),
I,
I.getDebugLoc(),
TII.get(SPIRV::OpUndef))
1394 *ST.getRegisterInfo(), *ST.getRegBankInfo());
unsigned const MachineRegisterInfo * MRI
This file implements a class to represent arbitrary precision integral constant values and operations...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const HexagonInstrInfo * TII
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Register createTypeVReg(MachineIRBuilder &MIRBuilder)
APInt bitcastToAPInt() const
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
int64_t getSExtValue() const
Get sign extended value.
Class to represent array types.
uint64_t getNumElements() const
static ArrayType * get(Type *ElementType, uint64_t NumElements)
This static method is the primary way to construct an ArrayType.
Type * getElementType() const
static Constant * get(ArrayType *T, ArrayRef< Constant * > V)
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
static ConstantPointerNull * get(PointerType *T)
Static factory methods - Return objects of the specified value.
static Constant * getSplat(ElementCount EC, Constant *Elt)
Return a ConstantVector with the specified constant in each element.
This is an important base class in LLVM.
const APInt & getUniqueInteger() const
If C is a constant integer then return its value, otherwise C must be a vector of constant integers,...
bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
Class to represent fixed width SIMD vectors.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
MaybeAlign getAlign() const
Returns the alignment of the given variable or function.
Module * getParent()
Get the module that this global value is contained inside of...
@ ExternalLinkage
Externally visible function.
Class to represent integer types.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
This is an important class for using LLVM in a threaded context.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
LLVMContext & getContext() const
const TargetInstrInfo & getTII()
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)
Build and insert Res = G_SPLAT_VECTOR Val.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
A Module instance is used to store all the information related to an LLVM module.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
void add(const Type *Ty, const MachineFunction *MF, Register R)
Register find(const Type *Ty, const MachineFunction *MF)
const SPIRVDuplicatesTracker< Type > * getTypes()
SPIRVType * getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual)
unsigned getNumScalarOrVectorTotalBitWidth(const SPIRVType *Type) const
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
SPIRVType * assignFloatTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)
SPIRVType * assignVectTypeToVReg(SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)
Register getOrCreateUndef(MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntVector(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR=true)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
bool isBitcastCompatible(const SPIRVType *Type1, const SPIRVType *Type2) const
unsigned getScalarOrVectorComponentCount(Register VReg) const
SPIRVType * getOrCreateSPIRVFloatType(unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateOpTypeImage(MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled, SPIRV::ImageFormat::ImageFormat ImageFormat, SPIRV::AccessQualifier::AccessQualifier AccQual)
bool isScalarOrVectorSigned(const SPIRVType *Type) const
SPIRVGlobalRegistry(unsigned PointerSize)
unsigned getPointerSize() const
SPIRVType * getOrCreateOpTypeByOpcode(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode)
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
SPIRVType * assignIntTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)
unsigned getPointeeTypeOp(Register PtrReg)
SPIRVType * getOrCreateOpTypeSampledImage(SPIRVType *ImageType, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SC=SPIRV::StorageClass::Function, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite)
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
SPIRVType * getOrCreateOpTypeFunctionWithArgs(const Type *Ty, SPIRVType *RetType, const SmallVectorImpl< SPIRVType * > &ArgTypes, MachineIRBuilder &MIRBuilder)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
SPIRVType * getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateSPIRVArrayType(SPIRVType *BaseType, unsigned NumElements, MachineInstr &I, const SPIRVInstrInfo &TII)
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
SPIRVType * getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder)
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
Register getOrCreateConstFP(APFloat Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
const SPIRVType * retrieveScalarOrVectorIntType(const SPIRVType *Type) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
bool consume_back(StringRef Suffix)
Returns true if this StringRef has the given suffix and removes that suffix.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
bool consume_front(StringRef Prefix)
Returns true if this StringRef has the given prefix and removes that prefix.
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Class to represent struct types.
ArrayRef< Type * > elements() const
bool hasName() const
Return true if this is a named struct that has a non-empty name.
StringRef getName() const
Return the name for this struct type if it has an identity.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getHalfTy(LLVMContext &C)
static Type * getDoubleTy(LLVMContext &C)
bool isVectorTy() const
True if this is an instance of VectorType.
bool isArrayTy() const
True if this is an instance of ArrayType.
Type * getArrayElementType() const
uint64_t getArrayNumElements() const
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
static IntegerType * getInt8Ty(LLVMContext &C)
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
bool isVoidTy() const
Return true if this is 'void'.
A few GPU targets, such as DXIL and SPIR-V, have typed pointers.
Type * getElementType() const
static TypedPointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
'undef' values are things that do not have specified contents.
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
StringRef getName() const
Return a constant reference to the value's name.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
Type * getElementType() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
TargetExtType * parseBuiltinTypeNameToTargetExtType(std::string TypeName, LLVMContext &Context)
Translates a string representing a SPIR-V or OpenCL builtin type to a TargetExtType that can be furth...
SPIRVType * lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getPointerAddressSpace(const Type *T)
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
bool getSpirvBuiltInIdByName(llvm::StringRef Name, SPIRV::BuiltIn::BuiltIn &BI)
bool isTypedPointerTy(const Type *T)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
bool isSpecialOpaqueType(const Type *Ty)
bool isPointerTy(const Type *T)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)
Type * toTypedPointer(Type *Ty, LLVMContext &Ctx)
Type * parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx)
constexpr unsigned BitWidth
bool hasBuiltinTypePrefix(StringRef Name)
void addStringImm(const StringRef &Str, MCInst &Inst)
uint64_t value() const
This is a hole in the type system and should not be abused.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.