LLVM  16.0.0git
SPIRVTargetMachine.cpp
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1 //===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about SPIR-V target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SPIRVTargetMachine.h"
14 #include "SPIRV.h"
15 #include "SPIRVCallLowering.h"
16 #include "SPIRVGlobalRegistry.h"
17 #include "SPIRVLegalizerInfo.h"
18 #include "SPIRVTargetObjectFile.h"
25 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/InitializePasses.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Pass.h"
33 
34 using namespace llvm;
35 
37  // Register the target.
40 
44 }
45 
46 static std::string computeDataLayout(const Triple &TT) {
47  const auto Arch = TT.getArch();
48  if (Arch == Triple::spirv32)
49  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
50  "v96:128-v192:256-v256:256-v512:512-v1024:1024";
51  return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
52  "v96:128-v192:256-v256:256-v512:512-v1024:1024";
53 }
54 
56  if (!RM)
57  return Reloc::PIC_;
58  return *RM;
59 }
60 
61 // Pin SPIRVTargetObjectFile's vtables to this file.
63 
65  StringRef CPU, StringRef FS,
66  const TargetOptions &Options,
69  CodeGenOpt::Level OL, bool JIT)
73  TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
74  Subtarget(TT, CPU.str(), FS.str(), *this) {
75  initAsmInfo();
76  setGlobalISel(true);
77  setFastISel(false);
78  setO0WantsFastISel(false);
80 }
81 
82 namespace {
83 // SPIR-V Code Generator Pass Configuration Options.
84 class SPIRVPassConfig : public TargetPassConfig {
85 public:
86  SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
87  : TargetPassConfig(TM, PM) {}
88 
89  SPIRVTargetMachine &getSPIRVTargetMachine() const {
90  return getTM<SPIRVTargetMachine>();
91  }
92  void addIRPasses() override;
93  void addISelPrepare() override;
94 
95  bool addIRTranslator() override;
96  void addPreLegalizeMachineIR() override;
97  bool addLegalizeMachineIR() override;
98  bool addRegBankSelect() override;
99  bool addGlobalInstructionSelect() override;
100 
101  FunctionPass *createTargetRegisterAllocator(bool) override;
102  void addFastRegAlloc() override {}
103  void addOptimizedRegAlloc() override {}
104 
105  void addPostRegAlloc() override;
106 };
107 } // namespace
108 
109 // We do not use physical registers, and maintain virtual registers throughout
110 // the entire pipeline, so return nullptr to disable register allocation.
111 FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
112  return nullptr;
113 }
114 
115 // Disable passes that break from assuming no virtual registers exist.
116 void SPIRVPassConfig::addPostRegAlloc() {
117  // Do not work with vregs instead of physical regs.
118  disablePass(&MachineCopyPropagationID);
119  disablePass(&PostRAMachineSinkingID);
120  disablePass(&PostRASchedulerID);
121  disablePass(&FuncletLayoutID);
122  disablePass(&StackMapLivenessID);
123  disablePass(&PatchableFunctionID);
124  disablePass(&ShrinkWrapID);
125  disablePass(&LiveDebugValuesID);
126 
127  // Do not work with OpPhi.
128  disablePass(&BranchFolderPassID);
129  disablePass(&MachineBlockPlacementID);
130 
132 }
133 
136  return TargetTransformInfo(SPIRVTTIImpl(this, F));
137 }
138 
140  return new SPIRVPassConfig(*this, PM);
141 }
142 
143 void SPIRVPassConfig::addIRPasses() {
146 }
147 
148 void SPIRVPassConfig::addISelPrepare() {
149  addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
151 }
152 
153 bool SPIRVPassConfig::addIRTranslator() {
154  addPass(new IRTranslator(getOptLevel()));
155  return false;
156 }
157 
158 void SPIRVPassConfig::addPreLegalizeMachineIR() {
159  addPass(createSPIRVPreLegalizerPass());
160 }
161 
162 // Use a default legalizer.
163 bool SPIRVPassConfig::addLegalizeMachineIR() {
164  addPass(new Legalizer());
165  return false;
166 }
167 
168 // Do not add a RegBankSelect pass, as we only ever need virtual registers.
169 bool SPIRVPassConfig::addRegBankSelect() {
170  disablePass(&RegBankSelect::ID);
171  return false;
172 }
173 
174 namespace {
175 // A custom subclass of InstructionSelect, which is mostly the same except from
176 // not requiring RegBankSelect to occur previously.
177 class SPIRVInstructionSelect : public InstructionSelect {
178  // We don't use register banks, so unset the requirement for them
179  MachineFunctionProperties getRequiredProperties() const override {
182  }
183 };
184 } // namespace
185 
186 bool SPIRVPassConfig::addGlobalInstructionSelect() {
187  addPass(new SPIRVInstructionSelect());
188  return false;
189 }
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:420
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SPIRVLegalizerInfo.h
SPIRVCallLowering.h
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::Function
Definition: Function.h:60
Pass.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::SPIRVTargetMachine::SPIRVTargetMachine
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SPIRVTargetMachine.cpp:64
llvm::TargetLoweringObjectFileELF
Definition: TargetLoweringObjectFileImpl.h:34
InstructionSelect.h
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::Optional< Reloc::Model >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::Triple::spirv32
@ spirv32
Definition: Triple.h:98
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:354
LegacyPassManager.h
SPIRVTargetInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::initializeSPIRVModuleAnalysisPass
void initializeSPIRVModuleAnalysisPass(PassRegistry &)
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
computeDataLayout
static std::string computeDataLayout(const Triple &TT)
Definition: SPIRVTargetMachine.cpp:46
LLVMInitializeSPIRVTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget()
Definition: SPIRVTargetMachine.cpp:36
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:95
llvm::getTheSPIRV32Target
Target & getTheSPIRV32Target()
Definition: SPIRVTargetInfo.cpp:14
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::createSPIRVPrepareFunctionsPass
ModulePass * createSPIRVPrepareFunctionsPass()
Definition: SPIRVPrepareFunctions.cpp:286
llvm::Legalizer
Definition: Legalizer.h:36
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1318
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
SPIRVTargetMachine.h
llvm::TargetMachine::setO0WantsFastISel
void setO0WantsFastISel(bool Enable)
Definition: TargetMachine.h:248
SPIRVGlobalRegistry.h
llvm::TargetMachine::setRequiresStructuredCFG
void setRequiresStructuredCFG(bool Value)
Definition: TargetMachine.h:217
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
TargetPassConfig.h
llvm::MachineFunctionProperties::Property::RegBankSelected
@ RegBankSelected
SPIRVTargetTransformInfo.h
SPIRV.h
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:471
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::BranchFolderPassID
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Definition: BranchFolding.cpp:118
llvm::SPIRVTTIImpl
Definition: SPIRVTargetTransformInfo.h:25
IRTranslator.h
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:610
llvm::createSPIRVEmitIntrinsicsPass
FunctionPass * createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM)
Definition: SPIRVEmitIntrinsics.cpp:460
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:201
llvm::TargetMachine::setFastISel
void setFastISel(bool Enable)
Definition: TargetMachine.h:246
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getTheSPIRV64Target
Target & getTheSPIRV64Target()
Definition: SPIRVTargetInfo.cpp:18
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:506
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::InstructionSelect::getRequiredProperties
MachineFunctionProperties getRequiredProperties() const override
Definition: InstructionSelect.h:40
llvm::SPIRVTargetMachine
Definition: SPIRVTargetMachine.h:20
llvm::X86AS::FS
@ FS
Definition: X86.h:196
llvm::createSPIRVPreLegalizerPass
FunctionPass * createSPIRVPreLegalizerPass()
std
Definition: BitVector.h:851
RegBankSelect.h
llvm::SPIRVTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: SPIRVTargetMachine.cpp:139
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:249
SPIRVTargetObjectFile.h
Legalizer.h
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:1002
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::RegBankSelect::ID
static char ID
Definition: RegBankSelect.h:93
llvm::SPIRVTargetObjectFile::~SPIRVTargetObjectFile
~SPIRVTargetObjectFile() override
Definition: SPIRVTargetMachine.cpp:62
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::SPIRVTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: SPIRVTargetMachine.cpp:135
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1622
TargetRegistry.h
InitializePasses.h
TargetLoweringObjectFileImpl.h