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SPIRVTargetMachine.cpp
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1 //===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about SPIR-V target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SPIRVTargetMachine.h"
14 #include "SPIRV.h"
15 #include "SPIRVCallLowering.h"
16 #include "SPIRVGlobalRegistry.h"
17 #include "SPIRVLegalizerInfo.h"
18 #include "SPIRVTargetObjectFile.h"
25 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/InitializePasses.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Pass.h"
33 #include <optional>
34 
35 using namespace llvm;
36 
38  // Register the target.
41 
45 }
46 
47 static std::string computeDataLayout(const Triple &TT) {
48  const auto Arch = TT.getArch();
49  if (Arch == Triple::spirv32)
50  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
51  "v96:128-v192:256-v256:256-v512:512-v1024:1024";
52  return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
53  "v96:128-v192:256-v256:256-v512:512-v1024:1024";
54 }
55 
56 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
57  if (!RM)
58  return Reloc::PIC_;
59  return *RM;
60 }
61 
62 // Pin SPIRVTargetObjectFile's vtables to this file.
64 
66  StringRef CPU, StringRef FS,
67  const TargetOptions &Options,
68  std::optional<Reloc::Model> RM,
69  std::optional<CodeModel::Model> CM,
70  CodeGenOpt::Level OL, bool JIT)
74  TLOF(std::make_unique<SPIRVTargetObjectFile>()),
75  Subtarget(TT, CPU.str(), FS.str(), *this) {
76  initAsmInfo();
77  setGlobalISel(true);
78  setFastISel(false);
79  setO0WantsFastISel(false);
81 }
82 
83 namespace {
84 // SPIR-V Code Generator Pass Configuration Options.
85 class SPIRVPassConfig : public TargetPassConfig {
86 public:
87  SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
88  : TargetPassConfig(TM, PM) {}
89 
90  SPIRVTargetMachine &getSPIRVTargetMachine() const {
91  return getTM<SPIRVTargetMachine>();
92  }
93  void addIRPasses() override;
94  void addISelPrepare() override;
95 
96  bool addIRTranslator() override;
97  void addPreLegalizeMachineIR() override;
98  bool addLegalizeMachineIR() override;
99  bool addRegBankSelect() override;
100  bool addGlobalInstructionSelect() override;
101 
102  FunctionPass *createTargetRegisterAllocator(bool) override;
103  void addFastRegAlloc() override {}
104  void addOptimizedRegAlloc() override {}
105 
106  void addPostRegAlloc() override;
107 };
108 } // namespace
109 
110 // We do not use physical registers, and maintain virtual registers throughout
111 // the entire pipeline, so return nullptr to disable register allocation.
112 FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
113  return nullptr;
114 }
115 
116 // Disable passes that break from assuming no virtual registers exist.
117 void SPIRVPassConfig::addPostRegAlloc() {
118  // Do not work with vregs instead of physical regs.
119  disablePass(&MachineCopyPropagationID);
120  disablePass(&PostRAMachineSinkingID);
121  disablePass(&PostRASchedulerID);
122  disablePass(&FuncletLayoutID);
123  disablePass(&StackMapLivenessID);
124  disablePass(&PatchableFunctionID);
125  disablePass(&ShrinkWrapID);
126  disablePass(&LiveDebugValuesID);
127 
128  // Do not work with OpPhi.
129  disablePass(&BranchFolderPassID);
130  disablePass(&MachineBlockPlacementID);
131 
133 }
134 
137  return TargetTransformInfo(SPIRVTTIImpl(this, F));
138 }
139 
141  return new SPIRVPassConfig(*this, PM);
142 }
143 
144 void SPIRVPassConfig::addIRPasses() {
146  addPass(createSPIRVRegularizerPass());
148 }
149 
150 void SPIRVPassConfig::addISelPrepare() {
151  addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
153 }
154 
155 bool SPIRVPassConfig::addIRTranslator() {
156  addPass(new IRTranslator(getOptLevel()));
157  return false;
158 }
159 
160 void SPIRVPassConfig::addPreLegalizeMachineIR() {
161  addPass(createSPIRVPreLegalizerPass());
162 }
163 
164 // Use the default legalizer.
165 bool SPIRVPassConfig::addLegalizeMachineIR() {
166  addPass(new Legalizer());
167  return false;
168 }
169 
170 // Do not add the RegBankSelect pass, as we only ever need virtual registers.
171 bool SPIRVPassConfig::addRegBankSelect() {
172  disablePass(&RegBankSelect::ID);
173  return false;
174 }
175 
176 namespace {
177 // A custom subclass of InstructionSelect, which is mostly the same except from
178 // not requiring RegBankSelect to occur previously.
179 class SPIRVInstructionSelect : public InstructionSelect {
180  // We don't use register banks, so unset the requirement for them
181  MachineFunctionProperties getRequiredProperties() const override {
184  }
185 };
186 } // namespace
187 
188 // Add the custom SPIRVInstructionSelect from above.
189 bool SPIRVPassConfig::addGlobalInstructionSelect() {
190  addPass(new SPIRVInstructionSelect());
191  return false;
192 }
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:420
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SPIRVLegalizerInfo.h
SPIRVCallLowering.h
llvm::TargetOptions
Definition: TargetOptions.h:124
T
llvm::Function
Definition: Function.h:60
Pass.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:150
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::SPIRVTargetObjectFile
Definition: SPIRVTargetObjectFile.h:18
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
InstructionSelect.h
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::Triple::spirv32
@ spirv32
Definition: Triple.h:98
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:355
LegacyPassManager.h
SPIRVTargetInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::initializeSPIRVModuleAnalysisPass
void initializeSPIRVModuleAnalysisPass(PassRegistry &)
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
computeDataLayout
static std::string computeDataLayout(const Triple &TT)
Definition: SPIRVTargetMachine.cpp:47
LLVMInitializeSPIRVTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget()
Definition: SPIRVTargetMachine.cpp:37
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:95
llvm::getTheSPIRV32Target
Target & getTheSPIRV32Target()
Definition: SPIRVTargetInfo.cpp:14
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::createSPIRVPrepareFunctionsPass
ModulePass * createSPIRVPrepareFunctionsPass()
Definition: SPIRVPrepareFunctions.cpp:353
llvm::Legalizer
Definition: Legalizer.h:36
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1355
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createSPIRVRegularizerPass
FunctionPass * createSPIRVRegularizerPass()
Definition: SPIRVRegularizer.cpp:259
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
SPIRVTargetMachine.h
llvm::TargetMachine::setO0WantsFastISel
void setO0WantsFastISel(bool Enable)
Definition: TargetMachine.h:247
SPIRVGlobalRegistry.h
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:501
llvm::TargetMachine::setRequiresStructuredCFG
void setRequiresStructuredCFG(bool Value)
Definition: TargetMachine.h:216
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
TargetPassConfig.h
llvm::MachineFunctionProperties::Property::RegBankSelected
@ RegBankSelected
SPIRVTargetTransformInfo.h
SPIRV.h
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:42
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:493
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::BranchFolderPassID
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Definition: BranchFolding.cpp:118
llvm::SPIRVTTIImpl
Definition: SPIRVTargetTransformInfo.h:25
IRTranslator.h
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:622
llvm::createSPIRVEmitIntrinsicsPass
FunctionPass * createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM)
Definition: SPIRVEmitIntrinsics.cpp:473
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:201
llvm::TargetMachine::setFastISel
void setFastISel(bool Enable)
Definition: TargetMachine.h:245
llvm::getTheSPIRV64Target
Target & getTheSPIRV64Target()
Definition: SPIRVTargetInfo.cpp:18
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::InstructionSelect::getRequiredProperties
MachineFunctionProperties getRequiredProperties() const override
Definition: InstructionSelect.h:40
llvm::SPIRVTargetMachine
Definition: SPIRVTargetMachine.h:21
llvm::createSPIRVPreLegalizerPass
FunctionPass * createSPIRVPreLegalizerPass()
std
Definition: BitVector.h:851
RegBankSelect.h
llvm::SPIRVTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: SPIRVTargetMachine.cpp:140
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:408
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:248
SPIRVTargetObjectFile.h
Legalizer.h
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:1003
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::SPIRVTargetMachine::SPIRVTargetMachine
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SPIRVTargetMachine.cpp:65
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::RegBankSelect::ID
static char ID
Definition: RegBankSelect.h:93
llvm::SPIRVTargetObjectFile::~SPIRVTargetObjectFile
~SPIRVTargetObjectFile() override
Definition: SPIRVTargetMachine.cpp:63
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::SPIRVTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: SPIRVTargetMachine.cpp:136
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1622
TargetRegistry.h
InitializePasses.h
TargetLoweringObjectFileImpl.h