LLVM 17.0.0git
SPIRVTargetMachine.cpp
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1//===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about SPIR-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SPIRVTargetMachine.h"
14#include "SPIRV.h"
15#include "SPIRVCallLowering.h"
16#include "SPIRVGlobalRegistry.h"
17#include "SPIRVLegalizerInfo.h"
25#include "llvm/CodeGen/Passes.h"
30#include "llvm/Pass.h"
32#include <optional>
33
34using namespace llvm;
35
37 // Register the target.
40
44}
45
46static std::string computeDataLayout(const Triple &TT) {
47 const auto Arch = TT.getArch();
48 if (Arch == Triple::spirv32)
49 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
50 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
51 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
52 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
53}
54
55static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
56 if (!RM)
57 return Reloc::PIC_;
58 return *RM;
59}
60
61// Pin SPIRVTargetObjectFile's vtables to this file.
63
65 StringRef CPU, StringRef FS,
67 std::optional<Reloc::Model> RM,
68 std::optional<CodeModel::Model> CM,
69 CodeGenOpt::Level OL, bool JIT)
70 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
72 getEffectiveCodeModel(CM, CodeModel::Small), OL),
73 TLOF(std::make_unique<SPIRVTargetObjectFile>()),
74 Subtarget(TT, CPU.str(), FS.str(), *this) {
76 setGlobalISel(true);
77 setFastISel(false);
78 setO0WantsFastISel(false);
80}
81
82namespace {
83// SPIR-V Code Generator Pass Configuration Options.
84class SPIRVPassConfig : public TargetPassConfig {
85public:
86 SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
87 : TargetPassConfig(TM, PM) {}
88
89 SPIRVTargetMachine &getSPIRVTargetMachine() const {
90 return getTM<SPIRVTargetMachine>();
91 }
92 void addIRPasses() override;
93 void addISelPrepare() override;
94
95 bool addIRTranslator() override;
96 void addPreLegalizeMachineIR() override;
97 bool addLegalizeMachineIR() override;
98 bool addRegBankSelect() override;
99 bool addGlobalInstructionSelect() override;
100
101 FunctionPass *createTargetRegisterAllocator(bool) override;
102 void addFastRegAlloc() override {}
103 void addOptimizedRegAlloc() override {}
104
105 void addPostRegAlloc() override;
106};
107} // namespace
108
109// We do not use physical registers, and maintain virtual registers throughout
110// the entire pipeline, so return nullptr to disable register allocation.
111FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
112 return nullptr;
113}
114
115// Disable passes that break from assuming no virtual registers exist.
116void SPIRVPassConfig::addPostRegAlloc() {
117 // Do not work with vregs instead of physical regs.
118 disablePass(&MachineCopyPropagationID);
119 disablePass(&PostRAMachineSinkingID);
120 disablePass(&PostRASchedulerID);
121 disablePass(&FuncletLayoutID);
122 disablePass(&StackMapLivenessID);
123 disablePass(&PatchableFunctionID);
124 disablePass(&ShrinkWrapID);
125 disablePass(&LiveDebugValuesID);
126 disablePass(&MachineLateInstrsCleanupID);
127
128 // Do not work with OpPhi.
129 disablePass(&BranchFolderPassID);
130 disablePass(&MachineBlockPlacementID);
131
133}
134
137 return TargetTransformInfo(SPIRVTTIImpl(this, F));
138}
139
141 return new SPIRVPassConfig(*this, PM);
142}
143
144void SPIRVPassConfig::addIRPasses() {
148}
149
150void SPIRVPassConfig::addISelPrepare() {
151 addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
153}
154
155bool SPIRVPassConfig::addIRTranslator() {
156 addPass(new IRTranslator(getOptLevel()));
157 return false;
158}
159
160void SPIRVPassConfig::addPreLegalizeMachineIR() {
162}
163
164// Use the default legalizer.
165bool SPIRVPassConfig::addLegalizeMachineIR() {
166 addPass(new Legalizer());
167 return false;
168}
169
170// Do not add the RegBankSelect pass, as we only ever need virtual registers.
171bool SPIRVPassConfig::addRegBankSelect() {
172 disablePass(&RegBankSelect::ID);
173 return false;
174}
175
176namespace {
177// A custom subclass of InstructionSelect, which is mostly the same except from
178// not requiring RegBankSelect to occur previously.
179class SPIRVInstructionSelect : public InstructionSelect {
180 // We don't use register banks, so unset the requirement for them
181 MachineFunctionProperties getRequiredProperties() const override {
183 MachineFunctionProperties::Property::RegBankSelected);
184 }
185};
186} // namespace
187
188// Add the custom SPIRVInstructionSelect from above.
189bool SPIRVPassConfig::addGlobalInstructionSelect() {
190 addPass(new SPIRVInstructionSelect());
191 return false;
192}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget()
Target-Independent Code Generator Pass Configuration Options pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
This pass is responsible for selecting generic machine instructions to target-specific instructions.
MachineFunctionProperties getRequiredProperties() const override
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & reset(Property P)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void setFastISel(bool Enable)
void setRequiresStructuredCFG(bool Value)
void setGlobalISel(bool Enable)
void setO0WantsFastISel(bool Enable)
Target-Independent Code Generator Pass Configuration Options.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Level
Code generation optimization level.
Definition: CodeGen.h:57
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSPIRV32Target()
ModulePass * createSPIRVPrepareFunctionsPass()
FunctionPass * createSPIRVPreLegalizerPass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM)
char & LiveDebugValuesID
LiveDebugValues pass.
void initializeSPIRVModuleAnalysisPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Target & getTheSPIRV64Target()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
FunctionPass * createSPIRVRegularizerPass()
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: BitVector.h:858
RegisterTargetMachine - Helper template for registering a target machine implementation,...