LLVM 18.0.0git
SPIRVTargetMachine.cpp
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1//===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about SPIR-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SPIRVTargetMachine.h"
14#include "SPIRV.h"
15#include "SPIRVCallLowering.h"
16#include "SPIRVGlobalRegistry.h"
17#include "SPIRVLegalizerInfo.h"
25#include "llvm/CodeGen/Passes.h"
30#include "llvm/Pass.h"
32#include <optional>
33
34using namespace llvm;
35
37 // Register the target.
41
45}
46
47static std::string computeDataLayout(const Triple &TT) {
48 const auto Arch = TT.getArch();
49 // TODO: this probably needs to be revisited:
50 // Logical SPIR-V has no pointer size, so any fixed pointer size would be
51 // wrong. The choice to default to 32 or 64 is just motivated by another
52 // memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
53 // mean anything.
54 if (Arch == Triple::spirv32)
55 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
56 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
57 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
58 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
59}
60
61static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
62 if (!RM)
63 return Reloc::PIC_;
64 return *RM;
65}
66
67// Pin SPIRVTargetObjectFile's vtables to this file.
69
71 StringRef CPU, StringRef FS,
73 std::optional<Reloc::Model> RM,
74 std::optional<CodeModel::Model> CM,
75 CodeGenOptLevel OL, bool JIT)
76 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
78 getEffectiveCodeModel(CM, CodeModel::Small), OL),
79 TLOF(std::make_unique<SPIRVTargetObjectFile>()),
80 Subtarget(TT, CPU.str(), FS.str(), *this) {
82 setGlobalISel(true);
83 setFastISel(false);
84 setO0WantsFastISel(false);
86}
87
88namespace {
89// SPIR-V Code Generator Pass Configuration Options.
90class SPIRVPassConfig : public TargetPassConfig {
91public:
92 SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
93 : TargetPassConfig(TM, PM) {}
94
95 SPIRVTargetMachine &getSPIRVTargetMachine() const {
96 return getTM<SPIRVTargetMachine>();
97 }
98 void addIRPasses() override;
99 void addISelPrepare() override;
100
101 bool addIRTranslator() override;
102 void addPreLegalizeMachineIR() override;
103 bool addLegalizeMachineIR() override;
104 bool addRegBankSelect() override;
105 bool addGlobalInstructionSelect() override;
106
107 FunctionPass *createTargetRegisterAllocator(bool) override;
108 void addFastRegAlloc() override {}
109 void addOptimizedRegAlloc() override {}
110
111 void addPostRegAlloc() override;
112};
113} // namespace
114
115// We do not use physical registers, and maintain virtual registers throughout
116// the entire pipeline, so return nullptr to disable register allocation.
117FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
118 return nullptr;
119}
120
121// Disable passes that break from assuming no virtual registers exist.
122void SPIRVPassConfig::addPostRegAlloc() {
123 // Do not work with vregs instead of physical regs.
124 disablePass(&MachineCopyPropagationID);
125 disablePass(&PostRAMachineSinkingID);
126 disablePass(&PostRASchedulerID);
127 disablePass(&FuncletLayoutID);
128 disablePass(&StackMapLivenessID);
129 disablePass(&PatchableFunctionID);
130 disablePass(&ShrinkWrapID);
131 disablePass(&LiveDebugValuesID);
132 disablePass(&MachineLateInstrsCleanupID);
133
134 // Do not work with OpPhi.
135 disablePass(&BranchFolderPassID);
136 disablePass(&MachineBlockPlacementID);
137
139}
140
143 return TargetTransformInfo(SPIRVTTIImpl(this, F));
144}
145
147 return new SPIRVPassConfig(*this, PM);
148}
149
150void SPIRVPassConfig::addIRPasses() {
154}
155
156void SPIRVPassConfig::addISelPrepare() {
157 addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
159}
160
161bool SPIRVPassConfig::addIRTranslator() {
162 addPass(new IRTranslator(getOptLevel()));
163 return false;
164}
165
166void SPIRVPassConfig::addPreLegalizeMachineIR() {
168}
169
170// Use the default legalizer.
171bool SPIRVPassConfig::addLegalizeMachineIR() {
172 addPass(new Legalizer());
173 return false;
174}
175
176// Do not add the RegBankSelect pass, as we only ever need virtual registers.
177bool SPIRVPassConfig::addRegBankSelect() {
178 disablePass(&RegBankSelect::ID);
179 return false;
180}
181
182namespace {
183// A custom subclass of InstructionSelect, which is mostly the same except from
184// not requiring RegBankSelect to occur previously.
185class SPIRVInstructionSelect : public InstructionSelect {
186 // We don't use register banks, so unset the requirement for them
187 MachineFunctionProperties getRequiredProperties() const override {
189 MachineFunctionProperties::Property::RegBankSelected);
190 }
191};
192} // namespace
193
194// Add the custom SPIRVInstructionSelect from above.
195bool SPIRVPassConfig::addGlobalInstructionSelect() {
196 addPass(new SPIRVInstructionSelect());
197 return false;
198}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget()
Target-Independent Code Generator Pass Configuration Options pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
This pass is responsible for selecting generic machine instructions to target-specific instructions.
MachineFunctionProperties getRequiredProperties() const override
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & reset(Property P)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void setFastISel(bool Enable)
void setRequiresStructuredCFG(bool Value)
void setGlobalISel(bool Enable)
void setO0WantsFastISel(bool Enable)
Target-Independent Code Generator Pass Configuration Options.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSPIRV32Target()
ModulePass * createSPIRVPrepareFunctionsPass()
FunctionPass * createSPIRVPreLegalizerPass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM)
char & LiveDebugValuesID
LiveDebugValues pass.
void initializeSPIRVModuleAnalysisPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:286
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
Target & getTheSPIRV64Target()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
Target & getTheSPIRVLogicalTarget()
FunctionPass * createSPIRVRegularizerPass()
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
RegisterTargetMachine - Helper template for registering a target machine implementation,...