78#define DEBUG_TYPE "machine-cp"
80STATISTIC(NumDeletes,
"Number of dead copies deleted");
81STATISTIC(NumCopyForwards,
"Number of copy uses forwarded");
82STATISTIC(NumCopyBackwardPropagated,
"Number of copy defs backward propagated");
83STATISTIC(SpillageChainsLength,
"Length of spillage chains");
84STATISTIC(NumSpillageChains,
"Number of spillage chains");
86 "Controls which register COPYs are forwarded");
95static std::optional<DestSourcePair> isCopyInstr(
const MachineInstr &
MI,
99 return TII.isCopyInstr(
MI);
102 return std::optional<DestSourcePair>(
125 auto CI =
Copies.find(Unit);
127 CI->second.Avail =
false;
141 std::optional<DestSourcePair> CopyOperands =
142 isCopyInstr(*
MI,
TII, UseCopyInstr);
143 assert(CopyOperands &&
"Expect copy");
145 auto Dest =
TRI.regunits(CopyOperands->Destination->getReg().asMCReg());
146 auto Src =
TRI.regunits(CopyOperands->Source->getReg().asMCReg());
147 RegUnitsToInvalidate.
insert(Dest.begin(), Dest.end());
148 RegUnitsToInvalidate.
insert(Src.begin(), Src.end());
160 for (
MCRegUnit Unit : RegUnitsToInvalidate)
172 markRegsUnavailable(
I->second.DefRegs,
TRI);
176 std::optional<DestSourcePair> CopyOperands =
177 isCopyInstr(*
MI,
TII, UseCopyInstr);
178 markRegsUnavailable({CopyOperands->Destination->getReg().asMCReg()},
190 std::optional<DestSourcePair> CopyOperands =
191 isCopyInstr(*
MI,
TII, UseCopyInstr);
192 assert(CopyOperands &&
"Tracking non-copy?");
194 MCRegister Src = CopyOperands->Source->getReg().asMCReg();
195 MCRegister Def = CopyOperands->Destination->getReg().asMCReg();
199 Copies[Unit] = {
MI,
nullptr, {},
true};
204 auto I =
Copies.insert({Unit, {
nullptr,
nullptr, {},
false}});
205 auto &
Copy =
I.first->second;
207 Copy.DefRegs.push_back(Def);
208 Copy.LastSeenUseInCopy =
MI;
212 bool hasAnyCopies() {
218 bool MustBeAvailable =
false) {
219 auto CI =
Copies.find(RegUnit);
222 if (MustBeAvailable && !CI->second.Avail)
224 return CI->second.MI;
229 auto CI =
Copies.find(RegUnit);
232 if (CI->second.DefRegs.size() != 1)
234 MCRegUnit RU = *
TRI.regunits(CI->second.DefRegs[0]).begin();
235 return findCopyForUnit(RU,
TRI,
true);
248 std::optional<DestSourcePair> CopyOperands =
249 isCopyInstr(*AvailCopy,
TII, UseCopyInstr);
250 Register AvailSrc = CopyOperands->Source->getReg();
251 Register AvailDef = CopyOperands->Destination->getReg();
252 if (!
TRI.isSubRegisterEq(AvailSrc, Reg))
260 if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef))
273 findCopyForUnit(RU,
TRI,
true);
278 std::optional<DestSourcePair> CopyOperands =
279 isCopyInstr(*AvailCopy,
TII, UseCopyInstr);
280 Register AvailSrc = CopyOperands->Source->getReg();
281 Register AvailDef = CopyOperands->Destination->getReg();
282 if (!
TRI.isSubRegisterEq(AvailDef, Reg))
291 if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef))
304 auto CI =
Copies.find(RU);
305 if (CI ==
Copies.end() || !CI->second.Avail)
309 std::optional<DestSourcePair> CopyOperands =
310 isCopyInstr(*DefCopy,
TII, UseCopyInstr);
311 Register Def = CopyOperands->Destination->getReg();
312 if (!
TRI.isSubRegisterEq(Def, Reg))
320 if (MO.clobbersPhysReg(Def)) {
333 auto CI =
Copies.find(RU);
336 return CI->second.LastSeenUseInCopy;
355 MachineCopyPropagation(
bool CopyInstr =
false)
369 MachineFunctionProperties::Property::NoVRegs);
373 typedef enum { DebugUse =
false, RegularUse =
true }
DebugType;
382 bool isForwardableRegClassCopy(
const MachineInstr &Copy,
384 bool isBackwardPropagatableRegClassCopy(
const MachineInstr &Copy,
399 bool Changed =
false;
404char MachineCopyPropagation::ID = 0;
409 "Machine Copy Propagation Pass",
false,
false)
418 if (DT == RegularUse) {
419 LLVM_DEBUG(
dbgs() <<
"MCP: Copy is used - not dead: "; Copy->dump());
420 MaybeDeadCopies.remove(Copy);
422 CopyDbgUsers[Copy].insert(&Reader);
438 std::optional<DestSourcePair> CopyOperands =
439 isCopyInstr(PreviousCopy, *
TII, UseCopyInstr);
440 MCRegister PreviousSrc = CopyOperands->Source->getReg().asMCReg();
441 MCRegister PreviousDef = CopyOperands->Destination->getReg().asMCReg();
442 if (Src == PreviousSrc && Def == PreviousDef)
444 if (!
TRI->isSubRegister(PreviousSrc, Src))
446 unsigned SubIdx =
TRI->getSubRegIndex(PreviousSrc, Src);
447 return SubIdx ==
TRI->getSubRegIndex(PreviousDef, Def);
453bool MachineCopyPropagation::eraseIfRedundant(
MachineInstr &Copy,
457 if (
MRI->isReserved(Src) ||
MRI->isReserved(Def))
462 Tracker.findAvailCopy(Copy, Def, *
TRI, *
TII, UseCopyInstr);
466 auto PrevCopyOperands = isCopyInstr(*PrevCopy, *
TII, UseCopyInstr);
468 if (PrevCopyOperands->Destination->isDead())
477 std::optional<DestSourcePair> CopyOperands =
478 isCopyInstr(Copy, *
TII, UseCopyInstr);
481 Register CopyDef = CopyOperands->Destination->getReg();
482 assert(CopyDef == Src || CopyDef == Def);
485 MI.clearRegisterKills(CopyDef,
TRI);
488 if (!CopyOperands->Source->isUndef()) {
489 PrevCopy->
getOperand(PrevCopyOperands->Source->getOperandNo())
493 Copy.eraseFromParent();
499bool MachineCopyPropagation::isBackwardPropagatableRegClassCopy(
501 std::optional<DestSourcePair> CopyOperands =
502 isCopyInstr(Copy, *
TII, UseCopyInstr);
503 Register Def = CopyOperands->Destination->getReg();
507 return URC->contains(Def);
517bool MachineCopyPropagation::isForwardableRegClassCopy(
const MachineInstr &Copy,
520 std::optional<DestSourcePair> CopyOperands =
521 isCopyInstr(Copy, *
TII, UseCopyInstr);
522 Register CopySrcReg = CopyOperands->Source->getReg();
528 return URC->contains(CopySrcReg);
530 auto UseICopyOperands = isCopyInstr(UseI, *
TII, UseCopyInstr);
531 if (!UseICopyOperands)
554 Register UseDstReg = UseICopyOperands->Destination->getReg();
556 bool IsCrossClass =
false;
558 if (RC->contains(CopySrcReg) && RC->contains(UseDstReg)) {
560 if (
TRI->getCrossCopyRegClass(RC) != RC) {
572 Register CopyDstReg = CopyOperands->Destination->getReg();
574 if (RC->contains(CopySrcReg) && RC->contains(CopyDstReg) &&
575 TRI->getCrossCopyRegClass(RC) != RC)
589bool MachineCopyPropagation::hasImplicitOverlap(
const MachineInstr &
MI,
592 if (&MIUse != &
Use && MIUse.isReg() && MIUse.isImplicit() &&
593 MIUse.isUse() &&
TRI->regsOverlap(
Use.getReg(), MIUse.getReg()))
603bool MachineCopyPropagation::hasOverlappingMultipleDef(
606 if ((&MIDef != &MODef) && MIDef.isReg() &&
607 TRI->regsOverlap(Def, MIDef.getReg()))
617 if (!Tracker.hasAnyCopies())
623 for (
unsigned OpIdx = 0, OpEnd =
MI.getNumOperands(); OpIdx < OpEnd;
645 *
TRI, *
TII, UseCopyInstr);
649 std::optional<DestSourcePair> CopyOperands =
650 isCopyInstr(*Copy, *
TII, UseCopyInstr);
651 Register CopyDstReg = CopyOperands->Destination->getReg();
658 if (MOUse.
getReg() != CopyDstReg) {
659 unsigned SubRegIdx =
TRI->getSubRegIndex(CopyDstReg, MOUse.
getReg());
661 "MI source is not a sub-register of Copy destination");
662 ForwardedReg =
TRI->getSubReg(CopySrcReg, SubRegIdx);
664 LLVM_DEBUG(
dbgs() <<
"MCP: Copy source does not have sub-register "
665 <<
TRI->getSubRegIndexName(SubRegIdx) <<
'\n');
671 if (
MRI->isReserved(CopySrcReg) && !
MRI->isConstantPhysReg(CopySrcReg))
674 if (!isForwardableRegClassCopy(*Copy,
MI, OpIdx))
677 if (hasImplicitOverlap(
MI, MOUse))
683 if (isCopyInstr(
MI, *
TII, UseCopyInstr) &&
684 MI.modifiesRegister(CopySrcReg,
TRI) &&
685 !
MI.definesRegister(CopySrcReg)) {
691 LLVM_DEBUG(
dbgs() <<
"MCP: Skipping forwarding due to debug counter:\n "
698 <<
"\n in " <<
MI <<
" from " << *Copy);
700 MOUse.
setReg(ForwardedReg);
711 KMI.clearRegisterKills(CopySrcReg,
TRI);
724 std::optional<DestSourcePair> CopyOperands =
725 isCopyInstr(
MI, *
TII, UseCopyInstr);
728 Register RegSrc = CopyOperands->Source->getReg();
729 Register RegDef = CopyOperands->Destination->getReg();
731 if (!
TRI->regsOverlap(RegDef, RegSrc)) {
733 "MachineCopyPropagation should be run after register allocation!");
753 if (eraseIfRedundant(
MI, Def, Src) || eraseIfRedundant(
MI, Src, Def))
759 CopyOperands = isCopyInstr(
MI, *
TII, UseCopyInstr);
760 Src = CopyOperands->Source->getReg().asMCReg();
764 ReadRegister(Src,
MI, RegularUse);
766 if (!MO.isReg() || !MO.readsReg())
771 ReadRegister(Reg,
MI, RegularUse);
777 if (!
MRI->isReserved(Def))
778 MaybeDeadCopies.insert(&
MI);
787 Tracker.clobberRegister(Def, *
TRI, *
TII, UseCopyInstr);
789 if (!MO.isReg() || !MO.isDef())
794 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
797 Tracker.trackCopy(&
MI, *
TRI, *
TII, UseCopyInstr);
805 if (MO.isReg() && MO.isEarlyClobber()) {
811 ReadRegister(Reg,
MI, RegularUse);
812 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
830 "MachineCopyPropagation should be run after register allocation!");
832 if (MO.isDef() && !MO.isEarlyClobber()) {
835 }
else if (MO.readsReg())
836 ReadRegister(
Reg.asMCReg(),
MI, MO.isDebug() ? DebugUse : RegularUse);
845 MaybeDeadCopies.
begin();
846 DI != MaybeDeadCopies.end();) {
848 std::optional<DestSourcePair> CopyOperands =
849 isCopyInstr(*MaybeDead, *
TII, UseCopyInstr);
850 MCRegister Reg = CopyOperands->Destination->getReg().asMCReg();
858 LLVM_DEBUG(
dbgs() <<
"MCP: Removing copy due to regmask clobbering: ";
863 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
867 DI = MaybeDeadCopies.erase(DI);
876 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
884 LLVM_DEBUG(
dbgs() <<
"MCP: Removing copy due to no live-out succ: ";
887 std::optional<DestSourcePair> CopyOperands =
888 isCopyInstr(*MaybeDead, *
TII, UseCopyInstr);
891 Register SrcReg = CopyOperands->Source->getReg();
892 Register DestReg = CopyOperands->Destination->getReg();
897 CopyDbgUsers[MaybeDead].
begin(), CopyDbgUsers[MaybeDead].
end());
907 MaybeDeadCopies.clear();
908 CopyDbgUsers.clear();
921 if (
MRI.isReserved(Def) ||
MRI.isReserved(Src))
928 if (!Tracker.hasAnyCopies())
931 for (
unsigned OpIdx = 0, OpEnd =
MI.getNumOperands(); OpIdx != OpEnd;
954 std::optional<DestSourcePair> CopyOperands =
955 isCopyInstr(*Copy, *
TII, UseCopyInstr);
956 Register Def = CopyOperands->Destination->getReg();
957 Register Src = CopyOperands->Source->getReg();
959 if (MODef.
getReg() != Src)
962 if (!isBackwardPropagatableRegClassCopy(*Copy,
MI, OpIdx))
965 if (hasImplicitOverlap(
MI, MODef))
968 if (hasOverlappingMultipleDef(
MI, MODef, Def))
973 <<
MI <<
" from " << *Copy);
979 MaybeDeadCopies.insert(Copy);
981 ++NumCopyBackwardPropagated;
985void MachineCopyPropagation::BackwardCopyPropagateBlock(
992 std::optional<DestSourcePair> CopyOperands =
993 isCopyInstr(
MI, *
TII, UseCopyInstr);
994 if (CopyOperands &&
MI.getNumOperands() == 2) {
995 Register DefReg = CopyOperands->Destination->getReg();
996 Register SrcReg = CopyOperands->Source->getReg();
998 if (!
TRI->regsOverlap(DefReg, SrcReg)) {
1006 Tracker.trackCopy(&
MI, *
TRI, *
TII, UseCopyInstr);
1014 if (MO.isReg() && MO.isEarlyClobber()) {
1018 Tracker.invalidateRegister(Reg, *
TRI, *
TII, UseCopyInstr);
1030 Tracker.invalidateRegister(MO.getReg().asMCReg(), *
TRI, *
TII,
1033 if (MO.readsReg()) {
1038 for (
MCRegUnit Unit :
TRI->regunits(MO.getReg().asMCReg())) {
1039 if (
auto *Copy = Tracker.findCopyDefViaUnit(Unit, *
TRI)) {
1040 CopyDbgUsers[
Copy].insert(&
MI);
1044 Tracker.invalidateRegister(MO.getReg().asMCReg(), *
TRI, *
TII,
1051 for (
auto *Copy : MaybeDeadCopies) {
1052 std::optional<DestSourcePair> CopyOperands =
1053 isCopyInstr(*Copy, *
TII, UseCopyInstr);
1054 Register Src = CopyOperands->Source->getReg();
1055 Register Def = CopyOperands->Destination->getReg();
1057 CopyDbgUsers[Copy].
end());
1059 MRI->updateDbgUsersToReg(Src.asMCReg(),
Def.asMCReg(), MaybeDeadDbgUsers);
1060 Copy->eraseFromParent();
1064 MaybeDeadCopies.clear();
1065 CopyDbgUsers.clear();
1073 auto &SC = SpillChain[Leader];
1074 auto &RC = ReloadChain[Leader];
1075 for (
auto I = SC.rbegin(),
E = SC.rend();
I !=
E; ++
I)
1132 auto TryFoldSpillageCopies =
1135 assert(
SC.size() == RC.size() &&
"Spill-reload should be paired");
1151 if (CopySourceInvalid.
count(Spill))
1155 if (CopySourceInvalid.
count(Reload))
1160 if (RC->contains(Def) && RC->contains(Src))
1170 MO.setReg(
New->getReg());
1174 std::optional<DestSourcePair> InnerMostSpillCopy =
1175 isCopyInstr(*SC[0], *
TII, UseCopyInstr);
1176 std::optional<DestSourcePair> OuterMostSpillCopy =
1177 isCopyInstr(*
SC.back(), *
TII, UseCopyInstr);
1178 std::optional<DestSourcePair> InnerMostReloadCopy =
1179 isCopyInstr(*RC[0], *
TII, UseCopyInstr);
1180 std::optional<DestSourcePair> OuterMostReloadCopy =
1181 isCopyInstr(*RC.back(), *
TII, UseCopyInstr);
1182 if (!CheckCopyConstraint(OuterMostSpillCopy->Source->getReg(),
1183 InnerMostSpillCopy->Source->getReg()) ||
1184 !CheckCopyConstraint(InnerMostReloadCopy->Destination->getReg(),
1185 OuterMostReloadCopy->Destination->getReg()))
1188 SpillageChainsLength +=
SC.size() + RC.size();
1189 NumSpillageChains += 1;
1190 UpdateReg(SC[0], InnerMostSpillCopy->Destination,
1191 OuterMostSpillCopy->Source);
1192 UpdateReg(RC[0], InnerMostReloadCopy->Source,
1193 OuterMostReloadCopy->Destination);
1195 for (
size_t I = 1;
I <
SC.size() - 1; ++
I) {
1196 SC[
I]->eraseFromParent();
1197 RC[
I]->eraseFromParent();
1202 auto IsFoldableCopy = [
this](
const MachineInstr &MaybeCopy) {
1203 if (MaybeCopy.getNumImplicitOperands() > 0)
1205 std::optional<DestSourcePair> CopyOperands =
1206 isCopyInstr(MaybeCopy, *
TII, UseCopyInstr);
1209 Register Src = CopyOperands->Source->getReg();
1210 Register Def = CopyOperands->Destination->getReg();
1211 return Src &&
Def && !
TRI->regsOverlap(Src, Def) &&
1212 CopyOperands->Source->isRenamable() &&
1213 CopyOperands->Destination->isRenamable();
1216 auto IsSpillReloadPair = [&,
this](
const MachineInstr &Spill,
1218 if (!IsFoldableCopy(Spill) || !IsFoldableCopy(Reload))
1220 std::optional<DestSourcePair> SpillCopy =
1221 isCopyInstr(Spill, *
TII, UseCopyInstr);
1222 std::optional<DestSourcePair> ReloadCopy =
1223 isCopyInstr(Reload, *
TII, UseCopyInstr);
1224 if (!SpillCopy || !ReloadCopy)
1226 return SpillCopy->Source->getReg() == ReloadCopy->Destination->getReg() &&
1227 SpillCopy->Destination->getReg() == ReloadCopy->Source->getReg();
1230 auto IsChainedCopy = [&,
this](
const MachineInstr &Prev,
1232 if (!IsFoldableCopy(Prev) || !IsFoldableCopy(Current))
1234 std::optional<DestSourcePair> PrevCopy =
1235 isCopyInstr(Prev, *
TII, UseCopyInstr);
1236 std::optional<DestSourcePair> CurrentCopy =
1237 isCopyInstr(Current, *
TII, UseCopyInstr);
1238 if (!PrevCopy || !CurrentCopy)
1240 return PrevCopy->Source->getReg() == CurrentCopy->Destination->getReg();
1244 std::optional<DestSourcePair> CopyOperands =
1245 isCopyInstr(
MI, *
TII, UseCopyInstr);
1249 if (!CopyOperands) {
1257 Tracker.findLastSeenUseInCopy(
Reg.asMCReg(), *
TRI);
1263 CopySourceInvalid.
insert(LastUseCopy);
1271 if (Tracker.findLastSeenDefInCopy(
MI,
Reg.asMCReg(), *
TRI, *
TII,
1274 RegsToClobber.
insert(Reg);
1276 for (
Register Reg : RegsToClobber) {
1277 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
1284 Register Src = CopyOperands->Source->getReg();
1285 Register Def = CopyOperands->Destination->getReg();
1287 LLVM_DEBUG(
dbgs() <<
"MCP: Searching paired spill for reload: ");
1290 Tracker.findLastSeenDefInCopy(
MI, Src.asMCReg(), *
TRI, *
TII, UseCopyInstr);
1291 bool MaybeSpillIsChained = ChainLeader.
count(MaybeSpill);
1292 if (!MaybeSpillIsChained && MaybeSpill &&
1293 IsSpillReloadPair(*MaybeSpill,
MI)) {
1329 Tracker.findLastSeenUseInCopy(
Def.asMCReg(), *
TRI);
1330 auto Leader = ChainLeader.
find(MaybePrevReload);
1332 if (Leader == ChainLeader.
end() ||
1333 (MaybePrevReload && !IsChainedCopy(*MaybePrevReload,
MI))) {
1336 "SpillChain should not have contained newly found chain");
1338 assert(MaybePrevReload &&
1339 "Found a valid leader through nullptr should not happend");
1342 "Existing chain's length should be larger than zero");
1345 "Newly found paired spill-reload should not belong to any chain "
1347 ChainLeader.
insert({MaybeSpill,
L});
1349 SpillChain[
L].push_back(MaybeSpill);
1350 ReloadChain[
L].push_back(&
MI);
1353 }
else if (MaybeSpill && !MaybeSpillIsChained) {
1370 Tracker.clobberRegister(Src.asMCReg(), *
TRI, *
TII, UseCopyInstr);
1374 Tracker.trackCopy(&
MI, *
TRI, *
TII, UseCopyInstr);
1377 for (
auto I = SpillChain.
begin(),
E = SpillChain.
end();
I !=
E; ++
I) {
1378 auto &
SC =
I->second;
1380 "Reload chain of the same leader should exist");
1381 auto &RC = ReloadChain[
I->first];
1382 TryFoldSpillageCopies(SC, RC);
1385 MaybeDeadCopies.clear();
1386 CopyDbgUsers.clear();
1390bool MachineCopyPropagation::runOnMachineFunction(
MachineFunction &MF) {
1394 bool isSpillageCopyElimEnabled =
false;
1397 isSpillageCopyElimEnabled =
1401 isSpillageCopyElimEnabled =
true;
1404 isSpillageCopyElimEnabled =
false;
1415 if (isSpillageCopyElimEnabled)
1416 EliminateSpillageCopies(
MBB);
1417 BackwardCopyPropagateBlock(
MBB);
1418 ForwardCopyPropagateBlock(
MBB);
1426 return new MachineCopyPropagation(UseCopyInstr);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
static void clear(coro::Shape &Shape)
This file provides an implementation of debug counters.
#define DEBUG_COUNTER(VARNAME, COUNTERNAME, DESC)
This file defines the DenseMap class.
const HexagonInstrInfo * TII
static cl::opt< cl::boolOrDefault > EnableSpillageCopyElimination("enable-spill-copy-elim", cl::Hidden)
static void LLVM_ATTRIBUTE_UNUSED printSpillReloadChain(DenseMap< MachineInstr *, SmallVector< MachineInstr * > > &SpillChain, DenseMap< MachineInstr *, SmallVector< MachineInstr * > > &ReloadChain, MachineInstr *Leader)
static bool isBackwardPropagatableCopy(const DestSourcePair &CopyOperands, const MachineRegisterInfo &MRI, const TargetInstrInfo &TII)
static bool isNopCopy(const MachineInstr &PreviousCopy, MCRegister Src, MCRegister Def, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, bool UseCopyInstr)
Return true if PreviousCopy did copy register Src to register Def.
static cl::opt< bool > MCPUseCopyInstr("mcp-use-is-copy-instr", cl::init(false), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static bool shouldExecute(unsigned CounterName)
iterator find(const_arg_type_t< KeyT > Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Wrapper class representing physical registers. Should be passed by value.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
MachineOperand class - Representation of each machine instruction operand.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
iterator begin()
Get an iterator to the beginning of the SetVector.
A SetVector that performs no allocations if smaller than a certain size.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual bool enableSpillageCopyElimination() const
Enable spillage copy elimination in MachineCopyPropagation pass.
virtual const TargetInstrInfo * getInstrInfo() const
A Use represents the edge between a Value definition and its users.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
reverse_self_iterator getReverseIterator()
self_iterator getIterator()
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< DefNode * > Def
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
auto drop_end(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the last N elements excluded.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeMachineCopyPropagationPass(PassRegistry &)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
const MachineOperand * Source
const MachineOperand * Destination