78#define DEBUG_TYPE "machine-cp"
80STATISTIC(NumDeletes,
"Number of dead copies deleted");
81STATISTIC(NumCopyForwards,
"Number of copy uses forwarded");
82STATISTIC(NumCopyBackwardPropagated,
"Number of copy defs backward propagated");
83STATISTIC(SpillageChainsLength,
"Length of spillage chains");
84STATISTIC(NumSpillageChains,
"Number of spillage chains");
86 "Controls which register COPYs are forwarded");
95static std::optional<DestSourcePair> isCopyInstr(
const MachineInstr &
MI,
99 return TII.isCopyInstr(
MI);
102 return std::optional<DestSourcePair>(
125 auto CI =
Copies.find(*RUI);
127 CI->second.Avail =
false;
139 RegsToInvalidate.
insert(Reg);
144 std::optional<DestSourcePair> CopyOperands =
145 isCopyInstr(*
MI,
TII, UseCopyInstr);
146 assert(CopyOperands &&
"Expect copy");
149 CopyOperands->Destination->getReg().asMCReg());
150 RegsToInvalidate.
insert(CopyOperands->Source->getReg().asMCReg());
152 RegsToInvalidate.
insert(
I->second.DefRegs.begin(),
153 I->second.DefRegs.end());
156 for (
MCRegister InvalidReg : RegsToInvalidate)
169 markRegsUnavailable(
I->second.DefRegs,
TRI);
173 std::optional<DestSourcePair> CopyOperands =
174 isCopyInstr(*
MI,
TII, UseCopyInstr);
175 markRegsUnavailable({CopyOperands->Destination->getReg().asMCReg()},
187 std::optional<DestSourcePair> CopyOperands =
188 isCopyInstr(*
MI,
TII, UseCopyInstr);
189 assert(CopyOperands &&
"Tracking non-copy?");
191 MCRegister Src = CopyOperands->Source->getReg().asMCReg();
192 MCRegister Def = CopyOperands->Destination->getReg().asMCReg();
196 Copies[*RUI] = {
MI,
nullptr, {},
true};
201 auto I =
Copies.insert({*RUI, {
nullptr,
nullptr, {},
false}});
202 auto &
Copy =
I.first->second;
204 Copy.DefRegs.push_back(Def);
205 Copy.LastSeenUseInCopy =
MI;
209 bool hasAnyCopies() {
215 bool MustBeAvailable =
false) {
216 auto CI =
Copies.find(RegUnit);
219 if (MustBeAvailable && !CI->second.Avail)
221 return CI->second.MI;
226 auto CI =
Copies.find(RegUnit);
229 if (CI->second.DefRegs.size() != 1)
232 return findCopyForUnit(*RUI,
TRI,
true);
245 std::optional<DestSourcePair> CopyOperands =
246 isCopyInstr(*AvailCopy,
TII, UseCopyInstr);
247 Register AvailSrc = CopyOperands->Source->getReg();
248 Register AvailDef = CopyOperands->Destination->getReg();
249 if (!
TRI.isSubRegisterEq(AvailSrc, Reg))
257 if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef))
270 findCopyForUnit(*RUI,
TRI,
true);
275 std::optional<DestSourcePair> CopyOperands =
276 isCopyInstr(*AvailCopy,
TII, UseCopyInstr);
277 Register AvailSrc = CopyOperands->Source->getReg();
278 Register AvailDef = CopyOperands->Destination->getReg();
279 if (!
TRI.isSubRegisterEq(AvailDef, Reg))
288 if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef))
301 auto CI =
Copies.find(*RUI);
302 if (CI ==
Copies.end() || !CI->second.Avail)
306 std::optional<DestSourcePair> CopyOperands =
307 isCopyInstr(*DefCopy,
TII, UseCopyInstr);
308 Register Def = CopyOperands->Destination->getReg();
309 if (!
TRI.isSubRegisterEq(Def, Reg))
317 if (MO.clobbersPhysReg(Def)) {
330 auto CI =
Copies.find(*RUI);
333 return CI->second.LastSeenUseInCopy;
352 MachineCopyPropagation(
bool CopyInstr =
false)
366 MachineFunctionProperties::Property::NoVRegs);
370 typedef enum { DebugUse =
false, RegularUse =
true }
DebugType;
379 bool isForwardableRegClassCopy(
const MachineInstr &Copy,
381 bool isBackwardPropagatableRegClassCopy(
const MachineInstr &Copy,
401char MachineCopyPropagation::ID = 0;
406 "Machine Copy Propagation Pass",
false,
false)
415 if (DT == RegularUse) {
416 LLVM_DEBUG(
dbgs() <<
"MCP: Copy is used - not dead: "; Copy->dump());
417 MaybeDeadCopies.remove(Copy);
419 CopyDbgUsers[Copy].insert(&Reader);
435 std::optional<DestSourcePair> CopyOperands =
436 isCopyInstr(PreviousCopy, *
TII, UseCopyInstr);
437 MCRegister PreviousSrc = CopyOperands->Source->getReg().asMCReg();
438 MCRegister PreviousDef = CopyOperands->Destination->getReg().asMCReg();
439 if (Src == PreviousSrc && Def == PreviousDef)
441 if (!
TRI->isSubRegister(PreviousSrc, Src))
443 unsigned SubIdx =
TRI->getSubRegIndex(PreviousSrc, Src);
444 return SubIdx ==
TRI->getSubRegIndex(PreviousDef, Def);
450bool MachineCopyPropagation::eraseIfRedundant(
MachineInstr &Copy,
454 if (
MRI->isReserved(Src) ||
MRI->isReserved(Def))
459 Tracker.findAvailCopy(Copy, Def, *
TRI, *
TII, UseCopyInstr);
463 auto PrevCopyOperands = isCopyInstr(*PrevCopy, *
TII, UseCopyInstr);
465 if (PrevCopyOperands->Destination->isDead())
474 std::optional<DestSourcePair> CopyOperands =
475 isCopyInstr(Copy, *
TII, UseCopyInstr);
478 Register CopyDef = CopyOperands->Destination->getReg();
479 assert(CopyDef == Src || CopyDef == Def);
482 MI.clearRegisterKills(CopyDef,
TRI);
484 Copy.eraseFromParent();
490bool MachineCopyPropagation::isBackwardPropagatableRegClassCopy(
492 std::optional<DestSourcePair> CopyOperands =
493 isCopyInstr(Copy, *
TII, UseCopyInstr);
494 Register Def = CopyOperands->Destination->getReg();
498 return URC->contains(Def);
508bool MachineCopyPropagation::isForwardableRegClassCopy(
const MachineInstr &Copy,
511 std::optional<DestSourcePair> CopyOperands =
512 isCopyInstr(Copy, *
TII, UseCopyInstr);
513 Register CopySrcReg = CopyOperands->Source->getReg();
519 return URC->contains(CopySrcReg);
521 auto UseICopyOperands = isCopyInstr(UseI, *
TII, UseCopyInstr);
522 if (!UseICopyOperands)
545 Register UseDstReg = UseICopyOperands->Destination->getReg();
547 bool IsCrossClass =
false;
549 if (RC->contains(CopySrcReg) && RC->contains(UseDstReg)) {
551 if (
TRI->getCrossCopyRegClass(RC) != RC) {
563 Register CopyDstReg = CopyOperands->Destination->getReg();
565 if (RC->contains(CopySrcReg) && RC->contains(CopyDstReg) &&
566 TRI->getCrossCopyRegClass(RC) != RC)
580bool MachineCopyPropagation::hasImplicitOverlap(
const MachineInstr &
MI,
583 if (&MIUse != &
Use && MIUse.isReg() && MIUse.isImplicit() &&
584 MIUse.isUse() &&
TRI->regsOverlap(
Use.getReg(), MIUse.getReg()))
594bool MachineCopyPropagation::hasOverlappingMultipleDef(
597 if ((&MIDef != &MODef) && MIDef.isReg() &&
598 TRI->regsOverlap(Def, MIDef.getReg()))
608 if (!Tracker.hasAnyCopies())
614 for (
unsigned OpIdx = 0, OpEnd =
MI.getNumOperands(); OpIdx < OpEnd;
636 *
TRI, *
TII, UseCopyInstr);
640 std::optional<DestSourcePair> CopyOperands =
641 isCopyInstr(*Copy, *
TII, UseCopyInstr);
642 Register CopyDstReg = CopyOperands->Destination->getReg();
649 if (MOUse.
getReg() != CopyDstReg) {
650 unsigned SubRegIdx =
TRI->getSubRegIndex(CopyDstReg, MOUse.
getReg());
652 "MI source is not a sub-register of Copy destination");
653 ForwardedReg =
TRI->getSubReg(CopySrcReg, SubRegIdx);
655 LLVM_DEBUG(
dbgs() <<
"MCP: Copy source does not have sub-register "
656 <<
TRI->getSubRegIndexName(SubRegIdx) <<
'\n');
662 if (
MRI->isReserved(CopySrcReg) && !
MRI->isConstantPhysReg(CopySrcReg))
665 if (!isForwardableRegClassCopy(*Copy,
MI, OpIdx))
668 if (hasImplicitOverlap(
MI, MOUse))
674 if (isCopyInstr(
MI, *
TII, UseCopyInstr) &&
675 MI.modifiesRegister(CopySrcReg,
TRI) &&
676 !
MI.definesRegister(CopySrcReg)) {
682 LLVM_DEBUG(
dbgs() <<
"MCP: Skipping forwarding due to debug counter:\n "
689 <<
"\n in " <<
MI <<
" from " << *Copy);
691 MOUse.
setReg(ForwardedReg);
702 KMI.clearRegisterKills(CopySrcReg,
TRI);
715 std::optional<DestSourcePair> CopyOperands =
716 isCopyInstr(
MI, *
TII, UseCopyInstr);
719 Register RegSrc = CopyOperands->Source->getReg();
720 Register RegDef = CopyOperands->Destination->getReg();
722 if (!
TRI->regsOverlap(RegDef, RegSrc)) {
724 "MachineCopyPropagation should be run after register allocation!");
744 if (eraseIfRedundant(
MI, Def, Src) || eraseIfRedundant(
MI, Src, Def))
750 CopyOperands = isCopyInstr(
MI, *
TII, UseCopyInstr);
751 Src = CopyOperands->Source->getReg().asMCReg();
755 ReadRegister(Src,
MI, RegularUse);
757 if (!MO.isReg() || !MO.readsReg())
762 ReadRegister(Reg,
MI, RegularUse);
768 if (!
MRI->isReserved(Def))
769 MaybeDeadCopies.insert(&
MI);
778 Tracker.clobberRegister(Def, *
TRI, *
TII, UseCopyInstr);
780 if (!MO.isReg() || !MO.isDef())
785 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
788 Tracker.trackCopy(&
MI, *
TRI, *
TII, UseCopyInstr);
796 if (MO.isReg() && MO.isEarlyClobber()) {
802 ReadRegister(Reg,
MI, RegularUse);
803 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
821 "MachineCopyPropagation should be run after register allocation!");
823 if (MO.isDef() && !MO.isEarlyClobber()) {
826 }
else if (MO.readsReg())
827 ReadRegister(
Reg.asMCReg(),
MI, MO.isDebug() ? DebugUse : RegularUse);
836 MaybeDeadCopies.
begin();
837 DI != MaybeDeadCopies.end();) {
839 std::optional<DestSourcePair> CopyOperands =
840 isCopyInstr(*MaybeDead, *
TII, UseCopyInstr);
841 MCRegister Reg = CopyOperands->Destination->getReg().asMCReg();
849 LLVM_DEBUG(
dbgs() <<
"MCP: Removing copy due to regmask clobbering: ";
854 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
858 DI = MaybeDeadCopies.erase(DI);
867 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
875 LLVM_DEBUG(
dbgs() <<
"MCP: Removing copy due to no live-out succ: ";
878 std::optional<DestSourcePair> CopyOperands =
879 isCopyInstr(*MaybeDead, *
TII, UseCopyInstr);
882 Register SrcReg = CopyOperands->Source->getReg();
883 Register DestReg = CopyOperands->Destination->getReg();
888 CopyDbgUsers[MaybeDead].
begin(), CopyDbgUsers[MaybeDead].
end());
898 MaybeDeadCopies.clear();
899 CopyDbgUsers.clear();
912 if (
MRI.isReserved(Def) ||
MRI.isReserved(Src))
919 if (!Tracker.hasAnyCopies())
922 for (
unsigned OpIdx = 0, OpEnd =
MI.getNumOperands(); OpIdx != OpEnd;
945 std::optional<DestSourcePair> CopyOperands =
946 isCopyInstr(*Copy, *
TII, UseCopyInstr);
947 Register Def = CopyOperands->Destination->getReg();
948 Register Src = CopyOperands->Source->getReg();
950 if (MODef.
getReg() != Src)
953 if (!isBackwardPropagatableRegClassCopy(*Copy,
MI, OpIdx))
956 if (hasImplicitOverlap(
MI, MODef))
959 if (hasOverlappingMultipleDef(
MI, MODef, Def))
964 <<
MI <<
" from " << *Copy);
970 MaybeDeadCopies.insert(Copy);
972 ++NumCopyBackwardPropagated;
976void MachineCopyPropagation::BackwardCopyPropagateBlock(
983 std::optional<DestSourcePair> CopyOperands =
984 isCopyInstr(
MI, *
TII, UseCopyInstr);
985 if (CopyOperands &&
MI.getNumOperands() == 2) {
986 Register DefReg = CopyOperands->Destination->getReg();
987 Register SrcReg = CopyOperands->Source->getReg();
989 if (!
TRI->regsOverlap(DefReg, SrcReg)) {
997 Tracker.trackCopy(&
MI, *
TRI, *
TII, UseCopyInstr);
1005 if (MO.isReg() && MO.isEarlyClobber()) {
1009 Tracker.invalidateRegister(Reg, *
TRI, *
TII, UseCopyInstr);
1021 Tracker.invalidateRegister(MO.getReg().asMCReg(), *
TRI, *
TII,
1024 if (MO.readsReg()) {
1031 if (
auto *Copy = Tracker.findCopyDefViaUnit(*RUI, *
TRI)) {
1032 CopyDbgUsers[
Copy].insert(&
MI);
1036 Tracker.invalidateRegister(MO.getReg().asMCReg(), *
TRI, *
TII,
1043 for (
auto *Copy : MaybeDeadCopies) {
1044 std::optional<DestSourcePair> CopyOperands =
1045 isCopyInstr(*Copy, *
TII, UseCopyInstr);
1046 Register Src = CopyOperands->Source->getReg();
1047 Register Def = CopyOperands->Destination->getReg();
1049 CopyDbgUsers[Copy].
end());
1051 MRI->updateDbgUsersToReg(Src.asMCReg(),
Def.asMCReg(), MaybeDeadDbgUsers);
1052 Copy->eraseFromParent();
1056 MaybeDeadCopies.clear();
1057 CopyDbgUsers.clear();
1065 auto &SC = SpillChain[Leader];
1066 auto &RC = ReloadChain[Leader];
1067 for (
auto I = SC.rbegin(),
E = SC.rend();
I !=
E; ++
I)
1124 auto TryFoldSpillageCopies =
1127 assert(
SC.size() == RC.size() &&
"Spill-reload should be paired");
1143 if (CopySourceInvalid.
count(Spill))
1147 if (CopySourceInvalid.
count(Reload))
1152 if (RC->contains(Def) && RC->contains(Src))
1162 MO.setReg(
New->getReg());
1166 std::optional<DestSourcePair> InnerMostSpillCopy =
1167 isCopyInstr(*SC[0], *
TII, UseCopyInstr);
1168 std::optional<DestSourcePair> OuterMostSpillCopy =
1169 isCopyInstr(*
SC.back(), *
TII, UseCopyInstr);
1170 std::optional<DestSourcePair> InnerMostReloadCopy =
1171 isCopyInstr(*RC[0], *
TII, UseCopyInstr);
1172 std::optional<DestSourcePair> OuterMostReloadCopy =
1173 isCopyInstr(*RC.back(), *
TII, UseCopyInstr);
1174 if (!CheckCopyConstraint(OuterMostSpillCopy->Source->getReg(),
1175 InnerMostSpillCopy->Source->getReg()) ||
1176 !CheckCopyConstraint(InnerMostReloadCopy->Destination->getReg(),
1177 OuterMostReloadCopy->Destination->getReg()))
1180 SpillageChainsLength +=
SC.size() + RC.size();
1181 NumSpillageChains += 1;
1182 UpdateReg(SC[0], InnerMostSpillCopy->Destination,
1183 OuterMostSpillCopy->Source);
1184 UpdateReg(RC[0], InnerMostReloadCopy->Source,
1185 OuterMostReloadCopy->Destination);
1187 for (
size_t I = 1;
I <
SC.size() - 1; ++
I) {
1188 SC[
I]->eraseFromParent();
1189 RC[
I]->eraseFromParent();
1194 auto IsFoldableCopy = [
this](
const MachineInstr &MaybeCopy) {
1195 if (MaybeCopy.getNumImplicitOperands() > 0)
1197 std::optional<DestSourcePair> CopyOperands =
1198 isCopyInstr(MaybeCopy, *
TII, UseCopyInstr);
1201 Register Src = CopyOperands->Source->getReg();
1202 Register Def = CopyOperands->Destination->getReg();
1203 return Src &&
Def && !
TRI->regsOverlap(Src, Def) &&
1204 CopyOperands->Source->isRenamable() &&
1205 CopyOperands->Destination->isRenamable();
1208 auto IsSpillReloadPair = [&,
this](
const MachineInstr &Spill,
1210 if (!IsFoldableCopy(Spill) || !IsFoldableCopy(Reload))
1212 std::optional<DestSourcePair> SpillCopy =
1213 isCopyInstr(Spill, *
TII, UseCopyInstr);
1214 std::optional<DestSourcePair> ReloadCopy =
1215 isCopyInstr(Reload, *
TII, UseCopyInstr);
1216 if (!SpillCopy || !ReloadCopy)
1218 return SpillCopy->Source->getReg() == ReloadCopy->Destination->getReg() &&
1219 SpillCopy->Destination->getReg() == ReloadCopy->Source->getReg();
1222 auto IsChainedCopy = [&,
this](
const MachineInstr &Prev,
1224 if (!IsFoldableCopy(Prev) || !IsFoldableCopy(Current))
1226 std::optional<DestSourcePair> PrevCopy =
1227 isCopyInstr(Prev, *
TII, UseCopyInstr);
1228 std::optional<DestSourcePair> CurrentCopy =
1229 isCopyInstr(Current, *
TII, UseCopyInstr);
1230 if (!PrevCopy || !CurrentCopy)
1232 return PrevCopy->Source->getReg() == CurrentCopy->Destination->getReg();
1236 std::optional<DestSourcePair> CopyOperands =
1237 isCopyInstr(
MI, *
TII, UseCopyInstr);
1241 if (!CopyOperands) {
1249 Tracker.findLastSeenUseInCopy(
Reg.asMCReg(), *
TRI);
1255 CopySourceInvalid.
insert(LastUseCopy);
1263 if (Tracker.findLastSeenDefInCopy(
MI,
Reg.asMCReg(), *
TRI, *
TII,
1266 RegsToClobber.
insert(Reg);
1268 for (
Register Reg : RegsToClobber) {
1269 Tracker.clobberRegister(Reg, *
TRI, *
TII, UseCopyInstr);
1276 Register Src = CopyOperands->Source->getReg();
1277 Register Def = CopyOperands->Destination->getReg();
1279 LLVM_DEBUG(
dbgs() <<
"MCP: Searching paired spill for reload: ");
1282 Tracker.findLastSeenDefInCopy(
MI, Src.asMCReg(), *
TRI, *
TII, UseCopyInstr);
1283 bool MaybeSpillIsChained = ChainLeader.
count(MaybeSpill);
1284 if (!MaybeSpillIsChained && MaybeSpill &&
1285 IsSpillReloadPair(*MaybeSpill,
MI)) {
1321 Tracker.findLastSeenUseInCopy(
Def.asMCReg(), *
TRI);
1322 auto Leader = ChainLeader.
find(MaybePrevReload);
1324 if (Leader == ChainLeader.
end() ||
1325 (MaybePrevReload && !IsChainedCopy(*MaybePrevReload,
MI))) {
1328 "SpillChain should not have contained newly found chain");
1330 assert(MaybePrevReload &&
1331 "Found a valid leader through nullptr should not happend");
1334 "Existing chain's length should be larger than zero");
1337 "Newly found paired spill-reload should not belong to any chain "
1339 ChainLeader.
insert({MaybeSpill,
L});
1341 SpillChain[
L].push_back(MaybeSpill);
1342 ReloadChain[
L].push_back(&
MI);
1345 }
else if (MaybeSpill && !MaybeSpillIsChained) {
1362 Tracker.clobberRegister(Src.asMCReg(), *
TRI, *
TII, UseCopyInstr);
1366 Tracker.trackCopy(&
MI, *
TRI, *
TII, UseCopyInstr);
1369 for (
auto I = SpillChain.
begin(),
E = SpillChain.
end();
I !=
E; ++
I) {
1370 auto &
SC =
I->second;
1372 "Reload chain of the same leader should exist");
1373 auto &RC = ReloadChain[
I->first];
1374 TryFoldSpillageCopies(SC, RC);
1377 MaybeDeadCopies.clear();
1378 CopyDbgUsers.clear();
1382bool MachineCopyPropagation::runOnMachineFunction(
MachineFunction &MF) {
1386 bool isSpillageCopyElimEnabled =
false;
1389 isSpillageCopyElimEnabled =
1393 isSpillageCopyElimEnabled =
true;
1396 isSpillageCopyElimEnabled =
false;
1407 if (isSpillageCopyElimEnabled)
1408 EliminateSpillageCopies(
MBB);
1409 BackwardCopyPropagateBlock(
MBB);
1410 ForwardCopyPropagateBlock(
MBB);
1418 return new MachineCopyPropagation(UseCopyInstr);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
static void clear(coro::Shape &Shape)
This file provides an implementation of debug counters.
#define DEBUG_COUNTER(VARNAME, COUNTERNAME, DESC)
This file defines the DenseMap class.
const HexagonInstrInfo * TII
static cl::opt< cl::boolOrDefault > EnableSpillageCopyElimination("enable-spill-copy-elim", cl::Hidden)
static void LLVM_ATTRIBUTE_UNUSED printSpillReloadChain(DenseMap< MachineInstr *, SmallVector< MachineInstr * > > &SpillChain, DenseMap< MachineInstr *, SmallVector< MachineInstr * > > &ReloadChain, MachineInstr *Leader)
static bool isBackwardPropagatableCopy(const DestSourcePair &CopyOperands, const MachineRegisterInfo &MRI, const TargetInstrInfo &TII)
static bool isNopCopy(const MachineInstr &PreviousCopy, MCRegister Src, MCRegister Def, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, bool UseCopyInstr)
Return true if PreviousCopy did copy register Src to register Def.
static cl::opt< bool > MCPUseCopyInstr("mcp-use-is-copy-instr", cl::init(false), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static bool shouldExecute(unsigned CounterName)
iterator find(const_arg_type_t< KeyT > Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Wrapper class representing physical registers. Should be passed by value.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
MachineOperand class - Representation of each machine instruction operand.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
iterator begin()
Get an iterator to the beginning of the SetVector.
A SetVector that performs no allocations if smaller than a certain size.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual bool enableSpillageCopyElimination() const
Enable spillage copy elimination in MachineCopyPropagation pass.
virtual const TargetInstrInfo * getInstrInfo() const
A Use represents the edge between a Value definition and its users.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
reverse_self_iterator getReverseIterator()
self_iterator getIterator()
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeMachineCopyPropagationPass(PassRegistry &)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
const MachineOperand * Source
const MachineOperand * Destination