LLVM 18.0.0git
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1//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8/// \file
9/// This file a TargetTransformInfo::Concept conforming object specific to the
10/// X86 target machine. It uses the target's detailed information to
11/// provide more precise answers to certain TTI queries, while letting the
12/// target independent and default TTI implementations handle the rest.
19#include "X86TargetMachine.h"
22#include <optional>
24namespace llvm {
26class InstCombiner;
28class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
31 friend BaseT;
33 const X86Subtarget *ST;
34 const X86TargetLowering *TLI;
36 const X86Subtarget *getST() const { return ST; }
37 const X86TargetLowering *getTLI() const { return TLI; }
39 const FeatureBitset InlineFeatureIgnoreList = {
40 // This indicates the CPU is 64 bit capable not that we are in 64-bit
41 // mode.
42 X86::FeatureX86_64,
44 // These features don't have any intrinsics or ABI effect.
45 X86::FeatureNOPL,
46 X86::FeatureCX16,
47 X86::FeatureLAHFSAHF64,
49 // Some older targets can be setup to fold unaligned loads.
50 X86::FeatureSSEUnalignedMem,
52 // Codegen control options.
53 X86::TuningFast11ByteNOP,
54 X86::TuningFast15ByteNOP,
55 X86::TuningFastBEXTR,
56 X86::TuningFastHorizontalOps,
57 X86::TuningFastLZCNT,
58 X86::TuningFastScalarFSQRT,
59 X86::TuningFastSHLDRotate,
60 X86::TuningFastScalarShiftMasks,
61 X86::TuningFastVectorShiftMasks,
62 X86::TuningFastVariableCrossLaneShuffle,
63 X86::TuningFastVariablePerLaneShuffle,
64 X86::TuningFastVectorFSQRT,
65 X86::TuningLEAForSP,
66 X86::TuningLEAUsesAG,
67 X86::TuningLZCNTFalseDeps,
68 X86::TuningBranchFusion,
69 X86::TuningMacroFusion,
70 X86::TuningPadShortFunctions,
71 X86::TuningPOPCNTFalseDeps,
72 X86::TuningMULCFalseDeps,
73 X86::TuningPERMFalseDeps,
74 X86::TuningRANGEFalseDeps,
75 X86::TuningGETMANTFalseDeps,
76 X86::TuningMULLQFalseDeps,
77 X86::TuningSlow3OpsLEA,
78 X86::TuningSlowDivide32,
79 X86::TuningSlowDivide64,
80 X86::TuningSlowIncDec,
81 X86::TuningSlowLEA,
82 X86::TuningSlowPMADDWD,
83 X86::TuningSlowPMULLD,
84 X86::TuningSlowSHLD,
85 X86::TuningSlowTwoMemOps,
86 X86::TuningSlowUAMem16,
87 X86::TuningPreferMaskRegisters,
88 X86::TuningInsertVZEROUPPER,
89 X86::TuningUseSLMArithCosts,
90 X86::TuningUseGLMDivSqrtCosts,
91 X86::TuningNoDomainDelay,
92 X86::TuningNoDomainDelayMov,
93 X86::TuningNoDomainDelayShuffle,
94 X86::TuningNoDomainDelayBlend,
95 X86::TuningPreferShiftShuffle,
96 X86::TuningFastImmVectorShift,
98 // Perf-tuning flags.
99 X86::TuningFastGather,
100 X86::TuningSlowUAMem32,
101 X86::TuningAllowLight256Bit,
103 // Based on whether user set the -mprefer-vector-width command line.
104 X86::TuningPrefer128Bit,
105 X86::TuningPrefer256Bit,
107 // CPU name enums. These just follow CPU string.
108 X86::ProcIntelAtom
109 };
112 explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
113 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
114 TLI(ST->getTargetLowering()) {}
116 /// \name Scalar TTI Implementations
117 /// @{
120 /// @}
122 /// \name Cache TTI Implementation
123 /// @{
124 std::optional<unsigned> getCacheSize(
125 TargetTransformInfo::CacheLevel Level) const override;
126 std::optional<unsigned> getCacheAssociativity(
127 TargetTransformInfo::CacheLevel Level) const override;
128 /// @}
130 /// \name Vector TTI Implementations
131 /// @{
133 unsigned getNumberOfRegisters(unsigned ClassID) const;
135 unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
140 TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
141 ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
142 const Instruction *CxtI = nullptr);
143 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
144 ArrayRef<int> Mask,
146 VectorType *SubTp,
147 ArrayRef<const Value *> Args = std::nullopt);
148 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
151 const Instruction *I = nullptr);
152 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
153 CmpInst::Predicate VecPred,
155 const Instruction *I = nullptr);
157 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
159 unsigned Index, Value *Op0, Value *Op1);
160 InstructionCost getScalarizationOverhead(VectorType *Ty,
161 const APInt &DemandedElts,
162 bool Insert, bool Extract,
164 InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
165 int VF,
166 const APInt &DemandedDstElts,
168 InstructionCost
169 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
171 TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
172 const Instruction *I = nullptr);
173 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
174 Align Alignment, unsigned AddressSpace,
176 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
177 const Value *Ptr, bool VariableMask,
178 Align Alignment,
180 const Instruction *I);
181 InstructionCost getPointersChainCost(ArrayRef<const Value *> Ptrs,
182 const Value *Base,
183 const TTI::PointersChainInfo &Info,
184 Type *AccessTy,
186 InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE,
187 const SCEV *Ptr);
189 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
190 IntrinsicInst &II) const;
191 std::optional<Value *>
192 simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
193 APInt DemandedMask, KnownBits &Known,
194 bool &KnownBitsComputed) const;
195 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
196 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
197 APInt &UndefElts2, APInt &UndefElts3,
198 std::function<void(Instruction *, unsigned, APInt, APInt &)>
199 SimplifyAndSetOp) const;
203 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
206 InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
207 std::optional<FastMathFlags> FMF,
210 InstructionCost getMinMaxCost(Intrinsic::ID IID, Type *Ty,
212 FastMathFlags FMF);
214 InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
215 FastMathFlags FMF,
218 InstructionCost getInterleavedMemoryOpCost(
219 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
220 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
221 bool UseMaskForCond = false, bool UseMaskForGaps = false);
222 InstructionCost getInterleavedMemoryOpCostAVX512(
223 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
224 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
225 TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
226 bool UseMaskForGaps = false);
228 InstructionCost getIntImmCost(int64_t);
230 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
233 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
234 const Instruction *I = nullptr);
236 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
237 const APInt &Imm, Type *Ty,
239 Instruction *Inst = nullptr);
240 InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
241 const APInt &Imm, Type *Ty,
243 /// Return the cost of the scaling factor used in the addressing
244 /// mode represented by AM for this target, for a load/store
245 /// of the specified type.
246 /// If the AM is supported, the return value must be >= 0.
247 /// If the AM is not supported, it returns a negative value.
248 InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
249 int64_t BaseOffset, bool HasBaseReg,
250 int64_t Scale, unsigned AddrSpace) const;
252 bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
253 const TargetTransformInfo::LSRCost &C2);
254 bool canMacroFuseCmp();
255 bool isLegalMaskedLoad(Type *DataType, Align Alignment);
256 bool isLegalMaskedStore(Type *DataType, Align Alignment);
257 bool isLegalNTLoad(Type *DataType, Align Alignment);
258 bool isLegalNTStore(Type *DataType, Align Alignment);
259 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
260 bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment);
262 return forceScalarizeMaskedGather(VTy, Alignment);
263 }
264 bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment);
265 bool isLegalMaskedGather(Type *DataType, Align Alignment);
266 bool isLegalMaskedScatter(Type *DataType, Align Alignment);
267 bool isLegalMaskedExpandLoad(Type *DataType);
268 bool isLegalMaskedCompressStore(Type *DataType);
269 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
270 const SmallBitVector &OpcodeMask) const;
271 bool hasDivRemOp(Type *DataType, bool IsSigned);
274 bool areInlineCompatible(const Function *Caller,
275 const Function *Callee) const;
276 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
277 const ArrayRef<Type *> &Type) const;
280 return ST->getMaxInlineSizeThreshold();
281 }
284 bool IsZeroCmp) const;
285 bool prefersVectorizedAddressing() const;
290 bool supportsGather() const;
291 InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
292 bool VariableMask, Align Alignment,
293 unsigned AddressSpace);
294 InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
295 const Value *Ptr, Align Alignment,
296 unsigned AddressSpace);
298 int getGatherOverhead() const;
299 int getScatterOverhead() const;
301 /// @}
304} // end namespace llvm
static const Function * getParent(const Value *V)
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Machine InstCombiner
const char LLVMTargetMachineRef TM
This pass exposes codegen information to IR-level passes.
static constexpr uint32_t OpcodeMask
Definition: aarch32.h:219
static constexpr uint32_t Opcode
Definition: aarch32.h:200
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:79
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:748
Container class for subtarget features.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
const DataLayout & getDataLayout() const
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
The kind of cost model.
Flags indicating the kind of support for population count.
The various kinds of shuffle patterns for vector queries.
Represents a hint about the context in which a cast is used.
The possible cache levels.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
InstructionCost getInterleavedMemoryOpCostAVX512(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool isLegalMaskedGather(Type *DataType, Align Alignment)
std::optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool isLegalNTStore(Type *DataType, Align Alignment)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool isLegalNTLoad(Type *DataType, Align Alignment)
X86TTIImpl(const X86TargetMachine *TM, const Function &F)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment)
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
bool supportsEfficientVectorElementLoadStore() const
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
bool prefersVectorizedAddressing() const
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
std::optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const override
bool isLegalMaskedStore(Type *DataType, Align Alignment)
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Calculate the cost of Gather / Scatter operation.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
unsigned getMaxInterleaveFactor(ElementCount VF)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
unsigned getNumberOfRegisters(unsigned ClassID) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
bool isLegalMaskedExpandLoad(Type *DataType)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
unsigned getAtomicMemIntrinsicMaxElementSize() const
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
InstructionCost getIntImmCost(int64_t)
Calculate the cost of materializing a 64-bit value.
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr)
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
InstructionCost getMinMaxCost(Intrinsic::ID IID, Type *Ty, TTI::TargetCostKind CostKind, FastMathFlags FMF)
bool isLegalMaskedCompressStore(Type *DataType)
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Type) const
bool hasDivRemOp(Type *DataType, bool IsSigned)
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Definition: NVPTXBaseInfo.h:21
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Returns options for expansion of memcmp. IsZeroCmp is.