LLVM 17.0.0git
Go to the documentation of this file.
1//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8/// \file
9/// This file a TargetTransformInfo::Concept conforming object specific to the
10/// X86 target machine. It uses the target's detailed information to
11/// provide more precise answers to certain TTI queries, while letting the
12/// target independent and default TTI implementations handle the rest.
19#include "X86TargetMachine.h"
22#include <optional>
24namespace llvm {
26class InstCombiner;
28class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
31 friend BaseT;
33 const X86Subtarget *ST;
34 const X86TargetLowering *TLI;
36 const X86Subtarget *getST() const { return ST; }
37 const X86TargetLowering *getTLI() const { return TLI; }
39 const FeatureBitset InlineFeatureIgnoreList = {
40 // This indicates the CPU is 64 bit capable not that we are in 64-bit
41 // mode.
42 X86::FeatureX86_64,
44 // These features don't have any intrinsics or ABI effect.
45 X86::FeatureNOPL,
46 X86::FeatureCX16,
47 X86::FeatureLAHFSAHF64,
49 // Some older targets can be setup to fold unaligned loads.
50 X86::FeatureSSEUnalignedMem,
52 // Codegen control options.
53 X86::TuningFast11ByteNOP,
54 X86::TuningFast15ByteNOP,
55 X86::TuningFastBEXTR,
56 X86::TuningFastHorizontalOps,
57 X86::TuningFastLZCNT,
58 X86::TuningFastScalarFSQRT,
59 X86::TuningFastSHLDRotate,
60 X86::TuningFastScalarShiftMasks,
61 X86::TuningFastVectorShiftMasks,
62 X86::TuningFastVariableCrossLaneShuffle,
63 X86::TuningFastVariablePerLaneShuffle,
64 X86::TuningFastVectorFSQRT,
65 X86::TuningLEAForSP,
66 X86::TuningLEAUsesAG,
67 X86::TuningLZCNTFalseDeps,
68 X86::TuningBranchFusion,
69 X86::TuningMacroFusion,
70 X86::TuningPadShortFunctions,
71 X86::TuningPOPCNTFalseDeps,
72 X86::TuningMULCFalseDeps,
73 X86::TuningPERMFalseDeps,
74 X86::TuningRANGEFalseDeps,
75 X86::TuningGETMANTFalseDeps,
76 X86::TuningMULLQFalseDeps,
77 X86::TuningSlow3OpsLEA,
78 X86::TuningSlowDivide32,
79 X86::TuningSlowDivide64,
80 X86::TuningSlowIncDec,
81 X86::TuningSlowLEA,
82 X86::TuningSlowPMADDWD,
83 X86::TuningSlowPMULLD,
84 X86::TuningSlowSHLD,
85 X86::TuningSlowTwoMemOps,
86 X86::TuningSlowUAMem16,
87 X86::TuningPreferMaskRegisters,
88 X86::TuningInsertVZEROUPPER,
89 X86::TuningUseSLMArithCosts,
90 X86::TuningUseGLMDivSqrtCosts,
91 X86::TuningNoDomainDelay,
92 X86::TuningNoDomainDelayMov,
93 X86::TuningNoDomainDelayShuffle,
94 X86::TuningNoDomainDelayBlend,
95 X86::TuningPreferShiftShuffle,
97 // Perf-tuning flags.
98 X86::TuningFastGather,
99 X86::TuningSlowUAMem32,
100 X86::TuningAllowLight256Bit,
102 // Based on whether user set the -mprefer-vector-width command line.
103 X86::TuningPrefer128Bit,
104 X86::TuningPrefer256Bit,
106 // CPU name enums. These just follow CPU string.
107 X86::ProcIntelAtom
108 };
111 explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
112 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
113 TLI(ST->getTargetLowering()) {}
115 /// \name Scalar TTI Implementations
116 /// @{
119 /// @}
121 /// \name Cache TTI Implementation
122 /// @{
123 std::optional<unsigned> getCacheSize(
124 TargetTransformInfo::CacheLevel Level) const override;
125 std::optional<unsigned> getCacheAssociativity(
126 TargetTransformInfo::CacheLevel Level) const override;
127 /// @}
129 /// \name Vector TTI Implementations
130 /// @{
132 unsigned getNumberOfRegisters(unsigned ClassID) const;
134 unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
137 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
139 TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
140 ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
141 const Instruction *CxtI = nullptr);
142 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
143 ArrayRef<int> Mask,
145 VectorType *SubTp,
146 ArrayRef<const Value *> Args = std::nullopt);
147 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
150 const Instruction *I = nullptr);
151 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
152 CmpInst::Predicate VecPred,
154 const Instruction *I = nullptr);
156 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
158 unsigned Index, Value *Op0, Value *Op1);
159 InstructionCost getScalarizationOverhead(VectorType *Ty,
160 const APInt &DemandedElts,
161 bool Insert, bool Extract,
163 InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
164 int VF,
165 const APInt &DemandedDstElts,
167 InstructionCost
168 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
170 TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
171 const Instruction *I = nullptr);
172 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
173 Align Alignment, unsigned AddressSpace,
175 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
176 const Value *Ptr, bool VariableMask,
177 Align Alignment,
179 const Instruction *I);
180 InstructionCost getPointersChainCost(ArrayRef<const Value *> Ptrs,
181 const Value *Base,
182 const TTI::PointersChainInfo &Info,
183 Type *AccessTy,
185 InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE,
186 const SCEV *Ptr);
188 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
189 IntrinsicInst &II) const;
190 std::optional<Value *>
191 simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
192 APInt DemandedMask, KnownBits &Known,
193 bool &KnownBitsComputed) const;
194 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
195 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
196 APInt &UndefElts2, APInt &UndefElts3,
197 std::function<void(Instruction *, unsigned, APInt, APInt &)>
198 SimplifyAndSetOp) const;
202 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
205 InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
206 std::optional<FastMathFlags> FMF,
209 InstructionCost getMinMaxCost(Type *Ty, Type *CondTy,
210 TTI::TargetCostKind CostKind, bool IsUnsigned,
211 FastMathFlags FMF);
213 InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
214 bool IsUnsigned, FastMathFlags FMF,
217 InstructionCost getInterleavedMemoryOpCost(
218 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
219 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
220 bool UseMaskForCond = false, bool UseMaskForGaps = false);
221 InstructionCost getInterleavedMemoryOpCostAVX512(
222 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
223 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
224 TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
225 bool UseMaskForGaps = false);
227 InstructionCost getIntImmCost(int64_t);
229 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
232 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
233 const Instruction *I = nullptr);
235 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
236 const APInt &Imm, Type *Ty,
238 Instruction *Inst = nullptr);
239 InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
240 const APInt &Imm, Type *Ty,
242 /// Return the cost of the scaling factor used in the addressing
243 /// mode represented by AM for this target, for a load/store
244 /// of the specified type.
245 /// If the AM is supported, the return value must be >= 0.
246 /// If the AM is not supported, it returns a negative value.
247 InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
248 int64_t BaseOffset, bool HasBaseReg,
249 int64_t Scale, unsigned AddrSpace) const;
251 bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
252 const TargetTransformInfo::LSRCost &C2);
253 bool canMacroFuseCmp();
254 bool isLegalMaskedLoad(Type *DataType, Align Alignment);
255 bool isLegalMaskedStore(Type *DataType, Align Alignment);
256 bool isLegalNTLoad(Type *DataType, Align Alignment);
257 bool isLegalNTStore(Type *DataType, Align Alignment);
258 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
259 bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment);
261 return forceScalarizeMaskedGather(VTy, Alignment);
262 }
263 bool isLegalMaskedGather(Type *DataType, Align Alignment);
264 bool isLegalMaskedScatter(Type *DataType, Align Alignment);
265 bool isLegalMaskedExpandLoad(Type *DataType);
266 bool isLegalMaskedCompressStore(Type *DataType);
267 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
268 const SmallBitVector &OpcodeMask) const;
269 bool hasDivRemOp(Type *DataType, bool IsSigned);
272 bool areInlineCompatible(const Function *Caller,
273 const Function *Callee) const;
274 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
275 const ArrayRef<Type *> &Type) const;
277 bool IsZeroCmp) const;
278 bool prefersVectorizedAddressing() const;
283 bool supportsGather() const;
284 InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
285 bool VariableMask, Align Alignment,
286 unsigned AddressSpace);
287 InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
288 const Value *Ptr, Align Alignment,
289 unsigned AddressSpace);
291 int getGatherOverhead() const;
292 int getScatterOverhead() const;
294 /// @}
297} // end namespace llvm
amdgpu Simplify well known AMD library false FunctionCallee Callee
static const Function * getParent(const Value *V)
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Machine InstCombiner
const char LLVMTargetMachineRef TM
This pass exposes codegen information to IR-level passes.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:79
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:711
Container class for subtarget features.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
const DataLayout & getDataLayout() const
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
The kind of cost model.
Flags indicating the kind of support for population count.
The various kinds of shuffle patterns for vector queries.
Represents a hint about the context in which a cast is used.
The possible cache levels.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:400
InstructionCost getInterleavedMemoryOpCostAVX512(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool isLegalMaskedGather(Type *DataType, Align Alignment)
std::optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool isLegalNTStore(Type *DataType, Align Alignment)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, FastMathFlags FMF, TTI::TargetCostKind CostKind)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool isLegalNTLoad(Type *DataType, Align Alignment)
X86TTIImpl(const X86TargetMachine *TM, const Function &F)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
bool supportsEfficientVectorElementLoadStore() const
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
bool prefersVectorizedAddressing() const
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
std::optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const override
bool isLegalMaskedStore(Type *DataType, Align Alignment)
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Calculate the cost of Gather / Scatter operation.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
unsigned getMaxInterleaveFactor(ElementCount VF)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
unsigned getNumberOfRegisters(unsigned ClassID) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
bool isLegalMaskedExpandLoad(Type *DataType)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
unsigned getAtomicMemIntrinsicMaxElementSize() const
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
InstructionCost getIntImmCost(int64_t)
Calculate the cost of materializing a 64-bit value.
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, TTI::TargetCostKind CostKind, bool IsUnsigned, FastMathFlags FMF)
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr)
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
bool isLegalMaskedCompressStore(Type *DataType)
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Type) const
bool hasDivRemOp(Type *DataType, bool IsSigned)
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Definition: NVPTXBaseInfo.h:21
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Returns options for expansion of memcmp. IsZeroCmp is.