LLVM  15.0.0git
X86TargetTransformInfo.h
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1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// X86 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
18 
19 #include "X86TargetMachine.h"
22 
23 namespace llvm {
24 
25 class InstCombiner;
26 
27 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
29  typedef TargetTransformInfo TTI;
30  friend BaseT;
31 
32  const X86Subtarget *ST;
33  const X86TargetLowering *TLI;
34 
35  const X86Subtarget *getST() const { return ST; }
36  const X86TargetLowering *getTLI() const { return TLI; }
37 
38  const FeatureBitset InlineFeatureIgnoreList = {
39  // This indicates the CPU is 64 bit capable not that we are in 64-bit
40  // mode.
41  X86::FeatureX86_64,
42 
43  // These features don't have any intrinsics or ABI effect.
44  X86::FeatureNOPL,
45  X86::FeatureCX16,
46  X86::FeatureLAHFSAHF64,
47 
48  // Some older targets can be setup to fold unaligned loads.
49  X86::FeatureSSEUnalignedMem,
50 
51  // Codegen control options.
52  X86::TuningFast11ByteNOP,
53  X86::TuningFast15ByteNOP,
54  X86::TuningFastBEXTR,
55  X86::TuningFastHorizontalOps,
56  X86::TuningFastLZCNT,
57  X86::TuningFastScalarFSQRT,
58  X86::TuningFastSHLDRotate,
59  X86::TuningFastScalarShiftMasks,
60  X86::TuningFastVectorShiftMasks,
61  X86::TuningFastVariableCrossLaneShuffle,
62  X86::TuningFastVariablePerLaneShuffle,
63  X86::TuningFastVectorFSQRT,
64  X86::TuningLEAForSP,
65  X86::TuningLEAUsesAG,
66  X86::TuningLZCNTFalseDeps,
67  X86::TuningBranchFusion,
68  X86::TuningMacroFusion,
69  X86::TuningPadShortFunctions,
70  X86::TuningPOPCNTFalseDeps,
71  X86::TuningMULCFalseDeps,
72  X86::TuningPERMFalseDeps,
73  X86::TuningRANGEFalseDeps,
74  X86::TuningGETMANTFalseDeps,
75  X86::TuningMULLQFalseDeps,
76  X86::TuningSlow3OpsLEA,
77  X86::TuningSlowDivide32,
78  X86::TuningSlowDivide64,
79  X86::TuningSlowIncDec,
80  X86::TuningSlowLEA,
81  X86::TuningSlowPMADDWD,
82  X86::TuningSlowPMULLD,
83  X86::TuningSlowSHLD,
84  X86::TuningSlowTwoMemOps,
85  X86::TuningSlowUAMem16,
86  X86::TuningPreferMaskRegisters,
87  X86::TuningInsertVZEROUPPER,
88  X86::TuningUseSLMArithCosts,
89  X86::TuningUseGLMDivSqrtCosts,
90 
91  // Perf-tuning flags.
92  X86::TuningFastGather,
93  X86::TuningSlowUAMem32,
94 
95  // Based on whether user set the -mprefer-vector-width command line.
96  X86::TuningPrefer128Bit,
97  X86::TuningPrefer256Bit,
98 
99  // CPU name enums. These just follow CPU string.
100  X86::ProcIntelAtom
101  };
102 
103 public:
104  explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
105  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
106  TLI(ST->getTargetLowering()) {}
107 
108  /// \name Scalar TTI Implementations
109  /// @{
110  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
111 
112  /// @}
113 
114  /// \name Cache TTI Implementation
115  /// @{
117  TargetTransformInfo::CacheLevel Level) const override;
119  TargetTransformInfo::CacheLevel Level) const override;
120  /// @}
121 
122  /// \name Vector TTI Implementations
123  /// @{
124 
125  unsigned getNumberOfRegisters(unsigned ClassID) const;
127  unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
128  unsigned getMaxInterleaveFactor(unsigned VF);
130  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
136  const Instruction *CxtI = nullptr);
138  ArrayRef<int> Mask, int Index,
139  VectorType *SubTp,
141  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
144  const Instruction *I = nullptr);
145  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
146  CmpInst::Predicate VecPred,
148  const Instruction *I = nullptr);
149  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
150  unsigned Index);
152  const APInt &DemandedElts,
153  bool Insert, bool Extract);
154  InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
155  int VF,
156  const APInt &DemandedDstElts,
158  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
159  MaybeAlign Alignment, unsigned AddressSpace,
161  const Instruction *I = nullptr);
162  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
163  Align Alignment, unsigned AddressSpace,
165  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
166  const Value *Ptr, bool VariableMask,
167  Align Alignment,
169  const Instruction *I);
171  const SCEV *Ptr);
172 
174  IntrinsicInst &II) const;
177  APInt DemandedMask, KnownBits &Known,
178  bool &KnownBitsComputed) const;
180  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
181  APInt &UndefElts2, APInt &UndefElts3,
182  std::function<void(Instruction *, unsigned, APInt, APInt &)>
183  SimplifyAndSetOp) const;
184 
185  unsigned getAtomicMemIntrinsicMaxElementSize() const;
186 
192 
196 
197  InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
198 
200  bool IsUnsigned,
202 
204  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
205  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
206  bool UseMaskForCond = false, bool UseMaskForGaps = false);
208  unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
209  ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
210  TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
211  bool UseMaskForGaps = false);
212 
214 
217 
219  const Instruction *I = nullptr);
220 
221  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
222  const APInt &Imm, Type *Ty,
224  Instruction *Inst = nullptr);
226  const APInt &Imm, Type *Ty,
229  const TargetTransformInfo::LSRCost &C2);
230  bool canMacroFuseCmp();
231  bool isLegalMaskedLoad(Type *DataType, Align Alignment);
232  bool isLegalMaskedStore(Type *DataType, Align Alignment);
233  bool isLegalNTLoad(Type *DataType, Align Alignment);
234  bool isLegalNTStore(Type *DataType, Align Alignment);
235  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
236  bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment);
238  return forceScalarizeMaskedGather(VTy, Alignment);
239  }
240  bool isLegalMaskedGather(Type *DataType, Align Alignment);
241  bool isLegalMaskedScatter(Type *DataType, Align Alignment);
242  bool isLegalMaskedExpandLoad(Type *DataType);
243  bool isLegalMaskedCompressStore(Type *DataType);
244  bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
245  const SmallBitVector &OpcodeMask) const;
246  bool hasDivRemOp(Type *DataType, bool IsSigned);
248  bool areInlineCompatible(const Function *Caller,
249  const Function *Callee) const;
250  bool areTypesABICompatible(const Function *Caller, const Function *Callee,
251  const ArrayRef<Type *> &Type) const;
253  bool IsZeroCmp) const;
254  bool prefersVectorizedAddressing() const;
257 
258 private:
259  bool supportsGather() const;
260  InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
261  bool VariableMask, Align Alignment,
262  unsigned AddressSpace);
263  InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
264  const Value *Ptr, Align Alignment,
265  unsigned AddressSpace);
266 
267  int getGatherOverhead() const;
268  int getScatterOverhead() const;
269 
270  /// @}
271 };
272 
273 } // end namespace llvm
274 
275 #endif
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::X86TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: X86TargetTransformInfo.cpp:120
llvm::X86TTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4182
llvm::X86TTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: X86InstCombineIntrinsic.cpp:1776
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::X86TTIImpl::isLSRCostLess
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
Definition: X86TargetTransformInfo.cpp:5191
llvm::X86TTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4647
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::X86TTIImpl::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType)
Definition: X86TargetTransformInfo.cpp:5304
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::ElementCount
Definition: TypeSize.h:404
llvm::Function
Definition: Function.h:60
llvm::X86TTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: X86TargetTransformInfo.cpp:61
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:595
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:135
llvm::X86TTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: X86TargetTransformInfo.cpp:5393
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::X86TTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5327
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::X86TTIImpl::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType)
Definition: X86TargetTransformInfo.cpp:5280
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::Optional< unsigned >
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::X86TTIImpl::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: X86TargetTransformInfo.cpp:5470
llvm::X86TTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: X86TargetTransformInfo.cpp:1085
llvm::X86TTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Calculate the cost of Gather / Scatter operation.
Definition: X86TargetTransformInfo.cpp:5151
llvm::X86TTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const
Definition: X86TargetTransformInfo.cpp:154
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:525
llvm::X86TTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5206
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:986
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::X86TTIImpl::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5237
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:909
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:882
llvm::X86TTIImpl::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned)
Definition: X86TargetTransformInfo.cpp:5384
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1103
llvm::X86TTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: X86InstCombineIntrinsic.cpp:928
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::X86TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: X86TargetTransformInfo.cpp:134
llvm::Instruction
Definition: Instruction.h:42
llvm::X86TTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5233
llvm::X86TargetLowering
Definition: X86ISelLowering.h:937
llvm::X86TTIImpl::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Definition: X86TargetTransformInfo.cpp:5344
llvm::X86TTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:4027
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::None
const NoneType None
Definition: None.h:24
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::X86TTIImpl::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
Definition: X86TargetTransformInfo.cpp:5272
llvm::X86TTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4269
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::X86TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: X86TargetTransformInfo.cpp:159
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::X86TTIImpl::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5315
llvm::X86TTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4966
llvm::X86TTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr)
Definition: X86TargetTransformInfo.cpp:4240
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:417
llvm::X86TTIImpl::X86TTIImpl
X86TTIImpl(const X86TargetMachine *TM, const Function &F)
Definition: X86TargetTransformInfo.h:104
llvm::X86TTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:1641
llvm::X86TTIImpl::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)
Definition: X86TargetTransformInfo.cpp:5389
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:909
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
llvm::X86TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:5002
llvm::X86TTIImpl::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: X86TargetTransformInfo.cpp:5497
llvm::X86TTIImpl::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5248
llvm::X86TTIImpl::getMinMaxCost
InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned)
Definition: X86TargetTransformInfo.cpp:4518
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::X86TTIImpl::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: X86InstCombineIntrinsic.cpp:1736
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:901
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:784
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::X86TTIImpl::getIntImmCost
InstructionCost getIntImmCost(int64_t)
Calculate the cost of materializing a 64-bit value.
Definition: X86TargetTransformInfo.cpp:4822
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:845
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:902
llvm::X86TTIImpl::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override
Definition: X86TargetTransformInfo.cpp:99
llvm::X86TTIImpl::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: X86TargetTransformInfo.cpp:2837
llvm::X86TTIImpl
Definition: X86TargetTransformInfo.h:27
llvm::KnownBits
Definition: KnownBits.h:23
X86TargetMachine.h
llvm::TypeSize
Definition: TypeSize.h:435
llvm::X86TTIImpl::canMacroFuseCmp
bool canMacroFuseCmp()
Definition: X86TargetTransformInfo.cpp:5202
llvm::X86TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: X86TargetTransformInfo.cpp:3646
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::X86TTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: X86TargetTransformInfo.cpp:4867
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::X86TTIImpl::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Type) const
Definition: X86TargetTransformInfo.cpp:5447
llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512
InstructionCost getInterleavedMemoryOpCostAVX512(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:5512
llvm::X86TTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5377
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:930
llvm::X86TTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:2608
TargetTransformInfo.h
llvm::X86TTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:5666
llvm::X86TTIImpl::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
Definition: X86TargetTransformInfo.h:237
llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost
InstructionCost getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:2840
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86TTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:3527
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::X86TTIImpl::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const override
Definition: X86TargetTransformInfo.cpp:69
llvm::X86TTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: X86TargetTransformInfo.cpp:177
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::X86TTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: X86TargetTransformInfo.cpp:5501
llvm::X86TTIImpl::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: X86TargetTransformInfo.cpp:5493
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::X86TTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: X86TargetTransformInfo.cpp:3778
llvm::X86TTIImpl::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:3919