LLVM  14.0.0git
X86TargetTransformInfo.h
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1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// X86 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
18 
19 #include "X86TargetMachine.h"
22 
23 namespace llvm {
24 
25 class InstCombiner;
26 
27 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
29  typedef TargetTransformInfo TTI;
30  friend BaseT;
31 
32  const X86Subtarget *ST;
33  const X86TargetLowering *TLI;
34 
35  const X86Subtarget *getST() const { return ST; }
36  const X86TargetLowering *getTLI() const { return TLI; }
37 
38  const FeatureBitset InlineFeatureIgnoreList = {
39  // This indicates the CPU is 64 bit capable not that we are in 64-bit
40  // mode.
41  X86::Feature64Bit,
42 
43  // These features don't have any intrinsics or ABI effect.
44  X86::FeatureNOPL,
45  X86::FeatureCMPXCHG16B,
46  X86::FeatureLAHFSAHF,
47 
48  // Some older targets can be setup to fold unaligned loads.
49  X86::FeatureSSEUnalignedMem,
50 
51  // Codegen control options.
52  X86::TuningFast11ByteNOP,
53  X86::TuningFast15ByteNOP,
54  X86::TuningFastBEXTR,
55  X86::TuningFastHorizontalOps,
56  X86::TuningFastLZCNT,
57  X86::TuningFastScalarFSQRT,
58  X86::TuningFastSHLDRotate,
59  X86::TuningFastScalarShiftMasks,
60  X86::TuningFastVectorShiftMasks,
61  X86::TuningFastVariableCrossLaneShuffle,
62  X86::TuningFastVariablePerLaneShuffle,
63  X86::TuningFastVectorFSQRT,
64  X86::TuningLEAForSP,
65  X86::TuningLEAUsesAG,
66  X86::TuningLZCNTFalseDeps,
67  X86::TuningBranchFusion,
68  X86::TuningMacroFusion,
69  X86::TuningPadShortFunctions,
70  X86::TuningPOPCNTFalseDeps,
71  X86::TuningSlow3OpsLEA,
72  X86::TuningSlowDivide32,
73  X86::TuningSlowDivide64,
74  X86::TuningSlowIncDec,
75  X86::TuningSlowLEA,
76  X86::TuningSlowPMADDWD,
77  X86::TuningSlowPMULLD,
78  X86::TuningSlowSHLD,
79  X86::TuningSlowTwoMemOps,
80  X86::TuningSlowUAMem16,
81  X86::TuningPreferMaskRegisters,
82  X86::TuningInsertVZEROUPPER,
83  X86::TuningUseSLMArithCosts,
84  X86::TuningUseGLMDivSqrtCosts,
85 
86  // Perf-tuning flags.
87  X86::TuningFastGather,
88  X86::TuningSlowUAMem32,
89 
90  // Based on whether user set the -mprefer-vector-width command line.
91  X86::TuningPrefer128Bit,
92  X86::TuningPrefer256Bit,
93 
94  // CPU name enums. These just follow CPU string.
95  X86::ProcIntelAtom
96  };
97 
98 public:
99  explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
100  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
101  TLI(ST->getTargetLowering()) {}
102 
103  /// \name Scalar TTI Implementations
104  /// @{
105  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
106 
107  /// @}
108 
109  /// \name Cache TTI Implementation
110  /// @{
112  TargetTransformInfo::CacheLevel Level) const override;
114  TargetTransformInfo::CacheLevel Level) const override;
115  /// @}
116 
117  /// \name Vector TTI Implementations
118  /// @{
119 
120  unsigned getNumberOfRegisters(unsigned ClassID) const;
122  unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
123  unsigned getMaxInterleaveFactor(unsigned VF);
125  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
131  const Instruction *CxtI = nullptr);
133  ArrayRef<int> Mask, int Index,
134  VectorType *SubTp);
135  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
138  const Instruction *I = nullptr);
139  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
140  CmpInst::Predicate VecPred,
142  const Instruction *I = nullptr);
143  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
144  unsigned Index);
146  const APInt &DemandedElts,
147  bool Insert, bool Extract);
148  InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
149  int VF,
150  const APInt &DemandedDstElts,
152  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
153  MaybeAlign Alignment, unsigned AddressSpace,
155  const Instruction *I = nullptr);
156  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
157  Align Alignment, unsigned AddressSpace,
159  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
160  const Value *Ptr, bool VariableMask,
161  Align Alignment,
163  const Instruction *I);
165  const SCEV *Ptr);
166 
168  IntrinsicInst &II) const;
171  APInt DemandedMask, KnownBits &Known,
172  bool &KnownBitsComputed) const;
174  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
175  APInt &UndefElts2, APInt &UndefElts3,
176  std::function<void(Instruction *, unsigned, APInt, APInt &)>
177  SimplifyAndSetOp) const;
178 
179  unsigned getAtomicMemIntrinsicMaxElementSize() const;
180 
186 
190 
191  InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
192 
194  bool IsUnsigned,
196 
198  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
199  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
200  bool UseMaskForCond = false, bool UseMaskForGaps = false);
202  unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
203  ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
204  TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
205  bool UseMaskForGaps = false);
206 
208 
209  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
211 
213  const Instruction *I = nullptr);
214 
215  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
216  const APInt &Imm, Type *Ty,
218  Instruction *Inst = nullptr);
220  const APInt &Imm, Type *Ty,
224  bool canMacroFuseCmp();
225  bool isLegalMaskedLoad(Type *DataType, Align Alignment);
226  bool isLegalMaskedStore(Type *DataType, Align Alignment);
227  bool isLegalNTLoad(Type *DataType, Align Alignment);
228  bool isLegalNTStore(Type *DataType, Align Alignment);
229  bool isLegalMaskedGather(Type *DataType, Align Alignment);
230  bool isLegalMaskedScatter(Type *DataType, Align Alignment);
231  bool isLegalMaskedExpandLoad(Type *DataType);
232  bool isLegalMaskedCompressStore(Type *DataType);
233  bool hasDivRemOp(Type *DataType, bool IsSigned);
235  bool areInlineCompatible(const Function *Caller,
236  const Function *Callee) const;
237  bool areFunctionArgsABICompatible(const Function *Caller,
238  const Function *Callee,
241  bool IsZeroCmp) const;
242  bool prefersVectorizedAddressing() const;
245 
246 private:
247  bool supportsGather() const;
248  InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
249  bool VariableMask, Align Alignment,
250  unsigned AddressSpace);
251  InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
252  const Value *Ptr, Align Alignment,
253  unsigned AddressSpace);
254 
255  int getGatherOverhead() const;
256  int getScatterOverhead() const;
257 
258  /// @}
259 };
260 
261 } // end namespace llvm
262 
263 #endif
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::X86TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: X86TargetTransformInfo.cpp:119
llvm::X86TTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4000
llvm::X86TTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: X86InstCombineIntrinsic.cpp:1780
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:212
llvm::X86TTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4465
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::X86TTIImpl::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType)
Definition: X86TargetTransformInfo.cpp:5106
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::Function
Definition: Function.h:62
llvm::X86TTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: X86TargetTransformInfo.cpp:60
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:596
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:136
llvm::X86TTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: X86TargetTransformInfo.cpp:5176
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:169
llvm::X86TTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5117
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::X86TTIImpl::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType)
Definition: X86TargetTransformInfo.cpp:5082
llvm::X86TTIImpl::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: X86TargetTransformInfo.cpp:5191
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::Optional< unsigned >
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::X86TTIImpl::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: X86TargetTransformInfo.cpp:5219
llvm::X86TTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Calculate the cost of Gather / Scatter operation.
Definition: X86TargetTransformInfo.cpp:4969
llvm::X86TTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const
Definition: X86TargetTransformInfo.cpp:153
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:525
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::X86TTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5016
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:955
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:49
llvm::X86TTIImpl::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5047
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:890
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:863
llvm::X86TTIImpl::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned)
Definition: X86TargetTransformInfo.cpp:5167
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1069
llvm::X86TTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: X86InstCombineIntrinsic.cpp:930
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::X86TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: X86TargetTransformInfo.cpp:133
llvm::Instruction
Definition: Instruction.h:45
llvm::X86TTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5043
llvm::X86TargetLowering
Definition: X86ISelLowering.h:937
llvm::X86TTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:3845
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:119
llvm::X86TTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4087
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::X86TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: X86TargetTransformInfo.cpp:158
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:77
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::X86TTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4784
llvm::X86TTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr)
Definition: X86TargetTransformInfo.cpp:4058
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:418
llvm::X86TTIImpl::X86TTIImpl
X86TTIImpl(const X86TargetMachine *TM, const Function &F)
Definition: X86TargetTransformInfo.h:99
llvm::X86TTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:1562
llvm::X86TTIImpl::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)
Definition: X86TargetTransformInfo.cpp:5172
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:890
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
llvm::X86TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:4820
llvm::X86TTIImpl::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
Definition: X86TargetTransformInfo.cpp:5246
llvm::X86TTIImpl::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5058
llvm::X86TTIImpl::getMinMaxCost
InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned)
Definition: X86TargetTransformInfo.cpp:4336
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::X86TTIImpl::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: X86InstCombineIntrinsic.cpp:1740
llvm::X86TTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
Definition: X86TargetTransformInfo.cpp:1080
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:882
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:765
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::X86TTIImpl::getIntImmCost
InstructionCost getIntImmCost(int64_t)
Calculate the cost of materializing a 64-bit value.
Definition: X86TargetTransformInfo.cpp:4640
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:870
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:883
llvm::X86TTIImpl::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override
Definition: X86TargetTransformInfo.cpp:98
llvm::X86TTIImpl::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: X86TargetTransformInfo.cpp:2733
llvm::X86TTIImpl
Definition: X86TargetTransformInfo.h:27
llvm::KnownBits
Definition: KnownBits.h:23
X86TargetMachine.h
llvm::TypeSize
Definition: TypeSize.h:416
llvm::X86TTIImpl::canMacroFuseCmp
bool canMacroFuseCmp()
Definition: X86TargetTransformInfo.cpp:5012
llvm::X86TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: X86TargetTransformInfo.cpp:3524
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::X86TTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: X86TargetTransformInfo.cpp:4685
llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512
InstructionCost getInterleavedMemoryOpCostAVX512(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:5261
llvm::X86TTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:5160
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:911
llvm::X86TTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:2525
TargetTransformInfo.h
llvm::X86TTIImpl::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2)
Definition: X86TargetTransformInfo.cpp:5001
llvm::X86TTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:5415
llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost
InstructionCost getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:2736
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86TTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:3423
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
BasicTTIImpl.h
llvm::X86TTIImpl::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const override
Definition: X86TargetTransformInfo.cpp:68
llvm::X86TTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: X86TargetTransformInfo.cpp:176
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::X86TTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: X86TargetTransformInfo.cpp:5250
llvm::X86TTIImpl::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: X86TargetTransformInfo.cpp:5242
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::X86TTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: X86TargetTransformInfo.cpp:3649
llvm::X86TTIImpl::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:3736