LLVM  13.0.0git
X86TargetTransformInfo.h
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1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// X86 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
18 
19 #include "X86TargetMachine.h"
22 
23 namespace llvm {
24 
25 class InstCombiner;
26 
27 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
29  typedef TargetTransformInfo TTI;
30  friend BaseT;
31 
32  const X86Subtarget *ST;
33  const X86TargetLowering *TLI;
34 
35  const X86Subtarget *getST() const { return ST; }
36  const X86TargetLowering *getTLI() const { return TLI; }
37 
38  const FeatureBitset InlineFeatureIgnoreList = {
39  // This indicates the CPU is 64 bit capable not that we are in 64-bit
40  // mode.
41  X86::Feature64Bit,
42 
43  // These features don't have any intrinsics or ABI effect.
44  X86::FeatureNOPL,
45  X86::FeatureCMPXCHG16B,
46  X86::FeatureLAHFSAHF,
47 
48  // Codegen control options.
49  X86::FeatureFast11ByteNOP,
50  X86::FeatureFast15ByteNOP,
51  X86::FeatureFastBEXTR,
52  X86::FeatureFastHorizontalOps,
53  X86::FeatureFastLZCNT,
54  X86::FeatureFastScalarFSQRT,
55  X86::FeatureFastSHLDRotate,
56  X86::FeatureFastScalarShiftMasks,
57  X86::FeatureFastVectorShiftMasks,
58  X86::FeatureFastVariableCrossLaneShuffle,
59  X86::FeatureFastVariablePerLaneShuffle,
60  X86::FeatureFastVectorFSQRT,
61  X86::FeatureLEAForSP,
62  X86::FeatureLEAUsesAG,
63  X86::FeatureLZCNTFalseDeps,
64  X86::FeatureBranchFusion,
65  X86::FeatureMacroFusion,
66  X86::FeaturePadShortFunctions,
67  X86::FeaturePOPCNTFalseDeps,
68  X86::FeatureSSEUnalignedMem,
69  X86::FeatureSlow3OpsLEA,
70  X86::FeatureSlowDivide32,
71  X86::FeatureSlowDivide64,
72  X86::FeatureSlowIncDec,
73  X86::FeatureSlowLEA,
74  X86::FeatureSlowPMADDWD,
75  X86::FeatureSlowPMULLD,
76  X86::FeatureSlowSHLD,
77  X86::FeatureSlowTwoMemOps,
78  X86::FeatureSlowUAMem16,
79  X86::FeaturePreferMaskRegisters,
80  X86::FeatureInsertVZEROUPPER,
81  X86::FeatureUseGLMDivSqrtCosts,
82 
83  // Perf-tuning flags.
84  X86::FeatureHasFastGather,
85  X86::FeatureSlowUAMem32,
86 
87  // Based on whether user set the -mprefer-vector-width command line.
88  X86::FeaturePrefer128Bit,
89  X86::FeaturePrefer256Bit,
90 
91  // CPU name enums. These just follow CPU string.
92  X86::ProcIntelAtom,
93  X86::ProcIntelSLM,
94  };
95 
96 public:
97  explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
98  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
99  TLI(ST->getTargetLowering()) {}
100 
101  /// \name Scalar TTI Implementations
102  /// @{
103  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
104 
105  /// @}
106 
107  /// \name Cache TTI Implementation
108  /// @{
110  TargetTransformInfo::CacheLevel Level) const override;
112  TargetTransformInfo::CacheLevel Level) const override;
113  /// @}
114 
115  /// \name Vector TTI Implementations
116  /// @{
117 
118  unsigned getNumberOfRegisters(unsigned ClassID) const;
120  unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
121  unsigned getMaxInterleaveFactor(unsigned VF);
123  unsigned Opcode, Type *Ty,
130  const Instruction *CxtI = nullptr);
132  ArrayRef<int> Mask, int Index,
133  VectorType *SubTp);
134  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
137  const Instruction *I = nullptr);
138  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
139  CmpInst::Predicate VecPred,
141  const Instruction *I = nullptr);
142  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
143  unsigned Index);
145  const APInt &DemandedElts,
146  bool Insert, bool Extract);
147  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
148  MaybeAlign Alignment, unsigned AddressSpace,
150  const Instruction *I = nullptr);
152  getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
153  unsigned AddressSpace,
155  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
156  const Value *Ptr, bool VariableMask,
157  Align Alignment,
159  const Instruction *I);
161  const SCEV *Ptr);
162 
164  IntrinsicInst &II) const;
167  APInt DemandedMask, KnownBits &Known,
168  bool &KnownBitsComputed) const;
170  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
171  APInt &UndefElts2, APInt &UndefElts3,
172  std::function<void(Instruction *, unsigned, APInt, APInt &)>
173  SimplifyAndSetOp) const;
174 
175  unsigned getAtomicMemIntrinsicMaxElementSize() const;
176 
182 
184  unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
186 
187  InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
188 
190  bool IsPairwiseForm, bool IsUnsigned,
192 
194  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
195  Align Alignment, unsigned AddressSpace,
197  bool UseMaskForCond = false, bool UseMaskForGaps = false);
199  unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
200  ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
202  bool UseMaskForCond = false, bool UseMaskForGaps = false);
204  unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
205  ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
207  bool UseMaskForCond = false, bool UseMaskForGaps = false);
208 
210 
211  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
213 
215  const Instruction *I = nullptr);
216 
217  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
218  const APInt &Imm, Type *Ty,
220  Instruction *Inst = nullptr);
222  const APInt &Imm, Type *Ty,
226  bool canMacroFuseCmp();
227  bool isLegalMaskedLoad(Type *DataType, Align Alignment);
228  bool isLegalMaskedStore(Type *DataType, Align Alignment);
229  bool isLegalNTLoad(Type *DataType, Align Alignment);
230  bool isLegalNTStore(Type *DataType, Align Alignment);
231  bool isLegalMaskedGather(Type *DataType, Align Alignment);
232  bool isLegalMaskedScatter(Type *DataType, Align Alignment);
233  bool isLegalMaskedExpandLoad(Type *DataType);
234  bool isLegalMaskedCompressStore(Type *DataType);
235  bool hasDivRemOp(Type *DataType, bool IsSigned);
237  bool areInlineCompatible(const Function *Caller,
238  const Function *Callee) const;
239  bool areFunctionArgsABICompatible(const Function *Caller,
240  const Function *Callee,
243  bool IsZeroCmp) const;
245 
246 private:
247  InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
248  bool VariableMask, Align Alignment,
249  unsigned AddressSpace);
250  InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
251  const Value *Ptr, Align Alignment,
252  unsigned AddressSpace);
253 
254  int getGatherOverhead() const;
255  int getScatterOverhead() const;
256 
257  /// @}
258 };
259 
260 } // end namespace llvm
261 
262 #endif
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::X86TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: X86TargetTransformInfo.cpp:119
llvm::X86TTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: X86InstCombineIntrinsic.cpp:1781
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm
Definition: AllocatorList.h:23
llvm::X86TTIImpl::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType)
Definition: X86TargetTransformInfo.cpp:4630
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::Function
Definition: Function.h:61
llvm::X86TTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: X86TargetTransformInfo.cpp:60
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512
InstructionCost getInterleavedMemoryOpCostAVX512(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:4881
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:136
llvm::X86TTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: X86TargetTransformInfo.cpp:4688
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::X86TTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:4634
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::X86TTIImpl::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType)
Definition: X86TargetTransformInfo.cpp:4606
llvm::X86TTIImpl::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: X86TargetTransformInfo.cpp:4703
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::Optional< unsigned >
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::X86TTIImpl::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: X86TargetTransformInfo.cpp:4731
llvm::X86TTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:5004
llvm::X86TTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:3973
llvm::X86TTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Calculate the cost of Gather / Scatter operation.
Definition: X86TargetTransformInfo.cpp:4483
llvm::X86TTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const
Definition: X86TargetTransformInfo.cpp:153
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:527
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::X86TTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:4543
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:970
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::X86TTIImpl::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:4571
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:908
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:850
llvm::X86TTIImpl::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned)
Definition: X86TargetTransformInfo.cpp:4679
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1084
llvm::X86TTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: X86InstCombineIntrinsic.cpp:930
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::X86TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: X86TargetTransformInfo.cpp:133
llvm::Instruction
Definition: Instruction.h:45
llvm::X86TTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:4567
llvm::X86TargetLowering
Definition: X86ISelLowering.h:895
llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX2
InstructionCost getInterleavedMemoryOpCostAVX2(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: X86TargetTransformInfo.cpp:4773
llvm::X86TTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:3352
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::X86TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: X86TargetTransformInfo.cpp:158
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::X86TTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:4298
llvm::X86TTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr)
Definition: X86TargetTransformInfo.cpp:3565
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:409
llvm::X86TTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: X86TargetTransformInfo.cpp:3507
llvm::X86TTIImpl::X86TTIImpl
X86TTIImpl(const X86TargetMachine *TM, const Function &F)
Definition: X86TargetTransformInfo.h:97
llvm::X86TTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:1507
llvm::X86TTIImpl::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)
Definition: X86TargetTransformInfo.cpp:4684
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:908
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:76
llvm::X86TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:4334
llvm::X86TTIImpl::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:4582
llvm::X86TTIImpl::getMinMaxCost
InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned)
Definition: X86TargetTransformInfo.cpp:3844
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::X86TTIImpl::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Definition: X86InstCombineIntrinsic.cpp:1740
llvm::X86TTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
Definition: X86TargetTransformInfo.cpp:1051
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:900
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:752
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:214
llvm::X86TTIImpl::getIntImmCost
InstructionCost getIntImmCost(int64_t)
Calculate the cost of materializing a 64-bit value.
Definition: X86TargetTransformInfo.cpp:4154
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:767
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:901
llvm::X86TTIImpl::getCacheAssociativity
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override
Definition: X86TargetTransformInfo.cpp:98
llvm::X86TTIImpl::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: X86TargetTransformInfo.cpp:2418
llvm::X86TTIImpl
Definition: X86TargetTransformInfo.h:27
llvm::KnownBits
Definition: KnownBits.h:23
X86TargetMachine.h
llvm::TypeSize
Definition: TypeSize.h:417
llvm::X86TTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: X86TargetTransformInfo.cpp:176
llvm::X86TTIImpl::canMacroFuseCmp
bool canMacroFuseCmp()
Definition: X86TargetTransformInfo.cpp:4539
llvm::X86TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: X86TargetTransformInfo.cpp:3171
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::X86TTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: X86TargetTransformInfo.cpp:4199
llvm::X86TTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, bool IsPairwiseForm, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: X86TargetTransformInfo.cpp:3592
llvm::X86TTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: X86TargetTransformInfo.cpp:4672
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:929
llvm::X86TTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: X86TargetTransformInfo.cpp:2223
TargetTransformInfo.h
llvm::X86TTIImpl::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2)
Definition: X86TargetTransformInfo.cpp:4528
llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost
InstructionCost getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:2421
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86TTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: X86TargetTransformInfo.cpp:3070
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
BasicTTIImpl.h
llvm::X86TTIImpl::getCacheSize
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const override
Definition: X86TargetTransformInfo.cpp:68
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::X86TTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: X86TargetTransformInfo.cpp:4754
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::X86TTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: X86TargetTransformInfo.cpp:3266