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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 
19 
20 namespace llvm {
21  class X86Subtarget;
22  class X86TargetMachine;
23 
24  namespace X86ISD {
25  // X86 Specific DAG Nodes
26  enum NodeType : unsigned {
27  // Start the numbering where the builtin ops leave off.
29 
30  /// Bit scan forward.
31  BSF,
32  /// Bit scan reverse.
33  BSR,
34 
35  /// X86 funnel/double shift i16 instructions. These correspond to
36  /// X86::SHLDW and X86::SHRDW instructions which have different amt
37  /// modulo rules to generic funnel shifts.
38  /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.
41 
42  /// Bitwise logical AND of floating point values. This corresponds
43  /// to X86::ANDPS or X86::ANDPD.
45 
46  /// Bitwise logical OR of floating point values. This corresponds
47  /// to X86::ORPS or X86::ORPD.
48  FOR,
49 
50  /// Bitwise logical XOR of floating point values. This corresponds
51  /// to X86::XORPS or X86::XORPD.
53 
54  /// Bitwise logical ANDNOT of floating point values. This
55  /// corresponds to X86::ANDNPS or X86::ANDNPD.
57 
58  /// These operations represent an abstract X86 call
59  /// instruction, which includes a bunch of information. In particular the
60  /// operands of these node are:
61  ///
62  /// #0 - The incoming token chain
63  /// #1 - The callee
64  /// #2 - The number of arg bytes the caller pushes on the stack.
65  /// #3 - The number of arg bytes the callee pops off the stack.
66  /// #4 - The value to pass in AL/AX/EAX (optional)
67  /// #5 - The value to pass in DL/DX/EDX (optional)
68  ///
69  /// The result values of these nodes are:
70  ///
71  /// #0 - The outgoing token chain
72  /// #1 - The first register result value (optional)
73  /// #2 - The second register result value (optional)
74  ///
76 
77  /// Same as call except it adds the NoTrack prefix.
79 
80  // Pseudo for a OBJC call that gets emitted together with a special
81  // marker instruction.
83 
84  /// X86 compare and logical compare instructions.
85  CMP,
89 
90  /// X86 bit-test instructions.
91  BT,
92 
93  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94  /// operand, usually produced by a CMP instruction.
96 
97  /// X86 Select
99 
100  // Same as SETCC except it's materialized with a sbb and the value is all
101  // one's or all zero's.
102  SETCC_CARRY, // R = carry_bit ? ~0 : 0
103 
104  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105  /// Operands are two FP values to compare; result is a mask of
106  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
108 
109  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
110  /// and a version with SAE.
113 
114  /// X86 conditional moves. Operand 0 and operand 1 are the two values
115  /// to select from. Operand 2 is the condition code, and operand 3 is the
116  /// flag operand produced by a CMP or TEST instruction.
118 
119  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120  /// is the block to branch if condition is true, operand 2 is the
121  /// condition code, and operand 3 is the flag operand produced by a CMP
122  /// or TEST instruction.
124 
125  /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
126  /// operand 1 is the target address.
128 
129  /// Return with a flag operand. Operand 0 is the chain operand, operand
130  /// 1 is the number of bytes of stack to pop.
132 
133  /// Return from interrupt. Operand 0 is the number of bytes to pop.
135 
136  /// Repeat fill, corresponds to X86::REP_STOSx.
138 
139  /// Repeat move, corresponds to X86::REP_MOVSx.
141 
142  /// On Darwin, this node represents the result of the popl
143  /// at function entry, used for PIC code.
145 
146  /// A wrapper node for TargetConstantPool, TargetJumpTable,
147  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
148  /// MCSymbol and TargetBlockAddress.
150 
151  /// Special wrapper used under X86-64 PIC mode for RIP
152  /// relative displacements.
154 
155  /// Copies a 64-bit value from an MMX vector to the low word
156  /// of an XMM vector, with the high word zero filled.
158 
159  /// Copies a 64-bit value from the low word of an XMM vector
160  /// to an MMX vector.
162 
163  /// Copies a 32-bit value from the low word of a MMX
164  /// vector to a GPR.
166 
167  /// Copies a GPR into the low 32-bit word of a MMX vector
168  /// and zero out the high word.
170 
171  /// Extract an 8-bit value from a vector and zero extend it to
172  /// i32, corresponds to X86::PEXTRB.
174 
175  /// Extract a 16-bit value from a vector and zero extend it to
176  /// i32, corresponds to X86::PEXTRW.
178 
179  /// Insert any element of a 4 x float vector into any element
180  /// of a destination 4 x floatvector.
182 
183  /// Insert the lower 8-bits of a 32-bit value to a vector,
184  /// corresponds to X86::PINSRB.
186 
187  /// Insert the lower 16-bits of a 32-bit value to a vector,
188  /// corresponds to X86::PINSRW.
190 
191  /// Shuffle 16 8-bit values within a vector.
193 
194  /// Compute Sum of Absolute Differences.
196  /// Compute Double Block Packed Sum-Absolute-Differences
198 
199  /// Bitwise Logical AND NOT of Packed FP values.
201 
202  /// Blend where the selector is an immediate.
204 
205  /// Dynamic (non-constant condition) vector blend where only the sign bits
206  /// of the condition elements are used. This is used to enforce that the
207  /// condition mask is not valid for generic VSELECT optimizations. This
208  /// is also used to implement the intrinsics.
209  /// Operands are in VSELECT order: MASK, TRUE, FALSE
211 
212  /// Combined add and sub on an FP vector.
214 
215  // FP vector ops with rounding mode.
235 
236  // FP vector get exponent.
241  // Extract Normalized Mantissas.
246  // FP Scale.
251 
252  // Unsigned Integer average.
254 
255  /// Integer horizontal add/sub.
258 
259  /// Floating point horizontal add/sub.
262 
263  // Detect Conflicts Within a Vector
265 
266  /// Floating point max and min.
269 
270  /// Commutative FMIN and FMAX.
273 
274  /// Scalar intrinsic floating point max and min.
277 
278  /// Floating point reciprocal-sqrt and reciprocal approximation.
279  /// Note that these typically require refinement
280  /// in order to obtain suitable precision.
283 
284  // AVX-512 reciprocal approximations with a little more precision.
289 
290  // Thread Local Storage.
292 
293  // Thread Local Storage. A call to get the start address
294  // of the TLS block for the current module.
296 
297  // Thread Local Storage. When calling to an OS provided
298  // thunk at the address from an earlier relocation.
300 
301  // Exception Handling helpers.
303 
304  // SjLj exception handling setjmp.
306 
307  // SjLj exception handling longjmp.
309 
310  // SjLj exception handling dispatch.
312 
313  /// Tail call return. See X86TargetLowering::LowerCall for
314  /// the list of operands.
316 
317  // Vector move to low scalar and zero higher vector elements.
319 
320  // Vector integer truncate.
322  // Vector integer truncate with unsigned/signed saturation.
325 
326  // Masked version of the above. Used when less than a 128-bit result is
327  // produced since the mask only applies to the lower elements and can't
328  // be represented by a select.
329  // SRC, PASSTHRU, MASK
333 
334  // Vector FP extend.
339 
340  // Vector FP round.
345 
346  // Masked version of above. Used for v2f64->v4f32.
347  // SRC, PASSTHRU, MASK
349 
350  // 128-bit vector logical left / right shift
353 
354  // Vector shift elements
358 
359  // Vector variable shift
363 
364  // Vector shift elements by immediate
368 
369  // Shifts of mask registers.
372 
373  // Bit rotate by immediate
376 
377  // Vector packed double/float comparison.
379 
380  // Vector integer comparisons.
383 
384  // v8i16 Horizontal minimum and position.
386 
388 
389  /// Vector comparison generating mask bits for fp and
390  /// integer signed and unsigned data types.
392  // Vector mask comparison generating mask bits for FP values.
394  // Vector mask comparison with SAE for FP values.
396 
397  // Arithmetic operations with FLAGS results.
404  OR,
407 
408  // Bit field extract.
411 
412  // Zero High Bits Starting with Specified Bit Position.
414 
415  // Parallel extract and deposit.
418 
419  // X86-specific multiply by immediate.
421 
422  // Vector sign bit extraction.
424 
425  // Vector bitwise comparisons.
427 
428  // Vector packed fp sign bitwise comparisons.
430 
431  // OR/AND test for masks.
434 
435  // ADD for masks.
437 
438  // Several flavors of instructions with vector shuffle behaviors.
439  // Saturated signed/unnsigned packing.
442  // Intra-lane alignr.
444  // AVX512 inter-lane alignr.
450  // VBMI2 Concat & Shift.
455  // Shuffle Packed Values at 128-bit granularity.
471 
472  // Variable Permute (VPERM).
473  // Res = VPERMV MaskV, V0
475 
476  // 3-op Variable Permute (VPERMT2).
477  // Res = VPERMV3 V0, MaskV, V1
479 
480  // Bitwise ternary logic.
482  // Fix Up Special Packed Float32/64 values.
487  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
492  // Reduce - Perform Reduction Transformation on scalar\packed FP.
497  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
498  // Also used by the legacy (V)ROUND intrinsics where we mask out the
499  // scaling part of the immediate.
504  // Tests Types Of a FP Values for packed types.
506  // Tests Types Of a FP Values for scalar types.
508 
509  // Broadcast (splat) scalar or element 0 of a vector. If the operand is
510  // a vector, this node may change the vector length as part of the splat.
512  // Broadcast mask to vector.
514 
515  /// SSE4A Extraction and Insertion.
518 
519  // XOP arithmetic/logical shifts.
522  // XOP signed/unsigned integer comparisons.
525  // XOP packed permute bytes.
527  // XOP two source permutation.
529 
530  // Vector multiply packed unsigned doubleword integers.
532  // Vector multiply packed signed doubleword integers.
534  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
536 
537  // Multiply and Add Packed Integers.
540 
541  // AVX512IFMA multiply and add.
542  // NOTE: These are different than the instruction and perform
543  // op0 x op1 + op2.
546 
547  // VNNI
552 
553  // FMA nodes.
554  // We use the target independent ISD::FMA for the non-inverted case.
560 
561  // FMA with rounding mode.
568 
569  // AVX512-FP16 complex addition and multiplication.
574 
579 
584 
589 
590  // Compress and expand.
593 
594  // Bits shuffle
596 
597  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
604 
605  // Vector float/double to signed/unsigned integer.
610  // Scalar float/double to signed/unsigned integer.
615 
616  // Vector float/double to signed/unsigned integer with truncation.
621  // Scalar float/double to signed/unsigned integer with truncation.
626 
627  // Vector signed/unsigned integer to float/double.
630 
631  // Masked versions of above. Used for v2f64->v4f32.
632  // SRC, PASSTHRU, MASK
639 
640  // Vector float to bfloat16.
641  // Convert TWO packed single data to one packed BF16 data
643  // Convert packed single data to packed BF16 data
645  // Masked version of above.
646  // SRC, PASSTHRU, MASK
648 
649  // Dot product of BF16 pairs to accumulated into
650  // packed single precision.
652 
653  // Save xmm argument registers to the stack, according to %al. An operator
654  // is needed so that this can be expanded with control flow.
656 
657  // A stack checking function call. On Windows it's _chkstk call.
659 
660  // For allocating variable amounts of stack space when using
661  // segmented stacks. Check if the current stacklet has enough space, and
662  // falls back to heap allocation if not.
664 
665  // For allocating stack space when using stack clash protector.
666  // Allocation is performed by block, and each block is probed.
668 
669  // Memory barriers.
672 
673  // Get a random integer and indicate whether it is valid in CF.
675 
676  // Get a NIST SP800-90B & C compliant random integer and
677  // indicate whether it is valid in CF.
679 
680  // Protection keys
681  // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
682  // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
683  // value for ECX.
686 
687  // SSE42 string comparisons.
688  // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
689  // will emit one or two instructions based on which results are used. If
690  // flags and index/mask this allows us to use a single instruction since
691  // we won't have to pick and opcode for flags. Instead we can rely on the
692  // DAG to CSE everything and decide at isel.
695 
696  // Test if in transactional execution.
698 
699  // ERI instructions.
710 
711  // Conversions between float and half-float.
715 
716  // Masked version of above.
717  // SRC, RND, PASSTHRU, MASK
719 
720  // Galois Field Arithmetic Instructions
724 
725  // LWP insert record.
727 
728  // User level wait
731 
732  // Enqueue Stores Instructions
735 
736  // For avx512-vp2intersect
738 
739  // User level interrupts - testui
741 
742  /// X86 strict FP compare instructions.
745 
746  // Vector packed double/float comparison.
748 
749  /// Vector comparison generating mask bits for fp and
750  /// integer signed and unsigned data types.
752 
753  // Vector float/double to signed/unsigned integer with truncation.
756 
757  // Vector FP extend.
759 
760  // Vector FP round.
762 
763  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
764  // Also used by the legacy (V)ROUND intrinsics where we mask out the
765  // scaling part of the immediate.
767 
768  // Vector signed/unsigned integer to float/double.
771 
772  // Strict FMA nodes.
776 
777  // Conversions between float and half-float.
780 
781  // WARNING: Only add nodes here if they are stric FP nodes. Non-memory and
782  // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE.
783 
784  // Compare and swap.
789 
790  /// LOCK-prefixed arithmetic read-modify-write instructions.
791  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
797 
798  // Load, scalar_to_vector, and zero extend.
800 
801  // extract_vector_elt, store.
803 
804  // scalar broadcast from memory.
806 
807  // subvector broadcast from memory.
809 
810  // Store FP control word into i16 memory.
812 
813  // Load FP control word from i16 memory.
815 
816  /// This instruction implements FP_TO_SINT with the
817  /// integer destination in memory and a FP reg source. This corresponds
818  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
819  /// has two inputs (token chain and address) and two outputs (int value
820  /// and token chain). Memory VT specifies the type to store to.
822 
823  /// This instruction implements SINT_TO_FP with the
824  /// integer source in memory and FP reg result. This corresponds to the
825  /// X86::FILD*m instructions. It has two inputs (token chain and address)
826  /// and two outputs (FP value and token chain). The integer source type is
827  /// specified by the memory VT.
829 
830  /// This instruction implements a fp->int store from FP stack
831  /// slots. This corresponds to the fist instruction. It takes a
832  /// chain operand, value to store, address, and glue. The memory VT
833  /// specifies the type to store as.
835 
836  /// This instruction implements an extending load to FP stack slots.
837  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
838  /// operand, and ptr to load from. The memory VT specifies the type to
839  /// load from.
841 
842  /// This instruction implements a truncating store from FP stack
843  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
844  /// chain operand, value to store, address, and glue. The memory VT
845  /// specifies the type to store as.
847 
848  /// These instructions grab the address of the next argument
849  /// from a va_list. (reads and modifies the va_list in memory)
852 
853  // Vector truncating store with unsigned/signed saturation
856  // Vector truncating masked store with unsigned/signed saturation
859 
860  // X86 specific gather and scatter
863 
864  // Key locker nodes that produce flags.
873 
874  // WARNING: Do not add anything in the end unless you want the node to
875  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
876  // opcodes will be thought as target memory ops!
877  };
878  } // end namespace X86ISD
879 
880  namespace X86 {
881  /// Current rounding mode is represented in bits 11:10 of FPSR. These
882  /// values are same as corresponding constants for rounding mode used
883  /// in glibc.
885  rmToNearest = 0, // FE_TONEAREST
886  rmDownward = 1 << 10, // FE_DOWNWARD
887  rmUpward = 2 << 10, // FE_UPWARD
888  rmTowardZero = 3 << 10, // FE_TOWARDZERO
889  rmMask = 3 << 10 // Bit mask selecting rounding mode
890  };
891  }
892 
893  /// Define some predicates that are used for node matching.
894  namespace X86 {
895  /// Returns true if Elt is a constant zero or floating point constant +0.0.
896  bool isZeroNode(SDValue Elt);
897 
898  /// Returns true of the given offset can be
899  /// fit into displacement field of the instruction.
901  bool hasSymbolicDisplacement);
902 
903  /// Determines whether the callee is required to pop its
904  /// own arguments. Callee pop is necessary to support tail calls.
906  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
907 
908  /// If Op is a constant whose elements are all the same constant or
909  /// undefined, return true and return the constant value in \p SplatVal.
910  /// If we have undef bits that don't cover an entire element, we treat these
911  /// as zero if AllowPartialUndefs is set, else we fail and return false.
912  bool isConstantSplat(SDValue Op, APInt &SplatVal,
913  bool AllowPartialUndefs = true);
914  } // end namespace X86
915 
916  //===--------------------------------------------------------------------===//
917  // X86 Implementation of the TargetLowering interface
918  class X86TargetLowering final : public TargetLowering {
919  public:
920  explicit X86TargetLowering(const X86TargetMachine &TM,
921  const X86Subtarget &STI);
922 
923  unsigned getJumpTableEncoding() const override;
924  bool useSoftFloat() const override;
925 
926  void markLibCallAttributes(MachineFunction *MF, unsigned CC,
927  ArgListTy &Args) const override;
928 
929  MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
930  return MVT::i8;
931  }
932 
933  const MCExpr *
935  const MachineBasicBlock *MBB, unsigned uid,
936  MCContext &Ctx) const override;
937 
938  /// Returns relocation base for the given PIC jumptable.
940  SelectionDAG &DAG) const override;
941  const MCExpr *
943  unsigned JTI, MCContext &Ctx) const override;
944 
945  /// Return the desired alignment for ByVal aggregate
946  /// function arguments in the caller parameter area. For X86, aggregates
947  /// that contains are placed at 16-byte boundaries while the rest are at
948  /// 4-byte boundaries.
950  const DataLayout &DL) const override;
951 
953  const AttributeList &FuncAttributes) const override;
954 
955  /// Returns true if it's safe to use load / store of the
956  /// specified type to expand memcpy / memset inline. This is mostly true
957  /// for all types except for some special cases. For example, on X86
958  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
959  /// also does type conversion. Note the specified type doesn't have to be
960  /// legal as the hook is used before type legalization.
961  bool isSafeMemOpType(MVT VT) const override;
962 
963  /// Returns true if the target allows unaligned memory accesses of the
964  /// specified type. Returns whether it is "fast" in the last argument.
965  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
967  bool *Fast) const override;
968 
969  /// Provide custom lowering hooks for some operations.
970  ///
971  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
972 
973  /// Replace the results of node with an illegal result
974  /// type with new values built out of custom code.
975  ///
977  SelectionDAG &DAG) const override;
978 
979  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
980 
981  /// Return true if the target has native support for
982  /// the specified value type and it is 'desirable' to use the type for the
983  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
984  /// instruction encodings are longer and some i16 instructions are slow.
985  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
986 
987  /// Return true if the target has native support for the
988  /// specified value type and it is 'desirable' to use the type. e.g. On x86
989  /// i16 is legal, but undesirable since i16 instruction encodings are longer
990  /// and some i16 instructions are slow.
991  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
992 
993  /// Return the newly negated expression if the cost is not expensive and
994  /// set the cost in \p Cost to indicate that if it is cheaper or neutral to
995  /// do the negation.
997  bool LegalOperations, bool ForCodeSize,
998  NegatibleCost &Cost,
999  unsigned Depth) const override;
1000 
1003  MachineBasicBlock *MBB) const override;
1004 
1005  /// This method returns the name of a target specific DAG node.
1006  const char *getTargetNodeName(unsigned Opcode) const override;
1007 
1008  /// Do not merge vector stores after legalization because that may conflict
1009  /// with x86-specific store splitting optimizations.
1010  bool mergeStoresAfterLegalization(EVT MemVT) const override {
1011  return !MemVT.isVector();
1012  }
1013 
1014  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
1015  const MachineFunction &MF) const override;
1016 
1017  bool isCheapToSpeculateCttz() const override;
1018 
1019  bool isCheapToSpeculateCtlz() const override;
1020 
1021  bool isCtlzFast() const override;
1022 
1023  bool hasBitPreservingFPLogic(EVT VT) const override {
1024  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector() ||
1025  (VT == MVT::f16 && X86ScalarSSEf16);
1026  }
1027 
1028  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
1029  // If the pair to store is a mixture of float and int values, we will
1030  // save two bitwise instructions and one float-to-int instruction and
1031  // increase one store instruction. There is potentially a more
1032  // significant benefit because it avoids the float->int domain switch
1033  // for input value. So It is more likely a win.
1034  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
1035  (LTy.isInteger() && HTy.isFloatingPoint()))
1036  return true;
1037  // If the pair only contains int values, we will save two bitwise
1038  // instructions and increase one store instruction (costing one more
1039  // store buffer). Since the benefit is more blurred so we leave
1040  // such pair out until we get testcase to prove it is a win.
1041  return false;
1042  }
1043 
1044  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1045 
1046  bool hasAndNotCompare(SDValue Y) const override;
1047 
1048  bool hasAndNot(SDValue Y) const override;
1049 
1050  bool hasBitTest(SDValue X, SDValue Y) const override;
1051 
1054  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
1055  SelectionDAG &DAG) const override;
1056 
1058  CombineLevel Level) const override;
1059 
1060  bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
1061 
1062  bool
1064  unsigned KeptBits) const override {
1065  // For vectors, we don't have a preference..
1066  if (XVT.isVector())
1067  return false;
1068 
1069  auto VTIsOk = [](EVT VT) -> bool {
1070  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
1071  VT == MVT::i64;
1072  };
1073 
1074  // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
1075  // XVT will be larger than KeptBitsVT.
1076  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
1077  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
1078  }
1079 
1080  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
1081 
1082  bool shouldSplatInsEltVarIndex(EVT VT) const override;
1083 
1084  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
1085  return VT.isScalarInteger();
1086  }
1087 
1088  /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
1089  MVT hasFastEqualityCompare(unsigned NumBits) const override;
1090 
1091  /// Return the value type to use for ISD::SETCC.
1093  EVT VT) const override;
1094 
1096  const APInt &DemandedElts,
1097  TargetLoweringOpt &TLO) const override;
1098 
1099  /// Determine which of the bits specified in Mask are known to be either
1100  /// zero or one and return them in the KnownZero/KnownOne bitsets.
1102  KnownBits &Known,
1103  const APInt &DemandedElts,
1104  const SelectionDAG &DAG,
1105  unsigned Depth = 0) const override;
1106 
1107  /// Determine the number of bits in the operation that are sign bits.
1109  const APInt &DemandedElts,
1110  const SelectionDAG &DAG,
1111  unsigned Depth) const override;
1112 
1114  const APInt &DemandedElts,
1115  APInt &KnownUndef,
1116  APInt &KnownZero,
1117  TargetLoweringOpt &TLO,
1118  unsigned Depth) const override;
1119 
1121  const APInt &DemandedElts,
1122  unsigned MaskIndex,
1123  TargetLoweringOpt &TLO,
1124  unsigned Depth) const;
1125 
1127  const APInt &DemandedBits,
1128  const APInt &DemandedElts,
1129  KnownBits &Known,
1130  TargetLoweringOpt &TLO,
1131  unsigned Depth) const override;
1132 
1134  SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1135  SelectionDAG &DAG, unsigned Depth) const override;
1136 
1137  const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
1138 
1139  SDValue unwrapAddress(SDValue N) const override;
1140 
1142 
1143  bool ExpandInlineAsm(CallInst *CI) const override;
1144 
1145  ConstraintType getConstraintType(StringRef Constraint) const override;
1146 
1147  /// Examine constraint string and operand type and determine a weight value.
1148  /// The operand object must already have been set up with the operand type.
1150  getSingleConstraintMatchWeight(AsmOperandInfo &info,
1151  const char *constraint) const override;
1152 
1153  const char *LowerXConstraint(EVT ConstraintVT) const override;
1154 
1155  /// Lower the specified operand into the Ops vector. If it is invalid, don't
1156  /// add anything to Ops. If hasMemory is true it means one of the asm
1157  /// constraint of the inline asm instruction being processed is 'm'.
1159  std::string &Constraint,
1160  std::vector<SDValue> &Ops,
1161  SelectionDAG &DAG) const override;
1162 
1163  unsigned
1164  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1165  if (ConstraintCode == "v")
1166  return InlineAsm::Constraint_v;
1167  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1168  }
1169 
1170  /// Handle Lowering flag assembly outputs.
1172  const SDLoc &DL,
1173  const AsmOperandInfo &Constraint,
1174  SelectionDAG &DAG) const override;
1175 
1176  /// Given a physical register constraint
1177  /// (e.g. {edx}), return the register number and the register class for the
1178  /// register. This should only be used for C_Register constraints. On
1179  /// error, this returns a register number of 0.
1180  std::pair<unsigned, const TargetRegisterClass *>
1182  StringRef Constraint, MVT VT) const override;
1183 
1184  /// Return true if the addressing mode represented
1185  /// by AM is legal for this target, for a load/store of the specified type.
1186  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1187  Type *Ty, unsigned AS,
1188  Instruction *I = nullptr) const override;
1189 
1190  /// Return true if the specified immediate is legal
1191  /// icmp immediate, that is the target has icmp instructions which can
1192  /// compare a register against the immediate without having to materialize
1193  /// the immediate into a register.
1194  bool isLegalICmpImmediate(int64_t Imm) const override;
1195 
1196  /// Return true if the specified immediate is legal
1197  /// add immediate, that is the target has add instructions which can
1198  /// add a register and the immediate without having to materialize
1199  /// the immediate into a register.
1200  bool isLegalAddImmediate(int64_t Imm) const override;
1201 
1202  bool isLegalStoreImmediate(int64_t Imm) const override;
1203 
1204  /// Return the cost of the scaling factor used in the addressing
1205  /// mode represented by AM for this target, for a load/store
1206  /// of the specified type.
1207  /// If the AM is supported, the return value must be >= 0.
1208  /// If the AM is not supported, it returns a negative value.
1210  const AddrMode &AM, Type *Ty,
1211  unsigned AS) const override;
1212 
1213  /// This is used to enable splatted operand transforms for vector shifts
1214  /// and vector funnel shifts.
1215  bool isVectorShiftByScalarCheap(Type *Ty) const override;
1216 
1217  /// Add x86-specific opcodes to the default list.
1218  bool isBinOp(unsigned Opcode) const override;
1219 
1220  /// Returns true if the opcode is a commutative binary operation.
1221  bool isCommutativeBinOp(unsigned Opcode) const override;
1222 
1223  /// Return true if it's free to truncate a value of
1224  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1225  /// register EAX to i16 by referencing its sub-register AX.
1226  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1227  bool isTruncateFree(EVT VT1, EVT VT2) const override;
1228 
1229  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
1230 
1231  /// Return true if any actual instruction that defines a
1232  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1233  /// register. This does not necessarily include registers defined in
1234  /// unknown ways, such as incoming arguments, or copies from unknown
1235  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1236  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1237  /// all instructions that define 32-bit values implicit zero-extend the
1238  /// result out to 64 bits.
1239  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
1240  bool isZExtFree(EVT VT1, EVT VT2) const override;
1241  bool isZExtFree(SDValue Val, EVT VT2) const override;
1242 
1244  SmallVectorImpl<Use *> &Ops) const override;
1245  bool shouldConvertPhiType(Type *From, Type *To) const override;
1246 
1247  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1248  /// extend node) is profitable.
1249  bool isVectorLoadExtDesirable(SDValue) const override;
1250 
1251  /// Return true if an FMA operation is faster than a pair of fmul and fadd
1252  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
1253  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
1255  EVT VT) const override;
1256 
1257  /// Return true if it's profitable to narrow
1258  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1259  /// from i32 to i8 but not from i32 to i16.
1260  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
1261 
1262  /// Given an intrinsic, checks if on the target the intrinsic will need to map
1263  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1264  /// true and stores the intrinsic information into the IntrinsicInfo that was
1265  /// passed to the function.
1266  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1267  MachineFunction &MF,
1268  unsigned Intrinsic) const override;
1269 
1270  /// Returns true if the target can instruction select the
1271  /// specified FP immediate natively. If false, the legalizer will
1272  /// materialize the FP immediate as a load from a constant pool.
1273  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1274  bool ForCodeSize) const override;
1275 
1276  /// Targets can use this to indicate that they only support *some*
1277  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1278  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1279  /// be legal.
1280  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1281 
1282  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1283  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1284  /// constant pool entry.
1285  bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1286 
1287  /// Returns true if lowering to a jump table is allowed.
1288  bool areJTsAllowed(const Function *Fn) const override;
1289 
1290  /// If true, then instruction selection should
1291  /// seek to shrink the FP constant of the specified type to a smaller type
1292  /// in order to save space and / or reduce runtime.
1293  bool ShouldShrinkFPConstant(EVT VT) const override {
1294  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
1295  // expensive than a straight movsd. On the other hand, it's important to
1296  // shrink long double fp constant since fldt is very slow.
1297  return !X86ScalarSSEf64 || VT == MVT::f80;
1298  }
1299 
1300  /// Return true if we believe it is correct and profitable to reduce the
1301  /// load node to a smaller type.
1303  EVT NewVT) const override;
1304 
1305  /// Return true if the specified scalar FP type is computed in an SSE
1306  /// register, not on the X87 floating point stack.
1307  bool isScalarFPTypeInSSEReg(EVT VT) const {
1308  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
1309  (VT == MVT::f32 && X86ScalarSSEf32) || // f32 is when SSE1
1310  (VT == MVT::f16 && X86ScalarSSEf16); // f16 is when AVX512FP16
1311  }
1312 
1313  /// Returns true if it is beneficial to convert a load of a constant
1314  /// to just the constant itself.
1315  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1316  Type *Ty) const override;
1317 
1318  bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override;
1319 
1320  bool convertSelectOfConstantsToMath(EVT VT) const override;
1321 
1323  SDValue C) const override;
1324 
1325  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1326  /// with this index.
1327  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1328  unsigned Index) const override;
1329 
1330  /// Scalar ops always have equal or better analysis/performance/power than
1331  /// the vector equivalent, so this always makes sense if the scalar op is
1332  /// supported.
1333  bool shouldScalarizeBinop(SDValue) const override;
1334 
1335  /// Extract of a scalar FP value from index 0 of a vector is free.
1336  bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1337  EVT EltVT = VT.getScalarType();
1338  return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
1339  }
1340 
1341  /// Overflow nodes should get combined/lowered to optimal instructions
1342  /// (they should allow eliminating explicit compares by getting flags from
1343  /// math ops).
1344  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
1345  bool MathUsed) const override;
1346 
1347  bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
1348  unsigned AddrSpace) const override {
1349  // If we can replace more than 2 scalar stores, there will be a reduction
1350  // in instructions even after we add a vector constant load.
1351  return NumElem > 2;
1352  }
1353 
1354  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
1355  const SelectionDAG &DAG,
1356  const MachineMemOperand &MMO) const override;
1357 
1358  /// Intel processors have a unified instruction and data cache
1359  const char * getClearCacheBuiltinName() const override {
1360  return nullptr; // nothing to do, move along.
1361  }
1362 
1363  Register getRegisterByName(const char* RegName, LLT VT,
1364  const MachineFunction &MF) const override;
1365 
1366  /// If a physical register, this returns the register that receives the
1367  /// exception address on entry to an EH pad.
1368  Register
1369  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1370 
1371  /// If a physical register, this returns the register that receives the
1372  /// exception typeid on entry to a landing pad.
1373  Register
1374  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1375 
1376  virtual bool needsFixedCatchObjects() const override;
1377 
1378  /// This method returns a target specific FastISel object,
1379  /// or null if the target does not support "fast" ISel.
1381  const TargetLibraryInfo *libInfo) const override;
1382 
1383  /// If the target has a standard location for the stack protector cookie,
1384  /// returns the address of that location. Otherwise, returns nullptr.
1385  Value *getIRStackGuard(IRBuilderBase &IRB) const override;
1386 
1387  bool useLoadStackGuardNode() const override;
1388  bool useStackGuardXorFP() const override;
1389  void insertSSPDeclarations(Module &M) const override;
1390  Value *getSDagStackGuard(const Module &M) const override;
1391  Function *getSSPStackGuardCheck(const Module &M) const override;
1393  const SDLoc &DL) const override;
1394 
1395 
1396  /// Return true if the target stores SafeStack pointer at a fixed offset in
1397  /// some non-standard address space, and populates the address space and
1398  /// offset as appropriate.
1399  Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
1400 
1401  std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
1402  SDValue Chain, SDValue Pointer,
1403  MachinePointerInfo PtrInfo,
1404  Align Alignment,
1405  SelectionDAG &DAG) const;
1406 
1407  /// Customize the preferred legalization strategy for certain types.
1408  LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1409 
1410  bool softPromoteHalfType() const override { return true; }
1411 
1413  EVT VT) const override;
1414 
1416  CallingConv::ID CC,
1417  EVT VT) const override;
1418 
1420  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
1421  unsigned &NumIntermediates, MVT &RegisterVT) const override;
1422 
1423  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1424 
1425  bool supportSwiftError() const override;
1426 
1427  bool hasStackProbeSymbol(MachineFunction &MF) const override;
1428  bool hasInlineStackProbe(MachineFunction &MF) const override;
1430 
1431  unsigned getStackProbeSize(MachineFunction &MF) const;
1432 
1433  bool hasVectorBlend() const override { return true; }
1434 
1435  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1436 
1437  /// Lower interleaved load(s) into target specific
1438  /// instructions/intrinsics.
1439  bool lowerInterleavedLoad(LoadInst *LI,
1441  ArrayRef<unsigned> Indices,
1442  unsigned Factor) const override;
1443 
1444  /// Lower interleaved store(s) into target specific
1445  /// instructions/intrinsics.
1447  unsigned Factor) const override;
1448 
1450  SDValue Addr, SelectionDAG &DAG)
1451  const override;
1452 
1453  Align getPrefLoopAlignment(MachineLoop *ML) const override;
1454 
1455  protected:
1456  std::pair<const TargetRegisterClass *, uint8_t>
1458  MVT VT) const override;
1459 
1460  private:
1461  /// Keep a reference to the X86Subtarget around so that we can
1462  /// make the right decision when generating code for different targets.
1463  const X86Subtarget &Subtarget;
1464 
1465  /// Select between SSE or x87 floating point ops.
1466  /// When SSE is available, use it for f32 operations.
1467  /// When SSE2 is available, use it for f64 operations.
1468  bool X86ScalarSSEf32;
1469  bool X86ScalarSSEf64;
1470  bool X86ScalarSSEf16;
1471 
1472  /// A list of legal FP immediates.
1473  std::vector<APFloat> LegalFPImmediates;
1474 
1475  /// Indicate that this x86 target can instruction
1476  /// select the specified FP immediate natively.
1477  void addLegalFPImmediate(const APFloat& Imm) {
1478  LegalFPImmediates.push_back(Imm);
1479  }
1480 
1481  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1482  CallingConv::ID CallConv, bool isVarArg,
1483  const SmallVectorImpl<ISD::InputArg> &Ins,
1484  const SDLoc &dl, SelectionDAG &DAG,
1485  SmallVectorImpl<SDValue> &InVals,
1486  uint32_t *RegMask) const;
1487  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1488  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1489  const SDLoc &dl, SelectionDAG &DAG,
1490  const CCValAssign &VA, MachineFrameInfo &MFI,
1491  unsigned i) const;
1492  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1493  const SDLoc &dl, SelectionDAG &DAG,
1494  const CCValAssign &VA,
1495  ISD::ArgFlagsTy Flags, bool isByval) const;
1496 
1497  // Call lowering helpers.
1498 
1499  /// Check whether the call is eligible for tail call optimization. Targets
1500  /// that want to do tail call optimization should implement this function.
1501  bool IsEligibleForTailCallOptimization(
1502  SDValue Callee, CallingConv::ID CalleeCC, bool IsCalleeStackStructRet,
1503  bool isVarArg, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs,
1504  const SmallVectorImpl<SDValue> &OutVals,
1505  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1506  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1507  SDValue Chain, bool IsTailCall,
1508  bool Is64Bit, int FPDiff,
1509  const SDLoc &dl) const;
1510 
1511  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1512  SelectionDAG &DAG) const;
1513 
1514  unsigned getAddressSpace(void) const;
1515 
1516  SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned,
1517  SDValue &Chain) const;
1518  SDValue LRINT_LLRINTHelper(SDNode *N, SelectionDAG &DAG) const;
1519 
1520  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1521  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1522  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1523  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1524 
1525  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr,
1526  const unsigned char OpFlags = 0) const;
1527  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1528  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1529  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1530  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1531  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1532 
1533  /// Creates target global address or external symbol nodes for calls or
1534  /// other uses.
1535  SDValue LowerGlobalOrExternal(SDValue Op, SelectionDAG &DAG,
1536  bool ForCall) const;
1537 
1538  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1539  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1540  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1541  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1542  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1543  SDValue LowerLRINT_LLRINT(SDValue Op, SelectionDAG &DAG) const;
1544  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1545  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1546  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1547  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1548  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1549  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1550  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1551  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1552  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1553  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1554  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1555  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1556  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1557  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1558  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1559  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1560  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1561  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1562  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1563  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1564  SDValue LowerWin64_FP_TO_INT128(SDValue Op, SelectionDAG &DAG,
1565  SDValue &Chain) const;
1566  SDValue LowerWin64_INT128_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1567  SDValue LowerGC_TRANSITION(SDValue Op, SelectionDAG &DAG) const;
1568  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1569  SDValue lowerFaddFsub(SDValue Op, SelectionDAG &DAG) const;
1570  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1571  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1572 
1573  SDValue
1574  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1575  const SmallVectorImpl<ISD::InputArg> &Ins,
1576  const SDLoc &dl, SelectionDAG &DAG,
1577  SmallVectorImpl<SDValue> &InVals) const override;
1578  SDValue LowerCall(CallLoweringInfo &CLI,
1579  SmallVectorImpl<SDValue> &InVals) const override;
1580 
1581  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1582  const SmallVectorImpl<ISD::OutputArg> &Outs,
1583  const SmallVectorImpl<SDValue> &OutVals,
1584  const SDLoc &dl, SelectionDAG &DAG) const override;
1585 
1586  bool supportSplitCSR(MachineFunction *MF) const override {
1587  return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
1588  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1589  }
1590  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1591  void insertCopiesSplitCSR(
1592  MachineBasicBlock *Entry,
1593  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1594 
1595  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1596 
1597  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1598 
1599  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1600  ISD::NodeType ExtendKind) const override;
1601 
1602  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1603  bool isVarArg,
1604  const SmallVectorImpl<ISD::OutputArg> &Outs,
1605  LLVMContext &Context) const override;
1606 
1607  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1608 
1610  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
1611  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1613  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1614 
1615  LoadInst *
1616  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1617 
1618  bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const override;
1619  bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const override;
1620 
1621  bool needsCmpXchgNb(Type *MemType) const;
1622 
1623  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1624  MachineBasicBlock *DispatchBB, int FI) const;
1625 
1626  // Utility function to emit the low-level va_arg code for X86-64.
1627  MachineBasicBlock *
1628  EmitVAARGWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
1629 
1630  /// Utility function to emit the xmm reg save portion of va_start.
1631  MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1632  MachineInstr &MI2,
1633  MachineBasicBlock *BB) const;
1634 
1635  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1636  MachineBasicBlock *BB) const;
1637 
1638  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1639  MachineBasicBlock *BB) const;
1640 
1641  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1642  MachineBasicBlock *BB) const;
1643 
1644  MachineBasicBlock *EmitLoweredProbedAlloca(MachineInstr &MI,
1645  MachineBasicBlock *BB) const;
1646 
1647  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1648  MachineBasicBlock *BB) const;
1649 
1650  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1651  MachineBasicBlock *BB) const;
1652 
1653  MachineBasicBlock *EmitLoweredIndirectThunk(MachineInstr &MI,
1654  MachineBasicBlock *BB) const;
1655 
1656  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1657  MachineBasicBlock *MBB) const;
1658 
1659  void emitSetJmpShadowStackFix(MachineInstr &MI,
1660  MachineBasicBlock *MBB) const;
1661 
1662  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1663  MachineBasicBlock *MBB) const;
1664 
1665  MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1666  MachineBasicBlock *MBB) const;
1667 
1668  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1669  MachineBasicBlock *MBB) const;
1670 
1671  /// Emit flags for the given setcc condition and operands. Also returns the
1672  /// corresponding X86 condition code constant in X86CC.
1673  SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC,
1674  const SDLoc &dl, SelectionDAG &DAG,
1675  SDValue &X86CC) const;
1676 
1677  /// Check if replacement of SQRT with RSQRT should be disabled.
1678  bool isFsqrtCheap(SDValue Op, SelectionDAG &DAG) const override;
1679 
1680  /// Use rsqrt* to speed up sqrt calculations.
1681  SDValue getSqrtEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1682  int &RefinementSteps, bool &UseOneConstNR,
1683  bool Reciprocal) const override;
1684 
1685  /// Use rcp* to speed up fdiv calculations.
1686  SDValue getRecipEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1687  int &RefinementSteps) const override;
1688 
1689  /// Reassociate floating point divisions into multiply by reciprocal.
1690  unsigned combineRepeatedFPDivisors() const override;
1691 
1692  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1693  SmallVectorImpl<SDNode *> &Created) const override;
1694  };
1695 
1696  namespace X86 {
1697  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1698  const TargetLibraryInfo *libInfo);
1699  } // end namespace X86
1700 
1701  // X86 specific Gather/Scatter nodes.
1702  // The class has the same order of operands as MaskedGatherScatterSDNode for
1703  // convenience.
1705  public:
1706  // This is a intended as a utility and should never be directly created.
1707  X86MaskedGatherScatterSDNode() = delete;
1708  ~X86MaskedGatherScatterSDNode() = delete;
1709 
1710  const SDValue &getBasePtr() const { return getOperand(3); }
1711  const SDValue &getIndex() const { return getOperand(4); }
1712  const SDValue &getMask() const { return getOperand(2); }
1713  const SDValue &getScale() const { return getOperand(5); }
1714 
1715  static bool classof(const SDNode *N) {
1716  return N->getOpcode() == X86ISD::MGATHER ||
1717  N->getOpcode() == X86ISD::MSCATTER;
1718  }
1719  };
1720 
1722  public:
1723  const SDValue &getPassThru() const { return getOperand(1); }
1724 
1725  static bool classof(const SDNode *N) {
1726  return N->getOpcode() == X86ISD::MGATHER;
1727  }
1728  };
1729 
1731  public:
1732  const SDValue &getValue() const { return getOperand(1); }
1733 
1734  static bool classof(const SDNode *N) {
1735  return N->getOpcode() == X86ISD::MSCATTER;
1736  }
1737  };
1738 
1739  /// Generate unpacklo/unpackhi shuffle mask.
1740  void createUnpackShuffleMask(EVT VT, SmallVectorImpl<int> &Mask, bool Lo,
1741  bool Unary);
1742 
1743  /// Similar to unpacklo/unpackhi, but without the 128-bit lane limitation
1744  /// imposed by AVX and specific to the unary pattern. Example:
1745  /// v8iX Lo --> <0, 0, 1, 1, 2, 2, 3, 3>
1746  /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7>
1747  void createSplat2ShuffleMask(MVT VT, SmallVectorImpl<int> &Mask, bool Lo);
1748 
1749 } // end namespace llvm
1750 
1751 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
llvm::X86ISD::FDIVS
@ FDIVS
Definition: X86ISelLowering.h:226
llvm::X86ISD::UINT_TO_FP_RND
@ UINT_TO_FP_RND
Definition: X86ISelLowering.h:599
llvm::X86ISD::VFPROUND
@ VFPROUND
Definition: X86ISelLowering.h:341
llvm::X86ISD::RCP28S_SAE
@ RCP28S_SAE
Definition: X86ISelLowering.h:707
i
i
Definition: README.txt:29
llvm::X86ISD::EXPAND
@ EXPAND
Definition: X86ISelLowering.h:592
llvm::X86ISD::VGETMANTS_SAE
@ VGETMANTS_SAE
Definition: X86ISelLowering.h:245
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::X86ISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: X86ISelLowering.h:744
llvm::X86ISD::STRICT_VFPEXT
@ STRICT_VFPEXT
Definition: X86ISelLowering.h:758
llvm::X86ISD::FMUL_RND
@ FMUL_RND
Definition: X86ISelLowering.h:222
llvm::X86TargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: X86ISelLowering.cpp:53566
llvm::X86TargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: X86ISelLowering.cpp:5638
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1556
llvm::X86ISD::UMWAIT
@ UMWAIT
Definition: X86ISelLowering.h:729
llvm::X86ISD::STRICT_VRNDSCALE
@ STRICT_VRNDSCALE
Definition: X86ISelLowering.h:766
llvm::X86TargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: X86ISelLowering.cpp:27467
llvm::X86ISD::PCMPESTR
@ PCMPESTR
Definition: X86ISelLowering.h:694
llvm::X86TargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: X86ISelLowering.cpp:53205
llvm::X86ISD::TLSADDR
@ TLSADDR
Definition: X86ISelLowering.h:291
llvm::X86ISD::VFCMULCSH_RND
@ VFCMULCSH_RND
Definition: X86ISelLowering.h:588
llvm::X86ISD::AESDEC128KL
@ AESDEC128KL
Definition: X86ISelLowering.h:866
llvm::X86ISD::FADD_RND
@ FADD_RND
Definition: X86ISelLowering.h:216
llvm::X86ISD::FMINS
@ FMINS
Definition: X86ISelLowering.h:276
llvm::X86ISD::FMAXS_SAE
@ FMAXS_SAE
Definition: X86ISelLowering.h:229
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::X86TargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: X86ISelLowering.h:1084
llvm::X86MaskedGatherScatterSDNode::getIndex
const SDValue & getIndex() const
Definition: X86ISelLowering.h:1711
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::X86ISD::PACKUS
@ PACKUS
Definition: X86ISelLowering.h:441
llvm::X86ISD::RCP28_SAE
@ RCP28_SAE
Definition: X86ISelLowering.h:705
llvm::X86ISD::PEXTRW
@ PEXTRW
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
Definition: X86ISelLowering.h:177
llvm::X86ISD::VPERMIL2
@ VPERMIL2
Definition: X86ISelLowering.h:528
llvm::X86ISD::SCALEFS_RND
@ SCALEFS_RND
Definition: X86ISelLowering.h:250
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::X86ISD::MCVTSI2P
@ MCVTSI2P
Definition: X86ISelLowering.h:637
llvm::X86TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:5137
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::X86TargetLowering::hasStackProbeSymbol
bool hasStackProbeSymbol(MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Definition: X86ISelLowering.cpp:54086
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::X86TargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Return true if sinking I's operands to the same basic block as I is profitable, e....
Definition: X86ISelLowering.cpp:32905
llvm::X86ISD::VFCMULC_RND
@ VFCMULC_RND
Definition: X86ISelLowering.h:578
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::X86TargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: X86ISelLowering.cpp:35530
llvm::X86ISD::PALIGNR
@ PALIGNR
Definition: X86ISelLowering.h:443
llvm::X86ISD::VFPEXTS_SAE
@ VFPEXTS_SAE
Definition: X86ISelLowering.h:338
llvm::X86ISD::DYN_ALLOCA
@ DYN_ALLOCA
Definition: X86ISelLowering.h:658
llvm::X86ISD::VMTRUNCUS
@ VMTRUNCUS
Definition: X86ISelLowering.h:331
llvm::X86ISD::VRANGES_SAE
@ VRANGES_SAE
Definition: X86ISelLowering.h:491
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4155
llvm::X86TargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: X86ISelLowering.cpp:2771
llvm::X86TargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: X86ISelLowering.cpp:2669
llvm::X86ISD::SHUF128
@ SHUF128
Definition: X86ISelLowering.h:456
llvm::X86ISD::STRICT_FNMSUB
@ STRICT_FNMSUB
Definition: X86ISelLowering.h:775
llvm::X86TargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: X86ISelLowering.h:1164
llvm::X86ISD::LADD
@ LADD
LOCK-prefixed arithmetic read-modify-write instructions.
Definition: X86ISelLowering.h:792
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Function
Definition: Function.h:62
llvm::X86ISD::GF2P8MULB
@ GF2P8MULB
Definition: X86ISelLowering.h:723
llvm::X86ISD::MULHRS
@ MULHRS
Definition: X86ISelLowering.h:535
llvm::X86ISD::VPPERM
@ VPPERM
Definition: X86ISelLowering.h:526
llvm::X86ISD::LWPINS
@ LWPINS
Definition: X86ISelLowering.h:726
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::X86ISD::FSETCC
@ FSETCC
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
Definition: X86ISelLowering.h:107
llvm::X86ISD::FDIVS_RND
@ FDIVS_RND
Definition: X86ISelLowering.h:227
llvm::X86ISD::FMAX
@ FMAX
Floating point max and min.
Definition: X86ISelLowering.h:267
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::X86ISD::SUBV_BROADCAST_LOAD
@ SUBV_BROADCAST_LOAD
Definition: X86ISelLowering.h:808
llvm::X86TargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
Definition: X86InterleavedAccess.cpp:810
llvm::X86ISD::CVTPH2PS
@ CVTPH2PS
Definition: X86ISelLowering.h:713
llvm::X86TargetLowering::isVectorClearMaskLegal
bool isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
Definition: X86ISelLowering.cpp:33030
llvm::X86ISD::SETCC_CARRY
@ SETCC_CARRY
Definition: X86ISelLowering.h:102
llvm::X86ISD::GF2P8AFFINEQB
@ GF2P8AFFINEQB
Definition: X86ISelLowering.h:722
llvm::X86ISD::CVTTP2SI_SAE
@ CVTTP2SI_SAE
Definition: X86ISelLowering.h:619
llvm::X86ISD::VSHRDV
@ VSHRDV
Definition: X86ISelLowering.h:454
llvm::X86ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: X86ISelLowering.h:308
llvm::X86ISD::FXOR
@ FXOR
Bitwise logical XOR of floating point values.
Definition: X86ISelLowering.h:52
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::X86ISD::STRICT_CVTUI2P
@ STRICT_CVTUI2P
Definition: X86ISelLowering.h:770
llvm::X86ISD::FGETEXP_SAE
@ FGETEXP_SAE
Definition: X86ISelLowering.h:238
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86ISD::CVTP2UI_RND
@ CVTP2UI_RND
Definition: X86ISelLowering.h:609
llvm::X86ISD::SCALEFS
@ SCALEFS
Definition: X86ISelLowering.h:249
llvm::X86ISD::FMADD_RND
@ FMADD_RND
Definition: X86ISelLowering.h:562
llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: X86ISelLowering.cpp:5707
llvm::X86ISD::TPAUSE
@ TPAUSE
Definition: X86ISelLowering.h:730
llvm::X86ISD::SELECTS
@ SELECTS
X86 Select.
Definition: X86ISelLowering.h:98
llvm::X86ISD::MCVTTP2UI
@ MCVTTP2UI
Definition: X86ISelLowering.h:636
llvm::X86ISD::BRCOND
@ BRCOND
X86 conditional branches.
Definition: X86ISelLowering.h:123
llvm::X86ISD::CVTTS2UI
@ CVTTS2UI
Definition: X86ISelLowering.h:623
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::X86TargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: X86ISelLowering.cpp:2591
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Definition: X86ISelLowering.h:1307
llvm::X86ISD::EXP2
@ EXP2
Definition: X86ISelLowering.h:708
llvm::X86ISD::LCMPXCHG_DAG
@ LCMPXCHG_DAG
Definition: X86ISelLowering.h:785
llvm::X86ISD::PSHUFLW
@ PSHUFLW
Definition: X86ISelLowering.h:448
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2281
llvm::X86TargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: X86ISelLowering.h:1435
llvm::MemOp
Definition: TargetLowering.h:112
llvm::X86ISD::FST
@ FST
This instruction implements a truncating store from FP stack slots.
Definition: X86ISelLowering.h:846
llvm::X86ISD::CALL_RVMARKER
@ CALL_RVMARKER
Definition: X86ISelLowering.h:82
llvm::X86TargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
Definition: X86ISelLowering.cpp:53139
llvm::X86ISD::BLENDV
@ BLENDV
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
Definition: X86ISelLowering.h:210
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::X86TargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: X86ISelLowering.cpp:2373
llvm::X86TargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: X86ISelLowering.cpp:54132
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::X86ISD::RCP28
@ RCP28
Definition: X86ISelLowering.h:704
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::X86ISD::CVTS2SI_RND
@ CVTS2SI_RND
Definition: X86ISelLowering.h:613
llvm::X86ISD::FNMADD
@ FNMADD
Definition: X86ISelLowering.h:555
llvm::X86TargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: X86ISelLowering.cpp:53991
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::X86TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: X86ISelLowering.cpp:5620
llvm::X86ISD::MCVTP2SI
@ MCVTP2SI
Definition: X86ISelLowering.h:633
llvm::X86MaskedGatherScatterSDNode
Definition: X86ISelLowering.h:1704
llvm::AttributeList
Definition: Attributes.h:399
llvm::X86ISD::VSHLDQ
@ VSHLDQ
Definition: X86ISelLowering.h:351
llvm::X86ISD::SBB
@ SBB
Definition: X86ISelLowering.h:401
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::X86ISD::VFIXUPIMMS
@ VFIXUPIMMS
Definition: X86ISelLowering.h:485
llvm::X86TargetLowering::storeOfVectorConstantIsCheap
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
Definition: X86ISelLowering.h:1347
llvm::X86ISD::FNMSUB_RND
@ FNMSUB_RND
Definition: X86ISelLowering.h:565
llvm::X86ISD::KSHIFTL
@ KSHIFTL
Definition: X86ISelLowering.h:370
llvm::X86ISD::ANDNP
@ ANDNP
Bitwise Logical AND NOT of Packed FP values.
Definition: X86ISelLowering.h:200
llvm::X86ISD::PACKSS
@ PACKSS
Definition: X86ISelLowering.h:440
llvm::X86TargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: X86ISelLowering.cpp:2601
llvm::X86::isOffsetSuitableForCodeModel
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
Returns true of the given offset can be fit into displacement field of the instruction.
Definition: X86ISelLowering.cpp:5155
llvm::X86ISD::VTRUNCSTORES
@ VTRUNCSTORES
Definition: X86ISelLowering.h:855
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::X86MaskedGatherScatterSDNode::X86MaskedGatherScatterSDNode
X86MaskedGatherScatterSDNode()=delete
llvm::X86ISD::VPMADDWD
@ VPMADDWD
Definition: X86ISelLowering.h:539
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::X86ISD::VSHLV
@ VSHLV
Definition: X86ISelLowering.h:360
llvm::X86ISD::VPMADDUBSW
@ VPMADDUBSW
Definition: X86ISelLowering.h:538
llvm::X86ISD::LAND
@ LAND
Definition: X86ISelLowering.h:796
llvm::X86TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: X86ISelLowering.cpp:32317
llvm::X86ISD::STRICT_CMPP
@ STRICT_CMPP
Definition: X86ISelLowering.h:747
llvm::X86ISD::BSR
@ BSR
Bit scan reverse.
Definition: X86ISelLowering.h:33
llvm::X86ISD::HSUB
@ HSUB
Definition: X86ISelLowering.h:257
llvm::X86ISD::PDEP
@ PDEP
Definition: X86ISelLowering.h:416
llvm::X86ISD::VASTART_SAVE_XMM_REGS
@ VASTART_SAVE_XMM_REGS
Definition: X86ISelLowering.h:655
llvm::X86ISD::LOR
@ LOR
Definition: X86ISelLowering.h:794
llvm::X86ISD::PSHUFHW
@ PSHUFHW
Definition: X86ISelLowering.h:447
llvm::X86ISD::VSRLDQ
@ VSRLDQ
Definition: X86ISelLowering.h:352
llvm::X86ISD::FMADDSUB
@ FMADDSUB
Definition: X86ISelLowering.h:558
llvm::X86ISD::SMUL
@ SMUL
Definition: X86ISelLowering.h:402
llvm::X86ISD::VFPEXT
@ VFPEXT
Definition: X86ISelLowering.h:335
llvm::X86ISD::RSQRT28
@ RSQRT28
Definition: X86ISelLowering.h:700
llvm::X86ISD::VTRUNC
@ VTRUNC
Definition: X86ISelLowering.h:321
llvm::X86TargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: X86ISelLowering.cpp:32854
llvm::X86ISD::FMAXC
@ FMAXC
Commutative FMIN and FMAX.
Definition: X86ISelLowering.h:271
llvm::X86ISD::VRANGE
@ VRANGE
Definition: X86ISelLowering.h:488
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::X86ISD::BEXTRI
@ BEXTRI
Definition: X86ISelLowering.h:410
llvm::X86TargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: X86ISelLowering.h:1293
llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle
bool SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) const
Definition: X86ISelLowering.cpp:39622
llvm::X86ISD::STRICT_CVTPH2PS
@ STRICT_CVTPH2PS
Definition: X86ISelLowering.h:779
llvm::X86ISD::MCVTPS2PH
@ MCVTPS2PH
Definition: X86ISelLowering.h:718
llvm::X86ISD::RSQRT14S
@ RSQRT14S
Definition: X86ISelLowering.h:286
llvm::X86ISD::MCVTTP2SI
@ MCVTTP2SI
Definition: X86ISelLowering.h:635
llvm::X86TargetLowering::shouldScalarizeBinop
bool shouldScalarizeBinop(SDValue) const override
Scalar ops always have equal or better analysis/performance/power than the vector equivalent,...
Definition: X86ISelLowering.cpp:5565
llvm::X86TargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: X86ISelLowering.cpp:5491
llvm::X86ISD::FSETCCM
@ FSETCCM
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.
Definition: X86ISelLowering.h:111
llvm::X86TargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: X86ISelLowering.h:1023
llvm::X86ISD::VPERMI
@ VPERMI
Definition: X86ISelLowering.h:469
llvm::X86TargetLowering::getClearCacheBuiltinName
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
Definition: X86ISelLowering.h:1359
llvm::X86ISD::PSHUFD
@ PSHUFD
Definition: X86ISelLowering.h:446
llvm::X86ISD::VRNDSCALES
@ VRNDSCALES
Definition: X86ISelLowering.h:502
llvm::X86TargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: X86ISelLowering.cpp:35621
llvm::X86ISD::CMPP
@ CMPP
Definition: X86ISelLowering.h:378
llvm::X86ISD::FMSUBADD_RND
@ FMSUBADD_RND
Definition: X86ISelLowering.h:567
llvm::X86ISD::VFPROUNDS
@ VFPROUNDS
Definition: X86ISelLowering.h:343
llvm::X86ISD::MOVLHPS
@ MOVLHPS
Definition: X86ISelLowering.h:460
llvm::X86ISD::CMPMM
@ CMPMM
Definition: X86ISelLowering.h:393
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::X86TargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: X86ISelLowering.cpp:5345
llvm::X86ISD::CALL
@ CALL
These operations represent an abstract X86 call instruction, which includes a bunch of information.
Definition: X86ISelLowering.h:75
llvm::X86TargetLowering::getSafeStackPointerLocation
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
Definition: X86ISelLowering.cpp:2790
llvm::X86ISD::MSCATTER
@ MSCATTER
Definition: X86ISelLowering.h:862
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::X86TargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: X86ISelLowering.cpp:53027
llvm::X86ISD::CVTS2SI
@ CVTS2SI
Definition: X86ISelLowering.h:611
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1341
llvm::X86TargetLowering::LowerAsmOutputForConstraint
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Handle Lowering flag assembly outputs.
Definition: X86ISelLowering.cpp:53363
TargetLowering.h
llvm::X86ISD::SUB
@ SUB
Definition: X86ISelLowering.h:399
llvm::X86ISD::COMPRESS
@ COMPRESS
Definition: X86ISelLowering.h:591
llvm::X86ISD::RCP14S
@ RCP14S
Definition: X86ISelLowering.h:288
llvm::X86ISD::SEG_ALLOCA
@ SEG_ALLOCA
Definition: X86ISelLowering.h:663
llvm::X86ISD::PMULDQ
@ PMULDQ
Definition: X86ISelLowering.h:533
llvm::X86ISD::CMPM
@ CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
Definition: X86ISelLowering.h:391
llvm::X86ISD::VSRA
@ VSRA
Definition: X86ISelLowering.h:357
llvm::X86ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: X86ISelLowering.h:311
llvm::X86ISD::PINSRW
@ PINSRW
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
Definition: X86ISelLowering.h:189
llvm::MemIntrinsicSDNode
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
Definition: SelectionDAGNodes.h:1472
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:59
llvm::X86ISD::STRICT_CMPM
@ STRICT_CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
Definition: X86ISelLowering.h:751
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::X86TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: X86ISelLowering.cpp:35111
llvm::X86TargetLowering::useStackGuardXorFP
bool useStackGuardXorFP() const override
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
Definition: X86ISelLowering.cpp:2290
llvm::X86ISD::PSHUFB
@ PSHUFB
Shuffle 16 8-bit values within a vector.
Definition: X86ISelLowering.h:192
llvm::X86ISD::VMTRUNCSTOREUS
@ VMTRUNCSTOREUS
Definition: X86ISelLowering.h:857
llvm::X86ISD::VPSHUFBITQMB
@ VPSHUFBITQMB
Definition: X86ISelLowering.h:595
llvm::X86ISD::FNMSUB
@ FNMSUB
Definition: X86ISelLowering.h:557
llvm::X86ISD::MOVSLDUP
@ MOVSLDUP
Definition: X86ISelLowering.h:459
llvm::X86ISD::CMOV
@ CMOV
X86 conditional moves.
Definition: X86ISelLowering.h:117
llvm::X86TargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: X86ISelLowering.cpp:52845
llvm::X86TargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: X86ISelLowering.cpp:27512
llvm::X86ISD::VTRUNCS
@ VTRUNCS
Definition: X86ISelLowering.h:324
llvm::X86ISD::RDRAND
@ RDRAND
Definition: X86ISelLowering.h:674
llvm::X86ISD::BT
@ BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:91
llvm::X86ISD::GF2P8AFFINEINVQB
@ GF2P8AFFINEINVQB
Definition: X86ISelLowering.h:721
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::X86ISD::FMADDSUB_RND
@ FMADDSUB_RND
Definition: X86ISelLowering.h:566
llvm::X86ISD::MOVSHDUP
@ MOVSHDUP
Definition: X86ISelLowering.h:458
llvm::X86ISD::FADDS_RND
@ FADDS_RND
Definition: X86ISelLowering.h:218
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::X86ISD::RDSEED
@ RDSEED
Definition: X86ISelLowering.h:678
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::X86ISD::VBROADCAST_LOAD
@ VBROADCAST_LOAD
Definition: X86ISelLowering.h:805
llvm::X86ISD::VSRLI
@ VSRLI
Definition: X86ISelLowering.h:366
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3187
llvm::X86TargetLowering::hasVectorBlend
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Definition: X86ISelLowering.h:1433
llvm::X86ISD::ENQCMDS
@ ENQCMDS
Definition: X86ISelLowering.h:734
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::X86::isConstantSplat
bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs)
If Op is a constant whose elements are all the same constant or undefined, return true and return the...
Definition: X86ISelLowering.cpp:7076
llvm::X86TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: X86ISelLowering.cpp:31169
llvm::X86ISD::STRICT_VFPROUND
@ STRICT_VFPROUND
Definition: X86ISelLowering.h:761
llvm::X86ISD::FHSUB
@ FHSUB
Definition: X86ISelLowering.h:261
llvm::X86ISD::WRPKRU
@ WRPKRU
Definition: X86ISelLowering.h:685
llvm::X86ISD::VZEXT_LOAD
@ VZEXT_LOAD
Definition: X86ISelLowering.h:799
llvm::X86ISD::NT_CALL
@ NT_CALL
Same as call except it adds the NoTrack prefix.
Definition: X86ISelLowering.h:78
llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: X86ISelLowering.cpp:40311
llvm::X86ISD::VSHLD
@ VSHLD
Definition: X86ISelLowering.h:451
llvm::X86TargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: X86ISelLowering.cpp:2286
llvm::X86ISD::FILD
@ FILD
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.
Definition: X86ISelLowering.h:828
llvm::X86ISD::SCALEF_RND
@ SCALEF_RND
Definition: X86ISelLowering.h:248
llvm::X86ISD::MFENCE
@ MFENCE
Definition: X86ISelLowering.h:671
llvm::InlineAsm::Constraint_v
@ Constraint_v
Definition: InlineAsm.h:249
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::X86ISD::CVTNEPS2BF16
@ CVTNEPS2BF16
Definition: X86ISelLowering.h:644
llvm::X86TargetLowering::markLibCallAttributes
void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override
Definition: X86ISelLowering.cpp:2605
llvm::createSplat2ShuffleMask
void createSplat2ShuffleMask(MVT VT, SmallVectorImpl< int > &Mask, bool Lo)
Similar to unpacklo/unpackhi, but without the 128-bit lane limitation imposed by AVX and specific to ...
Definition: X86ISelLowering.cpp:6668
llvm::X86TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
Definition: X86ISelLowering.cpp:32871
llvm::X86ISD::VPERM2X128
@ VPERM2X128
Definition: X86ISelLowering.h:470
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:145
llvm::X86TargetLowering::needsFixedCatchObjects
virtual bool needsFixedCatchObjects() const override
Definition: X86ISelLowering.cpp:27520
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::X86MaskedGatherScatterSDNode::getMask
const SDValue & getMask() const
Definition: X86ISelLowering.h:1712
llvm::X86ISD::VFCMADDC
@ VFCMADDC
Definition: X86ISelLowering.h:572
llvm::X86TargetLowering::isLoadBitCastBeneficial
bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const override
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Definition: X86ISelLowering.cpp:5602
llvm::X86ISD::VPDPBUSDS
@ VPDPBUSDS
Definition: X86ISelLowering.h:549
llvm::X86ISD::FSUBS_RND
@ FSUBS_RND
Definition: X86ISelLowering.h:221
llvm::X86ISD::VSHLDV
@ VSHLDV
Definition: X86ISelLowering.h:453
llvm::X86ISD::SCALAR_UINT_TO_FP
@ SCALAR_UINT_TO_FP
Definition: X86ISelLowering.h:601
llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: X86ISelLowering.cpp:32981
llvm::X86TargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: X86ISelLowering.cpp:53351
llvm::X86ISD::FGETEXPS_SAE
@ FGETEXPS_SAE
Definition: X86ISelLowering.h:240
llvm::X86ISD::AESDEC256KL
@ AESDEC256KL
Definition: X86ISelLowering.h:868
llvm::X86ISD::RSQRT28S
@ RSQRT28S
Definition: X86ISelLowering.h:702
llvm::X86TargetLowering
Definition: X86ISelLowering.h:918
llvm::X86ISD::PEXTRB
@ PEXTRB
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
Definition: X86ISelLowering.h:173
llvm::X86TargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: X86ISelLowering.cpp:5642
llvm::X86ISD::VAARG_64
@ VAARG_64
These instructions grab the address of the next argument from a va_list.
Definition: X86ISelLowering.h:850
llvm::X86ISD::VEXTRACT_STORE
@ VEXTRACT_STORE
Definition: X86ISelLowering.h:802
llvm::X86ISD::IRET
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
Definition: X86ISelLowering.h:134
llvm::X86TargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: X86ISelLowering.cpp:32836
llvm::X86ISD::CVTTP2UI
@ CVTTP2UI
Definition: X86ISelLowering.h:618
llvm::X86ISD::FMAXS
@ FMAXS
Scalar intrinsic floating point max and min.
Definition: X86ISelLowering.h:275
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86ISD::CVTS2UI_RND
@ CVTS2UI_RND
Definition: X86ISelLowering.h:614
llvm::X86ISD::LCMPXCHG16_DAG
@ LCMPXCHG16_DAG
Definition: X86ISelLowering.h:787
llvm::X86TargetLowering::areJTsAllowed
bool areJTsAllowed(const Function *Fn) const override
Returns true if lowering to a jump table is allowed.
Definition: X86ISelLowering.cpp:33042
llvm::X86ISD::CVTTS2UI_SAE
@ CVTTS2UI_SAE
Definition: X86ISelLowering.h:625
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::X86ISD::MOVHLPS
@ MOVHLPS
Definition: X86ISelLowering.h:461
llvm::X86TargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: X86ISelLowering.cpp:54091
llvm::X86ISD::SCALAR_SINT_TO_FP
@ SCALAR_SINT_TO_FP
Definition: X86ISelLowering.h:600
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::X86ISD::VFIXUPIMM_SAE
@ VFIXUPIMM_SAE
Definition: X86ISelLowering.h:484
llvm::X86TargetLowering::isVectorShiftByScalarCheap
bool isVectorShiftByScalarCheap(Type *Ty) const override
This is used to enable splatted operand transforms for vector shifts and vector funnel shifts.
Definition: X86ISelLowering.cpp:32767
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::X86ISD::VPERMILPI
@ VPERMILPI
Definition: X86ISelLowering.h:468
llvm::X86ISD::CVTNE2PS2BF16
@ CVTNE2PS2BF16
Definition: X86ISelLowering.h:642
llvm::X86TargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: X86ISelLowering.cpp:33013
llvm::X86TargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: X86ISelLowering.cpp:2645
llvm::X86ISD::GlobalBaseReg
@ GlobalBaseReg
On Darwin, this node represents the result of the popl at function entry, used for PIC code.
Definition: X86ISelLowering.h:144
llvm::X86ISD::VFPCLASS
@ VFPCLASS
Definition: X86ISelLowering.h:505
llvm::X86ISD::EXTRQI
@ EXTRQI
SSE4A Extraction and Insertion.
Definition: X86ISelLowering.h:516
llvm::X86MaskedGatherScatterSDNode::getScale
const SDValue & getScale() const
Definition: X86ISelLowering.h:1713
llvm::X86ISD::DPBF16PS
@ DPBF16PS
Definition: X86ISelLowering.h:651
llvm::X86ISD::VREDUCES
@ VREDUCES
Definition: X86ISelLowering.h:495
llvm::X86ISD::FGETEXP
@ FGETEXP
Definition: X86ISelLowering.h:237
llvm::X86ISD::AESENC256KL
@ AESENC256KL
Definition: X86ISelLowering.h:867
llvm::X86ISD::INSERTQI
@ INSERTQI
Definition: X86ISelLowering.h:517
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:57
llvm::X86ISD::MCVTNEPS2BF16
@ MCVTNEPS2BF16
Definition: X86ISelLowering.h:647
llvm::X86MaskedGatherScatterSDNode::~X86MaskedGatherScatterSDNode
~X86MaskedGatherScatterSDNode()=delete
llvm::X86TargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code.
Definition: X86ISelLowering.cpp:31317
llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode
bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
Definition: X86ISelLowering.cpp:39689
llvm::X86ISD::ADD
@ ADD
Definition: X86ISelLowering.h:398
llvm::X86ISD::VRNDSCALE
@ VRNDSCALE
Definition: X86ISelLowering.h:500
llvm::X86ISD::PHMINPOS
@ PHMINPOS
Definition: X86ISelLowering.h:385
llvm::X86::rmMask
@ rmMask
Definition: X86ISelLowering.h:889
llvm::X86ISD::CVTS2UI
@ CVTS2UI
Definition: X86ISelLowering.h:612
llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair
bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
Definition: X86ISelLowering.cpp:5725
llvm::APFloat
Definition: APFloat.h:701
llvm::X86ISD::FMINC
@ FMINC
Definition: X86ISelLowering.h:272
llvm::X86ISD::CVTUI2P
@ CVTUI2P
Definition: X86ISelLowering.h:629
llvm::X86ISD::FMIN_SAE
@ FMIN_SAE
Definition: X86ISelLowering.h:230
llvm::X86TargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: X86ISelLowering.cpp:5647
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::X86ISD::VFCMULC
@ VFCMULC
Definition: X86ISelLowering.h:577
llvm::X86ISD::VPSHA
@ VPSHA
Definition: X86ISelLowering.h:520
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::X86ISD::MGATHER
@ MGATHER
Definition: X86ISelLowering.h:861
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::X86ISD::KADD
@ KADD
Definition: X86ISelLowering.h:436
llvm::X86TargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: X86ISelLowering.cpp:5519
llvm::X86ISD::VBROADCASTM
@ VBROADCASTM
Definition: X86ISelLowering.h:513
llvm::X86ISD::CVTP2SI_RND
@ CVTP2SI_RND
Definition: X86ISelLowering.h:608
llvm::X86ISD::MOVQ2DQ
@ MOVQ2DQ
Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero fi...
Definition: X86ISelLowering.h:157
llvm::createUnpackShuffleMask
void createUnpackShuffleMask(EVT VT, SmallVectorImpl< int > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
Definition: X86ISelLowering.cpp:6648
llvm::X86TargetLowering::getPreferredVectorAction
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Customize the preferred legalization strategy for certain types.
Definition: X86ISelLowering.cpp:2304
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::X86ISD::FSQRTS_RND
@ FSQRTS_RND
Definition: X86ISelLowering.h:234
llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: X86ISelLowering.cpp:2658
uint64_t
llvm::X86ISD::FSHL
@ FSHL
X86 funnel/double shift i16 instructions.
Definition: X86ISelLowering.h:39
llvm::X86ISD::VRNDSCALE_SAE
@ VRNDSCALE_SAE
Definition: X86ISelLowering.h:501
llvm::X86ISD::VFMADDCSH_RND
@ VFMADDCSH_RND
Definition: X86ISelLowering.h:581
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1255
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::X86::isZeroNode
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
Definition: X86ISelLowering.cpp:6002
llvm::X86ISD::VTRUNCSTOREUS
@ VTRUNCSTOREUS
Definition: X86ISelLowering.h:854
llvm::X86ISD::FOR
@ FOR
Bitwise logical OR of floating point values.
Definition: X86ISelLowering.h:48
llvm::X86ISD::VFPEXTS
@ VFPEXTS
Definition: X86ISelLowering.h:337
llvm::X86TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: X86ISelLowering.cpp:2556
llvm::X86ISD::STRICT_FMSUB
@ STRICT_FMSUB
Definition: X86ISelLowering.h:774
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::X86ISD::VFCMADDC_RND
@ VFCMADDC_RND
Definition: X86ISelLowering.h:573
llvm::X86ISD::FSETCCM_SAE
@ FSETCCM_SAE
Definition: X86ISelLowering.h:112
llvm::X86ISD::VFMULCSH_RND
@ VFMULCSH_RND
Definition: X86ISelLowering.h:586
llvm::X86ISD::VPERMV3
@ VPERMV3
Definition: X86ISelLowering.h:478
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::X86TargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: X86ISelLowering.cpp:32968
llvm::X86ISD::VFPROUND_RND
@ VFPROUND_RND
Definition: X86ISelLowering.h:342
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:904
llvm::X86ISD::RSQRT28_SAE
@ RSQRT28_SAE
Definition: X86ISelLowering.h:701
llvm::X86ISD::MOVSS
@ MOVSS
Definition: X86ISelLowering.h:463
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::X86ISD::CVTTP2UI_SAE
@ CVTTP2UI_SAE
Definition: X86ISelLowering.h:620
llvm::X86TargetLowering::X86TargetLowering
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
Definition: X86ISelLowering.cpp:107
llvm::X86ISD::PEXT
@ PEXT
Definition: X86ISelLowering.h:417
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::X86ISD::ENQCMD
@ ENQCMD
Definition: X86ISelLowering.h:733
llvm::X86ISD::VFPCLASSS
@ VFPCLASSS
Definition: X86ISelLowering.h:507
llvm::X86ISD::VREDUCE
@ VREDUCE
Definition: X86ISelLowering.h:493
llvm::X86ISD::VPDPWSSD
@ VPDPWSSD
Definition: X86ISelLowering.h:550
llvm::X86ISD::INSERTPS
@ INSERTPS
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
Definition: X86ISelLowering.h:181
llvm::TargetLoweringBase::NegatibleCost
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition: TargetLowering.h:268
llvm::X86ISD::BSF
@ BSF
Bit scan forward.
Definition: X86ISelLowering.h:31
llvm::X86ISD::VSRAV
@ VSRAV
Definition: X86ISelLowering.h:362
llvm::X86ISD::UNPCKL
@ UNPCKL
Definition: X86ISelLowering.h:465
llvm::X86ISD::COMI
@ COMI
Definition: X86ISelLowering.h:87
llvm::X86TargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: X86ISelLowering.cpp:54144
llvm::X86ISD::UMUL
@ UMUL
Definition: X86ISelLowering.h:403
llvm::X86MaskedScatterSDNode::getValue
const SDValue & getValue() const
Definition: X86ISelLowering.h:1732
llvm::X86ISD::FMSUB
@ FMSUB
Definition: X86ISelLowering.h:556
llvm::X86ISD::FRCP
@ FRCP
Definition: X86ISelLowering.h:282
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::X86ISD::MEMBARRIER
@ MEMBARRIER
Definition: X86ISelLowering.h:670
llvm::X86TargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
Definition: X86ISelLowering.cpp:5455
llvm::X86TargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: X86ISelLowering.cpp:53390
llvm::X86ISD::VSRAI
@ VSRAI
Definition: X86ISelLowering.h:367
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::X86ISD::BZHI
@ BZHI
Definition: X86ISelLowering.h:413
llvm::X86ISD::VRANGES
@ VRANGES
Definition: X86ISelLowering.h:490
llvm::X86ISD::CVTTS2SI_SAE
@ CVTTS2SI_SAE
Definition: X86ISelLowering.h:624
llvm::X86MaskedScatterSDNode
Definition: X86ISelLowering.h:1730
llvm::X86::RoundingMode
RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
Definition: X86ISelLowering.h:884
llvm::X86ISD::REP_STOS
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
Definition: X86ISelLowering.h:137
llvm::X86ISD::VAARG_X32
@ VAARG_X32
Definition: X86ISelLowering.h:851
llvm::X86TargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: X86ISelLowering.cpp:2350
llvm::X86ISD::FRSQRT
@ FRSQRT
Floating point reciprocal-sqrt and reciprocal approximation.
Definition: X86ISelLowering.h:281
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::X86ISD::RCP14
@ RCP14
Definition: X86ISelLowering.h:287
llvm::X86ISD::MOVDQ2Q
@ MOVDQ2Q
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
Definition: X86ISelLowering.h:161
llvm::X86ISD::VSRLV
@ VSRLV
Definition: X86ISelLowering.h:361
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::X86TargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: X86ISelLowering.cpp:27504
llvm::X86MaskedGatherSDNode
Definition: X86ISelLowering.h:1721
llvm::X86ISD::VFCMULCSH
@ VFCMULCSH
Definition: X86ISelLowering.h:587
llvm::X86ISD::AND
@ AND
Definition: X86ISelLowering.h:406
llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: X86ISelLowering.cpp:5685
llvm::X86ISD::VFPROUNDS_RND
@ VFPROUNDS_RND
Definition: X86ISelLowering.h:344
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1361
llvm::X86ISD::DBPSADBW
@ DBPSADBW
Compute Double Block Packed Sum-Absolute-Differences.
Definition: X86ISelLowering.h:197
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
llvm::X86TargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: X86ISelLowering.cpp:5446
llvm::X86ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: X86ISelLowering.h:305
llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
Definition: X86ISelLowering.h:1028
llvm::X86ISD::MOVDDUP
@ MOVDDUP
Definition: X86ISelLowering.h:457
llvm::X86ISD::STRICT_CVTSI2P
@ STRICT_CVTSI2P
Definition: X86ISelLowering.h:769
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::X86TargetLowering::IsDesirableToPromoteOp
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: X86ISelLowering.cpp:52907
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::X86ISD::VFIXUPIMM
@ VFIXUPIMM
Definition: X86ISelLowering.h:483
llvm::X86ISD::NT_BRIND
@ NT_BRIND
BRIND node with NoTrack prefix.
Definition: X86ISelLowering.h:127
llvm::X86ISD::VFCMADDCSH_RND
@ VFCMADDCSH_RND
Definition: X86ISelLowering.h:583
llvm::X86ISD::FMINS_SAE
@ FMINS_SAE
Definition: X86ISelLowering.h:231
llvm::X86ISD::TESTUI
@ TESTUI
Definition: X86ISelLowering.h:740
llvm::X86ISD::XTEST
@ XTEST
Definition: X86ISelLowering.h:697
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::X86ISD::VRNDSCALES_SAE
@ VRNDSCALES_SAE
Definition: X86ISelLowering.h:503
llvm::X86TargetLowering::unwrapAddress
SDValue unwrapAddress(SDValue N) const override
Definition: X86ISelLowering.cpp:36060
llvm::X86ISD::EH_RETURN
@ EH_RETURN
Definition: X86ISelLowering.h:302
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::X86TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: X86ISelLowering.h:929
llvm::X86ISD::TLSCALL
@ TLSCALL
Definition: X86ISelLowering.h:299
llvm::X86TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: X86ISelLowering.cpp:32715
llvm::X86TargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: X86ISelLowering.cpp:2634
llvm::X86::rmUpward
@ rmUpward
Definition: X86ISelLowering.h:887
llvm::X86ISD::AESENCWIDE256KL
@ AESENCWIDE256KL
Definition: X86ISelLowering.h:871
llvm::X86ISD::FMULS
@ FMULS
Definition: X86ISelLowering.h:223
llvm::X86ISD::UNPCKH
@ UNPCKH
Definition: X86ISelLowering.h:466
llvm::X86ISD::VGETMANTS
@ VGETMANTS
Definition: X86ISelLowering.h:244
llvm::X86ISD::MCVTP2UI
@ MCVTP2UI
Definition: X86ISelLowering.h:634
llvm::X86ISD::AESENCWIDE128KL
@ AESENCWIDE128KL
Definition: X86ISelLowering.h:869
llvm::X86::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: X86ISelLowering.cpp:5187
llvm::X86ISD::SCALEF
@ SCALEF
Definition: X86ISelLowering.h:247
llvm::X86ISD::MUL_IMM
@ MUL_IMM
Definition: X86ISelLowering.h:420
llvm::ArrayRef< int >
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:155
llvm::X86TargetLowering::isExtractVecEltCheap
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
Definition: X86ISelLowering.h:1336
llvm::X86ISD::PSADBW
@ PSADBW
Compute Sum of Absolute Differences.
Definition: X86ISelLowering.h:195
llvm::X86ISD::KSHIFTR
@ KSHIFTR
Definition: X86ISelLowering.h:371
llvm::X86::rmToNearest
@ rmToNearest
Definition: X86ISelLowering.h:885
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::X86ISD::FP_TO_INT_IN_MEM
@ FP_TO_INT_IN_MEM
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.
Definition: X86ISelLowering.h:821
llvm::X86MaskedGatherSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1725
llvm::X86ISD::FADDS
@ FADDS
Definition: X86ISelLowering.h:217
llvm::X86TargetLowering::getIRStackGuard
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
Definition: X86ISelLowering.cpp:2713
llvm::X86ISD::STRICT_FNMADD
@ STRICT_FNMADD
Definition: X86ISelLowering.h:773
llvm::X86TargetLowering::emitStackGuardXorFP
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override
Definition: X86ISelLowering.cpp:2295
llvm::X86ISD::REP_MOVS
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
Definition: X86ISelLowering.h:140
llvm::X86ISD::VPMADD52L
@ VPMADD52L
Definition: X86ISelLowering.h:544
uint32_t
llvm::X86ISD::FLD
@ FLD
This instruction implements an extending load to FP stack slots.
Definition: X86ISelLowering.h:840
llvm::X86ISD::BLENDI
@ BLENDI
Blend where the selector is an immediate.
Definition: X86ISelLowering.h:203
llvm::X86ISD::VPTERNLOG
@ VPTERNLOG
Definition: X86ISelLowering.h:481
llvm::X86ISD::VGETMANT
@ VGETMANT
Definition: X86ISelLowering.h:242
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86ISD::VFMULC
@ VFMULC
Definition: X86ISelLowering.h:575
llvm::X86MaskedGatherSDNode::getPassThru
const SDValue & getPassThru() const
Definition: X86ISelLowering.h:1723
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::X86ISD::VREDUCE_SAE
@ VREDUCE_SAE
Definition: X86ISelLowering.h:494
llvm::X86TargetLowering::expandIndirectJTBranch
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expanasion.
Definition: X86ISelLowering.cpp:52891
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::X86ISD::FMSUBADD
@ FMSUBADD
Definition: X86ISelLowering.h:559
llvm::X86ISD::XOR
@ XOR
Definition: X86ISelLowering.h:405
llvm::X86ISD::RSQRT14
@ RSQRT14
Definition: X86ISelLowering.h:285
llvm::X86ISD::LCMPXCHG8_DAG
@ LCMPXCHG8_DAG
Definition: X86ISelLowering.h:786
llvm::X86::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: X86FastISel.cpp:4013
llvm::X86ISD::VPCOMU
@ VPCOMU
Definition: X86ISelLowering.h:524
llvm::X86TargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: X86ISelLowering.cpp:2780
llvm::X86TargetLowering::shouldTransformSignedTruncationCheck
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition: X86ISelLowering.h:1063
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::X86::rmTowardZero
@ rmTowardZero
Definition: X86ISelLowering.h:888
llvm::X86ISD::VPDPWSSDS
@ VPDPWSSDS
Definition: X86ISelLowering.h:551
llvm::X86ISD::FCMP
@ FCMP
Definition: X86ISelLowering.h:86
llvm::X86ISD::CVTSI2P
@ CVTSI2P
Definition: X86ISelLowering.h:628
llvm::X86ISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress,...
Definition: X86ISelLowering.h:149
llvm::X86TargetLowering::getByValTypeAlignment
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
Definition: X86ISelLowering.cpp:2482
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:304
llvm::X86ISD::VPERMILPV
@ VPERMILPV
Definition: X86ISelLowering.h:467
llvm::X86TargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: X86ISelLowering.cpp:5551
llvm::X86TargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
Definition: X86ISelLowering.cpp:2502
llvm::X86MaskedGatherScatterSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: X86ISelLowering.h:1710
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86ISD::KTEST
@ KTEST
Definition: X86ISelLowering.h:433
llvm::X86ISD::FHADD
@ FHADD
Floating point horizontal add/sub.
Definition: X86ISelLowering.h:260
llvm::X86ISD::MOVSD
@ MOVSD
Definition: X86ISelLowering.h:462
llvm::X86ISD::VSRL
@ VSRL
Definition: X86ISelLowering.h:356
llvm::X86ISD::VSHLI
@ VSHLI
Definition: X86ISelLowering.h:365
llvm::X86ISD::MMX_MOVW2D
@ MMX_MOVW2D
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.
Definition: X86ISelLowering.h:169
llvm::X86ISD::VTRUNCUS
@ VTRUNCUS
Definition: X86ISelLowering.h:323
llvm::X86ISD::FSQRTS
@ FSQRTS
Definition: X86ISelLowering.h:233
llvm::X86ISD::CVTP2UI
@ CVTP2UI
Definition: X86ISelLowering.h:607
llvm::X86ISD::VPERMV
@ VPERMV
Definition: X86ISelLowering.h:474
llvm::X86ISD::MOVSH
@ MOVSH
Definition: X86ISelLowering.h:464
llvm::X86TargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: X86ISelLowering.cpp:5597
llvm::X86TargetLowering::shouldConvertPhiType
bool shouldConvertPhiType(Type *From, Type *To) const override
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
Definition: X86ISelLowering.cpp:32962
llvm::KnownBits
Definition: KnownBits.h:23
llvm::X86ISD::VBROADCAST
@ VBROADCAST
Definition: X86ISelLowering.h:511
llvm::X86ISD::FSHR
@ FSHR
Definition: X86ISelLowering.h:40
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::X86TargetLowering::getNegatedExpression
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Definition: X86ISelLowering.cpp:48685
llvm::X86MaskedGatherScatterSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1715
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
llvm::X86ISD::VFMADDC_RND
@ VFMADDC_RND
Definition: X86ISelLowering.h:571
llvm::X86ISD::VROTRI
@ VROTRI
Definition: X86ISelLowering.h:375
llvm::X86TargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
Definition: X86ISelLowering.h:1010
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:296
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::X86ISD::VPMADD52H
@ VPMADD52H
Definition: X86ISelLowering.h:545
llvm::X86ISD::KORTEST
@ KORTEST
Definition: X86ISelLowering.h:432
llvm::X86ISD::SCALAR_UINT_TO_FP_RND
@ SCALAR_UINT_TO_FP_RND
Definition: X86ISelLowering.h:603
llvm::X86ISD::SETCC
@ SETCC
X86 SetCC.
Definition: X86ISelLowering.h:95
llvm::X86ISD::RSQRT28S_SAE
@ RSQRT28S_SAE
Definition: X86ISelLowering.h:703
llvm::X86ISD::AESDECWIDE256KL
@ AESDECWIDE256KL
Definition: X86ISelLowering.h:872
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4164
llvm::X86TargetLowering::getTargetConstantFromLoad
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
Definition: X86ISelLowering.cpp:6738
llvm::X86ISD::VZEXT_MOVL
@ VZEXT_MOVL
Definition: X86ISelLowering.h:318
llvm::X86ISD::FSUBS
@ FSUBS
Definition: X86ISelLowering.h:220
llvm::X86ISD::VMTRUNCS
@ VMTRUNCS
Definition: X86ISelLowering.h:332
llvm::X86ISD::FAND
@ FAND
Bitwise logical AND of floating point values.
Definition: X86ISelLowering.h:44
llvm::X86ISD::PCMPEQ
@ PCMPEQ
Definition: X86ISelLowering.h:381
llvm::X86ISD::FMIN
@ FMIN
Definition: X86ISelLowering.h:268
llvm::X86ISD::FMULS_RND
@ FMULS_RND
Definition: X86ISelLowering.h:224
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::X86TargetLowering::hasFastEqualityCompare
MVT hasFastEqualityCompare(unsigned NumBits) const override
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
Definition: X86ISelLowering.cpp:5753
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::X86ISD::RET_FLAG
@ RET_FLAG
Return with a flag operand.
Definition: X86ISelLowering.h:131
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::X86ISD::VGETMANT_SAE
@ VGETMANT_SAE
Definition: X86ISelLowering.h:243
llvm::X86ISD::HADD
@ HADD
Integer horizontal add/sub.
Definition: X86ISelLowering.h:256
llvm::X86ISD::LSUB
@ LSUB
Definition: X86ISelLowering.h:793
llvm::X86ISD::FDIV_RND
@ FDIV_RND
Definition: X86ISelLowering.h:225
llvm::X86ISD::CMPMM_SAE
@ CMPMM_SAE
Definition: X86ISelLowering.h:395
llvm::X86TargetLowering::isBinOp
bool isBinOp(unsigned Opcode) const override
Add x86-specific opcodes to the default list.
Definition: X86ISelLowering.cpp:32795
llvm::X86ISD::VFPEXT_SAE
@ VFPEXT_SAE
Definition: X86ISelLowering.h:336
llvm::X86ISD::VMFPROUND
@ VMFPROUND
Definition: X86ISelLowering.h:348
llvm::X86ISD::STRICT_CVTTP2SI
@ STRICT_CVTTP2SI
Definition: X86ISelLowering.h:754
llvm::X86ISD::VPDPBUSD
@ VPDPBUSD
Definition: X86ISelLowering.h:548
llvm::X86ISD::FSQRT_RND
@ FSQRT_RND
Definition: X86ISelLowering.h:232
llvm::X86ISD::FNMADD_RND
@ FNMADD_RND
Definition: X86ISelLowering.h:563
llvm::X86ISD::MOVMSK
@ MOVMSK
Definition: X86ISelLowering.h:423
llvm::X86ISD::VP2INTERSECT
@ VP2INTERSECT
Definition: X86ISelLowering.h:737
llvm::X86ISD::TESTP
@ TESTP
Definition: X86ISelLowering.h:429
llvm::X86ISD::RDPKRU
@ RDPKRU
Definition: X86ISelLowering.h:684
llvm::X86TargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: X86ISelLowering.cpp:5680
llvm::X86ISD::AVG
@ AVG
Definition: X86ISelLowering.h:253
llvm::X86TargetLowering::isCommutativeBinOp
bool isCommutativeBinOp(unsigned Opcode) const override
Returns true if the opcode is a commutative binary operation.
Definition: X86ISelLowering.cpp:32810
llvm::X86ISD::CVTP2SI
@ CVTP2SI
Definition: X86ISelLowering.h:606
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2009
llvm::X86TargetLowering::BuildFILD
std::pair< SDValue, SDValue > BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:20543
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::X86TargetLowering::shouldSplatInsEltVarIndex
bool shouldSplatInsEltVarIndex(EVT VT) const override
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
Definition: X86ISelLowering.cpp:5747
llvm::X86TargetLowering::isLegalStoreImmediate
bool isLegalStoreImmediate(int64_t Imm) const override
Return true if the specified immediate is legal for the value input of a store instruction.
Definition: X86ISelLowering.cpp:32859
llvm::X86ISD::SHUFP
@ SHUFP
Definition: X86ISelLowering.h:449
llvm::X86ISD::SCALAR_SINT_TO_FP_RND
@ SCALAR_SINT_TO_FP_RND
Definition: X86ISelLowering.h:602
llvm::X86ISD::MULTISHIFT
@ MULTISHIFT
Definition: X86ISelLowering.h:387
llvm::X86TargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: X86ISelLowering.cpp:5510
llvm::X86ISD::VPSHL
@ VPSHL
Definition: X86ISelLowering.h:521
llvm::X86ISD::ADDSUB
@ ADDSUB
Combined add and sub on an FP vector.
Definition: X86ISelLowering.h:213
llvm::X86TargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: X86ISelLowering.cpp:2743
llvm::X86ISD::VALIGN
@ VALIGN
Definition: X86ISelLowering.h:445
llvm::X86ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: X86ISelLowering.h:28
llvm::X86TargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: X86ISelLowering.cpp:5663
llvm::X86ISD::SINT_TO_FP_RND
@ SINT_TO_FP_RND
Definition: X86ISelLowering.h:598
llvm::X86TargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: X86ISelLowering.cpp:5592
llvm::X86TargetLowering::isSafeMemOpType
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
Definition: X86ISelLowering.cpp:2548
llvm::X86TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: X86ISelLowering.cpp:32850
llvm::X86ISD::CONFLICT
@ CONFLICT
Definition: X86ISelLowering.h:264
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:54
llvm::X86ISD::VFMULC_RND
@ VFMULC_RND
Definition: X86ISelLowering.h:576
llvm::X86ISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: X86ISelLowering.h:667
N
#define N
llvm::X86ISD::FLDCW16m
@ FLDCW16m
Definition: X86ISelLowering.h:814
llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: X86ISelLowering.cpp:2396
llvm::X86ISD::VREDUCES_SAE
@ VREDUCES_SAE
Definition: X86ISelLowering.h:496
llvm::X86ISD::VSHL
@ VSHL
Definition: X86ISelLowering.h:355
llvm::X86TargetLowering::getStackProbeSymbolName
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Definition: X86ISelLowering.cpp:54109
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4256
llvm::X86ISD::BEXTR
@ BEXTR
Definition: X86ISelLowering.h:409
llvm::X86ISD::AESDECWIDE128KL
@ AESDECWIDE128KL
Definition: X86ISelLowering.h:870
llvm::X86ISD::CVTPH2PS_SAE
@ CVTPH2PS_SAE
Definition: X86ISelLowering.h:714
llvm::X86ISD::PCMPISTR
@ PCMPISTR
Definition: X86ISelLowering.h:693
llvm::X86ISD::LCMPXCHG16_SAVE_RBX_DAG
@ LCMPXCHG16_SAVE_RBX_DAG
Definition: X86ISelLowering.h:788
llvm::X86ISD::CVTPS2PH
@ CVTPS2PH
Definition: X86ISelLowering.h:712
llvm::X86ISD::CMP
@ CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:85
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::X86ISD::FNSTCW16m
@ FNSTCW16m
Definition: X86ISelLowering.h:811
llvm::X86ISD::VMTRUNCSTORES
@ VMTRUNCSTORES
Definition: X86ISelLowering.h:858
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::X86TargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating exp...
Definition: X86ISelLowering.cpp:5584
RegName
#define RegName(no)
llvm::X86ISD::FANDN
@ FANDN
Bitwise logical ANDNOT of floating point values.
Definition: X86ISelLowering.h:56
llvm::X86ISD::CVTTS2SI
@ CVTTS2SI
Definition: X86ISelLowering.h:622
llvm::X86ISD::FSUB_RND
@ FSUB_RND
Definition: X86ISelLowering.h:219
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86ISD::CVTTP2SI
@ CVTTP2SI
Definition: X86ISelLowering.h:617
llvm::X86ISD::ADC
@ ADC
Definition: X86ISelLowering.h:400
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:491
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::X86ISD::VROTLI
@ VROTLI
Definition: X86ISelLowering.h:374
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::X86TargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: X86ISelLowering.cpp:5739
llvm::X86TargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: X86ISelLowering.h:1410
llvm::X86ISD::PCMPGT
@ PCMPGT
Definition: X86ISelLowering.h:382
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::X86ISD::FMSUB_RND
@ FMSUB_RND
Definition: X86ISelLowering.h:564
llvm::X86ISD::LXOR
@ LXOR
Definition: X86ISelLowering.h:795
llvm::X86TargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition: X86ISelLowering.cpp:5033
llvm::X86ISD::VFIXUPIMMS_SAE
@ VFIXUPIMMS_SAE
Definition: X86ISelLowering.h:486
llvm::X86ISD::FMAX_SAE
@ FMAX_SAE
Definition: X86ISelLowering.h:228
llvm::X86ISD::PTEST
@ PTEST
Definition: X86ISelLowering.h:426
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::X86ISD::OR
@ OR
Definition: X86ISelLowering.h:404
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::X86ISD::WrapperRIP
@ WrapperRIP
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
Definition: X86ISelLowering.h:153
llvm::X86ISD::VFMADDCSH
@ VFMADDCSH
Definition: X86ISelLowering.h:580
llvm::X86TargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: X86ISelLowering.cpp:54020
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::X86ISD::FIST
@ FIST
This instruction implements a fp->int store from FP stack slots.
Definition: X86ISelLowering.h:834
llvm::X86ISD::VFMADDC
@ VFMADDC
Definition: X86ISelLowering.h:570
llvm::X86TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: X86ISelLowering.cpp:54081
llvm::X86TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Definition: X86ISelLowering.cpp:2424
llvm::X86::rmDownward
@ rmDownward
Definition: X86ISelLowering.h:886
MachineFunction.h
llvm::X86ISD::EXP2_SAE
@ EXP2_SAE
Definition: X86ISelLowering.h:709
llvm::X86ISD::UCOMI
@ UCOMI
Definition: X86ISelLowering.h:88
llvm::X86ISD::VFMULCSH
@ VFMULCSH
Definition: X86ISelLowering.h:585
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::X86ISD::FGETEXPS
@ FGETEXPS
Definition: X86ISelLowering.h:239
llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const override
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
Definition: X86ISelLowering.cpp:40727
llvm::X86TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: X86ISelLowering.cpp:52662
llvm::X86ISD::MCVTUI2P
@ MCVTUI2P
Definition: X86ISelLowering.h:638
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::X86TargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower interleaved store(s) into target specific instructions/intrinsics.
Definition: X86InterleavedAccess.cpp:827
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: X86ISelLowering.cpp:35909
llvm::X86ISD::VPCOM
@ VPCOM
Definition: X86ISelLowering.h:523
llvm::X86ISD::PINSRB
@ PINSRB
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
Definition: X86ISelLowering.h:185
llvm::X86ISD::STRICT_FCMP
@ STRICT_FCMP
X86 strict FP compare instructions.
Definition: X86ISelLowering.h:743
llvm::X86ISD::TLSBASEADDR
@ TLSBASEADDR
Definition: X86ISelLowering.h:295
llvm::X86ISD::VRANGE_SAE
@ VRANGE_SAE
Definition: X86ISelLowering.h:489
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:140
llvm::X86ISD::PMULUDQ
@ PMULUDQ
Definition: X86ISelLowering.h:531
llvm::X86ISD::AESENC128KL
@ AESENC128KL
Definition: X86ISelLowering.h:865
llvm::X86ISD::MMX_MOVD2W
@ MMX_MOVD2W
Copies a 32-bit value from the low word of a MMX vector to a GPR.
Definition: X86ISelLowering.h:165
llvm::X86ISD::STRICT_CVTPS2PH
@ STRICT_CVTPS2PH
Definition: X86ISelLowering.h:778
llvm::X86ISD::VSHRD
@ VSHRD
Definition: X86ISelLowering.h:452
llvm::X86TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: X86ISelLowering.cpp:32828
llvm::X86ISD::TC_RETURN
@ TC_RETURN
Tail call return.
Definition: X86ISelLowering.h:315
llvm::X86ISD::VFCMADDCSH
@ VFCMADDCSH
Definition: X86ISelLowering.h:582
llvm::X86MaskedScatterSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1734
llvm::X86TargetLowering::isNarrowingProfitable
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
Definition: X86ISelLowering.cpp:33004
llvm::X86ISD::RCP28S
@ RCP28S
Definition: X86ISelLowering.h:706
llvm::X86ISD::NodeType
NodeType
Definition: X86ISelLowering.h:26
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1158
llvm::X86ISD::STRICT_CVTTP2UI
@ STRICT_CVTTP2UI
Definition: X86ISelLowering.h:755
llvm::X86ISD::VMTRUNC
@ VMTRUNC
Definition: X86ISelLowering.h:330
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::X86TargetLowering::reduceSelectOfFPConstantLoads
bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
Definition: X86ISelLowering.cpp:5501