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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 
18 
19 namespace llvm {
20  class X86Subtarget;
21  class X86TargetMachine;
22 
23  namespace X86ISD {
24  // X86 Specific DAG Nodes
25  enum NodeType : unsigned {
26  // Start the numbering where the builtin ops leave off.
28 
29  /// Bit scan forward.
30  BSF,
31  /// Bit scan reverse.
32  BSR,
33 
34  /// X86 funnel/double shift i16 instructions. These correspond to
35  /// X86::SHLDW and X86::SHRDW instructions which have different amt
36  /// modulo rules to generic funnel shifts.
37  /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.
40 
41  /// Bitwise logical AND of floating point values. This corresponds
42  /// to X86::ANDPS or X86::ANDPD.
44 
45  /// Bitwise logical OR of floating point values. This corresponds
46  /// to X86::ORPS or X86::ORPD.
47  FOR,
48 
49  /// Bitwise logical XOR of floating point values. This corresponds
50  /// to X86::XORPS or X86::XORPD.
52 
53  /// Bitwise logical ANDNOT of floating point values. This
54  /// corresponds to X86::ANDNPS or X86::ANDNPD.
56 
57  /// These operations represent an abstract X86 call
58  /// instruction, which includes a bunch of information. In particular the
59  /// operands of these node are:
60  ///
61  /// #0 - The incoming token chain
62  /// #1 - The callee
63  /// #2 - The number of arg bytes the caller pushes on the stack.
64  /// #3 - The number of arg bytes the callee pops off the stack.
65  /// #4 - The value to pass in AL/AX/EAX (optional)
66  /// #5 - The value to pass in DL/DX/EDX (optional)
67  ///
68  /// The result values of these nodes are:
69  ///
70  /// #0 - The outgoing token chain
71  /// #1 - The first register result value (optional)
72  /// #2 - The second register result value (optional)
73  ///
75 
76  /// Same as call except it adds the NoTrack prefix.
78 
79  // Pseudo for a OBJC call that gets emitted together with a special
80  // marker instruction.
82 
83  /// X86 compare and logical compare instructions.
84  CMP,
88 
89  /// X86 bit-test instructions.
90  BT,
91 
92  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
93  /// operand, usually produced by a CMP instruction.
95 
96  /// X86 Select
98 
99  // Same as SETCC except it's materialized with a sbb and the value is all
100  // one's or all zero's.
101  SETCC_CARRY, // R = carry_bit ? ~0 : 0
102 
103  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
104  /// Operands are two FP values to compare; result is a mask of
105  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
107 
108  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
109  /// and a version with SAE.
112 
113  /// X86 conditional moves. Operand 0 and operand 1 are the two values
114  /// to select from. Operand 2 is the condition code, and operand 3 is the
115  /// flag operand produced by a CMP or TEST instruction.
117 
118  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
119  /// is the block to branch if condition is true, operand 2 is the
120  /// condition code, and operand 3 is the flag operand produced by a CMP
121  /// or TEST instruction.
123 
124  /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
125  /// operand 1 is the target address.
127 
128  /// Return with a flag operand. Operand 0 is the chain operand, operand
129  /// 1 is the number of bytes of stack to pop.
131 
132  /// Return from interrupt. Operand 0 is the number of bytes to pop.
134 
135  /// Repeat fill, corresponds to X86::REP_STOSx.
137 
138  /// Repeat move, corresponds to X86::REP_MOVSx.
140 
141  /// On Darwin, this node represents the result of the popl
142  /// at function entry, used for PIC code.
144 
145  /// A wrapper node for TargetConstantPool, TargetJumpTable,
146  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
147  /// MCSymbol and TargetBlockAddress.
149 
150  /// Special wrapper used under X86-64 PIC mode for RIP
151  /// relative displacements.
153 
154  /// Copies a 64-bit value from an MMX vector to the low word
155  /// of an XMM vector, with the high word zero filled.
157 
158  /// Copies a 64-bit value from the low word of an XMM vector
159  /// to an MMX vector.
161 
162  /// Copies a 32-bit value from the low word of a MMX
163  /// vector to a GPR.
165 
166  /// Copies a GPR into the low 32-bit word of a MMX vector
167  /// and zero out the high word.
169 
170  /// Extract an 8-bit value from a vector and zero extend it to
171  /// i32, corresponds to X86::PEXTRB.
173 
174  /// Extract a 16-bit value from a vector and zero extend it to
175  /// i32, corresponds to X86::PEXTRW.
177 
178  /// Insert any element of a 4 x float vector into any element
179  /// of a destination 4 x floatvector.
181 
182  /// Insert the lower 8-bits of a 32-bit value to a vector,
183  /// corresponds to X86::PINSRB.
185 
186  /// Insert the lower 16-bits of a 32-bit value to a vector,
187  /// corresponds to X86::PINSRW.
189 
190  /// Shuffle 16 8-bit values within a vector.
192 
193  /// Compute Sum of Absolute Differences.
195  /// Compute Double Block Packed Sum-Absolute-Differences
197 
198  /// Bitwise Logical AND NOT of Packed FP values.
200 
201  /// Blend where the selector is an immediate.
203 
204  /// Dynamic (non-constant condition) vector blend where only the sign bits
205  /// of the condition elements are used. This is used to enforce that the
206  /// condition mask is not valid for generic VSELECT optimizations. This
207  /// is also used to implement the intrinsics.
208  /// Operands are in VSELECT order: MASK, TRUE, FALSE
210 
211  /// Combined add and sub on an FP vector.
213 
214  // FP vector ops with rounding mode.
234 
235  // FP vector get exponent.
240  // Extract Normalized Mantissas.
245  // FP Scale.
250 
251  // Unsigned Integer average.
253 
254  /// Integer horizontal add/sub.
257 
258  /// Floating point horizontal add/sub.
261 
262  // Detect Conflicts Within a Vector
264 
265  /// Floating point max and min.
268 
269  /// Commutative FMIN and FMAX.
272 
273  /// Scalar intrinsic floating point max and min.
276 
277  /// Floating point reciprocal-sqrt and reciprocal approximation.
278  /// Note that these typically require refinement
279  /// in order to obtain suitable precision.
282 
283  // AVX-512 reciprocal approximations with a little more precision.
288 
289  // Thread Local Storage.
291 
292  // Thread Local Storage. A call to get the start address
293  // of the TLS block for the current module.
295 
296  // Thread Local Storage. When calling to an OS provided
297  // thunk at the address from an earlier relocation.
299 
300  // Exception Handling helpers.
302 
303  // SjLj exception handling setjmp.
305 
306  // SjLj exception handling longjmp.
308 
309  // SjLj exception handling dispatch.
311 
312  /// Tail call return. See X86TargetLowering::LowerCall for
313  /// the list of operands.
315 
316  // Vector move to low scalar and zero higher vector elements.
318 
319  // Vector integer truncate.
321  // Vector integer truncate with unsigned/signed saturation.
324 
325  // Masked version of the above. Used when less than a 128-bit result is
326  // produced since the mask only applies to the lower elements and can't
327  // be represented by a select.
328  // SRC, PASSTHRU, MASK
332 
333  // Vector FP extend.
338 
339  // Vector FP round.
344 
345  // Masked version of above. Used for v2f64->v4f32.
346  // SRC, PASSTHRU, MASK
348 
349  // 128-bit vector logical left / right shift
352 
353  // Vector shift elements
357 
358  // Vector variable shift
362 
363  // Vector shift elements by immediate
367 
368  // Shifts of mask registers.
371 
372  // Bit rotate by immediate
375 
376  // Vector packed double/float comparison.
378 
379  // Vector integer comparisons.
382 
383  // v8i16 Horizontal minimum and position.
385 
387 
388  /// Vector comparison generating mask bits for fp and
389  /// integer signed and unsigned data types.
391  // Vector mask comparison generating mask bits for FP values.
393  // Vector mask comparison with SAE for FP values.
395 
396  // Arithmetic operations with FLAGS results.
403  OR,
406 
407  // Bit field extract.
410 
411  // Zero High Bits Starting with Specified Bit Position.
413 
414  // Parallel extract and deposit.
417 
418  // X86-specific multiply by immediate.
420 
421  // Vector sign bit extraction.
423 
424  // Vector bitwise comparisons.
426 
427  // Vector packed fp sign bitwise comparisons.
429 
430  // OR/AND test for masks.
433 
434  // ADD for masks.
436 
437  // Several flavors of instructions with vector shuffle behaviors.
438  // Saturated signed/unnsigned packing.
441  // Intra-lane alignr.
443  // AVX512 inter-lane alignr.
449  // VBMI2 Concat & Shift.
454  // Shuffle Packed Values at 128-bit granularity.
469 
470  // Variable Permute (VPERM).
471  // Res = VPERMV MaskV, V0
473 
474  // 3-op Variable Permute (VPERMT2).
475  // Res = VPERMV3 V0, MaskV, V1
477 
478  // Bitwise ternary logic.
480  // Fix Up Special Packed Float32/64 values.
485  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
490  // Reduce - Perform Reduction Transformation on scalar\packed FP.
495  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
496  // Also used by the legacy (V)ROUND intrinsics where we mask out the
497  // scaling part of the immediate.
502  // Tests Types Of a FP Values for packed types.
504  // Tests Types Of a FP Values for scalar types.
506 
507  // Broadcast (splat) scalar or element 0 of a vector. If the operand is
508  // a vector, this node may change the vector length as part of the splat.
510  // Broadcast mask to vector.
512 
513  /// SSE4A Extraction and Insertion.
516 
517  // XOP arithmetic/logical shifts.
520  // XOP signed/unsigned integer comparisons.
523  // XOP packed permute bytes.
525  // XOP two source permutation.
527 
528  // Vector multiply packed unsigned doubleword integers.
530  // Vector multiply packed signed doubleword integers.
532  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
534 
535  // Multiply and Add Packed Integers.
538 
539  // AVX512IFMA multiply and add.
540  // NOTE: These are different than the instruction and perform
541  // op0 x op1 + op2.
544 
545  // VNNI
550 
551  // FMA nodes.
552  // We use the target independent ISD::FMA for the non-inverted case.
558 
559  // FMA with rounding mode.
566 
567  // Compress and expand.
570 
571  // Bits shuffle
573 
574  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
581 
582  // Vector float/double to signed/unsigned integer.
587  // Scalar float/double to signed/unsigned integer.
592 
593  // Vector float/double to signed/unsigned integer with truncation.
598  // Scalar float/double to signed/unsigned integer with truncation.
603 
604  // Vector signed/unsigned integer to float/double.
607 
608  // Masked versions of above. Used for v2f64->v4f32.
609  // SRC, PASSTHRU, MASK
616 
617  // Vector float to bfloat16.
618  // Convert TWO packed single data to one packed BF16 data
620  // Convert packed single data to packed BF16 data
622  // Masked version of above.
623  // SRC, PASSTHRU, MASK
625 
626  // Dot product of BF16 pairs to accumulated into
627  // packed single precision.
629 
630  // Save xmm argument registers to the stack, according to %al. An operator
631  // is needed so that this can be expanded with control flow.
633 
634  // Windows's _chkstk call to do stack probing.
636 
637  // For allocating variable amounts of stack space when using
638  // segmented stacks. Check if the current stacklet has enough space, and
639  // falls back to heap allocation if not.
641 
642  // For allocating stack space when using stack clash protector.
643  // Allocation is performed by block, and each block is probed.
645 
646  // Memory barriers.
649 
650  // Get a random integer and indicate whether it is valid in CF.
652 
653  // Get a NIST SP800-90B & C compliant random integer and
654  // indicate whether it is valid in CF.
656 
657  // Protection keys
658  // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
659  // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
660  // value for ECX.
663 
664  // SSE42 string comparisons.
665  // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
666  // will emit one or two instructions based on which results are used. If
667  // flags and index/mask this allows us to use a single instruction since
668  // we won't have to pick and opcode for flags. Instead we can rely on the
669  // DAG to CSE everything and decide at isel.
672 
673  // Test if in transactional execution.
675 
676  // ERI instructions.
687 
688  // Conversions between float and half-float.
692 
693  // Masked version of above.
694  // SRC, RND, PASSTHRU, MASK
696 
697  // Galois Field Arithmetic Instructions
701 
702  // LWP insert record.
704 
705  // User level wait
708 
709  // Enqueue Stores Instructions
712 
713  // For avx512-vp2intersect
715 
716  // User level interrupts - testui
718 
719  /// X86 strict FP compare instructions.
722 
723  // Vector packed double/float comparison.
725 
726  /// Vector comparison generating mask bits for fp and
727  /// integer signed and unsigned data types.
729 
730  // Vector float/double to signed/unsigned integer with truncation.
733 
734  // Vector FP extend.
736 
737  // Vector FP round.
739 
740  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
741  // Also used by the legacy (V)ROUND intrinsics where we mask out the
742  // scaling part of the immediate.
744 
745  // Vector signed/unsigned integer to float/double.
748 
749  // Strict FMA nodes.
753 
754  // Conversions between float and half-float.
757 
758  // WARNING: Only add nodes here if they are stric FP nodes. Non-memory and
759  // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE.
760 
761  // Compare and swap.
766 
767  /// LOCK-prefixed arithmetic read-modify-write instructions.
768  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
774 
775  // Load, scalar_to_vector, and zero extend.
777 
778  // extract_vector_elt, store.
780 
781  // scalar broadcast from memory.
783 
784  // subvector broadcast from memory.
786 
787  // Store FP control word into i16 memory.
789 
790  // Load FP control word from i16 memory.
792 
793  /// This instruction implements FP_TO_SINT with the
794  /// integer destination in memory and a FP reg source. This corresponds
795  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
796  /// has two inputs (token chain and address) and two outputs (int value
797  /// and token chain). Memory VT specifies the type to store to.
799 
800  /// This instruction implements SINT_TO_FP with the
801  /// integer source in memory and FP reg result. This corresponds to the
802  /// X86::FILD*m instructions. It has two inputs (token chain and address)
803  /// and two outputs (FP value and token chain). The integer source type is
804  /// specified by the memory VT.
806 
807  /// This instruction implements a fp->int store from FP stack
808  /// slots. This corresponds to the fist instruction. It takes a
809  /// chain operand, value to store, address, and glue. The memory VT
810  /// specifies the type to store as.
812 
813  /// This instruction implements an extending load to FP stack slots.
814  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
815  /// operand, and ptr to load from. The memory VT specifies the type to
816  /// load from.
818 
819  /// This instruction implements a truncating store from FP stack
820  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
821  /// chain operand, value to store, address, and glue. The memory VT
822  /// specifies the type to store as.
824 
825  /// These instructions grab the address of the next argument
826  /// from a va_list. (reads and modifies the va_list in memory)
829 
830  // Vector truncating store with unsigned/signed saturation
833  // Vector truncating masked store with unsigned/signed saturation
836 
837  // X86 specific gather and scatter
840 
841  // Key locker nodes that produce flags.
850 
851  // WARNING: Do not add anything in the end unless you want the node to
852  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
853  // opcodes will be thought as target memory ops!
854  };
855  } // end namespace X86ISD
856 
857  namespace X86 {
858  /// Current rounding mode is represented in bits 11:10 of FPSR. These
859  /// values are same as corresponding constants for rounding mode used
860  /// in glibc.
862  rmToNearest = 0, // FE_TONEAREST
863  rmDownward = 1 << 10, // FE_DOWNWARD
864  rmUpward = 2 << 10, // FE_UPWARD
865  rmTowardZero = 3 << 10, // FE_TOWARDZERO
866  rmMask = 3 << 10 // Bit mask selecting rounding mode
867  };
868  }
869 
870  /// Define some predicates that are used for node matching.
871  namespace X86 {
872  /// Returns true if Elt is a constant zero or floating point constant +0.0.
873  bool isZeroNode(SDValue Elt);
874 
875  /// Returns true of the given offset can be
876  /// fit into displacement field of the instruction.
878  bool hasSymbolicDisplacement);
879 
880  /// Determines whether the callee is required to pop its
881  /// own arguments. Callee pop is necessary to support tail calls.
883  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
884 
885  /// If Op is a constant whose elements are all the same constant or
886  /// undefined, return true and return the constant value in \p SplatVal.
887  /// If we have undef bits that don't cover an entire element, we treat these
888  /// as zero if AllowPartialUndefs is set, else we fail and return false.
889  bool isConstantSplat(SDValue Op, APInt &SplatVal,
890  bool AllowPartialUndefs = true);
891  } // end namespace X86
892 
893  //===--------------------------------------------------------------------===//
894  // X86 Implementation of the TargetLowering interface
895  class X86TargetLowering final : public TargetLowering {
896  public:
897  explicit X86TargetLowering(const X86TargetMachine &TM,
898  const X86Subtarget &STI);
899 
900  unsigned getJumpTableEncoding() const override;
901  bool useSoftFloat() const override;
902 
903  void markLibCallAttributes(MachineFunction *MF, unsigned CC,
904  ArgListTy &Args) const override;
905 
906  MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
907  return MVT::i8;
908  }
909 
910  const MCExpr *
912  const MachineBasicBlock *MBB, unsigned uid,
913  MCContext &Ctx) const override;
914 
915  /// Returns relocation base for the given PIC jumptable.
917  SelectionDAG &DAG) const override;
918  const MCExpr *
920  unsigned JTI, MCContext &Ctx) const override;
921 
922  /// Return the desired alignment for ByVal aggregate
923  /// function arguments in the caller parameter area. For X86, aggregates
924  /// that contains are placed at 16-byte boundaries while the rest are at
925  /// 4-byte boundaries.
926  unsigned getByValTypeAlignment(Type *Ty,
927  const DataLayout &DL) const override;
928 
930  const AttributeList &FuncAttributes) const override;
931 
932  /// Returns true if it's safe to use load / store of the
933  /// specified type to expand memcpy / memset inline. This is mostly true
934  /// for all types except for some special cases. For example, on X86
935  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
936  /// also does type conversion. Note the specified type doesn't have to be
937  /// legal as the hook is used before type legalization.
938  bool isSafeMemOpType(MVT VT) const override;
939 
940  /// Returns true if the target allows unaligned memory accesses of the
941  /// specified type. Returns whether it is "fast" in the last argument.
942  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
944  bool *Fast) const override;
945 
946  /// Provide custom lowering hooks for some operations.
947  ///
948  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
949 
950  /// Replace the results of node with an illegal result
951  /// type with new values built out of custom code.
952  ///
954  SelectionDAG &DAG) const override;
955 
956  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
957 
958  /// Return true if the target has native support for
959  /// the specified value type and it is 'desirable' to use the type for the
960  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
961  /// instruction encodings are longer and some i16 instructions are slow.
962  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
963 
964  /// Return true if the target has native support for the
965  /// specified value type and it is 'desirable' to use the type. e.g. On x86
966  /// i16 is legal, but undesirable since i16 instruction encodings are longer
967  /// and some i16 instructions are slow.
968  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
969 
970  /// Return the newly negated expression if the cost is not expensive and
971  /// set the cost in \p Cost to indicate that if it is cheaper or neutral to
972  /// do the negation.
974  bool LegalOperations, bool ForCodeSize,
975  NegatibleCost &Cost,
976  unsigned Depth) const override;
977 
980  MachineBasicBlock *MBB) const override;
981 
982  /// This method returns the name of a target specific DAG node.
983  const char *getTargetNodeName(unsigned Opcode) const override;
984 
985  /// Do not merge vector stores after legalization because that may conflict
986  /// with x86-specific store splitting optimizations.
987  bool mergeStoresAfterLegalization(EVT MemVT) const override {
988  return !MemVT.isVector();
989  }
990 
991  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
992  const SelectionDAG &DAG) const override;
993 
994  bool isCheapToSpeculateCttz() const override;
995 
996  bool isCheapToSpeculateCtlz() const override;
997 
998  bool isCtlzFast() const override;
999 
1000  bool hasBitPreservingFPLogic(EVT VT) const override {
1001  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
1002  }
1003 
1004  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
1005  // If the pair to store is a mixture of float and int values, we will
1006  // save two bitwise instructions and one float-to-int instruction and
1007  // increase one store instruction. There is potentially a more
1008  // significant benefit because it avoids the float->int domain switch
1009  // for input value. So It is more likely a win.
1010  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
1011  (LTy.isInteger() && HTy.isFloatingPoint()))
1012  return true;
1013  // If the pair only contains int values, we will save two bitwise
1014  // instructions and increase one store instruction (costing one more
1015  // store buffer). Since the benefit is more blurred so we leave
1016  // such pair out until we get testcase to prove it is a win.
1017  return false;
1018  }
1019 
1020  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1021 
1022  bool hasAndNotCompare(SDValue Y) const override;
1023 
1024  bool hasAndNot(SDValue Y) const override;
1025 
1026  bool hasBitTest(SDValue X, SDValue Y) const override;
1027 
1030  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
1031  SelectionDAG &DAG) const override;
1032 
1034  CombineLevel Level) const override;
1035 
1036  bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
1037 
1038  bool
1040  unsigned KeptBits) const override {
1041  // For vectors, we don't have a preference..
1042  if (XVT.isVector())
1043  return false;
1044 
1045  auto VTIsOk = [](EVT VT) -> bool {
1046  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
1047  VT == MVT::i64;
1048  };
1049 
1050  // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
1051  // XVT will be larger than KeptBitsVT.
1052  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
1053  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
1054  }
1055 
1056  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
1057 
1058  bool shouldSplatInsEltVarIndex(EVT VT) const override;
1059 
1060  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
1061  return VT.isScalarInteger();
1062  }
1063 
1064  /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
1065  MVT hasFastEqualityCompare(unsigned NumBits) const override;
1066 
1067  /// Return the value type to use for ISD::SETCC.
1069  EVT VT) const override;
1070 
1072  const APInt &DemandedElts,
1073  TargetLoweringOpt &TLO) const override;
1074 
1075  /// Determine which of the bits specified in Mask are known to be either
1076  /// zero or one and return them in the KnownZero/KnownOne bitsets.
1078  KnownBits &Known,
1079  const APInt &DemandedElts,
1080  const SelectionDAG &DAG,
1081  unsigned Depth = 0) const override;
1082 
1083  /// Determine the number of bits in the operation that are sign bits.
1085  const APInt &DemandedElts,
1086  const SelectionDAG &DAG,
1087  unsigned Depth) const override;
1088 
1090  const APInt &DemandedElts,
1091  APInt &KnownUndef,
1092  APInt &KnownZero,
1093  TargetLoweringOpt &TLO,
1094  unsigned Depth) const override;
1095 
1097  const APInt &DemandedElts,
1098  unsigned MaskIndex,
1099  TargetLoweringOpt &TLO,
1100  unsigned Depth) const;
1101 
1103  const APInt &DemandedBits,
1104  const APInt &DemandedElts,
1105  KnownBits &Known,
1106  TargetLoweringOpt &TLO,
1107  unsigned Depth) const override;
1108 
1110  SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1111  SelectionDAG &DAG, unsigned Depth) const override;
1112 
1113  const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
1114 
1115  SDValue unwrapAddress(SDValue N) const override;
1116 
1118 
1119  bool ExpandInlineAsm(CallInst *CI) const override;
1120 
1121  ConstraintType getConstraintType(StringRef Constraint) const override;
1122 
1123  /// Examine constraint string and operand type and determine a weight value.
1124  /// The operand object must already have been set up with the operand type.
1126  getSingleConstraintMatchWeight(AsmOperandInfo &info,
1127  const char *constraint) const override;
1128 
1129  const char *LowerXConstraint(EVT ConstraintVT) const override;
1130 
1131  /// Lower the specified operand into the Ops vector. If it is invalid, don't
1132  /// add anything to Ops. If hasMemory is true it means one of the asm
1133  /// constraint of the inline asm instruction being processed is 'm'.
1135  std::string &Constraint,
1136  std::vector<SDValue> &Ops,
1137  SelectionDAG &DAG) const override;
1138 
1139  unsigned
1140  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1141  if (ConstraintCode == "v")
1142  return InlineAsm::Constraint_v;
1143  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1144  }
1145 
1146  /// Handle Lowering flag assembly outputs.
1148  const SDLoc &DL,
1149  const AsmOperandInfo &Constraint,
1150  SelectionDAG &DAG) const override;
1151 
1152  /// Given a physical register constraint
1153  /// (e.g. {edx}), return the register number and the register class for the
1154  /// register. This should only be used for C_Register constraints. On
1155  /// error, this returns a register number of 0.
1156  std::pair<unsigned, const TargetRegisterClass *>
1158  StringRef Constraint, MVT VT) const override;
1159 
1160  /// Return true if the addressing mode represented
1161  /// by AM is legal for this target, for a load/store of the specified type.
1162  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1163  Type *Ty, unsigned AS,
1164  Instruction *I = nullptr) const override;
1165 
1166  /// Return true if the specified immediate is legal
1167  /// icmp immediate, that is the target has icmp instructions which can
1168  /// compare a register against the immediate without having to materialize
1169  /// the immediate into a register.
1170  bool isLegalICmpImmediate(int64_t Imm) const override;
1171 
1172  /// Return true if the specified immediate is legal
1173  /// add immediate, that is the target has add instructions which can
1174  /// add a register and the immediate without having to materialize
1175  /// the immediate into a register.
1176  bool isLegalAddImmediate(int64_t Imm) const override;
1177 
1178  bool isLegalStoreImmediate(int64_t Imm) const override;
1179 
1180  /// Return the cost of the scaling factor used in the addressing
1181  /// mode represented by AM for this target, for a load/store
1182  /// of the specified type.
1183  /// If the AM is supported, the return value must be >= 0.
1184  /// If the AM is not supported, it returns a negative value.
1186  const AddrMode &AM, Type *Ty,
1187  unsigned AS) const override;
1188 
1189  /// This is used to enable splatted operand transforms for vector shifts
1190  /// and vector funnel shifts.
1191  bool isVectorShiftByScalarCheap(Type *Ty) const override;
1192 
1193  /// Add x86-specific opcodes to the default list.
1194  bool isBinOp(unsigned Opcode) const override;
1195 
1196  /// Returns true if the opcode is a commutative binary operation.
1197  bool isCommutativeBinOp(unsigned Opcode) const override;
1198 
1199  /// Return true if it's free to truncate a value of
1200  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1201  /// register EAX to i16 by referencing its sub-register AX.
1202  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1203  bool isTruncateFree(EVT VT1, EVT VT2) const override;
1204 
1205  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
1206 
1207  /// Return true if any actual instruction that defines a
1208  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1209  /// register. This does not necessarily include registers defined in
1210  /// unknown ways, such as incoming arguments, or copies from unknown
1211  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1212  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1213  /// all instructions that define 32-bit values implicit zero-extend the
1214  /// result out to 64 bits.
1215  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
1216  bool isZExtFree(EVT VT1, EVT VT2) const override;
1217  bool isZExtFree(SDValue Val, EVT VT2) const override;
1218 
1220  SmallVectorImpl<Use *> &Ops) const override;
1221  bool shouldConvertPhiType(Type *From, Type *To) const override;
1222 
1223  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1224  /// extend node) is profitable.
1225  bool isVectorLoadExtDesirable(SDValue) const override;
1226 
1227  /// Return true if an FMA operation is faster than a pair of fmul and fadd
1228  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
1229  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
1231  EVT VT) const override;
1232 
1233  /// Return true if it's profitable to narrow
1234  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1235  /// from i32 to i8 but not from i32 to i16.
1236  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
1237 
1238  /// Given an intrinsic, checks if on the target the intrinsic will need to map
1239  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1240  /// true and stores the intrinsic information into the IntrinsicInfo that was
1241  /// passed to the function.
1242  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1243  MachineFunction &MF,
1244  unsigned Intrinsic) const override;
1245 
1246  /// Returns true if the target can instruction select the
1247  /// specified FP immediate natively. If false, the legalizer will
1248  /// materialize the FP immediate as a load from a constant pool.
1249  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1250  bool ForCodeSize) const override;
1251 
1252  /// Targets can use this to indicate that they only support *some*
1253  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1254  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1255  /// be legal.
1256  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1257 
1258  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1259  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1260  /// constant pool entry.
1261  bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1262 
1263  /// Returns true if lowering to a jump table is allowed.
1264  bool areJTsAllowed(const Function *Fn) const override;
1265 
1266  /// If true, then instruction selection should
1267  /// seek to shrink the FP constant of the specified type to a smaller type
1268  /// in order to save space and / or reduce runtime.
1269  bool ShouldShrinkFPConstant(EVT VT) const override {
1270  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
1271  // expensive than a straight movsd. On the other hand, it's important to
1272  // shrink long double fp constant since fldt is very slow.
1273  return !X86ScalarSSEf64 || VT == MVT::f80;
1274  }
1275 
1276  /// Return true if we believe it is correct and profitable to reduce the
1277  /// load node to a smaller type.
1279  EVT NewVT) const override;
1280 
1281  /// Return true if the specified scalar FP type is computed in an SSE
1282  /// register, not on the X87 floating point stack.
1283  bool isScalarFPTypeInSSEReg(EVT VT) const {
1284  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
1285  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
1286  }
1287 
1288  /// Returns true if it is beneficial to convert a load of a constant
1289  /// to just the constant itself.
1290  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1291  Type *Ty) const override;
1292 
1293  bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override;
1294 
1295  bool convertSelectOfConstantsToMath(EVT VT) const override;
1296 
1298  SDValue C) const override;
1299 
1300  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1301  /// with this index.
1302  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1303  unsigned Index) const override;
1304 
1305  /// Scalar ops always have equal or better analysis/performance/power than
1306  /// the vector equivalent, so this always makes sense if the scalar op is
1307  /// supported.
1308  bool shouldScalarizeBinop(SDValue) const override;
1309 
1310  /// Extract of a scalar FP value from index 0 of a vector is free.
1311  bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1312  EVT EltVT = VT.getScalarType();
1313  return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
1314  }
1315 
1316  /// Overflow nodes should get combined/lowered to optimal instructions
1317  /// (they should allow eliminating explicit compares by getting flags from
1318  /// math ops).
1319  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
1320  bool MathUsed) const override;
1321 
1322  bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
1323  unsigned AddrSpace) const override {
1324  // If we can replace more than 2 scalar stores, there will be a reduction
1325  // in instructions even after we add a vector constant load.
1326  return NumElem > 2;
1327  }
1328 
1329  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
1330  const SelectionDAG &DAG,
1331  const MachineMemOperand &MMO) const override;
1332 
1333  /// Intel processors have a unified instruction and data cache
1334  const char * getClearCacheBuiltinName() const override {
1335  return nullptr; // nothing to do, move along.
1336  }
1337 
1338  Register getRegisterByName(const char* RegName, LLT VT,
1339  const MachineFunction &MF) const override;
1340 
1341  /// If a physical register, this returns the register that receives the
1342  /// exception address on entry to an EH pad.
1343  Register
1344  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1345 
1346  /// If a physical register, this returns the register that receives the
1347  /// exception typeid on entry to a landing pad.
1348  Register
1349  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1350 
1351  virtual bool needsFixedCatchObjects() const override;
1352 
1353  /// This method returns a target specific FastISel object,
1354  /// or null if the target does not support "fast" ISel.
1356  const TargetLibraryInfo *libInfo) const override;
1357 
1358  /// If the target has a standard location for the stack protector cookie,
1359  /// returns the address of that location. Otherwise, returns nullptr.
1360  Value *getIRStackGuard(IRBuilderBase &IRB) const override;
1361 
1362  bool useLoadStackGuardNode() const override;
1363  bool useStackGuardXorFP() const override;
1364  void insertSSPDeclarations(Module &M) const override;
1365  Value *getSDagStackGuard(const Module &M) const override;
1366  Function *getSSPStackGuardCheck(const Module &M) const override;
1368  const SDLoc &DL) const override;
1369 
1370 
1371  /// Return true if the target stores SafeStack pointer at a fixed offset in
1372  /// some non-standard address space, and populates the address space and
1373  /// offset as appropriate.
1374  Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
1375 
1376  std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
1377  SDValue Chain, SDValue Pointer,
1378  MachinePointerInfo PtrInfo,
1379  Align Alignment,
1380  SelectionDAG &DAG) const;
1381 
1382  /// Customize the preferred legalization strategy for certain types.
1383  LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1384 
1385  bool softPromoteHalfType() const override { return true; }
1386 
1388  EVT VT) const override;
1389 
1391  CallingConv::ID CC,
1392  EVT VT) const override;
1393 
1395  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
1396  unsigned &NumIntermediates, MVT &RegisterVT) const override;
1397 
1398  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1399 
1400  bool supportSwiftError() const override;
1401 
1402  bool hasStackProbeSymbol(MachineFunction &MF) const override;
1403  bool hasInlineStackProbe(MachineFunction &MF) const override;
1405 
1406  unsigned getStackProbeSize(MachineFunction &MF) const;
1407 
1408  bool hasVectorBlend() const override { return true; }
1409 
1410  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1411 
1412  /// Lower interleaved load(s) into target specific
1413  /// instructions/intrinsics.
1414  bool lowerInterleavedLoad(LoadInst *LI,
1416  ArrayRef<unsigned> Indices,
1417  unsigned Factor) const override;
1418 
1419  /// Lower interleaved store(s) into target specific
1420  /// instructions/intrinsics.
1422  unsigned Factor) const override;
1423 
1425  SDValue Addr, SelectionDAG &DAG)
1426  const override;
1427 
1428  Align getPrefLoopAlignment(MachineLoop *ML) const override;
1429 
1430  protected:
1431  std::pair<const TargetRegisterClass *, uint8_t>
1433  MVT VT) const override;
1434 
1435  private:
1436  /// Keep a reference to the X86Subtarget around so that we can
1437  /// make the right decision when generating code for different targets.
1438  const X86Subtarget &Subtarget;
1439 
1440  /// Select between SSE or x87 floating point ops.
1441  /// When SSE is available, use it for f32 operations.
1442  /// When SSE2 is available, use it for f64 operations.
1443  bool X86ScalarSSEf32;
1444  bool X86ScalarSSEf64;
1445 
1446  /// A list of legal FP immediates.
1447  std::vector<APFloat> LegalFPImmediates;
1448 
1449  /// Indicate that this x86 target can instruction
1450  /// select the specified FP immediate natively.
1451  void addLegalFPImmediate(const APFloat& Imm) {
1452  LegalFPImmediates.push_back(Imm);
1453  }
1454 
1455  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1456  CallingConv::ID CallConv, bool isVarArg,
1457  const SmallVectorImpl<ISD::InputArg> &Ins,
1458  const SDLoc &dl, SelectionDAG &DAG,
1459  SmallVectorImpl<SDValue> &InVals,
1460  uint32_t *RegMask) const;
1461  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1462  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1463  const SDLoc &dl, SelectionDAG &DAG,
1464  const CCValAssign &VA, MachineFrameInfo &MFI,
1465  unsigned i) const;
1466  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1467  const SDLoc &dl, SelectionDAG &DAG,
1468  const CCValAssign &VA,
1469  ISD::ArgFlagsTy Flags, bool isByval) const;
1470 
1471  // Call lowering helpers.
1472 
1473  /// Check whether the call is eligible for tail call optimization. Targets
1474  /// that want to do tail call optimization should implement this function.
1475  bool IsEligibleForTailCallOptimization(SDValue Callee,
1476  CallingConv::ID CalleeCC,
1477  bool isVarArg,
1478  bool isCalleeStructRet,
1479  bool isCallerStructRet,
1480  Type *RetTy,
1481  const SmallVectorImpl<ISD::OutputArg> &Outs,
1482  const SmallVectorImpl<SDValue> &OutVals,
1483  const SmallVectorImpl<ISD::InputArg> &Ins,
1484  SelectionDAG& DAG) const;
1485  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1486  SDValue Chain, bool IsTailCall,
1487  bool Is64Bit, int FPDiff,
1488  const SDLoc &dl) const;
1489 
1490  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1491  SelectionDAG &DAG) const;
1492 
1493  unsigned getAddressSpace(void) const;
1494 
1495  SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned,
1496  SDValue &Chain) const;
1497  SDValue LRINT_LLRINTHelper(SDNode *N, SelectionDAG &DAG) const;
1498 
1499  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1500  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1501  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1502  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1503 
1504  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr,
1505  const unsigned char OpFlags = 0) const;
1506  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1507  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1508  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1509  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1510  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1511 
1512  /// Creates target global address or external symbol nodes for calls or
1513  /// other uses.
1514  SDValue LowerGlobalOrExternal(SDValue Op, SelectionDAG &DAG,
1515  bool ForCall) const;
1516 
1517  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1518  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1519  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1520  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1521  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1522  SDValue LowerLRINT_LLRINT(SDValue Op, SelectionDAG &DAG) const;
1523  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1524  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1525  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1526  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1527  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1528  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1529  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1530  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1531  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1532  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1533  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1534  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1535  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1536  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1537  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1538  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1539  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1540  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1541  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1542  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1543  SDValue LowerGC_TRANSITION(SDValue Op, SelectionDAG &DAG) const;
1544  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1545  SDValue lowerFaddFsub(SDValue Op, SelectionDAG &DAG) const;
1546  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1547  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1548 
1549  SDValue
1550  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1551  const SmallVectorImpl<ISD::InputArg> &Ins,
1552  const SDLoc &dl, SelectionDAG &DAG,
1553  SmallVectorImpl<SDValue> &InVals) const override;
1554  SDValue LowerCall(CallLoweringInfo &CLI,
1555  SmallVectorImpl<SDValue> &InVals) const override;
1556 
1557  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1558  const SmallVectorImpl<ISD::OutputArg> &Outs,
1559  const SmallVectorImpl<SDValue> &OutVals,
1560  const SDLoc &dl, SelectionDAG &DAG) const override;
1561 
1562  bool supportSplitCSR(MachineFunction *MF) const override {
1563  return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
1564  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1565  }
1566  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1567  void insertCopiesSplitCSR(
1568  MachineBasicBlock *Entry,
1569  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1570 
1571  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1572 
1573  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1574 
1575  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1576  ISD::NodeType ExtendKind) const override;
1577 
1578  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1579  bool isVarArg,
1580  const SmallVectorImpl<ISD::OutputArg> &Outs,
1581  LLVMContext &Context) const override;
1582 
1583  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1584 
1586  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
1587  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1589  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1590 
1591  LoadInst *
1592  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1593 
1594  bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const override;
1595  bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const override;
1596 
1597  bool needsCmpXchgNb(Type *MemType) const;
1598 
1599  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1600  MachineBasicBlock *DispatchBB, int FI) const;
1601 
1602  // Utility function to emit the low-level va_arg code for X86-64.
1603  MachineBasicBlock *
1604  EmitVAARGWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
1605 
1606  /// Utility function to emit the xmm reg save portion of va_start.
1607  MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1608  MachineInstr &MI2,
1609  MachineBasicBlock *BB) const;
1610 
1611  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1612  MachineBasicBlock *BB) const;
1613 
1614  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1615  MachineBasicBlock *BB) const;
1616 
1617  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1618  MachineBasicBlock *BB) const;
1619 
1620  MachineBasicBlock *EmitLoweredProbedAlloca(MachineInstr &MI,
1621  MachineBasicBlock *BB) const;
1622 
1623  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1624  MachineBasicBlock *BB) const;
1625 
1626  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1627  MachineBasicBlock *BB) const;
1628 
1629  MachineBasicBlock *EmitLoweredIndirectThunk(MachineInstr &MI,
1630  MachineBasicBlock *BB) const;
1631 
1632  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1633  MachineBasicBlock *MBB) const;
1634 
1635  void emitSetJmpShadowStackFix(MachineInstr &MI,
1636  MachineBasicBlock *MBB) const;
1637 
1638  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1639  MachineBasicBlock *MBB) const;
1640 
1641  MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1642  MachineBasicBlock *MBB) const;
1643 
1644  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1645  MachineBasicBlock *MBB) const;
1646 
1647  /// Emit flags for the given setcc condition and operands. Also returns the
1648  /// corresponding X86 condition code constant in X86CC.
1649  SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC,
1650  const SDLoc &dl, SelectionDAG &DAG,
1651  SDValue &X86CC) const;
1652 
1653  /// Check if replacement of SQRT with RSQRT should be disabled.
1654  bool isFsqrtCheap(SDValue Op, SelectionDAG &DAG) const override;
1655 
1656  /// Use rsqrt* to speed up sqrt calculations.
1657  SDValue getSqrtEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1658  int &RefinementSteps, bool &UseOneConstNR,
1659  bool Reciprocal) const override;
1660 
1661  /// Use rcp* to speed up fdiv calculations.
1662  SDValue getRecipEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1663  int &RefinementSteps) const override;
1664 
1665  /// Reassociate floating point divisions into multiply by reciprocal.
1666  unsigned combineRepeatedFPDivisors() const override;
1667 
1668  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1669  SmallVectorImpl<SDNode *> &Created) const override;
1670  };
1671 
1672  namespace X86 {
1673  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1674  const TargetLibraryInfo *libInfo);
1675  } // end namespace X86
1676 
1677  // X86 specific Gather/Scatter nodes.
1678  // The class has the same order of operands as MaskedGatherScatterSDNode for
1679  // convenience.
1681  public:
1682  // This is a intended as a utility and should never be directly created.
1683  X86MaskedGatherScatterSDNode() = delete;
1684  ~X86MaskedGatherScatterSDNode() = delete;
1685 
1686  const SDValue &getBasePtr() const { return getOperand(3); }
1687  const SDValue &getIndex() const { return getOperand(4); }
1688  const SDValue &getMask() const { return getOperand(2); }
1689  const SDValue &getScale() const { return getOperand(5); }
1690 
1691  static bool classof(const SDNode *N) {
1692  return N->getOpcode() == X86ISD::MGATHER ||
1693  N->getOpcode() == X86ISD::MSCATTER;
1694  }
1695  };
1696 
1698  public:
1699  const SDValue &getPassThru() const { return getOperand(1); }
1700 
1701  static bool classof(const SDNode *N) {
1702  return N->getOpcode() == X86ISD::MGATHER;
1703  }
1704  };
1705 
1707  public:
1708  const SDValue &getValue() const { return getOperand(1); }
1709 
1710  static bool classof(const SDNode *N) {
1711  return N->getOpcode() == X86ISD::MSCATTER;
1712  }
1713  };
1714 
1715  /// Generate unpacklo/unpackhi shuffle mask.
1716  void createUnpackShuffleMask(EVT VT, SmallVectorImpl<int> &Mask, bool Lo,
1717  bool Unary);
1718 
1719  /// Similar to unpacklo/unpackhi, but without the 128-bit lane limitation
1720  /// imposed by AVX and specific to the unary pattern. Example:
1721  /// v8iX Lo --> <0, 0, 1, 1, 2, 2, 3, 3>
1722  /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7>
1723  void createSplat2ShuffleMask(MVT VT, SmallVectorImpl<int> &Mask, bool Lo);
1724 
1725 } // end namespace llvm
1726 
1727 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
llvm::X86ISD::FDIVS
@ FDIVS
Definition: X86ISelLowering.h:225
llvm::X86ISD::UINT_TO_FP_RND
@ UINT_TO_FP_RND
Definition: X86ISelLowering.h:576
llvm::X86ISD::VFPROUND
@ VFPROUND
Definition: X86ISelLowering.h:340
llvm::X86ISD::RCP28S_SAE
@ RCP28S_SAE
Definition: X86ISelLowering.h:684
i
i
Definition: README.txt:29
llvm::X86ISD::EXPAND
@ EXPAND
Definition: X86ISelLowering.h:569
llvm::X86ISD::VGETMANTS_SAE
@ VGETMANTS_SAE
Definition: X86ISelLowering.h:244
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::X86ISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: X86ISelLowering.h:721
llvm::X86ISD::STRICT_VFPEXT
@ STRICT_VFPEXT
Definition: X86ISelLowering.h:735
llvm::X86ISD::FMUL_RND
@ FMUL_RND
Definition: X86ISelLowering.h:221
llvm::X86TargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: X86ISelLowering.cpp:52064
llvm::InlineAsm::Constraint_v
@ Constraint_v
Definition: InlineAsm.h:249
llvm::X86TargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: X86ISelLowering.cpp:5414
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1542
llvm::X86ISD::UMWAIT
@ UMWAIT
Definition: X86ISelLowering.h:706
llvm::X86ISD::STRICT_VRNDSCALE
@ STRICT_VRNDSCALE
Definition: X86ISelLowering.h:743
llvm::X86TargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: X86ISelLowering.cpp:26846
llvm::X86ISD::PCMPESTR
@ PCMPESTR
Definition: X86ISelLowering.h:671
llvm::X86TargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: X86ISelLowering.cpp:51704
llvm::X86ISD::TLSADDR
@ TLSADDR
Definition: X86ISelLowering.h:290
llvm::X86ISD::AESDEC128KL
@ AESDEC128KL
Definition: X86ISelLowering.h:843
llvm::X86ISD::FADD_RND
@ FADD_RND
Definition: X86ISelLowering.h:215
llvm::X86ISD::FMINS
@ FMINS
Definition: X86ISelLowering.h:275
llvm::X86ISD::FMAXS_SAE
@ FMAXS_SAE
Definition: X86ISelLowering.h:228
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm::X86TargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: X86ISelLowering.h:1060
llvm::X86MaskedGatherScatterSDNode::getIndex
const SDValue & getIndex() const
Definition: X86ISelLowering.h:1687
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::X86ISD::PACKUS
@ PACKUS
Definition: X86ISelLowering.h:440
llvm::X86ISD::RCP28_SAE
@ RCP28_SAE
Definition: X86ISelLowering.h:682
llvm::X86ISD::PEXTRW
@ PEXTRW
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
Definition: X86ISelLowering.h:176
llvm::X86ISD::VPERMIL2
@ VPERMIL2
Definition: X86ISelLowering.h:526
llvm::X86ISD::SCALEFS_RND
@ SCALEFS_RND
Definition: X86ISelLowering.h:249
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::X86ISD::MCVTSI2P
@ MCVTSI2P
Definition: X86ISelLowering.h:614
llvm::X86TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:4918
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::X86TargetLowering::hasStackProbeSymbol
bool hasStackProbeSymbol(MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Definition: X86ISelLowering.cpp:52550
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::X86TargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Return true if sinking I's operands to the same basic block as I is profitable, e....
Definition: X86ISelLowering.cpp:32048
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::X86TargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: X86ISelLowering.cpp:34638
llvm::X86ISD::PALIGNR
@ PALIGNR
Definition: X86ISelLowering.h:442
llvm::X86ISD::VFPEXTS_SAE
@ VFPEXTS_SAE
Definition: X86ISelLowering.h:337
llvm::X86ISD::VMTRUNCUS
@ VMTRUNCUS
Definition: X86ISelLowering.h:330
llvm::X86ISD::VRANGES_SAE
@ VRANGES_SAE
Definition: X86ISelLowering.h:489
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4133
llvm::X86TargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: X86ISelLowering.cpp:2564
llvm::X86TargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: X86ISelLowering.cpp:2462
llvm::X86ISD::SHUF128
@ SHUF128
Definition: X86ISelLowering.h:455
llvm::X86ISD::STRICT_FNMSUB
@ STRICT_FNMSUB
Definition: X86ISelLowering.h:752
llvm::X86TargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: X86ISelLowering.h:1140
llvm::X86ISD::LADD
@ LADD
LOCK-prefixed arithmetic read-modify-write instructions.
Definition: X86ISelLowering.h:769
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Function
Definition: Function.h:61
llvm::X86ISD::GF2P8MULB
@ GF2P8MULB
Definition: X86ISelLowering.h:700
llvm::X86ISD::MULHRS
@ MULHRS
Definition: X86ISelLowering.h:533
llvm::X86ISD::VPPERM
@ VPPERM
Definition: X86ISelLowering.h:524
llvm::X86ISD::LWPINS
@ LWPINS
Definition: X86ISelLowering.h:703
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1005
llvm::X86ISD::FSETCC
@ FSETCC
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
Definition: X86ISelLowering.h:106
llvm::X86ISD::FDIVS_RND
@ FDIVS_RND
Definition: X86ISelLowering.h:226
llvm::X86ISD::FMAX
@ FMAX
Floating point max and min.
Definition: X86ISelLowering.h:266
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::X86ISD::SUBV_BROADCAST_LOAD
@ SUBV_BROADCAST_LOAD
Definition: X86ISelLowering.h:785
llvm::X86TargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
Definition: X86InterleavedAccess.cpp:810
llvm::X86ISD::CVTPH2PS
@ CVTPH2PS
Definition: X86ISelLowering.h:690
llvm::X86TargetLowering::isVectorClearMaskLegal
bool isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
Definition: X86ISelLowering.cpp:32141
llvm::X86ISD::SETCC_CARRY
@ SETCC_CARRY
Definition: X86ISelLowering.h:101
llvm::X86ISD::GF2P8AFFINEQB
@ GF2P8AFFINEQB
Definition: X86ISelLowering.h:699
llvm::X86ISD::CVTTP2SI_SAE
@ CVTTP2SI_SAE
Definition: X86ISelLowering.h:596
llvm::X86ISD::VSHRDV
@ VSHRDV
Definition: X86ISelLowering.h:453
llvm::X86ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: X86ISelLowering.h:307
llvm::X86ISD::FXOR
@ FXOR
Bitwise logical XOR of floating point values.
Definition: X86ISelLowering.h:51
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::X86ISD::STRICT_CVTUI2P
@ STRICT_CVTUI2P
Definition: X86ISelLowering.h:747
llvm::X86ISD::FGETEXP_SAE
@ FGETEXP_SAE
Definition: X86ISelLowering.h:237
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86ISD::CVTP2UI_RND
@ CVTP2UI_RND
Definition: X86ISelLowering.h:586
llvm::X86ISD::SCALEFS
@ SCALEFS
Definition: X86ISelLowering.h:248
llvm::X86ISD::FMADD_RND
@ FMADD_RND
Definition: X86ISelLowering.h:560
llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: X86ISelLowering.cpp:5483
llvm::X86ISD::TPAUSE
@ TPAUSE
Definition: X86ISelLowering.h:707
llvm::X86ISD::SELECTS
@ SELECTS
X86 Select.
Definition: X86ISelLowering.h:97
llvm::X86ISD::MCVTTP2UI
@ MCVTTP2UI
Definition: X86ISelLowering.h:613
llvm::X86ISD::BRCOND
@ BRCOND
X86 conditional branches.
Definition: X86ISelLowering.h:122
llvm::X86ISD::CVTTS2UI
@ CVTTS2UI
Definition: X86ISelLowering.h:600
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::X86TargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: X86ISelLowering.cpp:2384
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Definition: X86ISelLowering.h:1283
llvm::X86ISD::EXP2
@ EXP2
Definition: X86ISelLowering.h:685
llvm::X86ISD::LCMPXCHG_DAG
@ LCMPXCHG_DAG
Definition: X86ISelLowering.h:762
llvm::X86ISD::PSHUFLW
@ PSHUFLW
Definition: X86ISelLowering.h:447
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2263
llvm::X86TargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: X86ISelLowering.h:1410
llvm::X86TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: X86ISelLowering.cpp:5395
llvm::MemOp
Definition: TargetLowering.h:111
llvm::X86ISD::FST
@ FST
This instruction implements a truncating store from FP stack slots.
Definition: X86ISelLowering.h:823
llvm::X86ISD::CALL_RVMARKER
@ CALL_RVMARKER
Definition: X86ISelLowering.h:81
llvm::X86TargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
Definition: X86ISelLowering.cpp:51638
llvm::X86ISD::BLENDV
@ BLENDV
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
Definition: X86ISelLowering.h:209
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::X86TargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: X86ISelLowering.cpp:2171
llvm::X86TargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: X86ISelLowering.cpp:52596
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::X86ISD::RCP28
@ RCP28
Definition: X86ISelLowering.h:681
llvm::X86ISD::CVTS2SI_RND
@ CVTS2SI_RND
Definition: X86ISelLowering.h:590
llvm::X86ISD::FNMADD
@ FNMADD
Definition: X86ISelLowering.h:553
llvm::X86TargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: X86ISelLowering.cpp:52455
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::X86ISD::MCVTP2SI
@ MCVTP2SI
Definition: X86ISelLowering.h:610
llvm::X86MaskedGatherScatterSDNode
Definition: X86ISelLowering.h:1680
llvm::AttributeList
Definition: Attributes.h:398
llvm::X86ISD::VSHLDQ
@ VSHLDQ
Definition: X86ISelLowering.h:350
llvm::X86ISD::SBB
@ SBB
Definition: X86ISelLowering.h:400
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::X86ISD::VFIXUPIMMS
@ VFIXUPIMMS
Definition: X86ISelLowering.h:483
llvm::X86TargetLowering::storeOfVectorConstantIsCheap
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
Definition: X86ISelLowering.h:1322
llvm::X86ISD::FNMSUB_RND
@ FNMSUB_RND
Definition: X86ISelLowering.h:563
llvm::X86ISD::KSHIFTL
@ KSHIFTL
Definition: X86ISelLowering.h:369
llvm::X86ISD::ANDNP
@ ANDNP
Bitwise Logical AND NOT of Packed FP values.
Definition: X86ISelLowering.h:199
llvm::X86ISD::PACKSS
@ PACKSS
Definition: X86ISelLowering.h:439
llvm::X86TargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: X86ISelLowering.cpp:2394
llvm::X86::isOffsetSuitableForCodeModel
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
Returns true of the given offset can be fit into displacement field of the instruction.
Definition: X86ISelLowering.cpp:4936
llvm::X86ISD::VTRUNCSTORES
@ VTRUNCSTORES
Definition: X86ISelLowering.h:832
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::X86MaskedGatherScatterSDNode::X86MaskedGatherScatterSDNode
X86MaskedGatherScatterSDNode()=delete
llvm::X86ISD::VPMADDWD
@ VPMADDWD
Definition: X86ISelLowering.h:537
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::X86ISD::VSHLV
@ VSHLV
Definition: X86ISelLowering.h:359
llvm::X86ISD::VPMADDUBSW
@ VPMADDUBSW
Definition: X86ISelLowering.h:536
llvm::X86ISD::LAND
@ LAND
Definition: X86ISelLowering.h:773
llvm::X86TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: X86ISelLowering.cpp:31478
llvm::X86ISD::STRICT_CMPP
@ STRICT_CMPP
Definition: X86ISelLowering.h:724
llvm::X86ISD::BSR
@ BSR
Bit scan reverse.
Definition: X86ISelLowering.h:32
llvm::X86ISD::HSUB
@ HSUB
Definition: X86ISelLowering.h:256
llvm::X86ISD::PDEP
@ PDEP
Definition: X86ISelLowering.h:415
llvm::X86ISD::VASTART_SAVE_XMM_REGS
@ VASTART_SAVE_XMM_REGS
Definition: X86ISelLowering.h:632
llvm::X86ISD::LOR
@ LOR
Definition: X86ISelLowering.h:771
llvm::X86ISD::PSHUFHW
@ PSHUFHW
Definition: X86ISelLowering.h:446
llvm::X86ISD::VSRLDQ
@ VSRLDQ
Definition: X86ISelLowering.h:351
llvm::X86ISD::FMADDSUB
@ FMADDSUB
Definition: X86ISelLowering.h:556
llvm::X86ISD::SMUL
@ SMUL
Definition: X86ISelLowering.h:401
llvm::X86ISD::VFPEXT
@ VFPEXT
Definition: X86ISelLowering.h:334
llvm::X86ISD::RSQRT28
@ RSQRT28
Definition: X86ISelLowering.h:677
llvm::X86ISD::VTRUNC
@ VTRUNC
Definition: X86ISelLowering.h:320
llvm::X86TargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: X86ISelLowering.cpp:31997
llvm::X86ISD::FMAXC
@ FMAXC
Commutative FMIN and FMAX.
Definition: X86ISelLowering.h:270
llvm::X86ISD::VRANGE
@ VRANGE
Definition: X86ISelLowering.h:486
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::X86ISD::BEXTRI
@ BEXTRI
Definition: X86ISelLowering.h:409
llvm::X86TargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: X86ISelLowering.h:1269
llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle
bool SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) const
Definition: X86ISelLowering.cpp:38582
llvm::X86ISD::STRICT_CVTPH2PS
@ STRICT_CVTPH2PS
Definition: X86ISelLowering.h:756
llvm::X86ISD::MCVTPS2PH
@ MCVTPS2PH
Definition: X86ISelLowering.h:695
llvm::X86ISD::RSQRT14S
@ RSQRT14S
Definition: X86ISelLowering.h:285
llvm::X86ISD::MCVTTP2SI
@ MCVTTP2SI
Definition: X86ISelLowering.h:612
llvm::X86TargetLowering::shouldScalarizeBinop
bool shouldScalarizeBinop(SDValue) const override
Scalar ops always have equal or better analysis/performance/power than the vector equivalent,...
Definition: X86ISelLowering.cpp:5340
llvm::X86TargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: X86ISelLowering.cpp:5269
llvm::X86ISD::FSETCCM
@ FSETCCM
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.
Definition: X86ISelLowering.h:110
llvm::X86TargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: X86ISelLowering.h:1000
llvm::X86ISD::VPERMI
@ VPERMI
Definition: X86ISelLowering.h:467
llvm::X86TargetLowering::getClearCacheBuiltinName
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
Definition: X86ISelLowering.h:1334
llvm::X86ISD::PSHUFD
@ PSHUFD
Definition: X86ISelLowering.h:445
llvm::X86ISD::VRNDSCALES
@ VRNDSCALES
Definition: X86ISelLowering.h:500
llvm::X86TargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: X86ISelLowering.cpp:34729
llvm::X86ISD::CMPP
@ CMPP
Definition: X86ISelLowering.h:377
llvm::X86ISD::FMSUBADD_RND
@ FMSUBADD_RND
Definition: X86ISelLowering.h:565
llvm::X86ISD::VFPROUNDS
@ VFPROUNDS
Definition: X86ISelLowering.h:342
llvm::X86ISD::MOVLHPS
@ MOVLHPS
Definition: X86ISelLowering.h:459
llvm::X86ISD::CMPMM
@ CMPMM
Definition: X86ISelLowering.h:392
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::X86TargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: X86ISelLowering.cpp:5123
llvm::X86ISD::CALL
@ CALL
These operations represent an abstract X86 call instruction, which includes a bunch of information.
Definition: X86ISelLowering.h:74
llvm::X86TargetLowering::getSafeStackPointerLocation
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
Definition: X86ISelLowering.cpp:2583
llvm::X86ISD::MSCATTER
@ MSCATTER
Definition: X86ISelLowering.h:839
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::X86TargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: X86ISelLowering.cpp:51526
llvm::X86ISD::CVTS2SI
@ CVTS2SI
Definition: X86ISelLowering.h:588
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1335
llvm::X86TargetLowering::LowerAsmOutputForConstraint
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Handle Lowering flag assembly outputs.
Definition: X86ISelLowering.cpp:51862
TargetLowering.h
llvm::X86ISD::SUB
@ SUB
Definition: X86ISelLowering.h:398
llvm::X86ISD::COMPRESS
@ COMPRESS
Definition: X86ISelLowering.h:568
llvm::X86ISD::RCP14S
@ RCP14S
Definition: X86ISelLowering.h:287
llvm::X86ISD::SEG_ALLOCA
@ SEG_ALLOCA
Definition: X86ISelLowering.h:640
llvm::X86ISD::PMULDQ
@ PMULDQ
Definition: X86ISelLowering.h:531
llvm::X86ISD::CMPM
@ CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
Definition: X86ISelLowering.h:390
llvm::X86ISD::VSRA
@ VSRA
Definition: X86ISelLowering.h:356
llvm::X86ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: X86ISelLowering.h:310
llvm::X86ISD::PINSRW
@ PINSRW
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
Definition: X86ISelLowering.h:188
llvm::MemIntrinsicSDNode
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
Definition: SelectionDAGNodes.h:1458
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:59
llvm::X86ISD::STRICT_CMPM
@ STRICT_CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
Definition: X86ISelLowering.h:728
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::X86TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: X86ISelLowering.cpp:34221
llvm::X86TargetLowering::useStackGuardXorFP
bool useStackGuardXorFP() const override
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
Definition: X86ISelLowering.cpp:2093
llvm::X86ISD::PSHUFB
@ PSHUFB
Shuffle 16 8-bit values within a vector.
Definition: X86ISelLowering.h:191
llvm::X86ISD::VMTRUNCSTOREUS
@ VMTRUNCSTOREUS
Definition: X86ISelLowering.h:834
llvm::X86ISD::VPSHUFBITQMB
@ VPSHUFBITQMB
Definition: X86ISelLowering.h:572
llvm::X86ISD::FNMSUB
@ FNMSUB
Definition: X86ISelLowering.h:555
llvm::X86ISD::MOVSLDUP
@ MOVSLDUP
Definition: X86ISelLowering.h:458
llvm::X86ISD::CMOV
@ CMOV
X86 conditional moves.
Definition: X86ISelLowering.h:116
llvm::X86TargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: X86ISelLowering.cpp:51344
llvm::X86TargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: X86ISelLowering.cpp:26891
llvm::X86ISD::VTRUNCS
@ VTRUNCS
Definition: X86ISelLowering.h:323
llvm::X86ISD::RDRAND
@ RDRAND
Definition: X86ISelLowering.h:651
llvm::X86ISD::BT
@ BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:90
llvm::X86ISD::GF2P8AFFINEINVQB
@ GF2P8AFFINEINVQB
Definition: X86ISelLowering.h:698
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::X86ISD::FMADDSUB_RND
@ FMADDSUB_RND
Definition: X86ISelLowering.h:564
llvm::X86ISD::MOVSHDUP
@ MOVSHDUP
Definition: X86ISelLowering.h:457
llvm::X86ISD::FADDS_RND
@ FADDS_RND
Definition: X86ISelLowering.h:217
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::X86ISD::RDSEED
@ RDSEED
Definition: X86ISelLowering.h:655
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::X86ISD::VBROADCAST_LOAD
@ VBROADCAST_LOAD
Definition: X86ISelLowering.h:782
llvm::X86ISD::VSRLI
@ VSRLI
Definition: X86ISelLowering.h:365
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3165
llvm::X86TargetLowering::hasVectorBlend
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Definition: X86ISelLowering.h:1408
llvm::X86ISD::ENQCMDS
@ ENQCMDS
Definition: X86ISelLowering.h:711
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::X86::isConstantSplat
bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs)
If Op is a constant whose elements are all the same constant or undefined, return true and return the...
Definition: X86ISelLowering.cpp:6841
llvm::X86TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: X86ISelLowering.cpp:30430
llvm::X86ISD::STRICT_VFPROUND
@ STRICT_VFPROUND
Definition: X86ISelLowering.h:738
llvm::X86ISD::FHSUB
@ FHSUB
Definition: X86ISelLowering.h:260
llvm::X86ISD::WRPKRU
@ WRPKRU
Definition: X86ISelLowering.h:662
llvm::X86ISD::VZEXT_LOAD
@ VZEXT_LOAD
Definition: X86ISelLowering.h:776
llvm::X86ISD::NT_CALL
@ NT_CALL
Same as call except it adds the NoTrack prefix.
Definition: X86ISelLowering.h:77
llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: X86ISelLowering.cpp:39220
llvm::X86ISD::VSHLD
@ VSHLD
Definition: X86ISelLowering.h:450
llvm::X86TargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: X86ISelLowering.cpp:2089
llvm::X86ISD::FILD
@ FILD
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.
Definition: X86ISelLowering.h:805
llvm::X86ISD::SCALEF_RND
@ SCALEF_RND
Definition: X86ISelLowering.h:247
llvm::X86ISD::MFENCE
@ MFENCE
Definition: X86ISelLowering.h:648
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::X86ISD::CVTNEPS2BF16
@ CVTNEPS2BF16
Definition: X86ISelLowering.h:621
llvm::X86TargetLowering::markLibCallAttributes
void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override
Definition: X86ISelLowering.cpp:2398
llvm::createSplat2ShuffleMask
void createSplat2ShuffleMask(MVT VT, SmallVectorImpl< int > &Mask, bool Lo)
Similar to unpacklo/unpackhi, but without the 128-bit lane limitation imposed by AVX and specific to ...
Definition: X86ISelLowering.cpp:6437
llvm::X86TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
Definition: X86ISelLowering.cpp:32014
llvm::X86ISD::VPERM2X128
@ VPERM2X128
Definition: X86ISelLowering.h:468
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:145
llvm::X86TargetLowering::needsFixedCatchObjects
virtual bool needsFixedCatchObjects() const override
Definition: X86ISelLowering.cpp:26899
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::X86MaskedGatherScatterSDNode::getMask
const SDValue & getMask() const
Definition: X86ISelLowering.h:1688
llvm::X86TargetLowering::isLoadBitCastBeneficial
bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const override
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Definition: X86ISelLowering.cpp:5377
llvm::X86ISD::VPDPBUSDS
@ VPDPBUSDS
Definition: X86ISelLowering.h:547
llvm::X86ISD::FSUBS_RND
@ FSUBS_RND
Definition: X86ISelLowering.h:220
llvm::X86ISD::VSHLDV
@ VSHLDV
Definition: X86ISelLowering.h:452
llvm::X86ISD::SCALAR_UINT_TO_FP
@ SCALAR_UINT_TO_FP
Definition: X86ISelLowering.h:578
llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: X86ISelLowering.cpp:32094
llvm::X86TargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: X86ISelLowering.cpp:51850
llvm::X86ISD::FGETEXPS_SAE
@ FGETEXPS_SAE
Definition: X86ISelLowering.h:239
llvm::X86ISD::AESDEC256KL
@ AESDEC256KL
Definition: X86ISelLowering.h:845
llvm::X86ISD::RSQRT28S
@ RSQRT28S
Definition: X86ISelLowering.h:679
llvm::X86TargetLowering
Definition: X86ISelLowering.h:895
llvm::X86ISD::PEXTRB
@ PEXTRB
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
Definition: X86ISelLowering.h:172
llvm::X86TargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: X86ISelLowering.cpp:5418
llvm::X86ISD::VAARG_64
@ VAARG_64
These instructions grab the address of the next argument from a va_list.
Definition: X86ISelLowering.h:827
llvm::X86ISD::VEXTRACT_STORE
@ VEXTRACT_STORE
Definition: X86ISelLowering.h:779
llvm::X86ISD::IRET
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
Definition: X86ISelLowering.h:133
llvm::X86TargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: X86ISelLowering.cpp:31979
llvm::X86ISD::CVTTP2UI
@ CVTTP2UI
Definition: X86ISelLowering.h:595
llvm::X86ISD::FMAXS
@ FMAXS
Scalar intrinsic floating point max and min.
Definition: X86ISelLowering.h:274
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86ISD::CVTS2UI_RND
@ CVTS2UI_RND
Definition: X86ISelLowering.h:591
llvm::X86ISD::LCMPXCHG16_DAG
@ LCMPXCHG16_DAG
Definition: X86ISelLowering.h:764
llvm::X86TargetLowering::areJTsAllowed
bool areJTsAllowed(const Function *Fn) const override
Returns true if lowering to a jump table is allowed.
Definition: X86ISelLowering.cpp:32153
llvm::X86ISD::CVTTS2UI_SAE
@ CVTTS2UI_SAE
Definition: X86ISelLowering.h:602
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::X86ISD::MOVHLPS
@ MOVHLPS
Definition: X86ISelLowering.h:460
llvm::X86TargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: X86ISelLowering.cpp:52555
llvm::X86ISD::SCALAR_SINT_TO_FP
@ SCALAR_SINT_TO_FP
Definition: X86ISelLowering.h:577
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::X86ISD::VFIXUPIMM_SAE
@ VFIXUPIMM_SAE
Definition: X86ISelLowering.h:482
llvm::X86TargetLowering::isVectorShiftByScalarCheap
bool isVectorShiftByScalarCheap(Type *Ty) const override
This is used to enable splatted operand transforms for vector shifts and vector funnel shifts.
Definition: X86ISelLowering.cpp:31911
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::X86ISD::VPERMILPI
@ VPERMILPI
Definition: X86ISelLowering.h:466
llvm::X86ISD::CVTNE2PS2BF16
@ CVTNE2PS2BF16
Definition: X86ISelLowering.h:619
llvm::X86TargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: X86ISelLowering.cpp:32124
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::X86TargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: X86ISelLowering.cpp:2438
llvm::X86ISD::GlobalBaseReg
@ GlobalBaseReg
On Darwin, this node represents the result of the popl at function entry, used for PIC code.
Definition: X86ISelLowering.h:143
llvm::X86ISD::VFPCLASS
@ VFPCLASS
Definition: X86ISelLowering.h:503
llvm::X86ISD::EXTRQI
@ EXTRQI
SSE4A Extraction and Insertion.
Definition: X86ISelLowering.h:514
llvm::X86MaskedGatherScatterSDNode::getScale
const SDValue & getScale() const
Definition: X86ISelLowering.h:1689
llvm::X86ISD::DPBF16PS
@ DPBF16PS
Definition: X86ISelLowering.h:628
llvm::X86ISD::VREDUCES
@ VREDUCES
Definition: X86ISelLowering.h:493
llvm::X86ISD::FGETEXP
@ FGETEXP
Definition: X86ISelLowering.h:236
llvm::X86ISD::AESENC256KL
@ AESENC256KL
Definition: X86ISelLowering.h:844
llvm::X86ISD::INSERTQI
@ INSERTQI
Definition: X86ISelLowering.h:515
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:57
llvm::X86ISD::MCVTNEPS2BF16
@ MCVTNEPS2BF16
Definition: X86ISelLowering.h:624
llvm::X86MaskedGatherScatterSDNode::~X86MaskedGatherScatterSDNode
~X86MaskedGatherScatterSDNode()=delete
llvm::X86TargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code.
Definition: X86ISelLowering.cpp:30577
llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode
bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
Definition: X86ISelLowering.cpp:38649
llvm::X86ISD::ADD
@ ADD
Definition: X86ISelLowering.h:397
llvm::X86ISD::VRNDSCALE
@ VRNDSCALE
Definition: X86ISelLowering.h:498
llvm::X86ISD::PHMINPOS
@ PHMINPOS
Definition: X86ISelLowering.h:384
llvm::X86::rmMask
@ rmMask
Definition: X86ISelLowering.h:866
llvm::X86ISD::CVTS2UI
@ CVTS2UI
Definition: X86ISelLowering.h:589
llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair
bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
Definition: X86ISelLowering.cpp:5501
llvm::APFloat
Definition: APFloat.h:701
llvm::X86ISD::FMINC
@ FMINC
Definition: X86ISelLowering.h:271
llvm::X86ISD::CVTUI2P
@ CVTUI2P
Definition: X86ISelLowering.h:606
llvm::X86ISD::FMIN_SAE
@ FMIN_SAE
Definition: X86ISelLowering.h:229
llvm::X86TargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: X86ISelLowering.cpp:5423
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::X86ISD::VPSHA
@ VPSHA
Definition: X86ISelLowering.h:518
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::X86ISD::MGATHER
@ MGATHER
Definition: X86ISelLowering.h:838
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::X86ISD::KADD
@ KADD
Definition: X86ISelLowering.h:435
llvm::X86TargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: X86ISelLowering.cpp:5297
llvm::X86ISD::VBROADCASTM
@ VBROADCASTM
Definition: X86ISelLowering.h:511
llvm::X86ISD::CVTP2SI_RND
@ CVTP2SI_RND
Definition: X86ISelLowering.h:585
llvm::X86ISD::MOVQ2DQ
@ MOVQ2DQ
Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero fi...
Definition: X86ISelLowering.h:156
llvm::createUnpackShuffleMask
void createUnpackShuffleMask(EVT VT, SmallVectorImpl< int > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
Definition: X86ISelLowering.cpp:6417
llvm::X86TargetLowering::getPreferredVectorAction
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Customize the preferred legalization strategy for certain types.
Definition: X86ISelLowering.cpp:2107
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::X86ISD::FSQRTS_RND
@ FSQRTS_RND
Definition: X86ISelLowering.h:233
llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: X86ISelLowering.cpp:2451
llvm::X86ISD::FSHL
@ FSHL
X86 funnel/double shift i16 instructions.
Definition: X86ISelLowering.h:38
llvm::X86ISD::VRNDSCALE_SAE
@ VRNDSCALE_SAE
Definition: X86ISelLowering.h:499
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1255
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::X86::isZeroNode
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
Definition: X86ISelLowering.cpp:5778
llvm::X86ISD::VTRUNCSTOREUS
@ VTRUNCSTOREUS
Definition: X86ISelLowering.h:831
llvm::X86ISD::FOR
@ FOR
Bitwise logical OR of floating point values.
Definition: X86ISelLowering.h:47
llvm::X86ISD::VFPEXTS
@ VFPEXTS
Definition: X86ISelLowering.h:336
llvm::X86TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: X86ISelLowering.cpp:2349
llvm::X86ISD::STRICT_FMSUB
@ STRICT_FMSUB
Definition: X86ISelLowering.h:751
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::X86ISD::FSETCCM_SAE
@ FSETCCM_SAE
Definition: X86ISelLowering.h:111
llvm::X86ISD::VPERMV3
@ VPERMV3
Definition: X86ISelLowering.h:476
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::X86TargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: X86ISelLowering.cpp:32081
llvm::X86ISD::VFPROUND_RND
@ VFPROUND_RND
Definition: X86ISelLowering.h:341
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:896
llvm::X86ISD::RSQRT28_SAE
@ RSQRT28_SAE
Definition: X86ISelLowering.h:678
llvm::X86ISD::MOVSS
@ MOVSS
Definition: X86ISelLowering.h:462
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::X86ISD::CVTTP2UI_SAE
@ CVTTP2UI_SAE
Definition: X86ISelLowering.h:597
llvm::X86TargetLowering::X86TargetLowering
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
Definition: X86ISelLowering.cpp:114
llvm::X86ISD::PEXT
@ PEXT
Definition: X86ISelLowering.h:416
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:130
llvm::X86ISD::ENQCMD
@ ENQCMD
Definition: X86ISelLowering.h:710
llvm::X86ISD::VFPCLASSS
@ VFPCLASSS
Definition: X86ISelLowering.h:505
llvm::X86ISD::VREDUCE
@ VREDUCE
Definition: X86ISelLowering.h:491
llvm::X86ISD::VPDPWSSD
@ VPDPWSSD
Definition: X86ISelLowering.h:548
llvm::X86ISD::INSERTPS
@ INSERTPS
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
Definition: X86ISelLowering.h:180
llvm::TargetLoweringBase::NegatibleCost
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition: TargetLowering.h:267
llvm::X86ISD::BSF
@ BSF
Bit scan forward.
Definition: X86ISelLowering.h:30
llvm::X86ISD::VSRAV
@ VSRAV
Definition: X86ISelLowering.h:361
llvm::X86ISD::UNPCKL
@ UNPCKL
Definition: X86ISelLowering.h:463
llvm::X86ISD::COMI
@ COMI
Definition: X86ISelLowering.h:86
llvm::X86TargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: X86ISelLowering.cpp:52608
llvm::X86ISD::UMUL
@ UMUL
Definition: X86ISelLowering.h:402
llvm::X86MaskedScatterSDNode::getValue
const SDValue & getValue() const
Definition: X86ISelLowering.h:1708
llvm::X86ISD::FMSUB
@ FMSUB
Definition: X86ISelLowering.h:554
llvm::X86ISD::FRCP
@ FRCP
Definition: X86ISelLowering.h:281
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::X86ISD::MEMBARRIER
@ MEMBARRIER
Definition: X86ISelLowering.h:647
llvm::X86TargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
Definition: X86ISelLowering.cpp:5233
llvm::X86TargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: X86ISelLowering.cpp:51889
llvm::X86ISD::VSRAI
@ VSRAI
Definition: X86ISelLowering.h:366
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::X86ISD::BZHI
@ BZHI
Definition: X86ISelLowering.h:412
llvm::X86ISD::VRANGES
@ VRANGES
Definition: X86ISelLowering.h:488
llvm::X86ISD::CVTTS2SI_SAE
@ CVTTS2SI_SAE
Definition: X86ISelLowering.h:601
llvm::X86MaskedScatterSDNode
Definition: X86ISelLowering.h:1706
llvm::X86::RoundingMode
RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
Definition: X86ISelLowering.h:861
llvm::X86ISD::REP_STOS
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
Definition: X86ISelLowering.h:136
llvm::X86ISD::VAARG_X32
@ VAARG_X32
Definition: X86ISelLowering.h:828
llvm::X86TargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: X86ISelLowering.cpp:2153
llvm::X86ISD::FRSQRT
@ FRSQRT
Floating point reciprocal-sqrt and reciprocal approximation.
Definition: X86ISelLowering.h:280
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::X86ISD::RCP14
@ RCP14
Definition: X86ISelLowering.h:286
llvm::X86ISD::MOVDQ2Q
@ MOVDQ2Q
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
Definition: X86ISelLowering.h:160
llvm::X86ISD::VSRLV
@ VSRLV
Definition: X86ISelLowering.h:360
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::X86TargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: X86ISelLowering.cpp:26883
llvm::X86MaskedGatherSDNode
Definition: X86ISelLowering.h:1697
llvm::X86ISD::AND
@ AND
Definition: X86ISelLowering.h:405
llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: X86ISelLowering.cpp:5461
llvm::X86ISD::VFPROUNDS_RND
@ VFPROUNDS_RND
Definition: X86ISelLowering.h:343
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1355
llvm::X86ISD::DBPSADBW
@ DBPSADBW
Compute Double Block Packed Sum-Absolute-Differences.
Definition: X86ISelLowering.h:196
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
llvm::X86TargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: X86ISelLowering.cpp:5224
llvm::X86ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: X86ISelLowering.h:304
llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
Definition: X86ISelLowering.h:1004
llvm::X86ISD::MOVDDUP
@ MOVDDUP
Definition: X86ISelLowering.h:456
llvm::X86ISD::STRICT_CVTSI2P
@ STRICT_CVTSI2P
Definition: X86ISelLowering.h:746
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::X86TargetLowering::IsDesirableToPromoteOp
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: X86ISelLowering.cpp:51406
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::X86ISD::VFIXUPIMM
@ VFIXUPIMM
Definition: X86ISelLowering.h:481
llvm::X86ISD::NT_BRIND
@ NT_BRIND
BRIND node with NoTrack prefix.
Definition: X86ISelLowering.h:126
llvm::X86ISD::FMINS_SAE
@ FMINS_SAE
Definition: X86ISelLowering.h:230
llvm::X86ISD::TESTUI
@ TESTUI
Definition: X86ISelLowering.h:717
llvm::X86ISD::XTEST
@ XTEST
Definition: X86ISelLowering.h:674
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::X86ISD::VRNDSCALES_SAE
@ VRNDSCALES_SAE
Definition: X86ISelLowering.h:501
llvm::X86TargetLowering::unwrapAddress
SDValue unwrapAddress(SDValue N) const override
Definition: X86ISelLowering.cpp:35168
llvm::X86ISD::EH_RETURN
@ EH_RETURN
Definition: X86ISelLowering.h:301
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::X86TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: X86ISelLowering.h:906
llvm::X86ISD::TLSCALL
@ TLSCALL
Definition: X86ISelLowering.h:298
llvm::X86TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: X86ISelLowering.cpp:31859
llvm::X86TargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: X86ISelLowering.cpp:2427
llvm::X86::rmUpward
@ rmUpward
Definition: X86ISelLowering.h:864
llvm::X86ISD::AESENCWIDE256KL
@ AESENCWIDE256KL
Definition: X86ISelLowering.h:848
llvm::X86ISD::FMULS
@ FMULS
Definition: X86ISelLowering.h:222
llvm::X86ISD::UNPCKH
@ UNPCKH
Definition: X86ISelLowering.h:464
llvm::X86ISD::VGETMANTS
@ VGETMANTS
Definition: X86ISelLowering.h:243
llvm::X86ISD::MCVTP2UI
@ MCVTP2UI
Definition: X86ISelLowering.h:611
llvm::X86ISD::AESENCWIDE128KL
@ AESENCWIDE128KL
Definition: X86ISelLowering.h:846
llvm::X86::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: X86ISelLowering.cpp:4968
llvm::X86ISD::SCALEF
@ SCALEF
Definition: X86ISelLowering.h:246
llvm::X86ISD::MUL_IMM
@ MUL_IMM
Definition: X86ISelLowering.h:419
llvm::ArrayRef< int >
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:155
llvm::X86TargetLowering::isExtractVecEltCheap
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
Definition: X86ISelLowering.h:1311
llvm::X86ISD::PSADBW
@ PSADBW
Compute Sum of Absolute Differences.
Definition: X86ISelLowering.h:194
llvm::X86ISD::KSHIFTR
@ KSHIFTR
Definition: X86ISelLowering.h:370
llvm::X86::rmToNearest
@ rmToNearest
Definition: X86ISelLowering.h:862
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::X86ISD::FP_TO_INT_IN_MEM
@ FP_TO_INT_IN_MEM
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.
Definition: X86ISelLowering.h:798
llvm::X86MaskedGatherSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1701
llvm::X86ISD::FADDS
@ FADDS
Definition: X86ISelLowering.h:216
llvm::X86TargetLowering::getIRStackGuard
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
Definition: X86ISelLowering.cpp:2506
llvm::X86ISD::STRICT_FNMADD
@ STRICT_FNMADD
Definition: X86ISelLowering.h:750
llvm::X86TargetLowering::emitStackGuardXorFP
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override
Definition: X86ISelLowering.cpp:2098
llvm::X86ISD::REP_MOVS
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
Definition: X86ISelLowering.h:139
llvm::X86ISD::VPMADD52L
@ VPMADD52L
Definition: X86ISelLowering.h:542
uint32_t
llvm::X86ISD::FLD
@ FLD
This instruction implements an extending load to FP stack slots.
Definition: X86ISelLowering.h:817
llvm::X86ISD::BLENDI
@ BLENDI
Blend where the selector is an immediate.
Definition: X86ISelLowering.h:202
llvm::X86ISD::VPTERNLOG
@ VPTERNLOG
Definition: X86ISelLowering.h:479
llvm::X86ISD::VGETMANT
@ VGETMANT
Definition: X86ISelLowering.h:241
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86MaskedGatherSDNode::getPassThru
const SDValue & getPassThru() const
Definition: X86ISelLowering.h:1699
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::X86ISD::VREDUCE_SAE
@ VREDUCE_SAE
Definition: X86ISelLowering.h:492
llvm::X86TargetLowering::expandIndirectJTBranch
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expanasion.
Definition: X86ISelLowering.cpp:51390
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::X86ISD::FMSUBADD
@ FMSUBADD
Definition: X86ISelLowering.h:557
llvm::X86ISD::XOR
@ XOR
Definition: X86ISelLowering.h:404
llvm::X86ISD::RSQRT14
@ RSQRT14
Definition: X86ISelLowering.h:284
llvm::X86ISD::LCMPXCHG8_DAG
@ LCMPXCHG8_DAG
Definition: X86ISelLowering.h:763
llvm::X86::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: X86FastISel.cpp:4011
llvm::X86ISD::VPCOMU
@ VPCOMU
Definition: X86ISelLowering.h:522
llvm::X86TargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: X86ISelLowering.cpp:2573
llvm::X86TargetLowering::shouldTransformSignedTruncationCheck
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition: X86ISelLowering.h:1039
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::X86::rmTowardZero
@ rmTowardZero
Definition: X86ISelLowering.h:865
llvm::X86ISD::VPDPWSSDS
@ VPDPWSSDS
Definition: X86ISelLowering.h:549
llvm::X86ISD::FCMP
@ FCMP
Definition: X86ISelLowering.h:85
llvm::X86ISD::CVTSI2P
@ CVTSI2P
Definition: X86ISelLowering.h:605
llvm::X86ISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress,...
Definition: X86ISelLowering.h:148
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:303
llvm::X86ISD::VPERMILPV
@ VPERMILPV
Definition: X86ISelLowering.h:465
llvm::X86TargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: X86ISelLowering.cpp:5326
llvm::X86TargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
Definition: X86ISelLowering.cpp:2295
llvm::X86MaskedGatherScatterSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: X86ISelLowering.h:1686
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86ISD::KTEST
@ KTEST
Definition: X86ISelLowering.h:432
llvm::X86ISD::FHADD
@ FHADD
Floating point horizontal add/sub.
Definition: X86ISelLowering.h:259
llvm::X86ISD::MOVSD
@ MOVSD
Definition: X86ISelLowering.h:461
llvm::X86ISD::VSRL
@ VSRL
Definition: X86ISelLowering.h:355
llvm::X86ISD::VSHLI
@ VSHLI
Definition: X86ISelLowering.h:364
llvm::X86ISD::MMX_MOVW2D
@ MMX_MOVW2D
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.
Definition: X86ISelLowering.h:168
llvm::X86ISD::VTRUNCUS
@ VTRUNCUS
Definition: X86ISelLowering.h:322
llvm::X86ISD::FSQRTS
@ FSQRTS
Definition: X86ISelLowering.h:232
llvm::X86ISD::CVTP2UI
@ CVTP2UI
Definition: X86ISelLowering.h:584
llvm::X86ISD::VPERMV
@ VPERMV
Definition: X86ISelLowering.h:472
llvm::X86TargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: X86ISelLowering.cpp:5372
llvm::X86TargetLowering::shouldConvertPhiType
bool shouldConvertPhiType(Type *From, Type *To) const override
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
Definition: X86ISelLowering.cpp:32075
llvm::KnownBits
Definition: KnownBits.h:23
llvm::X86ISD::VBROADCAST
@ VBROADCAST
Definition: X86ISelLowering.h:509
llvm::X86ISD::FSHR
@ FSHR
Definition: X86ISelLowering.h:39
llvm::X86TargetLowering::getNegatedExpression
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Definition: X86ISelLowering.cpp:47370
llvm::X86MaskedGatherScatterSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1691
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::X86ISD::VROTRI
@ VROTRI
Definition: X86ISelLowering.h:374
llvm::X86TargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
Definition: X86ISelLowering.h:987
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:296
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::X86ISD::VPMADD52H
@ VPMADD52H
Definition: X86ISelLowering.h:543
llvm::X86ISD::KORTEST
@ KORTEST
Definition: X86ISelLowering.h:431
llvm::X86ISD::SCALAR_UINT_TO_FP_RND
@ SCALAR_UINT_TO_FP_RND
Definition: X86ISelLowering.h:580
llvm::X86ISD::SETCC
@ SETCC
X86 SetCC.
Definition: X86ISelLowering.h:94
llvm::X86ISD::RSQRT28S_SAE
@ RSQRT28S_SAE
Definition: X86ISelLowering.h:680
llvm::X86ISD::AESDECWIDE256KL
@ AESDECWIDE256KL
Definition: X86ISelLowering.h:849
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4142
llvm::X86TargetLowering::getTargetConstantFromLoad
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
Definition: X86ISelLowering.cpp:6507
llvm::X86ISD::VZEXT_MOVL
@ VZEXT_MOVL
Definition: X86ISelLowering.h:317
llvm::X86ISD::FSUBS
@ FSUBS
Definition: X86ISelLowering.h:219
llvm::X86ISD::VMTRUNCS
@ VMTRUNCS
Definition: X86ISelLowering.h:331
llvm::X86ISD::FAND
@ FAND
Bitwise logical AND of floating point values.
Definition: X86ISelLowering.h:43
llvm::X86ISD::PCMPEQ
@ PCMPEQ
Definition: X86ISelLowering.h:380
llvm::X86ISD::FMIN
@ FMIN
Definition: X86ISelLowering.h:267
llvm::X86ISD::FMULS_RND
@ FMULS_RND
Definition: X86ISelLowering.h:223
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::X86TargetLowering::hasFastEqualityCompare
MVT hasFastEqualityCompare(unsigned NumBits) const override
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
Definition: X86ISelLowering.cpp:5529
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::X86ISD::RET_FLAG
@ RET_FLAG
Return with a flag operand.
Definition: X86ISelLowering.h:130
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::X86ISD::VGETMANT_SAE
@ VGETMANT_SAE
Definition: X86ISelLowering.h:242
llvm::X86ISD::HADD
@ HADD
Integer horizontal add/sub.
Definition: X86ISelLowering.h:255
llvm::X86ISD::LSUB
@ LSUB
Definition: X86ISelLowering.h:770
llvm::X86ISD::FDIV_RND
@ FDIV_RND
Definition: X86ISelLowering.h:224
llvm::X86ISD::CMPMM_SAE
@ CMPMM_SAE
Definition: X86ISelLowering.h:394
llvm::X86TargetLowering::isBinOp
bool isBinOp(unsigned Opcode) const override
Add x86-specific opcodes to the default list.
Definition: X86ISelLowering.cpp:31939
llvm::X86ISD::VFPEXT_SAE
@ VFPEXT_SAE
Definition: X86ISelLowering.h:335
llvm::X86ISD::VMFPROUND
@ VMFPROUND
Definition: X86ISelLowering.h:347
llvm::X86ISD::STRICT_CVTTP2SI
@ STRICT_CVTTP2SI
Definition: X86ISelLowering.h:731
llvm::X86ISD::VPDPBUSD
@ VPDPBUSD
Definition: X86ISelLowering.h:546
llvm::X86ISD::FSQRT_RND
@ FSQRT_RND
Definition: X86ISelLowering.h:231
llvm::X86ISD::FNMADD_RND
@ FNMADD_RND
Definition: X86ISelLowering.h:561
llvm::X86ISD::MOVMSK
@ MOVMSK
Definition: X86ISelLowering.h:422
llvm::X86ISD::VP2INTERSECT
@ VP2INTERSECT
Definition: X86ISelLowering.h:714
llvm::X86ISD::TESTP
@ TESTP
Definition: X86ISelLowering.h:428
llvm::X86ISD::RDPKRU
@ RDPKRU
Definition: X86ISelLowering.h:661
llvm::X86TargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: X86ISelLowering.cpp:5456
llvm::X86ISD::AVG
@ AVG
Definition: X86ISelLowering.h:252
llvm::X86TargetLowering::isCommutativeBinOp
bool isCommutativeBinOp(unsigned Opcode) const override
Returns true if the opcode is a commutative binary operation.
Definition: X86ISelLowering.cpp:31954
llvm::X86ISD::CVTP2SI
@ CVTP2SI
Definition: X86ISelLowering.h:583
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2011
llvm::X86TargetLowering::BuildFILD
std::pair< SDValue, SDValue > BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:20105
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::X86TargetLowering::shouldSplatInsEltVarIndex
bool shouldSplatInsEltVarIndex(EVT VT) const override
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
Definition: X86ISelLowering.cpp:5523
llvm::X86TargetLowering::isLegalStoreImmediate
bool isLegalStoreImmediate(int64_t Imm) const override
Return true if the specified immediate is legal for the value input of a store instruction.
Definition: X86ISelLowering.cpp:32002
llvm::X86ISD::SHUFP
@ SHUFP
Definition: X86ISelLowering.h:448
llvm::X86ISD::SCALAR_SINT_TO_FP_RND
@ SCALAR_SINT_TO_FP_RND
Definition: X86ISelLowering.h:579
llvm::X86ISD::MULTISHIFT
@ MULTISHIFT
Definition: X86ISelLowering.h:386
llvm::X86TargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: X86ISelLowering.cpp:5288
llvm::X86ISD::VPSHL
@ VPSHL
Definition: X86ISelLowering.h:519
llvm::X86ISD::ADDSUB
@ ADDSUB
Combined add and sub on an FP vector.
Definition: X86ISelLowering.h:212
llvm::X86TargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: X86ISelLowering.cpp:2536
llvm::X86ISD::VALIGN
@ VALIGN
Definition: X86ISelLowering.h:444
llvm::X86ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: X86ISelLowering.h:27
llvm::X86TargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: X86ISelLowering.cpp:5439
llvm::X86ISD::SINT_TO_FP_RND
@ SINT_TO_FP_RND
Definition: X86ISelLowering.h:575
llvm::X86TargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: X86ISelLowering.cpp:5367
llvm::X86TargetLowering::isSafeMemOpType
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
Definition: X86ISelLowering.cpp:2341
llvm::X86TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: X86ISelLowering.cpp:31993
llvm::X86ISD::CONFLICT
@ CONFLICT
Definition: X86ISelLowering.h:263
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
llvm::X86ISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: X86ISelLowering.h:644
N
#define N
llvm::X86ISD::FLDCW16m
@ FLDCW16m
Definition: X86ISelLowering.h:791
llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: X86ISelLowering.cpp:2189
llvm::X86ISD::VREDUCES_SAE
@ VREDUCES_SAE
Definition: X86ISelLowering.h:494
llvm::X86ISD::VSHL
@ VSHL
Definition: X86ISelLowering.h:354
llvm::X86TargetLowering::getStackProbeSymbolName
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Definition: X86ISelLowering.cpp:52573
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4234
llvm::X86ISD::BEXTR
@ BEXTR
Definition: X86ISelLowering.h:408
llvm::X86ISD::AESDECWIDE128KL
@ AESDECWIDE128KL
Definition: X86ISelLowering.h:847
llvm::X86ISD::CVTPH2PS_SAE
@ CVTPH2PS_SAE
Definition: X86ISelLowering.h:691
llvm::X86ISD::PCMPISTR
@ PCMPISTR
Definition: X86ISelLowering.h:670
llvm::X86ISD::LCMPXCHG16_SAVE_RBX_DAG
@ LCMPXCHG16_SAVE_RBX_DAG
Definition: X86ISelLowering.h:765
llvm::X86ISD::CVTPS2PH
@ CVTPS2PH
Definition: X86ISelLowering.h:689
llvm::X86ISD::CMP
@ CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:84
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::X86ISD::FNSTCW16m
@ FNSTCW16m
Definition: X86ISelLowering.h:788
llvm::X86ISD::VMTRUNCSTORES
@ VMTRUNCSTORES
Definition: X86ISelLowering.h:835
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::X86TargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating exp...
Definition: X86ISelLowering.cpp:5359
RegName
#define RegName(no)
llvm::X86ISD::FANDN
@ FANDN
Bitwise logical ANDNOT of floating point values.
Definition: X86ISelLowering.h:55
llvm::X86ISD::CVTTS2SI
@ CVTTS2SI
Definition: X86ISelLowering.h:599
llvm::X86ISD::FSUB_RND
@ FSUB_RND
Definition: X86ISelLowering.h:218
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86ISD::CVTTP2SI
@ CVTTP2SI
Definition: X86ISelLowering.h:594
llvm::X86ISD::ADC
@ ADC
Definition: X86ISelLowering.h:399
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:490
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::X86ISD::VROTLI
@ VROTLI
Definition: X86ISelLowering.h:373
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::X86TargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: X86ISelLowering.cpp:5515
llvm::X86TargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: X86ISelLowering.h:1385
llvm::X86ISD::PCMPGT
@ PCMPGT
Definition: X86ISelLowering.h:381
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::X86ISD::FMSUB_RND
@ FMSUB_RND
Definition: X86ISelLowering.h:562
llvm::X86ISD::LXOR
@ LXOR
Definition: X86ISelLowering.h:772
llvm::X86TargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition: X86ISelLowering.cpp:4827
llvm::X86ISD::VFIXUPIMMS_SAE
@ VFIXUPIMMS_SAE
Definition: X86ISelLowering.h:484
llvm::X86ISD::FMAX_SAE
@ FMAX_SAE
Definition: X86ISelLowering.h:227
llvm::X86ISD::PTEST
@ PTEST
Definition: X86ISelLowering.h:425
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::X86ISD::OR
@ OR
Definition: X86ISelLowering.h:403
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::X86TargetLowering::getByValTypeAlignment
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
Definition: X86ISelLowering.cpp:2275
llvm::X86ISD::WrapperRIP
@ WrapperRIP
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
Definition: X86ISelLowering.h:152
llvm::X86TargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: X86ISelLowering.cpp:52484
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::X86ISD::FIST
@ FIST
This instruction implements a fp->int store from FP stack slots.
Definition: X86ISelLowering.h:811
llvm::X86TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: X86ISelLowering.cpp:52545
llvm::X86TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Definition: X86ISelLowering.cpp:2217
llvm::X86::rmDownward
@ rmDownward
Definition: X86ISelLowering.h:863
llvm::X86ISD::EXP2_SAE
@ EXP2_SAE
Definition: X86ISelLowering.h:686
llvm::X86ISD::UCOMI
@ UCOMI
Definition: X86ISelLowering.h:87
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::X86ISD::FGETEXPS
@ FGETEXPS
Definition: X86ISelLowering.h:238
llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const override
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
Definition: X86ISelLowering.cpp:39635
llvm::X86ISD::WIN_ALLOCA
@ WIN_ALLOCA
Definition: X86ISelLowering.h:635
llvm::X86TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: X86ISelLowering.cpp:51166
llvm::X86ISD::MCVTUI2P
@ MCVTUI2P
Definition: X86ISelLowering.h:615
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::X86TargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower interleaved store(s) into target specific instructions/intrinsics.
Definition: X86InterleavedAccess.cpp:827
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: X86ISelLowering.cpp:35017
llvm::X86ISD::VPCOM
@ VPCOM
Definition: X86ISelLowering.h:521
llvm::X86ISD::PINSRB
@ PINSRB
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
Definition: X86ISelLowering.h:184
llvm::X86ISD::STRICT_FCMP
@ STRICT_FCMP
X86 strict FP compare instructions.
Definition: X86ISelLowering.h:720
llvm::X86ISD::TLSBASEADDR
@ TLSBASEADDR
Definition: X86ISelLowering.h:294
llvm::X86ISD::VRANGE_SAE
@ VRANGE_SAE
Definition: X86ISelLowering.h:487
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:140
llvm::X86ISD::PMULUDQ
@ PMULUDQ
Definition: X86ISelLowering.h:529
llvm::X86ISD::AESENC128KL
@ AESENC128KL
Definition: X86ISelLowering.h:842
llvm::X86ISD::MMX_MOVD2W
@ MMX_MOVD2W
Copies a 32-bit value from the low word of a MMX vector to a GPR.
Definition: X86ISelLowering.h:164
llvm::X86ISD::STRICT_CVTPS2PH
@ STRICT_CVTPS2PH
Definition: X86ISelLowering.h:755
llvm::X86ISD::VSHRD
@ VSHRD
Definition: X86ISelLowering.h:451
llvm::X86TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: X86ISelLowering.cpp:31971
llvm::X86ISD::TC_RETURN
@ TC_RETURN
Tail call return.
Definition: X86ISelLowering.h:314
llvm::X86MaskedScatterSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1710
llvm::X86TargetLowering::isNarrowingProfitable
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
Definition: X86ISelLowering.cpp:32115
llvm::X86ISD::RCP28S
@ RCP28S
Definition: X86ISelLowering.h:683
llvm::X86ISD::NodeType
NodeType
Definition: X86ISelLowering.h:25
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1156
llvm::X86ISD::STRICT_CVTTP2UI
@ STRICT_CVTTP2UI
Definition: X86ISelLowering.h:732
llvm::X86ISD::VMTRUNC
@ VMTRUNC
Definition: X86ISelLowering.h:329
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::X86TargetLowering::reduceSelectOfFPConstantLoads
bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
Definition: X86ISelLowering.cpp:5279