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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 
19 
20 namespace llvm {
21  class X86Subtarget;
22  class X86TargetMachine;
23 
24  namespace X86ISD {
25  // X86 Specific DAG Nodes
26  enum NodeType : unsigned {
27  // Start the numbering where the builtin ops leave off.
29 
30  /// Bit scan forward.
31  BSF,
32  /// Bit scan reverse.
33  BSR,
34 
35  /// X86 funnel/double shift i16 instructions. These correspond to
36  /// X86::SHLDW and X86::SHRDW instructions which have different amt
37  /// modulo rules to generic funnel shifts.
38  /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.
41 
42  /// Bitwise logical AND of floating point values. This corresponds
43  /// to X86::ANDPS or X86::ANDPD.
45 
46  /// Bitwise logical OR of floating point values. This corresponds
47  /// to X86::ORPS or X86::ORPD.
48  FOR,
49 
50  /// Bitwise logical XOR of floating point values. This corresponds
51  /// to X86::XORPS or X86::XORPD.
53 
54  /// Bitwise logical ANDNOT of floating point values. This
55  /// corresponds to X86::ANDNPS or X86::ANDNPD.
57 
58  /// These operations represent an abstract X86 call
59  /// instruction, which includes a bunch of information. In particular the
60  /// operands of these node are:
61  ///
62  /// #0 - The incoming token chain
63  /// #1 - The callee
64  /// #2 - The number of arg bytes the caller pushes on the stack.
65  /// #3 - The number of arg bytes the callee pops off the stack.
66  /// #4 - The value to pass in AL/AX/EAX (optional)
67  /// #5 - The value to pass in DL/DX/EDX (optional)
68  ///
69  /// The result values of these nodes are:
70  ///
71  /// #0 - The outgoing token chain
72  /// #1 - The first register result value (optional)
73  /// #2 - The second register result value (optional)
74  ///
76 
77  /// Same as call except it adds the NoTrack prefix.
79 
80  // Pseudo for a OBJC call that gets emitted together with a special
81  // marker instruction.
83 
84  /// X86 compare and logical compare instructions.
85  CMP,
89 
90  /// X86 bit-test instructions.
91  BT,
92 
93  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94  /// operand, usually produced by a CMP instruction.
96 
97  /// X86 Select
99 
100  // Same as SETCC except it's materialized with a sbb and the value is all
101  // one's or all zero's.
102  SETCC_CARRY, // R = carry_bit ? ~0 : 0
103 
104  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105  /// Operands are two FP values to compare; result is a mask of
106  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
108 
109  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
110  /// and a version with SAE.
113 
114  /// X86 conditional moves. Operand 0 and operand 1 are the two values
115  /// to select from. Operand 2 is the condition code, and operand 3 is the
116  /// flag operand produced by a CMP or TEST instruction.
118 
119  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120  /// is the block to branch if condition is true, operand 2 is the
121  /// condition code, and operand 3 is the flag operand produced by a CMP
122  /// or TEST instruction.
124 
125  /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
126  /// operand 1 is the target address.
128 
129  /// Return with a flag operand. Operand 0 is the chain operand, operand
130  /// 1 is the number of bytes of stack to pop.
132 
133  /// Return from interrupt. Operand 0 is the number of bytes to pop.
135 
136  /// Repeat fill, corresponds to X86::REP_STOSx.
138 
139  /// Repeat move, corresponds to X86::REP_MOVSx.
141 
142  /// On Darwin, this node represents the result of the popl
143  /// at function entry, used for PIC code.
145 
146  /// A wrapper node for TargetConstantPool, TargetJumpTable,
147  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
148  /// MCSymbol and TargetBlockAddress.
150 
151  /// Special wrapper used under X86-64 PIC mode for RIP
152  /// relative displacements.
154 
155  /// Copies a 64-bit value from an MMX vector to the low word
156  /// of an XMM vector, with the high word zero filled.
158 
159  /// Copies a 64-bit value from the low word of an XMM vector
160  /// to an MMX vector.
162 
163  /// Copies a 32-bit value from the low word of a MMX
164  /// vector to a GPR.
166 
167  /// Copies a GPR into the low 32-bit word of a MMX vector
168  /// and zero out the high word.
170 
171  /// Extract an 8-bit value from a vector and zero extend it to
172  /// i32, corresponds to X86::PEXTRB.
174 
175  /// Extract a 16-bit value from a vector and zero extend it to
176  /// i32, corresponds to X86::PEXTRW.
178 
179  /// Insert any element of a 4 x float vector into any element
180  /// of a destination 4 x floatvector.
182 
183  /// Insert the lower 8-bits of a 32-bit value to a vector,
184  /// corresponds to X86::PINSRB.
186 
187  /// Insert the lower 16-bits of a 32-bit value to a vector,
188  /// corresponds to X86::PINSRW.
190 
191  /// Shuffle 16 8-bit values within a vector.
193 
194  /// Compute Sum of Absolute Differences.
196  /// Compute Double Block Packed Sum-Absolute-Differences
198 
199  /// Bitwise Logical AND NOT of Packed FP values.
201 
202  /// Blend where the selector is an immediate.
204 
205  /// Dynamic (non-constant condition) vector blend where only the sign bits
206  /// of the condition elements are used. This is used to enforce that the
207  /// condition mask is not valid for generic VSELECT optimizations. This
208  /// is also used to implement the intrinsics.
209  /// Operands are in VSELECT order: MASK, TRUE, FALSE
211 
212  /// Combined add and sub on an FP vector.
214 
215  // FP vector ops with rounding mode.
235 
236  // FP vector get exponent.
241  // Extract Normalized Mantissas.
246  // FP Scale.
251 
252  /// Integer horizontal add/sub.
255 
256  /// Floating point horizontal add/sub.
259 
260  // Detect Conflicts Within a Vector
262 
263  /// Floating point max and min.
266 
267  /// Commutative FMIN and FMAX.
270 
271  /// Scalar intrinsic floating point max and min.
274 
275  /// Floating point reciprocal-sqrt and reciprocal approximation.
276  /// Note that these typically require refinement
277  /// in order to obtain suitable precision.
280 
281  // AVX-512 reciprocal approximations with a little more precision.
286 
287  // Thread Local Storage.
289 
290  // Thread Local Storage. A call to get the start address
291  // of the TLS block for the current module.
293 
294  // Thread Local Storage. When calling to an OS provided
295  // thunk at the address from an earlier relocation.
297 
298  // Exception Handling helpers.
300 
301  // SjLj exception handling setjmp.
303 
304  // SjLj exception handling longjmp.
306 
307  // SjLj exception handling dispatch.
309 
310  /// Tail call return. See X86TargetLowering::LowerCall for
311  /// the list of operands.
313 
314  // Vector move to low scalar and zero higher vector elements.
316 
317  // Vector integer truncate.
319  // Vector integer truncate with unsigned/signed saturation.
322 
323  // Masked version of the above. Used when less than a 128-bit result is
324  // produced since the mask only applies to the lower elements and can't
325  // be represented by a select.
326  // SRC, PASSTHRU, MASK
330 
331  // Vector FP extend.
336 
337  // Vector FP round.
342 
343  // Masked version of above. Used for v2f64->v4f32.
344  // SRC, PASSTHRU, MASK
346 
347  // 128-bit vector logical left / right shift
350 
351  // Vector shift elements
355 
356  // Vector variable shift
360 
361  // Vector shift elements by immediate
365 
366  // Shifts of mask registers.
369 
370  // Bit rotate by immediate
373 
374  // Vector packed double/float comparison.
376 
377  // Vector integer comparisons.
380 
381  // v8i16 Horizontal minimum and position.
383 
385 
386  /// Vector comparison generating mask bits for fp and
387  /// integer signed and unsigned data types.
389  // Vector mask comparison generating mask bits for FP values.
391  // Vector mask comparison with SAE for FP values.
393 
394  // Arithmetic operations with FLAGS results.
401  OR,
404 
405  // Bit field extract.
408 
409  // Zero High Bits Starting with Specified Bit Position.
411 
412  // Parallel extract and deposit.
415 
416  // X86-specific multiply by immediate.
418 
419  // Vector sign bit extraction.
421 
422  // Vector bitwise comparisons.
424 
425  // Vector packed fp sign bitwise comparisons.
427 
428  // OR/AND test for masks.
431 
432  // ADD for masks.
434 
435  // Several flavors of instructions with vector shuffle behaviors.
436  // Saturated signed/unnsigned packing.
439  // Intra-lane alignr.
441  // AVX512 inter-lane alignr.
447  // VBMI2 Concat & Shift.
452  // Shuffle Packed Values at 128-bit granularity.
468 
469  // Variable Permute (VPERM).
470  // Res = VPERMV MaskV, V0
472 
473  // 3-op Variable Permute (VPERMT2).
474  // Res = VPERMV3 V0, MaskV, V1
476 
477  // Bitwise ternary logic.
479  // Fix Up Special Packed Float32/64 values.
484  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
489  // Reduce - Perform Reduction Transformation on scalar\packed FP.
494  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
495  // Also used by the legacy (V)ROUND intrinsics where we mask out the
496  // scaling part of the immediate.
501  // Tests Types Of a FP Values for packed types.
503  // Tests Types Of a FP Values for scalar types.
505 
506  // Broadcast (splat) scalar or element 0 of a vector. If the operand is
507  // a vector, this node may change the vector length as part of the splat.
509  // Broadcast mask to vector.
511 
512  /// SSE4A Extraction and Insertion.
515 
516  // XOP arithmetic/logical shifts.
519  // XOP signed/unsigned integer comparisons.
522  // XOP packed permute bytes.
524  // XOP two source permutation.
526 
527  // Vector multiply packed unsigned doubleword integers.
529  // Vector multiply packed signed doubleword integers.
531  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
533 
534  // Multiply and Add Packed Integers.
537 
538  // AVX512IFMA multiply and add.
539  // NOTE: These are different than the instruction and perform
540  // op0 x op1 + op2.
543 
544  // VNNI
549 
550  // FMA nodes.
551  // We use the target independent ISD::FMA for the non-inverted case.
557 
558  // FMA with rounding mode.
565 
566  // AVX512-FP16 complex addition and multiplication.
571 
576 
581 
586 
587  // Compress and expand.
590 
591  // Bits shuffle
593 
594  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
601 
602  // Vector float/double to signed/unsigned integer.
607  // Scalar float/double to signed/unsigned integer.
612 
613  // Vector float/double to signed/unsigned integer with truncation.
618  // Scalar float/double to signed/unsigned integer with truncation.
623 
624  // Vector signed/unsigned integer to float/double.
627 
628  // Masked versions of above. Used for v2f64->v4f32.
629  // SRC, PASSTHRU, MASK
636 
637  // Vector float to bfloat16.
638  // Convert TWO packed single data to one packed BF16 data
640  // Convert packed single data to packed BF16 data
642  // Masked version of above.
643  // SRC, PASSTHRU, MASK
645 
646  // Dot product of BF16 pairs to accumulated into
647  // packed single precision.
649 
650  // A stack checking function call. On Windows it's _chkstk call.
652 
653  // For allocating variable amounts of stack space when using
654  // segmented stacks. Check if the current stacklet has enough space, and
655  // falls back to heap allocation if not.
657 
658  // For allocating stack space when using stack clash protector.
659  // Allocation is performed by block, and each block is probed.
661 
662  // Memory barriers.
665 
666  // Get a random integer and indicate whether it is valid in CF.
668 
669  // Get a NIST SP800-90B & C compliant random integer and
670  // indicate whether it is valid in CF.
672 
673  // Protection keys
674  // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
675  // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
676  // value for ECX.
679 
680  // SSE42 string comparisons.
681  // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
682  // will emit one or two instructions based on which results are used. If
683  // flags and index/mask this allows us to use a single instruction since
684  // we won't have to pick and opcode for flags. Instead we can rely on the
685  // DAG to CSE everything and decide at isel.
688 
689  // Test if in transactional execution.
691 
692  // ERI instructions.
703 
704  // Conversions between float and half-float.
708 
709  // Masked version of above.
710  // SRC, RND, PASSTHRU, MASK
712 
713  // Galois Field Arithmetic Instructions
717 
718  // LWP insert record.
720 
721  // User level wait
724 
725  // Enqueue Stores Instructions
728 
729  // For avx512-vp2intersect
731 
732  // User level interrupts - testui
734 
735  /// X86 strict FP compare instructions.
738 
739  // Vector packed double/float comparison.
741 
742  /// Vector comparison generating mask bits for fp and
743  /// integer signed and unsigned data types.
745 
746  // Vector float/double to signed/unsigned integer with truncation.
749 
750  // Vector FP extend.
752 
753  // Vector FP round.
755 
756  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
757  // Also used by the legacy (V)ROUND intrinsics where we mask out the
758  // scaling part of the immediate.
760 
761  // Vector signed/unsigned integer to float/double.
764 
765  // Strict FMA nodes.
769 
770  // Conversions between float and half-float.
773 
774  // WARNING: Only add nodes here if they are stric FP nodes. Non-memory and
775  // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE.
776 
777  // Compare and swap.
782 
783  /// LOCK-prefixed arithmetic read-modify-write instructions.
784  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
793 
794  // Load, scalar_to_vector, and zero extend.
796 
797  // extract_vector_elt, store.
799 
800  // scalar broadcast from memory.
802 
803  // subvector broadcast from memory.
805 
806  // Store FP control word into i16 memory.
808 
809  // Load FP control word from i16 memory.
811 
812  /// This instruction implements FP_TO_SINT with the
813  /// integer destination in memory and a FP reg source. This corresponds
814  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
815  /// has two inputs (token chain and address) and two outputs (int value
816  /// and token chain). Memory VT specifies the type to store to.
818 
819  /// This instruction implements SINT_TO_FP with the
820  /// integer source in memory and FP reg result. This corresponds to the
821  /// X86::FILD*m instructions. It has two inputs (token chain and address)
822  /// and two outputs (FP value and token chain). The integer source type is
823  /// specified by the memory VT.
825 
826  /// This instruction implements a fp->int store from FP stack
827  /// slots. This corresponds to the fist instruction. It takes a
828  /// chain operand, value to store, address, and glue. The memory VT
829  /// specifies the type to store as.
831 
832  /// This instruction implements an extending load to FP stack slots.
833  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
834  /// operand, and ptr to load from. The memory VT specifies the type to
835  /// load from.
837 
838  /// This instruction implements a truncating store from FP stack
839  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
840  /// chain operand, value to store, address, and glue. The memory VT
841  /// specifies the type to store as.
843 
844  /// These instructions grab the address of the next argument
845  /// from a va_list. (reads and modifies the va_list in memory)
848 
849  // Vector truncating store with unsigned/signed saturation
852  // Vector truncating masked store with unsigned/signed saturation
855 
856  // X86 specific gather and scatter
859 
860  // Key locker nodes that produce flags.
869 
870  // Save xmm argument registers to the stack, according to %al. An operator
871  // is needed so that this can be expanded with control flow.
873 
874  // WARNING: Do not add anything in the end unless you want the node to
875  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
876  // opcodes will be thought as target memory ops!
877  };
878  } // end namespace X86ISD
879 
880  namespace X86 {
881  /// Current rounding mode is represented in bits 11:10 of FPSR. These
882  /// values are same as corresponding constants for rounding mode used
883  /// in glibc.
885  rmToNearest = 0, // FE_TONEAREST
886  rmDownward = 1 << 10, // FE_DOWNWARD
887  rmUpward = 2 << 10, // FE_UPWARD
888  rmTowardZero = 3 << 10, // FE_TOWARDZERO
889  rmMask = 3 << 10 // Bit mask selecting rounding mode
890  };
891  }
892 
893  /// Define some predicates that are used for node matching.
894  namespace X86 {
895  /// Returns true if Elt is a constant zero or floating point constant +0.0.
896  bool isZeroNode(SDValue Elt);
897 
898  /// Returns true of the given offset can be
899  /// fit into displacement field of the instruction.
900  bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
901  bool hasSymbolicDisplacement);
902 
903  /// Determines whether the callee is required to pop its
904  /// own arguments. Callee pop is necessary to support tail calls.
906  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
907 
908  /// If Op is a constant whose elements are all the same constant or
909  /// undefined, return true and return the constant value in \p SplatVal.
910  /// If we have undef bits that don't cover an entire element, we treat these
911  /// as zero if AllowPartialUndefs is set, else we fail and return false.
912  bool isConstantSplat(SDValue Op, APInt &SplatVal,
913  bool AllowPartialUndefs = true);
914 
915  /// Check if Op is a load operation that could be folded into some other x86
916  /// instruction as a memory operand. Example: vpaddd (%rdi), %xmm0, %xmm0.
917  bool mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget,
918  bool AssumeSingleUse = false);
919 
920  /// Check if Op is a load operation that could be folded into a vector splat
921  /// instruction as a memory operand. Example: vbroadcastss 16(%rdi), %xmm2.
922  bool mayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT,
923  const X86Subtarget &Subtarget,
924  bool AssumeSingleUse = false);
925 
926  /// Check if Op is a value that could be used to fold a store into some
927  /// other x86 instruction as a memory operand. Ex: pextrb $0, %xmm0, (%rdi).
928  bool mayFoldIntoStore(SDValue Op);
929 
930  /// Check if Op is an operation that could be folded into a zero extend x86
931  /// instruction.
932  bool mayFoldIntoZeroExtend(SDValue Op);
933  } // end namespace X86
934 
935  //===--------------------------------------------------------------------===//
936  // X86 Implementation of the TargetLowering interface
937  class X86TargetLowering final : public TargetLowering {
938  public:
939  explicit X86TargetLowering(const X86TargetMachine &TM,
940  const X86Subtarget &STI);
941 
942  unsigned getJumpTableEncoding() const override;
943  bool useSoftFloat() const override;
944 
945  void markLibCallAttributes(MachineFunction *MF, unsigned CC,
946  ArgListTy &Args) const override;
947 
948  MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
949  return MVT::i8;
950  }
951 
952  const MCExpr *
954  const MachineBasicBlock *MBB, unsigned uid,
955  MCContext &Ctx) const override;
956 
957  /// Returns relocation base for the given PIC jumptable.
959  SelectionDAG &DAG) const override;
960  const MCExpr *
962  unsigned JTI, MCContext &Ctx) const override;
963 
964  /// Return the desired alignment for ByVal aggregate
965  /// function arguments in the caller parameter area. For X86, aggregates
966  /// that contains are placed at 16-byte boundaries while the rest are at
967  /// 4-byte boundaries.
969  const DataLayout &DL) const override;
970 
972  const AttributeList &FuncAttributes) const override;
973 
974  /// Returns true if it's safe to use load / store of the
975  /// specified type to expand memcpy / memset inline. This is mostly true
976  /// for all types except for some special cases. For example, on X86
977  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
978  /// also does type conversion. Note the specified type doesn't have to be
979  /// legal as the hook is used before type legalization.
980  bool isSafeMemOpType(MVT VT) const override;
981 
982  /// Returns true if the target allows unaligned memory accesses of the
983  /// specified type. Returns whether it is "fast" in the last argument.
984  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
986  bool *Fast) const override;
987 
988  /// Provide custom lowering hooks for some operations.
989  ///
990  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
991 
992  /// Replace the results of node with an illegal result
993  /// type with new values built out of custom code.
994  ///
996  SelectionDAG &DAG) const override;
997 
998  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
999 
1000  /// Return true if the target has native support for
1001  /// the specified value type and it is 'desirable' to use the type for the
1002  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1003  /// instruction encodings are longer and some i16 instructions are slow.
1004  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
1005 
1006  /// Return true if the target has native support for the
1007  /// specified value type and it is 'desirable' to use the type. e.g. On x86
1008  /// i16 is legal, but undesirable since i16 instruction encodings are longer
1009  /// and some i16 instructions are slow.
1010  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
1011 
1012  /// Return the newly negated expression if the cost is not expensive and
1013  /// set the cost in \p Cost to indicate that if it is cheaper or neutral to
1014  /// do the negation.
1016  bool LegalOperations, bool ForCodeSize,
1017  NegatibleCost &Cost,
1018  unsigned Depth) const override;
1019 
1022  MachineBasicBlock *MBB) const override;
1023 
1024  /// This method returns the name of a target specific DAG node.
1025  const char *getTargetNodeName(unsigned Opcode) const override;
1026 
1027  /// Do not merge vector stores after legalization because that may conflict
1028  /// with x86-specific store splitting optimizations.
1029  bool mergeStoresAfterLegalization(EVT MemVT) const override {
1030  return !MemVT.isVector();
1031  }
1032 
1033  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
1034  const MachineFunction &MF) const override;
1035 
1036  bool isCheapToSpeculateCttz() const override;
1037 
1038  bool isCheapToSpeculateCtlz() const override;
1039 
1040  bool isCtlzFast() const override;
1041 
1042  bool hasBitPreservingFPLogic(EVT VT) const override;
1043 
1044  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
1045  // If the pair to store is a mixture of float and int values, we will
1046  // save two bitwise instructions and one float-to-int instruction and
1047  // increase one store instruction. There is potentially a more
1048  // significant benefit because it avoids the float->int domain switch
1049  // for input value. So It is more likely a win.
1050  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
1051  (LTy.isInteger() && HTy.isFloatingPoint()))
1052  return true;
1053  // If the pair only contains int values, we will save two bitwise
1054  // instructions and increase one store instruction (costing one more
1055  // store buffer). Since the benefit is more blurred so we leave
1056  // such pair out until we get testcase to prove it is a win.
1057  return false;
1058  }
1059 
1060  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1061 
1062  bool hasAndNotCompare(SDValue Y) const override;
1063 
1064  bool hasAndNot(SDValue Y) const override;
1065 
1066  bool hasBitTest(SDValue X, SDValue Y) const override;
1067 
1070  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
1071  SelectionDAG &DAG) const override;
1072 
1074  CombineLevel Level) const override;
1075 
1076  bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
1077 
1078  bool
1080  unsigned KeptBits) const override {
1081  // For vectors, we don't have a preference..
1082  if (XVT.isVector())
1083  return false;
1084 
1085  auto VTIsOk = [](EVT VT) -> bool {
1086  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
1087  VT == MVT::i64;
1088  };
1089 
1090  // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
1091  // XVT will be larger than KeptBitsVT.
1092  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
1093  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
1094  }
1095 
1096  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
1097 
1098  bool shouldSplatInsEltVarIndex(EVT VT) const override;
1099 
1100  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override {
1101  // Converting to sat variants holds little benefit on X86 as we will just
1102  // need to saturate the value back using fp arithmatic.
1104  }
1105 
1106  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
1107  return VT.isScalarInteger();
1108  }
1109 
1110  /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
1111  MVT hasFastEqualityCompare(unsigned NumBits) const override;
1112 
1113  /// Return the value type to use for ISD::SETCC.
1115  EVT VT) const override;
1116 
1118  const APInt &DemandedElts,
1119  TargetLoweringOpt &TLO) const override;
1120 
1121  /// Determine which of the bits specified in Mask are known to be either
1122  /// zero or one and return them in the KnownZero/KnownOne bitsets.
1124  KnownBits &Known,
1125  const APInt &DemandedElts,
1126  const SelectionDAG &DAG,
1127  unsigned Depth = 0) const override;
1128 
1129  /// Determine the number of bits in the operation that are sign bits.
1131  const APInt &DemandedElts,
1132  const SelectionDAG &DAG,
1133  unsigned Depth) const override;
1134 
1136  const APInt &DemandedElts,
1137  APInt &KnownUndef,
1138  APInt &KnownZero,
1139  TargetLoweringOpt &TLO,
1140  unsigned Depth) const override;
1141 
1143  const APInt &DemandedElts,
1144  unsigned MaskIndex,
1145  TargetLoweringOpt &TLO,
1146  unsigned Depth) const;
1147 
1149  const APInt &DemandedBits,
1150  const APInt &DemandedElts,
1151  KnownBits &Known,
1152  TargetLoweringOpt &TLO,
1153  unsigned Depth) const override;
1154 
1156  SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1157  SelectionDAG &DAG, unsigned Depth) const override;
1158 
1159  bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
1160  APInt &UndefElts,
1161  unsigned Depth) const override;
1162 
1163  const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
1164 
1165  SDValue unwrapAddress(SDValue N) const override;
1166 
1168 
1169  bool ExpandInlineAsm(CallInst *CI) const override;
1170 
1171  ConstraintType getConstraintType(StringRef Constraint) const override;
1172 
1173  /// Examine constraint string and operand type and determine a weight value.
1174  /// The operand object must already have been set up with the operand type.
1176  getSingleConstraintMatchWeight(AsmOperandInfo &info,
1177  const char *constraint) const override;
1178 
1179  const char *LowerXConstraint(EVT ConstraintVT) const override;
1180 
1181  /// Lower the specified operand into the Ops vector. If it is invalid, don't
1182  /// add anything to Ops. If hasMemory is true it means one of the asm
1183  /// constraint of the inline asm instruction being processed is 'm'.
1185  std::string &Constraint,
1186  std::vector<SDValue> &Ops,
1187  SelectionDAG &DAG) const override;
1188 
1189  unsigned
1190  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1191  if (ConstraintCode == "v")
1192  return InlineAsm::Constraint_v;
1193  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1194  }
1195 
1196  /// Handle Lowering flag assembly outputs.
1198  const SDLoc &DL,
1199  const AsmOperandInfo &Constraint,
1200  SelectionDAG &DAG) const override;
1201 
1202  /// Given a physical register constraint
1203  /// (e.g. {edx}), return the register number and the register class for the
1204  /// register. This should only be used for C_Register constraints. On
1205  /// error, this returns a register number of 0.
1206  std::pair<unsigned, const TargetRegisterClass *>
1208  StringRef Constraint, MVT VT) const override;
1209 
1210  /// Return true if the addressing mode represented
1211  /// by AM is legal for this target, for a load/store of the specified type.
1212  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1213  Type *Ty, unsigned AS,
1214  Instruction *I = nullptr) const override;
1215 
1216  /// Return true if the specified immediate is legal
1217  /// icmp immediate, that is the target has icmp instructions which can
1218  /// compare a register against the immediate without having to materialize
1219  /// the immediate into a register.
1220  bool isLegalICmpImmediate(int64_t Imm) const override;
1221 
1222  /// Return true if the specified immediate is legal
1223  /// add immediate, that is the target has add instructions which can
1224  /// add a register and the immediate without having to materialize
1225  /// the immediate into a register.
1226  bool isLegalAddImmediate(int64_t Imm) const override;
1227 
1228  bool isLegalStoreImmediate(int64_t Imm) const override;
1229 
1230  /// Return the cost of the scaling factor used in the addressing
1231  /// mode represented by AM for this target, for a load/store
1232  /// of the specified type.
1233  /// If the AM is supported, the return value must be >= 0.
1234  /// If the AM is not supported, it returns a negative value.
1236  const AddrMode &AM, Type *Ty,
1237  unsigned AS) const override;
1238 
1239  /// This is used to enable splatted operand transforms for vector shifts
1240  /// and vector funnel shifts.
1241  bool isVectorShiftByScalarCheap(Type *Ty) const override;
1242 
1243  /// Add x86-specific opcodes to the default list.
1244  bool isBinOp(unsigned Opcode) const override;
1245 
1246  /// Returns true if the opcode is a commutative binary operation.
1247  bool isCommutativeBinOp(unsigned Opcode) const override;
1248 
1249  /// Return true if it's free to truncate a value of
1250  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1251  /// register EAX to i16 by referencing its sub-register AX.
1252  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
1253  bool isTruncateFree(EVT VT1, EVT VT2) const override;
1254 
1255  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
1256 
1257  /// Return true if any actual instruction that defines a
1258  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1259  /// register. This does not necessarily include registers defined in
1260  /// unknown ways, such as incoming arguments, or copies from unknown
1261  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1262  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1263  /// all instructions that define 32-bit values implicit zero-extend the
1264  /// result out to 64 bits.
1265  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
1266  bool isZExtFree(EVT VT1, EVT VT2) const override;
1267  bool isZExtFree(SDValue Val, EVT VT2) const override;
1268 
1270  SmallVectorImpl<Use *> &Ops) const override;
1271  bool shouldConvertPhiType(Type *From, Type *To) const override;
1272 
1273  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1274  /// extend node) is profitable.
1275  bool isVectorLoadExtDesirable(SDValue) const override;
1276 
1277  /// Return true if an FMA operation is faster than a pair of fmul and fadd
1278  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
1279  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
1281  EVT VT) const override;
1282 
1283  /// Return true if it's profitable to narrow
1284  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1285  /// from i32 to i8 but not from i32 to i16.
1286  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
1287 
1288  bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
1289  EVT VT) const override;
1290 
1291  /// Given an intrinsic, checks if on the target the intrinsic will need to map
1292  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1293  /// true and stores the intrinsic information into the IntrinsicInfo that was
1294  /// passed to the function.
1295  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1296  MachineFunction &MF,
1297  unsigned Intrinsic) const override;
1298 
1299  /// Returns true if the target can instruction select the
1300  /// specified FP immediate natively. If false, the legalizer will
1301  /// materialize the FP immediate as a load from a constant pool.
1302  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1303  bool ForCodeSize) const override;
1304 
1305  /// Targets can use this to indicate that they only support *some*
1306  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1307  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1308  /// be legal.
1309  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1310 
1311  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1312  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1313  /// constant pool entry.
1314  bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1315 
1316  /// Returns true if lowering to a jump table is allowed.
1317  bool areJTsAllowed(const Function *Fn) const override;
1318 
1320  EVT ConditionVT) const override;
1321 
1322  /// If true, then instruction selection should
1323  /// seek to shrink the FP constant of the specified type to a smaller type
1324  /// in order to save space and / or reduce runtime.
1325  bool ShouldShrinkFPConstant(EVT VT) const override;
1326 
1327  /// Return true if we believe it is correct and profitable to reduce the
1328  /// load node to a smaller type.
1330  EVT NewVT) const override;
1331 
1332  /// Return true if the specified scalar FP type is computed in an SSE
1333  /// register, not on the X87 floating point stack.
1334  bool isScalarFPTypeInSSEReg(EVT VT) const;
1335 
1336  /// Returns true if it is beneficial to convert a load of a constant
1337  /// to just the constant itself.
1338  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1339  Type *Ty) const override;
1340 
1341  bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override;
1342 
1343  bool convertSelectOfConstantsToMath(EVT VT) const override;
1344 
1346  SDValue C) const override;
1347 
1348  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1349  /// with this index.
1350  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1351  unsigned Index) const override;
1352 
1353  /// Scalar ops always have equal or better analysis/performance/power than
1354  /// the vector equivalent, so this always makes sense if the scalar op is
1355  /// supported.
1356  bool shouldScalarizeBinop(SDValue) const override;
1357 
1358  /// Extract of a scalar FP value from index 0 of a vector is free.
1359  bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1360  EVT EltVT = VT.getScalarType();
1361  return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
1362  }
1363 
1364  /// Overflow nodes should get combined/lowered to optimal instructions
1365  /// (they should allow eliminating explicit compares by getting flags from
1366  /// math ops).
1367  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
1368  bool MathUsed) const override;
1369 
1370  bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
1371  unsigned AddrSpace) const override {
1372  // If we can replace more than 2 scalar stores, there will be a reduction
1373  // in instructions even after we add a vector constant load.
1374  return NumElem > 2;
1375  }
1376 
1377  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
1378  const SelectionDAG &DAG,
1379  const MachineMemOperand &MMO) const override;
1380 
1381  /// Intel processors have a unified instruction and data cache
1382  const char * getClearCacheBuiltinName() const override {
1383  return nullptr; // nothing to do, move along.
1384  }
1385 
1386  Register getRegisterByName(const char* RegName, LLT VT,
1387  const MachineFunction &MF) const override;
1388 
1389  /// If a physical register, this returns the register that receives the
1390  /// exception address on entry to an EH pad.
1391  Register
1392  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1393 
1394  /// If a physical register, this returns the register that receives the
1395  /// exception typeid on entry to a landing pad.
1396  Register
1397  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1398 
1399  virtual bool needsFixedCatchObjects() const override;
1400 
1401  /// This method returns a target specific FastISel object,
1402  /// or null if the target does not support "fast" ISel.
1404  const TargetLibraryInfo *libInfo) const override;
1405 
1406  /// If the target has a standard location for the stack protector cookie,
1407  /// returns the address of that location. Otherwise, returns nullptr.
1408  Value *getIRStackGuard(IRBuilderBase &IRB) const override;
1409 
1410  bool useLoadStackGuardNode() const override;
1411  bool useStackGuardXorFP() const override;
1412  void insertSSPDeclarations(Module &M) const override;
1413  Value *getSDagStackGuard(const Module &M) const override;
1414  Function *getSSPStackGuardCheck(const Module &M) const override;
1416  const SDLoc &DL) const override;
1417 
1418 
1419  /// Return true if the target stores SafeStack pointer at a fixed offset in
1420  /// some non-standard address space, and populates the address space and
1421  /// offset as appropriate.
1422  Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
1423 
1424  std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
1425  SDValue Chain, SDValue Pointer,
1426  MachinePointerInfo PtrInfo,
1427  Align Alignment,
1428  SelectionDAG &DAG) const;
1429 
1430  /// Customize the preferred legalization strategy for certain types.
1431  LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1432 
1433  bool softPromoteHalfType() const override { return true; }
1434 
1436  EVT VT) const override;
1437 
1439  CallingConv::ID CC,
1440  EVT VT) const override;
1441 
1443  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
1444  unsigned &NumIntermediates, MVT &RegisterVT) const override;
1445 
1446  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1447 
1448  bool supportSwiftError() const override;
1449 
1450  bool hasStackProbeSymbol(MachineFunction &MF) const override;
1451  bool hasInlineStackProbe(MachineFunction &MF) const override;
1453 
1454  unsigned getStackProbeSize(MachineFunction &MF) const;
1455 
1456  bool hasVectorBlend() const override { return true; }
1457 
1458  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1459 
1460  /// Lower interleaved load(s) into target specific
1461  /// instructions/intrinsics.
1462  bool lowerInterleavedLoad(LoadInst *LI,
1464  ArrayRef<unsigned> Indices,
1465  unsigned Factor) const override;
1466 
1467  /// Lower interleaved store(s) into target specific
1468  /// instructions/intrinsics.
1470  unsigned Factor) const override;
1471 
1473  SDValue Addr, SelectionDAG &DAG)
1474  const override;
1475 
1476  Align getPrefLoopAlignment(MachineLoop *ML) const override;
1477 
1478  protected:
1479  std::pair<const TargetRegisterClass *, uint8_t>
1481  MVT VT) const override;
1482 
1483  private:
1484  /// Keep a reference to the X86Subtarget around so that we can
1485  /// make the right decision when generating code for different targets.
1486  const X86Subtarget &Subtarget;
1487 
1488  /// A list of legal FP immediates.
1489  std::vector<APFloat> LegalFPImmediates;
1490 
1491  /// Indicate that this x86 target can instruction
1492  /// select the specified FP immediate natively.
1493  void addLegalFPImmediate(const APFloat& Imm) {
1494  LegalFPImmediates.push_back(Imm);
1495  }
1496 
1497  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1498  CallingConv::ID CallConv, bool isVarArg,
1499  const SmallVectorImpl<ISD::InputArg> &Ins,
1500  const SDLoc &dl, SelectionDAG &DAG,
1501  SmallVectorImpl<SDValue> &InVals,
1502  uint32_t *RegMask) const;
1503  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1504  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1505  const SDLoc &dl, SelectionDAG &DAG,
1506  const CCValAssign &VA, MachineFrameInfo &MFI,
1507  unsigned i) const;
1508  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1509  const SDLoc &dl, SelectionDAG &DAG,
1510  const CCValAssign &VA,
1511  ISD::ArgFlagsTy Flags, bool isByval) const;
1512 
1513  // Call lowering helpers.
1514 
1515  /// Check whether the call is eligible for tail call optimization. Targets
1516  /// that want to do tail call optimization should implement this function.
1517  bool IsEligibleForTailCallOptimization(
1518  SDValue Callee, CallingConv::ID CalleeCC, bool IsCalleeStackStructRet,
1519  bool isVarArg, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs,
1520  const SmallVectorImpl<SDValue> &OutVals,
1521  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1522  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1523  SDValue Chain, bool IsTailCall,
1524  bool Is64Bit, int FPDiff,
1525  const SDLoc &dl) const;
1526 
1527  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1528  SelectionDAG &DAG) const;
1529 
1530  unsigned getAddressSpace() const;
1531 
1532  SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned,
1533  SDValue &Chain) const;
1534  SDValue LRINT_LLRINTHelper(SDNode *N, SelectionDAG &DAG) const;
1535 
1536  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1537  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1538  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1539  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1540 
1541  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr,
1542  const unsigned char OpFlags = 0) const;
1543  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1544  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1545  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1546  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1547  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1548 
1549  /// Creates target global address or external symbol nodes for calls or
1550  /// other uses.
1551  SDValue LowerGlobalOrExternal(SDValue Op, SelectionDAG &DAG,
1552  bool ForCall) const;
1553 
1554  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1555  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1556  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1557  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1558  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1559  SDValue LowerLRINT_LLRINT(SDValue Op, SelectionDAG &DAG) const;
1560  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1561  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1562  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1563  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1564  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1565  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1566  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1567  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1568  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1569  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1570  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1571  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1572  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1573  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1574  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1575  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1576  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1577  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1578  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1579  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1580  SDValue LowerWin64_FP_TO_INT128(SDValue Op, SelectionDAG &DAG,
1581  SDValue &Chain) const;
1582  SDValue LowerWin64_INT128_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1583  SDValue LowerGC_TRANSITION(SDValue Op, SelectionDAG &DAG) const;
1584  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1585  SDValue lowerFaddFsub(SDValue Op, SelectionDAG &DAG) const;
1586  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1587  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1588 
1589  SDValue
1590  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1591  const SmallVectorImpl<ISD::InputArg> &Ins,
1592  const SDLoc &dl, SelectionDAG &DAG,
1593  SmallVectorImpl<SDValue> &InVals) const override;
1594  SDValue LowerCall(CallLoweringInfo &CLI,
1595  SmallVectorImpl<SDValue> &InVals) const override;
1596 
1597  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1598  const SmallVectorImpl<ISD::OutputArg> &Outs,
1599  const SmallVectorImpl<SDValue> &OutVals,
1600  const SDLoc &dl, SelectionDAG &DAG) const override;
1601 
1602  bool supportSplitCSR(MachineFunction *MF) const override {
1603  return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
1604  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1605  }
1606  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1607  void insertCopiesSplitCSR(
1608  MachineBasicBlock *Entry,
1609  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1610 
1611  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1612 
1613  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1614 
1615  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1616  ISD::NodeType ExtendKind) const override;
1617 
1618  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1619  bool isVarArg,
1620  const SmallVectorImpl<ISD::OutputArg> &Outs,
1621  LLVMContext &Context) const override;
1622 
1623  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1624 
1626  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
1628  shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1630  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1632  shouldExpandLogicAtomicRMWInIR(AtomicRMWInst *AI) const;
1633  void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const override;
1634 
1635  LoadInst *
1636  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1637 
1638  bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const override;
1639  bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const override;
1640 
1641  bool needsCmpXchgNb(Type *MemType) const;
1642 
1643  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1644  MachineBasicBlock *DispatchBB, int FI) const;
1645 
1646  // Utility function to emit the low-level va_arg code for X86-64.
1647  MachineBasicBlock *
1648  EmitVAARGWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
1649 
1650  /// Utility function to emit the xmm reg save portion of va_start.
1651  MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1652  MachineInstr &MI2,
1653  MachineBasicBlock *BB) const;
1654 
1655  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1656  MachineBasicBlock *BB) const;
1657 
1658  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1659  MachineBasicBlock *BB) const;
1660 
1661  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1662  MachineBasicBlock *BB) const;
1663 
1664  MachineBasicBlock *EmitLoweredProbedAlloca(MachineInstr &MI,
1665  MachineBasicBlock *BB) const;
1666 
1667  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1668  MachineBasicBlock *BB) const;
1669 
1670  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1671  MachineBasicBlock *BB) const;
1672 
1673  MachineBasicBlock *EmitLoweredIndirectThunk(MachineInstr &MI,
1674  MachineBasicBlock *BB) const;
1675 
1676  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1677  MachineBasicBlock *MBB) const;
1678 
1679  void emitSetJmpShadowStackFix(MachineInstr &MI,
1680  MachineBasicBlock *MBB) const;
1681 
1682  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1683  MachineBasicBlock *MBB) const;
1684 
1685  MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1686  MachineBasicBlock *MBB) const;
1687 
1688  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1689  MachineBasicBlock *MBB) const;
1690 
1691  /// Emit flags for the given setcc condition and operands. Also returns the
1692  /// corresponding X86 condition code constant in X86CC.
1693  SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC,
1694  const SDLoc &dl, SelectionDAG &DAG,
1695  SDValue &X86CC) const;
1696 
1697  /// Check if replacement of SQRT with RSQRT should be disabled.
1698  bool isFsqrtCheap(SDValue Op, SelectionDAG &DAG) const override;
1699 
1700  /// Use rsqrt* to speed up sqrt calculations.
1701  SDValue getSqrtEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1702  int &RefinementSteps, bool &UseOneConstNR,
1703  bool Reciprocal) const override;
1704 
1705  /// Use rcp* to speed up fdiv calculations.
1706  SDValue getRecipEstimate(SDValue Op, SelectionDAG &DAG, int Enabled,
1707  int &RefinementSteps) const override;
1708 
1709  /// Reassociate floating point divisions into multiply by reciprocal.
1710  unsigned combineRepeatedFPDivisors() const override;
1711 
1712  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1713  SmallVectorImpl<SDNode *> &Created) const override;
1714  };
1715 
1716  namespace X86 {
1717  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1718  const TargetLibraryInfo *libInfo);
1719  } // end namespace X86
1720 
1721  // X86 specific Gather/Scatter nodes.
1722  // The class has the same order of operands as MaskedGatherScatterSDNode for
1723  // convenience.
1725  public:
1726  // This is a intended as a utility and should never be directly created.
1727  X86MaskedGatherScatterSDNode() = delete;
1728  ~X86MaskedGatherScatterSDNode() = delete;
1729 
1730  const SDValue &getBasePtr() const { return getOperand(3); }
1731  const SDValue &getIndex() const { return getOperand(4); }
1732  const SDValue &getMask() const { return getOperand(2); }
1733  const SDValue &getScale() const { return getOperand(5); }
1734 
1735  static bool classof(const SDNode *N) {
1736  return N->getOpcode() == X86ISD::MGATHER ||
1737  N->getOpcode() == X86ISD::MSCATTER;
1738  }
1739  };
1740 
1742  public:
1743  const SDValue &getPassThru() const { return getOperand(1); }
1744 
1745  static bool classof(const SDNode *N) {
1746  return N->getOpcode() == X86ISD::MGATHER;
1747  }
1748  };
1749 
1751  public:
1752  const SDValue &getValue() const { return getOperand(1); }
1753 
1754  static bool classof(const SDNode *N) {
1755  return N->getOpcode() == X86ISD::MSCATTER;
1756  }
1757  };
1758 
1759  /// Generate unpacklo/unpackhi shuffle mask.
1760  void createUnpackShuffleMask(EVT VT, SmallVectorImpl<int> &Mask, bool Lo,
1761  bool Unary);
1762 
1763  /// Similar to unpacklo/unpackhi, but without the 128-bit lane limitation
1764  /// imposed by AVX and specific to the unary pattern. Example:
1765  /// v8iX Lo --> <0, 0, 1, 1, 2, 2, 3, 3>
1766  /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7>
1767  void createSplat2ShuffleMask(MVT VT, SmallVectorImpl<int> &Mask, bool Lo);
1768 
1769 } // end namespace llvm
1770 
1771 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
llvm::X86ISD::FDIVS
@ FDIVS
Definition: X86ISelLowering.h:226
llvm::X86ISD::UINT_TO_FP_RND
@ UINT_TO_FP_RND
Definition: X86ISelLowering.h:596
llvm::X86ISD::VFPROUND
@ VFPROUND
Definition: X86ISelLowering.h:338
llvm::X86ISD::RCP28S_SAE
@ RCP28S_SAE
Definition: X86ISelLowering.h:700
i
i
Definition: README.txt:29
llvm::X86ISD::EXPAND
@ EXPAND
Definition: X86ISelLowering.h:589
llvm::X86ISD::VGETMANTS_SAE
@ VGETMANTS_SAE
Definition: X86ISelLowering.h:245
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::X86ISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: X86ISelLowering.h:737
llvm::X86ISD::STRICT_VFPEXT
@ STRICT_VFPEXT
Definition: X86ISelLowering.h:751
llvm::X86ISD::FMUL_RND
@ FMUL_RND
Definition: X86ISelLowering.h:222
llvm::X86TargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: X86ISelLowering.cpp:55319
llvm::X86TargetLowering::isCtlzFast
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition: X86ISelLowering.cpp:5723
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::X86ISD::UMWAIT
@ UMWAIT
Definition: X86ISelLowering.h:722
llvm::X86ISD::STRICT_VRNDSCALE
@ STRICT_VRNDSCALE
Definition: X86ISelLowering.h:759
llvm::X86TargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: X86ISelLowering.cpp:27833
llvm::X86ISD::PCMPESTR
@ PCMPESTR
Definition: X86ISelLowering.h:687
llvm::X86TargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: X86ISelLowering.cpp:54957
llvm::X86ISD::TLSADDR
@ TLSADDR
Definition: X86ISelLowering.h:288
llvm::X86ISD::VFCMULCSH_RND
@ VFCMULCSH_RND
Definition: X86ISelLowering.h:585
llvm::X86ISD::AESDEC128KL
@ AESDEC128KL
Definition: X86ISelLowering.h:862
llvm::X86ISD::FADD_RND
@ FADD_RND
Definition: X86ISelLowering.h:216
llvm::X86ISD::FMINS
@ FMINS
Definition: X86ISelLowering.h:273
llvm::X86ISD::FMAXS_SAE
@ FMAXS_SAE
Definition: X86ISelLowering.h:229
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::X86TargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: X86ISelLowering.h:1106
llvm::X86MaskedGatherScatterSDNode::getIndex
const SDValue & getIndex() const
Definition: X86ISelLowering.h:1731
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::X86ISD::PACKUS
@ PACKUS
Definition: X86ISelLowering.h:438
llvm::X86ISD::RCP28_SAE
@ RCP28_SAE
Definition: X86ISelLowering.h:698
llvm::X86ISD::PEXTRW
@ PEXTRW
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
Definition: X86ISelLowering.h:177
llvm::X86ISD::VPERMIL2
@ VPERMIL2
Definition: X86ISelLowering.h:525
llvm::X86ISD::SCALEFS_RND
@ SCALEFS_RND
Definition: X86ISelLowering.h:250
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::X86ISD::MCVTSI2P
@ MCVTSI2P
Definition: X86ISelLowering.h:634
llvm::X86TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:5192
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::X86TargetLowering::hasStackProbeSymbol
bool hasStackProbeSymbol(MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Definition: X86ISelLowering.cpp:55839
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::X86TargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Return true if sinking I's operands to the same basic block as I is profitable, e....
Definition: X86ISelLowering.cpp:33567
llvm::X86ISD::VFCMULC_RND
@ VFCMULC_RND
Definition: X86ISelLowering.h:575
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::X86TargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: X86ISelLowering.cpp:36207
llvm::X86::mayFoldLoadIntoBroadcastFromMem
bool mayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into a vector splat instruction as a memory oper...
Definition: X86ISelLowering.cpp:5099
llvm::X86ISD::PALIGNR
@ PALIGNR
Definition: X86ISelLowering.h:440
llvm::X86ISD::VFPEXTS_SAE
@ VFPEXTS_SAE
Definition: X86ISelLowering.h:335
llvm::X86ISD::DYN_ALLOCA
@ DYN_ALLOCA
Definition: X86ISelLowering.h:651
llvm::X86ISD::VMTRUNCUS
@ VMTRUNCUS
Definition: X86ISelLowering.h:328
llvm::X86ISD::VRANGES_SAE
@ VRANGES_SAE
Definition: X86ISelLowering.h:488
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4394
llvm::X86TargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: X86ISelLowering.cpp:2793
llvm::X86TargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: X86ISelLowering.cpp:2691
llvm::X86ISD::SHUF128
@ SHUF128
Definition: X86ISelLowering.h:453
llvm::X86ISD::STRICT_FNMSUB
@ STRICT_FNMSUB
Definition: X86ISelLowering.h:768
llvm::X86TargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: X86ISelLowering.h:1190
llvm::X86ISD::LADD
@ LADD
LOCK-prefixed arithmetic read-modify-write instructions.
Definition: X86ISelLowering.h:785
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::Function
Definition: Function.h:60
llvm::X86ISD::GF2P8MULB
@ GF2P8MULB
Definition: X86ISelLowering.h:716
llvm::X86ISD::MULHRS
@ MULHRS
Definition: X86ISelLowering.h:532
llvm::X86ISD::VPPERM
@ VPPERM
Definition: X86ISelLowering.h:523
llvm::X86ISD::LWPINS
@ LWPINS
Definition: X86ISelLowering.h:719
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::X86ISD::FSETCC
@ FSETCC
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
Definition: X86ISelLowering.h:107
llvm::X86ISD::FDIVS_RND
@ FDIVS_RND
Definition: X86ISelLowering.h:227
llvm::X86ISD::FMAX
@ FMAX
Floating point max and min.
Definition: X86ISelLowering.h:264
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::X86ISD::SUBV_BROADCAST_LOAD
@ SUBV_BROADCAST_LOAD
Definition: X86ISelLowering.h:804
llvm::X86TargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
Definition: X86InterleavedAccess.cpp:810
llvm::X86ISD::CVTPH2PS
@ CVTPH2PS
Definition: X86ISelLowering.h:706
llvm::X86TargetLowering::isVectorClearMaskLegal
bool isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
Definition: X86ISelLowering.cpp:33706
llvm::X86ISD::SETCC_CARRY
@ SETCC_CARRY
Definition: X86ISelLowering.h:102
llvm::X86ISD::GF2P8AFFINEQB
@ GF2P8AFFINEQB
Definition: X86ISelLowering.h:715
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:839
llvm::X86ISD::CVTTP2SI_SAE
@ CVTTP2SI_SAE
Definition: X86ISelLowering.h:616
llvm::X86ISD::VSHRDV
@ VSHRDV
Definition: X86ISelLowering.h:451
llvm::X86ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: X86ISelLowering.h:305
llvm::X86ISD::FXOR
@ FXOR
Bitwise logical XOR of floating point values.
Definition: X86ISelLowering.h:52
llvm::X86ISD::STRICT_CVTUI2P
@ STRICT_CVTUI2P
Definition: X86ISelLowering.h:763
llvm::X86ISD::FGETEXP_SAE
@ FGETEXP_SAE
Definition: X86ISelLowering.h:238
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86ISD::CVTP2UI_RND
@ CVTP2UI_RND
Definition: X86ISelLowering.h:606
llvm::X86ISD::SCALEFS
@ SCALEFS
Definition: X86ISelLowering.h:249
llvm::X86ISD::FMADD_RND
@ FMADD_RND
Definition: X86ISelLowering.h:559
llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: X86ISelLowering.cpp:5792
llvm::X86ISD::TPAUSE
@ TPAUSE
Definition: X86ISelLowering.h:723
llvm::X86ISD::SELECTS
@ SELECTS
X86 Select.
Definition: X86ISelLowering.h:98
llvm::X86ISD::MCVTTP2UI
@ MCVTTP2UI
Definition: X86ISelLowering.h:633
llvm::X86ISD::BRCOND
@ BRCOND
X86 conditional branches.
Definition: X86ISelLowering.h:123
llvm::X86ISD::CVTTS2UI
@ CVTTS2UI
Definition: X86ISelLowering.h:620
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::X86TargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: X86ISelLowering.cpp:2613
llvm::X86ISD::EXP2
@ EXP2
Definition: X86ISelLowering.h:701
llvm::X86ISD::LCMPXCHG_DAG
@ LCMPXCHG_DAG
Definition: X86ISelLowering.h:778
llvm::X86ISD::PSHUFLW
@ PSHUFLW
Definition: X86ISelLowering.h:445
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2314
llvm::X86TargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: X86ISelLowering.h:1458
llvm::MemOp
Definition: TargetLowering.h:111
llvm::X86ISD::FST
@ FST
This instruction implements a truncating store from FP stack slots.
Definition: X86ISelLowering.h:842
llvm::X86ISD::CALL_RVMARKER
@ CALL_RVMARKER
Definition: X86ISelLowering.h:82
llvm::X86TargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
Definition: X86ISelLowering.cpp:54891
llvm::X86ISD::BLENDV
@ BLENDV
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
Definition: X86ISelLowering.h:210
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::X86TargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: X86ISelLowering.cpp:2386
llvm::X86TargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: X86ISelLowering.cpp:55885
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::X86ISD::RCP28
@ RCP28
Definition: X86ISelLowering.h:697
llvm::X86ISD::CVTS2SI_RND
@ CVTS2SI_RND
Definition: X86ISelLowering.h:610
llvm::X86ISD::FNMADD
@ FNMADD
Definition: X86ISelLowering.h:552
llvm::X86TargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: X86ISelLowering.cpp:55744
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::X86TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: X86ISelLowering.cpp:5705
llvm::X86ISD::MCVTP2SI
@ MCVTP2SI
Definition: X86ISelLowering.h:630
llvm::X86MaskedGatherScatterSDNode
Definition: X86ISelLowering.h:1724
llvm::AttributeList
Definition: Attributes.h:408
llvm::X86ISD::VSHLDQ
@ VSHLDQ
Definition: X86ISelLowering.h:348
llvm::X86ISD::SBB
@ SBB
Definition: X86ISelLowering.h:398
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::X86ISD::VFIXUPIMMS
@ VFIXUPIMMS
Definition: X86ISelLowering.h:482
llvm::X86TargetLowering::storeOfVectorConstantIsCheap
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
Definition: X86ISelLowering.h:1370
llvm::X86ISD::FNMSUB_RND
@ FNMSUB_RND
Definition: X86ISelLowering.h:562
llvm::X86ISD::KSHIFTL
@ KSHIFTL
Definition: X86ISelLowering.h:367
llvm::X86ISD::ANDNP
@ ANDNP
Bitwise Logical AND NOT of Packed FP values.
Definition: X86ISelLowering.h:200
llvm::X86ISD::PACKSS
@ PACKSS
Definition: X86ISelLowering.h:437
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::X86TargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: X86ISelLowering.cpp:2623
llvm::X86::isOffsetSuitableForCodeModel
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
Returns true of the given offset can be fit into displacement field of the instruction.
Definition: X86ISelLowering.cpp:5210
llvm::X86ISD::VTRUNCSTORES
@ VTRUNCSTORES
Definition: X86ISelLowering.h:851
llvm::X86MaskedGatherScatterSDNode::X86MaskedGatherScatterSDNode
X86MaskedGatherScatterSDNode()=delete
llvm::X86ISD::VPMADDWD
@ VPMADDWD
Definition: X86ISelLowering.h:536
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::X86::mayFoldLoad
bool mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into some other x86 instruction as a memory oper...
Definition: X86ISelLowering.cpp:5080
llvm::X86ISD::VSHLV
@ VSHLV
Definition: X86ISelLowering.h:357
llvm::X86ISD::VPMADDUBSW
@ VPMADDUBSW
Definition: X86ISelLowering.h:535
llvm::X86ISD::LAND
@ LAND
Definition: X86ISelLowering.h:789
llvm::X86TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: X86ISelLowering.cpp:32978
llvm::X86ISD::STRICT_CMPP
@ STRICT_CMPP
Definition: X86ISelLowering.h:740
llvm::X86ISD::BSR
@ BSR
Bit scan reverse.
Definition: X86ISelLowering.h:33
llvm::X86ISD::HSUB
@ HSUB
Definition: X86ISelLowering.h:254
llvm::X86ISD::PDEP
@ PDEP
Definition: X86ISelLowering.h:413
llvm::X86ISD::VASTART_SAVE_XMM_REGS
@ VASTART_SAVE_XMM_REGS
Definition: X86ISelLowering.h:872
llvm::X86ISD::LOR
@ LOR
Definition: X86ISelLowering.h:787
llvm::X86ISD::PSHUFHW
@ PSHUFHW
Definition: X86ISelLowering.h:444
llvm::X86ISD::VSRLDQ
@ VSRLDQ
Definition: X86ISelLowering.h:349
llvm::X86ISD::FMADDSUB
@ FMADDSUB
Definition: X86ISelLowering.h:555
llvm::X86ISD::SMUL
@ SMUL
Definition: X86ISelLowering.h:399
llvm::X86ISD::VFPEXT
@ VFPEXT
Definition: X86ISelLowering.h:332
llvm::X86ISD::RSQRT28
@ RSQRT28
Definition: X86ISelLowering.h:693
llvm::X86ISD::VTRUNC
@ VTRUNC
Definition: X86ISelLowering.h:318
llvm::X86TargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: X86ISelLowering.cpp:33516
llvm::X86ISD::FMAXC
@ FMAXC
Commutative FMIN and FMAX.
Definition: X86ISelLowering.h:268
llvm::X86ISD::VRANGE
@ VRANGE
Definition: X86ISelLowering.h:485
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::X86ISD::BEXTRI
@ BEXTRI
Definition: X86ISelLowering.h:407
llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle
bool SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) const
Definition: X86ISelLowering.cpp:40334
llvm::X86ISD::STRICT_CVTPH2PS
@ STRICT_CVTPH2PS
Definition: X86ISelLowering.h:772
llvm::X86ISD::MCVTPS2PH
@ MCVTPS2PH
Definition: X86ISelLowering.h:711
llvm::X86ISD::RSQRT14S
@ RSQRT14S
Definition: X86ISelLowering.h:283
llvm::X86ISD::MCVTTP2SI
@ MCVTTP2SI
Definition: X86ISelLowering.h:632
llvm::X86TargetLowering::shouldScalarizeBinop
bool shouldScalarizeBinop(SDValue) const override
Scalar ops always have equal or better analysis/performance/power than the vector equivalent,...
Definition: X86ISelLowering.cpp:5632
llvm::X86TargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: X86ISelLowering.cpp:5558
llvm::X86ISD::FSETCCM
@ FSETCCM
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.
Definition: X86ISelLowering.h:111
llvm::X86ISD::VPERMI
@ VPERMI
Definition: X86ISelLowering.h:466
llvm::X86ISD::LBTC
@ LBTC
Definition: X86ISelLowering.h:791
llvm::X86TargetLowering::getClearCacheBuiltinName
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
Definition: X86ISelLowering.h:1382
llvm::X86ISD::PSHUFD
@ PSHUFD
Definition: X86ISelLowering.h:443
llvm::X86ISD::VRNDSCALES
@ VRNDSCALES
Definition: X86ISelLowering.h:499
llvm::X86TargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: X86ISelLowering.cpp:36298
llvm::X86TargetLowering::isSplatValueForTargetNode
bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth) const override
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
Definition: X86ISelLowering.cpp:41643
llvm::X86ISD::CMPP
@ CMPP
Definition: X86ISelLowering.h:375
llvm::X86ISD::FMSUBADD_RND
@ FMSUBADD_RND
Definition: X86ISelLowering.h:564
llvm::X86ISD::VFPROUNDS
@ VFPROUNDS
Definition: X86ISelLowering.h:340
llvm::X86ISD::MOVLHPS
@ MOVLHPS
Definition: X86ISelLowering.h:457
llvm::X86ISD::CMPMM
@ CMPMM
Definition: X86ISelLowering.h:390
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::X86TargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: X86ISelLowering.cpp:5401
llvm::X86ISD::CALL
@ CALL
These operations represent an abstract X86 call instruction, which includes a bunch of information.
Definition: X86ISelLowering.h:75
llvm::X86TargetLowering::getSafeStackPointerLocation
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
Definition: X86ISelLowering.cpp:2812
llvm::X86ISD::MSCATTER
@ MSCATTER
Definition: X86ISelLowering.h:858
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::X86TargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: X86ISelLowering.cpp:54779
llvm::X86ISD::CVTS2SI
@ CVTS2SI
Definition: X86ISelLowering.h:608
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1384
llvm::X86TargetLowering::LowerAsmOutputForConstraint
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Handle Lowering flag assembly outputs.
Definition: X86ISelLowering.cpp:55115
TargetLowering.h
llvm::X86ISD::SUB
@ SUB
Definition: X86ISelLowering.h:396
llvm::X86ISD::COMPRESS
@ COMPRESS
Definition: X86ISelLowering.h:588
llvm::X86ISD::RCP14S
@ RCP14S
Definition: X86ISelLowering.h:285
llvm::X86ISD::SEG_ALLOCA
@ SEG_ALLOCA
Definition: X86ISelLowering.h:656
llvm::X86ISD::PMULDQ
@ PMULDQ
Definition: X86ISelLowering.h:530
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
Definition: TargetLowering.h:1158
llvm::X86ISD::CMPM
@ CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
Definition: X86ISelLowering.h:388
llvm::X86ISD::VSRA
@ VSRA
Definition: X86ISelLowering.h:354
llvm::X86ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: X86ISelLowering.h:308
llvm::X86ISD::PINSRW
@ PINSRW
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
Definition: X86ISelLowering.h:189
llvm::MemIntrinsicSDNode
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
Definition: SelectionDAGNodes.h:1480
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:58
llvm::X86ISD::STRICT_CMPM
@ STRICT_CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
Definition: X86ISelLowering.h:744
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::X86TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: X86ISelLowering.cpp:35788
llvm::X86TargetLowering::useStackGuardXorFP
bool useStackGuardXorFP() const override
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
Definition: X86ISelLowering.cpp:2298
llvm::X86ISD::PSHUFB
@ PSHUFB
Shuffle 16 8-bit values within a vector.
Definition: X86ISelLowering.h:192
llvm::X86ISD::VMTRUNCSTOREUS
@ VMTRUNCSTOREUS
Definition: X86ISelLowering.h:853
llvm::X86ISD::VPSHUFBITQMB
@ VPSHUFBITQMB
Definition: X86ISelLowering.h:592
llvm::X86ISD::FNMSUB
@ FNMSUB
Definition: X86ISelLowering.h:554
llvm::X86ISD::MOVSLDUP
@ MOVSLDUP
Definition: X86ISelLowering.h:456
llvm::X86ISD::CMOV
@ CMOV
X86 conditional moves.
Definition: X86ISelLowering.h:117
llvm::X86TargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: X86ISelLowering.cpp:54597
llvm::X86TargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: X86ISelLowering.cpp:27878
llvm::X86ISD::VTRUNCS
@ VTRUNCS
Definition: X86ISelLowering.h:321
llvm::X86ISD::RDRAND
@ RDRAND
Definition: X86ISelLowering.h:667
llvm::X86ISD::BT
@ BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:91
llvm::X86ISD::GF2P8AFFINEINVQB
@ GF2P8AFFINEINVQB
Definition: X86ISelLowering.h:714
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::X86ISD::FMADDSUB_RND
@ FMADDSUB_RND
Definition: X86ISelLowering.h:563
llvm::X86ISD::MOVSHDUP
@ MOVSHDUP
Definition: X86ISelLowering.h:455
llvm::X86ISD::FADDS_RND
@ FADDS_RND
Definition: X86ISelLowering.h:218
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::X86ISD::RDSEED
@ RDSEED
Definition: X86ISelLowering.h:671
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::X86ISD::VBROADCAST_LOAD
@ VBROADCAST_LOAD
Definition: X86ISelLowering.h:801
llvm::X86ISD::VSRLI
@ VSRLI
Definition: X86ISelLowering.h:363
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3394
llvm::X86TargetLowering::hasVectorBlend
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Definition: X86ISelLowering.h:1456
llvm::X86ISD::ENQCMDS
@ ENQCMDS
Definition: X86ISelLowering.h:727
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::X86::isConstantSplat
bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs)
If Op is a constant whose elements are all the same constant or undefined, return true and return the...
Definition: X86ISelLowering.cpp:7331
llvm::X86TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: X86ISelLowering.cpp:31831
llvm::X86ISD::STRICT_VFPROUND
@ STRICT_VFPROUND
Definition: X86ISelLowering.h:754
llvm::X86ISD::FHSUB
@ FHSUB
Definition: X86ISelLowering.h:258
llvm::X86ISD::WRPKRU
@ WRPKRU
Definition: X86ISelLowering.h:678
llvm::X86ISD::VZEXT_LOAD
@ VZEXT_LOAD
Definition: X86ISelLowering.h:795
llvm::X86ISD::NT_CALL
@ NT_CALL
Same as call except it adds the NoTrack prefix.
Definition: X86ISelLowering.h:78
llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: X86ISelLowering.cpp:41106
llvm::X86ISD::VSHLD
@ VSHLD
Definition: X86ISelLowering.h:448
llvm::X86TargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: X86ISelLowering.cpp:2294
llvm::X86ISD::FILD
@ FILD
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.
Definition: X86ISelLowering.h:824
llvm::X86ISD::SCALEF_RND
@ SCALEF_RND
Definition: X86ISelLowering.h:248
llvm::X86ISD::MFENCE
@ MFENCE
Definition: X86ISelLowering.h:664
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::X86ISD::CVTNEPS2BF16
@ CVTNEPS2BF16
Definition: X86ISelLowering.h:641
llvm::X86TargetLowering::markLibCallAttributes
void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override
Definition: X86ISelLowering.cpp:2627
llvm::createSplat2ShuffleMask
void createSplat2ShuffleMask(MVT VT, SmallVectorImpl< int > &Mask, bool Lo)
Similar to unpacklo/unpackhi, but without the 128-bit lane limitation imposed by AVX and specific to ...
Definition: X86ISelLowering.cpp:6859
llvm::X86TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
Definition: X86ISelLowering.cpp:33533
llvm::X86ISD::VPERM2X128
@ VPERM2X128
Definition: X86ISelLowering.h:467
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
llvm::X86TargetLowering::needsFixedCatchObjects
virtual bool needsFixedCatchObjects() const override
Definition: X86ISelLowering.cpp:27886
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::X86MaskedGatherScatterSDNode::getMask
const SDValue & getMask() const
Definition: X86ISelLowering.h:1732
llvm::X86ISD::VFCMADDC
@ VFCMADDC
Definition: X86ISelLowering.h:569
llvm::X86TargetLowering::isLoadBitCastBeneficial
bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const override
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Definition: X86ISelLowering.cpp:5687
llvm::X86ISD::VPDPBUSDS
@ VPDPBUSDS
Definition: X86ISelLowering.h:546
llvm::X86ISD::FSUBS_RND
@ FSUBS_RND
Definition: X86ISelLowering.h:221
llvm::X86ISD::VSHLDV
@ VSHLDV
Definition: X86ISelLowering.h:450
llvm::X86ISD::SCALAR_UINT_TO_FP
@ SCALAR_UINT_TO_FP
Definition: X86ISelLowering.h:598
llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: X86ISelLowering.cpp:33643
llvm::X86TargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: X86ISelLowering.cpp:55103
llvm::X86ISD::FGETEXPS_SAE
@ FGETEXPS_SAE
Definition: X86ISelLowering.h:240
llvm::X86ISD::AESDEC256KL
@ AESDEC256KL
Definition: X86ISelLowering.h:864
llvm::X86ISD::RSQRT28S
@ RSQRT28S
Definition: X86ISelLowering.h:695
llvm::X86TargetLowering
Definition: X86ISelLowering.h:937
llvm::X86ISD::PEXTRB
@ PEXTRB
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
Definition: X86ISelLowering.h:173
llvm::X86TargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: X86ISelLowering.cpp:5727
llvm::X86ISD::VAARG_64
@ VAARG_64
These instructions grab the address of the next argument from a va_list.
Definition: X86ISelLowering.h:846
llvm::X86TargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: X86ISelLowering.h:1100
llvm::X86ISD::VEXTRACT_STORE
@ VEXTRACT_STORE
Definition: X86ISelLowering.h:798
llvm::X86ISD::IRET
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
Definition: X86ISelLowering.h:134
llvm::X86TargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: X86ISelLowering.cpp:33498
llvm::X86ISD::CVTTP2UI
@ CVTTP2UI
Definition: X86ISelLowering.h:615
llvm::X86ISD::FMAXS
@ FMAXS
Scalar intrinsic floating point max and min.
Definition: X86ISelLowering.h:272
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::X86ISD::LBTR
@ LBTR
Definition: X86ISelLowering.h:792
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86ISD::CVTS2UI_RND
@ CVTS2UI_RND
Definition: X86ISelLowering.h:611
llvm::X86ISD::LCMPXCHG16_DAG
@ LCMPXCHG16_DAG
Definition: X86ISelLowering.h:780
llvm::X86TargetLowering::areJTsAllowed
bool areJTsAllowed(const Function *Fn) const override
Returns true if lowering to a jump table is allowed.
Definition: X86ISelLowering.cpp:33718
llvm::X86ISD::CVTTS2UI_SAE
@ CVTTS2UI_SAE
Definition: X86ISelLowering.h:622
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::X86ISD::MOVHLPS
@ MOVHLPS
Definition: X86ISelLowering.h:458
llvm::X86TargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: X86ISelLowering.cpp:55844
llvm::X86ISD::SCALAR_SINT_TO_FP
@ SCALAR_SINT_TO_FP
Definition: X86ISelLowering.h:597
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::X86ISD::VFIXUPIMM_SAE
@ VFIXUPIMM_SAE
Definition: X86ISelLowering.h:481
llvm::X86TargetLowering::isVectorShiftByScalarCheap
bool isVectorShiftByScalarCheap(Type *Ty) const override
This is used to enable splatted operand transforms for vector shifts and vector funnel shifts.
Definition: X86ISelLowering.cpp:33430
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::X86ISD::VPERMILPI
@ VPERMILPI
Definition: X86ISelLowering.h:465
llvm::X86ISD::LBTS
@ LBTS
Definition: X86ISelLowering.h:790
llvm::X86ISD::CVTNE2PS2BF16
@ CVTNE2PS2BF16
Definition: X86ISelLowering.h:639
llvm::InlineAsm::Constraint_v
@ Constraint_v
Definition: InlineAsm.h:257
llvm::X86TargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: X86ISelLowering.cpp:33689
llvm::X86TargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: X86ISelLowering.cpp:2667
llvm::X86ISD::GlobalBaseReg
@ GlobalBaseReg
On Darwin, this node represents the result of the popl at function entry, used for PIC code.
Definition: X86ISelLowering.h:144
llvm::X86ISD::VFPCLASS
@ VFPCLASS
Definition: X86ISelLowering.h:502
llvm::X86ISD::EXTRQI
@ EXTRQI
SSE4A Extraction and Insertion.
Definition: X86ISelLowering.h:513
llvm::X86MaskedGatherScatterSDNode::getScale
const SDValue & getScale() const
Definition: X86ISelLowering.h:1733
llvm::X86ISD::DPBF16PS
@ DPBF16PS
Definition: X86ISelLowering.h:648
llvm::X86ISD::VREDUCES
@ VREDUCES
Definition: X86ISelLowering.h:492
llvm::X86ISD::FGETEXP
@ FGETEXP
Definition: X86ISelLowering.h:237
llvm::X86ISD::AESENC256KL
@ AESENC256KL
Definition: X86ISelLowering.h:863
llvm::X86ISD::INSERTQI
@ INSERTQI
Definition: X86ISelLowering.h:514
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
llvm::X86ISD::MCVTNEPS2BF16
@ MCVTNEPS2BF16
Definition: X86ISelLowering.h:644
llvm::X86MaskedGatherScatterSDNode::~X86MaskedGatherScatterSDNode
~X86MaskedGatherScatterSDNode()=delete
llvm::X86TargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code.
Definition: X86ISelLowering.cpp:31979
llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode
bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
Definition: X86ISelLowering.cpp:40401
llvm::X86ISD::ADD
@ ADD
Definition: X86ISelLowering.h:395
llvm::X86ISD::VRNDSCALE
@ VRNDSCALE
Definition: X86ISelLowering.h:497
llvm::X86ISD::PHMINPOS
@ PHMINPOS
Definition: X86ISelLowering.h:382
llvm::X86::rmMask
@ rmMask
Definition: X86ISelLowering.h:889
llvm::X86ISD::CVTS2UI
@ CVTS2UI
Definition: X86ISelLowering.h:609
llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair
bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
Definition: X86ISelLowering.cpp:5810
llvm::APFloat
Definition: APFloat.h:700
llvm::X86ISD::FMINC
@ FMINC
Definition: X86ISelLowering.h:269
llvm::X86ISD::CVTUI2P
@ CVTUI2P
Definition: X86ISelLowering.h:626
llvm::X86ISD::FMIN_SAE
@ FMIN_SAE
Definition: X86ISelLowering.h:230
llvm::X86TargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: X86ISelLowering.cpp:5732
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:305
llvm::X86ISD::VFCMULC
@ VFCMULC
Definition: X86ISelLowering.h:574
llvm::X86ISD::VPSHA
@ VPSHA
Definition: X86ISelLowering.h:517
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::X86ISD::MGATHER
@ MGATHER
Definition: X86ISelLowering.h:857
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::X86ISD::KADD
@ KADD
Definition: X86ISelLowering.h:433
llvm::X86TargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: X86ISelLowering.cpp:5586
llvm::X86ISD::VBROADCASTM
@ VBROADCASTM
Definition: X86ISelLowering.h:510
llvm::X86ISD::CVTP2SI_RND
@ CVTP2SI_RND
Definition: X86ISelLowering.h:605
llvm::X86ISD::MOVQ2DQ
@ MOVQ2DQ
Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero fi...
Definition: X86ISelLowering.h:157
llvm::createUnpackShuffleMask
void createUnpackShuffleMask(EVT VT, SmallVectorImpl< int > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
Definition: X86ISelLowering.cpp:6839
llvm::X86TargetLowering::getPreferredVectorAction
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Customize the preferred legalization strategy for certain types.
Definition: X86ISelLowering.cpp:2312
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::X86ISD::FSQRTS_RND
@ FSQRTS_RND
Definition: X86ISelLowering.h:234
llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: X86ISelLowering.cpp:2680
uint64_t
llvm::X86ISD::FSHL
@ FSHL
X86 funnel/double shift i16 instructions.
Definition: X86ISelLowering.h:39
llvm::X86ISD::VRNDSCALE_SAE
@ VRNDSCALE_SAE
Definition: X86ISelLowering.h:498
llvm::X86ISD::VFMADDCSH_RND
@ VFMADDCSH_RND
Definition: X86ISelLowering.h:578
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1293
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::X86::isZeroNode
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
Definition: X86ISelLowering.cpp:6086
llvm::X86ISD::VTRUNCSTOREUS
@ VTRUNCSTOREUS
Definition: X86ISelLowering.h:850
llvm::X86ISD::FOR
@ FOR
Bitwise logical OR of floating point values.
Definition: X86ISelLowering.h:48
llvm::X86ISD::VFPEXTS
@ VFPEXTS
Definition: X86ISelLowering.h:334
llvm::X86TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: X86ISelLowering.cpp:2578
llvm::X86ISD::STRICT_FMSUB
@ STRICT_FMSUB
Definition: X86ISelLowering.h:767
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::X86ISD::VFCMADDC_RND
@ VFCMADDC_RND
Definition: X86ISelLowering.h:570
llvm::X86ISD::FSETCCM_SAE
@ FSETCCM_SAE
Definition: X86ISelLowering.h:112
llvm::X86ISD::VFMULCSH_RND
@ VFMULCSH_RND
Definition: X86ISelLowering.h:583
llvm::X86ISD::VPERMV3
@ VPERMV3
Definition: X86ISelLowering.h:475
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::X86TargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: X86ISelLowering.cpp:33630
llvm::X86ISD::VFPROUND_RND
@ VFPROUND_RND
Definition: X86ISelLowering.h:339
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:908
llvm::X86ISD::RSQRT28_SAE
@ RSQRT28_SAE
Definition: X86ISelLowering.h:694
llvm::X86ISD::MOVSS
@ MOVSS
Definition: X86ISelLowering.h:460
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::X86ISD::CVTTP2UI_SAE
@ CVTTP2UI_SAE
Definition: X86ISelLowering.h:617
llvm::X86TargetLowering::X86TargetLowering
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
Definition: X86ISelLowering.cpp:107
llvm::X86ISD::PEXT
@ PEXT
Definition: X86ISelLowering.h:414
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::X86ISD::ENQCMD
@ ENQCMD
Definition: X86ISelLowering.h:726
llvm::X86ISD::VFPCLASSS
@ VFPCLASSS
Definition: X86ISelLowering.h:504
llvm::X86ISD::VREDUCE
@ VREDUCE
Definition: X86ISelLowering.h:490
llvm::X86ISD::VPDPWSSD
@ VPDPWSSD
Definition: X86ISelLowering.h:547
llvm::X86ISD::INSERTPS
@ INSERTPS
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
Definition: X86ISelLowering.h:181
llvm::TargetLoweringBase::NegatibleCost
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition: TargetLowering.h:276
llvm::X86ISD::BSF
@ BSF
Bit scan forward.
Definition: X86ISelLowering.h:31
llvm::X86ISD::VSRAV
@ VSRAV
Definition: X86ISelLowering.h:359
llvm::X86ISD::UNPCKL
@ UNPCKL
Definition: X86ISelLowering.h:462
llvm::X86ISD::COMI
@ COMI
Definition: X86ISelLowering.h:87
llvm::X86TargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: X86ISelLowering.cpp:55897
llvm::X86ISD::UMUL
@ UMUL
Definition: X86ISelLowering.h:400
llvm::X86MaskedScatterSDNode::getValue
const SDValue & getValue() const
Definition: X86ISelLowering.h:1752
llvm::X86ISD::FMSUB
@ FMSUB
Definition: X86ISelLowering.h:553
llvm::X86ISD::FRCP
@ FRCP
Definition: X86ISelLowering.h:279
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::X86ISD::MEMBARRIER
@ MEMBARRIER
Definition: X86ISelLowering.h:663
llvm::X86TargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
Definition: X86ISelLowering.cpp:5522
llvm::X86TargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: X86ISelLowering.cpp:55142
llvm::X86ISD::VSRAI
@ VSRAI
Definition: X86ISelLowering.h:364
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::X86ISD::BZHI
@ BZHI
Definition: X86ISelLowering.h:410
llvm::X86ISD::VRANGES
@ VRANGES
Definition: X86ISelLowering.h:487
llvm::X86ISD::CVTTS2SI_SAE
@ CVTTS2SI_SAE
Definition: X86ISelLowering.h:621
llvm::X86MaskedScatterSDNode
Definition: X86ISelLowering.h:1750
llvm::X86::RoundingMode
RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
Definition: X86ISelLowering.h:884
llvm::X86ISD::REP_STOS
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
Definition: X86ISelLowering.h:137
llvm::X86ISD::VAARG_X32
@ VAARG_X32
Definition: X86ISelLowering.h:847
llvm::X86TargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: X86ISelLowering.cpp:2358
llvm::X86ISD::FRSQRT
@ FRSQRT
Floating point reciprocal-sqrt and reciprocal approximation.
Definition: X86ISelLowering.h:278
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::X86ISD::RCP14
@ RCP14
Definition: X86ISelLowering.h:284
llvm::X86ISD::MOVDQ2Q
@ MOVDQ2Q
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
Definition: X86ISelLowering.h:161
llvm::X86ISD::VSRLV
@ VSRLV
Definition: X86ISelLowering.h:358
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::X86TargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: X86ISelLowering.cpp:27870
llvm::X86MaskedGatherSDNode
Definition: X86ISelLowering.h:1741
llvm::X86ISD::VFCMULCSH
@ VFCMULCSH
Definition: X86ISelLowering.h:584
llvm::X86ISD::AND
@ AND
Definition: X86ISelLowering.h:403
llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: X86ISelLowering.cpp:5770
llvm::X86ISD::VFPROUNDS_RND
@ VFPROUNDS_RND
Definition: X86ISelLowering.h:341
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1404
llvm::X86ISD::DBPSADBW
@ DBPSADBW
Compute Double Block Packed Sum-Absolute-Differences.
Definition: X86ISelLowering.h:197
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
llvm::X86TargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: X86ISelLowering.cpp:5514
llvm::X86ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: X86ISelLowering.h:302
llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
Definition: X86ISelLowering.h:1044
llvm::X86ISD::MOVDDUP
@ MOVDDUP
Definition: X86ISelLowering.h:454
llvm::X86ISD::STRICT_CVTSI2P
@ STRICT_CVTSI2P
Definition: X86ISelLowering.h:762
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::X86TargetLowering::IsDesirableToPromoteOp
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: X86ISelLowering.cpp:54659
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::X86ISD::VFIXUPIMM
@ VFIXUPIMM
Definition: X86ISelLowering.h:480
llvm::X86ISD::NT_BRIND
@ NT_BRIND
BRIND node with NoTrack prefix.
Definition: X86ISelLowering.h:127
llvm::X86ISD::VFCMADDCSH_RND
@ VFCMADDCSH_RND
Definition: X86ISelLowering.h:580
llvm::X86ISD::FMINS_SAE
@ FMINS_SAE
Definition: X86ISelLowering.h:231
llvm::X86ISD::TESTUI
@ TESTUI
Definition: X86ISelLowering.h:733
llvm::X86ISD::XTEST
@ XTEST
Definition: X86ISelLowering.h:690
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::X86ISD::VRNDSCALES_SAE
@ VRNDSCALES_SAE
Definition: X86ISelLowering.h:500
llvm::X86TargetLowering::unwrapAddress
SDValue unwrapAddress(SDValue N) const override
Definition: X86ISelLowering.cpp:36746
llvm::X86ISD::EH_RETURN
@ EH_RETURN
Definition: X86ISelLowering.h:299
llvm::X86::mayFoldIntoZeroExtend
bool mayFoldIntoZeroExtend(SDValue Op)
Check if Op is an operation that could be folded into a zero extend x86 instruction.
Definition: X86ISelLowering.cpp:5117
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::X86TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: X86ISelLowering.h:948
llvm::X86ISD::TLSCALL
@ TLSCALL
Definition: X86ISelLowering.h:296
llvm::X86TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: X86ISelLowering.cpp:33378
llvm::X86TargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: X86ISelLowering.cpp:2656
llvm::X86::rmUpward
@ rmUpward
Definition: X86ISelLowering.h:887
llvm::X86ISD::AESENCWIDE256KL
@ AESENCWIDE256KL
Definition: X86ISelLowering.h:867
llvm::X86ISD::FMULS
@ FMULS
Definition: X86ISelLowering.h:223
llvm::X86ISD::UNPCKH
@ UNPCKH
Definition: X86ISelLowering.h:463
llvm::X86ISD::VGETMANTS
@ VGETMANTS
Definition: X86ISelLowering.h:244
llvm::X86ISD::MCVTP2UI
@ MCVTP2UI
Definition: X86ISelLowering.h:631
llvm::X86ISD::AESENCWIDE128KL
@ AESENCWIDE128KL
Definition: X86ISelLowering.h:865
llvm::X86::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: X86ISelLowering.cpp:5242
llvm::X86ISD::SCALEF
@ SCALEF
Definition: X86ISelLowering.h:247
llvm::X86ISD::MUL_IMM
@ MUL_IMM
Definition: X86ISelLowering.h:417
llvm::ArrayRef< int >
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::X86TargetLowering::isExtractVecEltCheap
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
Definition: X86ISelLowering.h:1359
llvm::X86ISD::PSADBW
@ PSADBW
Compute Sum of Absolute Differences.
Definition: X86ISelLowering.h:195
llvm::X86ISD::KSHIFTR
@ KSHIFTR
Definition: X86ISelLowering.h:368
llvm::X86::rmToNearest
@ rmToNearest
Definition: X86ISelLowering.h:885
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::X86ISD::FP_TO_INT_IN_MEM
@ FP_TO_INT_IN_MEM
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.
Definition: X86ISelLowering.h:817
llvm::X86MaskedGatherSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1745
llvm::X86ISD::FADDS
@ FADDS
Definition: X86ISelLowering.h:217
llvm::X86TargetLowering::getIRStackGuard
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
Definition: X86ISelLowering.cpp:2735
llvm::X86ISD::STRICT_FNMADD
@ STRICT_FNMADD
Definition: X86ISelLowering.h:766
llvm::X86TargetLowering::emitStackGuardXorFP
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override
Definition: X86ISelLowering.cpp:2303
llvm::X86ISD::REP_MOVS
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
Definition: X86ISelLowering.h:140
llvm::X86ISD::VPMADD52L
@ VPMADD52L
Definition: X86ISelLowering.h:541
uint32_t
llvm::X86ISD::FLD
@ FLD
This instruction implements an extending load to FP stack slots.
Definition: X86ISelLowering.h:836
llvm::X86ISD::BLENDI
@ BLENDI
Blend where the selector is an immediate.
Definition: X86ISelLowering.h:203
llvm::X86ISD::VPTERNLOG
@ VPTERNLOG
Definition: X86ISelLowering.h:478
llvm::X86ISD::VGETMANT
@ VGETMANT
Definition: X86ISelLowering.h:242
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86ISD::VFMULC
@ VFMULC
Definition: X86ISelLowering.h:572
llvm::X86MaskedGatherSDNode::getPassThru
const SDValue & getPassThru() const
Definition: X86ISelLowering.h:1743
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::X86ISD::VREDUCE_SAE
@ VREDUCE_SAE
Definition: X86ISelLowering.h:491
llvm::X86TargetLowering::expandIndirectJTBranch
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expanasion.
Definition: X86ISelLowering.cpp:54643
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1287
llvm::X86ISD::FMSUBADD
@ FMSUBADD
Definition: X86ISelLowering.h:556
llvm::X86ISD::XOR
@ XOR
Definition: X86ISelLowering.h:402
llvm::X86ISD::RSQRT14
@ RSQRT14
Definition: X86ISelLowering.h:282
llvm::X86ISD::LCMPXCHG8_DAG
@ LCMPXCHG8_DAG
Definition: X86ISelLowering.h:779
llvm::X86::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: X86FastISel.cpp:4005
llvm::X86ISD::VPCOMU
@ VPCOMU
Definition: X86ISelLowering.h:521
llvm::X86TargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: X86ISelLowering.cpp:2802
llvm::X86TargetLowering::shouldTransformSignedTruncationCheck
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition: X86ISelLowering.h:1079
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:176
llvm::X86::rmTowardZero
@ rmTowardZero
Definition: X86ISelLowering.h:888
llvm::X86ISD::VPDPWSSDS
@ VPDPWSSDS
Definition: X86ISelLowering.h:548
llvm::X86ISD::FCMP
@ FCMP
Definition: X86ISelLowering.h:86
llvm::X86ISD::CVTSI2P
@ CVTSI2P
Definition: X86ISelLowering.h:625
llvm::X86ISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress,...
Definition: X86ISelLowering.h:149
llvm::X86TargetLowering::getByValTypeAlignment
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
Definition: X86ISelLowering.cpp:2504
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:312
llvm::X86ISD::VPERMILPV
@ VPERMILPV
Definition: X86ISelLowering.h:464
llvm::X86TargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: X86ISelLowering.cpp:5618
llvm::X86TargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
Definition: X86ISelLowering.cpp:2524
llvm::X86MaskedGatherScatterSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: X86ISelLowering.h:1730
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86ISD::KTEST
@ KTEST
Definition: X86ISelLowering.h:430
llvm::X86ISD::FHADD
@ FHADD
Floating point horizontal add/sub.
Definition: X86ISelLowering.h:257
llvm::X86ISD::MOVSD
@ MOVSD
Definition: X86ISelLowering.h:459
llvm::X86ISD::VSRL
@ VSRL
Definition: X86ISelLowering.h:353
llvm::X86ISD::VSHLI
@ VSHLI
Definition: X86ISelLowering.h:362
llvm::X86ISD::MMX_MOVW2D
@ MMX_MOVW2D
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.
Definition: X86ISelLowering.h:169
llvm::X86ISD::VTRUNCUS
@ VTRUNCUS
Definition: X86ISelLowering.h:320
llvm::X86ISD::FSQRTS
@ FSQRTS
Definition: X86ISelLowering.h:233
llvm::X86ISD::CVTP2UI
@ CVTP2UI
Definition: X86ISelLowering.h:604
llvm::X86ISD::VPERMV
@ VPERMV
Definition: X86ISelLowering.h:471
llvm::X86ISD::MOVSH
@ MOVSH
Definition: X86ISelLowering.h:461
llvm::X86TargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: X86ISelLowering.cpp:5664
llvm::X86TargetLowering::shouldConvertPhiType
bool shouldConvertPhiType(Type *From, Type *To) const override
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
Definition: X86ISelLowering.cpp:33624
llvm::KnownBits
Definition: KnownBits.h:23
llvm::X86ISD::VBROADCAST
@ VBROADCAST
Definition: X86ISelLowering.h:508
llvm::X86ISD::FSHR
@ FSHR
Definition: X86ISelLowering.h:40
llvm::X86TargetLowering::getNegatedExpression
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Definition: X86ISelLowering.cpp:50238
llvm::X86MaskedGatherScatterSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1735
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::X86ISD::VFMADDC_RND
@ VFMADDC_RND
Definition: X86ISelLowering.h:568
llvm::X86ISD::VROTRI
@ VROTRI
Definition: X86ISelLowering.h:372
llvm::X86TargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
Definition: X86ISelLowering.h:1029
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::X86ISD::VPMADD52H
@ VPMADD52H
Definition: X86ISelLowering.h:542
llvm::X86ISD::KORTEST
@ KORTEST
Definition: X86ISelLowering.h:429
llvm::X86ISD::SCALAR_UINT_TO_FP_RND
@ SCALAR_UINT_TO_FP_RND
Definition: X86ISelLowering.h:600
llvm::X86ISD::SETCC
@ SETCC
X86 SetCC.
Definition: X86ISelLowering.h:95
llvm::X86ISD::RSQRT28S_SAE
@ RSQRT28S_SAE
Definition: X86ISelLowering.h:696
llvm::X86ISD::AESDECWIDE256KL
@ AESDECWIDE256KL
Definition: X86ISelLowering.h:868
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4404
llvm::X86TargetLowering::getTargetConstantFromLoad
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
Definition: X86ISelLowering.cpp:7016
llvm::X86ISD::VZEXT_MOVL
@ VZEXT_MOVL
Definition: X86ISelLowering.h:315
llvm::X86ISD::FSUBS
@ FSUBS
Definition: X86ISelLowering.h:220
llvm::X86ISD::VMTRUNCS
@ VMTRUNCS
Definition: X86ISelLowering.h:329
llvm::X86ISD::FAND
@ FAND
Bitwise logical AND of floating point values.
Definition: X86ISelLowering.h:44
llvm::X86ISD::PCMPEQ
@ PCMPEQ
Definition: X86ISelLowering.h:378
llvm::X86ISD::FMIN
@ FMIN
Definition: X86ISelLowering.h:265
llvm::X86ISD::FMULS_RND
@ FMULS_RND
Definition: X86ISelLowering.h:224
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::X86TargetLowering::hasFastEqualityCompare
MVT hasFastEqualityCompare(unsigned NumBits) const override
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
Definition: X86ISelLowering.cpp:5838
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:222
llvm::X86ISD::RET_FLAG
@ RET_FLAG
Return with a flag operand.
Definition: X86ISelLowering.h:131
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::X86ISD::VGETMANT_SAE
@ VGETMANT_SAE
Definition: X86ISelLowering.h:243
llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
Definition: X86ISelLowering.cpp:33671
llvm::X86ISD::HADD
@ HADD
Integer horizontal add/sub.
Definition: X86ISelLowering.h:253
llvm::X86ISD::LSUB
@ LSUB
Definition: X86ISelLowering.h:786
llvm::X86ISD::FDIV_RND
@ FDIV_RND
Definition: X86ISelLowering.h:225
llvm::X86ISD::CMPMM_SAE
@ CMPMM_SAE
Definition: X86ISelLowering.h:392
llvm::X86TargetLowering::isBinOp
bool isBinOp(unsigned Opcode) const override
Add x86-specific opcodes to the default list.
Definition: X86ISelLowering.cpp:33453
llvm::X86::mayFoldIntoStore
bool mayFoldIntoStore(SDValue Op)
Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory...
Definition: X86ISelLowering.cpp:5113
llvm::X86TargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: X86ISelLowering.cpp:5674
llvm::X86ISD::VFPEXT_SAE
@ VFPEXT_SAE
Definition: X86ISelLowering.h:333
llvm::X86ISD::VMFPROUND
@ VMFPROUND
Definition: X86ISelLowering.h:345
llvm::X86ISD::STRICT_CVTTP2SI
@ STRICT_CVTTP2SI
Definition: X86ISelLowering.h:747
llvm::X86ISD::VPDPBUSD
@ VPDPBUSD
Definition: X86ISelLowering.h:545
llvm::X86TargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: X86ISelLowering.cpp:5669
llvm::X86ISD::FSQRT_RND
@ FSQRT_RND
Definition: X86ISelLowering.h:232
llvm::X86ISD::FNMADD_RND
@ FNMADD_RND
Definition: X86ISelLowering.h:560
llvm::X86ISD::MOVMSK
@ MOVMSK
Definition: X86ISelLowering.h:420
llvm::X86ISD::VP2INTERSECT
@ VP2INTERSECT
Definition: X86ISelLowering.h:730
llvm::X86ISD::TESTP
@ TESTP
Definition: X86ISelLowering.h:426
llvm::X86ISD::RDPKRU
@ RDPKRU
Definition: X86ISelLowering.h:677
llvm::X86TargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: X86ISelLowering.cpp:5765
llvm::X86TargetLowering::isCommutativeBinOp
bool isCommutativeBinOp(unsigned Opcode) const override
Returns true if the opcode is a commutative binary operation.
Definition: X86ISelLowering.cpp:33473
llvm::X86ISD::CVTP2SI
@ CVTP2SI
Definition: X86ISelLowering.h:603
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2008
llvm::X86TargetLowering::BuildFILD
std::pair< SDValue, SDValue > BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:20824
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::X86TargetLowering::shouldSplatInsEltVarIndex
bool shouldSplatInsEltVarIndex(EVT VT) const override
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
Definition: X86ISelLowering.cpp:5832
llvm::X86TargetLowering::isLegalStoreImmediate
bool isLegalStoreImmediate(int64_t Imm) const override
Return true if the specified immediate is legal for the value input of a store instruction.
Definition: X86ISelLowering.cpp:33521
llvm::X86ISD::SHUFP
@ SHUFP
Definition: X86ISelLowering.h:446
llvm::X86ISD::SCALAR_SINT_TO_FP_RND
@ SCALAR_SINT_TO_FP_RND
Definition: X86ISelLowering.h:599
llvm::X86ISD::MULTISHIFT
@ MULTISHIFT
Definition: X86ISelLowering.h:384
llvm::X86TargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: X86ISelLowering.cpp:5577
llvm::X86ISD::VPSHL
@ VPSHL
Definition: X86ISelLowering.h:518
llvm::X86ISD::ADDSUB
@ ADDSUB
Combined add and sub on an FP vector.
Definition: X86ISelLowering.h:213
llvm::X86TargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: X86ISelLowering.cpp:2765
llvm::X86ISD::VALIGN
@ VALIGN
Definition: X86ISelLowering.h:442
llvm::X86ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: X86ISelLowering.h:28
llvm::X86TargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: X86ISelLowering.cpp:5748
llvm::X86ISD::SINT_TO_FP_RND
@ SINT_TO_FP_RND
Definition: X86ISelLowering.h:595
llvm::X86TargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: X86ISelLowering.cpp:5659
llvm::X86TargetLowering::isSafeMemOpType
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
Definition: X86ISelLowering.cpp:2570
llvm::X86TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: X86ISelLowering.cpp:33512
llvm::X86ISD::CONFLICT
@ CONFLICT
Definition: X86ISelLowering.h:261
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1299
llvm::X86ISD::VFMULC_RND
@ VFMULC_RND
Definition: X86ISelLowering.h:573
llvm::X86ISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: X86ISelLowering.h:660
N
#define N
llvm::X86ISD::FLDCW16m
@ FLDCW16m
Definition: X86ISelLowering.h:810
llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: X86ISelLowering.cpp:2418
llvm::X86ISD::VREDUCES_SAE
@ VREDUCES_SAE
Definition: X86ISelLowering.h:493
llvm::X86ISD::VSHL
@ VSHL
Definition: X86ISelLowering.h:352
llvm::X86TargetLowering::getStackProbeSymbolName
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Definition: X86ISelLowering.cpp:55862
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4496
llvm::X86ISD::BEXTR
@ BEXTR
Definition: X86ISelLowering.h:406
llvm::X86ISD::AESDECWIDE128KL
@ AESDECWIDE128KL
Definition: X86ISelLowering.h:866
llvm::X86ISD::CVTPH2PS_SAE
@ CVTPH2PS_SAE
Definition: X86ISelLowering.h:707
llvm::X86ISD::PCMPISTR
@ PCMPISTR
Definition: X86ISelLowering.h:686
llvm::X86ISD::LCMPXCHG16_SAVE_RBX_DAG
@ LCMPXCHG16_SAVE_RBX_DAG
Definition: X86ISelLowering.h:781
llvm::X86ISD::CVTPS2PH
@ CVTPS2PH
Definition: X86ISelLowering.h:705
llvm::X86ISD::CMP
@ CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:85
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::X86ISD::FNSTCW16m
@ FNSTCW16m
Definition: X86ISelLowering.h:807
llvm::X86ISD::VMTRUNCSTORES
@ VMTRUNCSTORES
Definition: X86ISelLowering.h:854
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::X86TargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating exp...
Definition: X86ISelLowering.cpp:5651
RegName
#define RegName(no)
llvm::X86TargetLowering::getPreferredSwitchConditionType
MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const override
Returns preferred type for switch condition.
Definition: X86ISelLowering.cpp:33727
llvm::X86ISD::FANDN
@ FANDN
Bitwise logical ANDNOT of floating point values.
Definition: X86ISelLowering.h:56
llvm::X86ISD::CVTTS2SI
@ CVTTS2SI
Definition: X86ISelLowering.h:619
llvm::X86ISD::FSUB_RND
@ FSUB_RND
Definition: X86ISelLowering.h:219
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86ISD::CVTTP2SI
@ CVTTP2SI
Definition: X86ISelLowering.h:614
llvm::X86ISD::ADC
@ ADC
Definition: X86ISelLowering.h:397
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:513
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::X86ISD::VROTLI
@ VROTLI
Definition: X86ISelLowering.h:371
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
llvm::X86TargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: X86ISelLowering.cpp:5824
llvm::X86TargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: X86ISelLowering.h:1433
llvm::X86ISD::PCMPGT
@ PCMPGT
Definition: X86ISelLowering.h:379
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::X86ISD::FMSUB_RND
@ FMSUB_RND
Definition: X86ISelLowering.h:561
llvm::X86ISD::LXOR
@ LXOR
Definition: X86ISelLowering.h:788
llvm::X86TargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition: X86ISelLowering.cpp:5071
llvm::X86ISD::VFIXUPIMMS_SAE
@ VFIXUPIMMS_SAE
Definition: X86ISelLowering.h:483
llvm::X86ISD::FMAX_SAE
@ FMAX_SAE
Definition: X86ISelLowering.h:228
llvm::X86ISD::PTEST
@ PTEST
Definition: X86ISelLowering.h:423
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::X86ISD::OR
@ OR
Definition: X86ISelLowering.h:401
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::X86ISD::WrapperRIP
@ WrapperRIP
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
Definition: X86ISelLowering.h:153
llvm::X86ISD::VFMADDCSH
@ VFMADDCSH
Definition: X86ISelLowering.h:577
llvm::X86TargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: X86ISelLowering.cpp:55773
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::X86ISD::FIST
@ FIST
This instruction implements a fp->int store from FP stack slots.
Definition: X86ISelLowering.h:830
llvm::X86ISD::VFMADDC
@ VFMADDC
Definition: X86ISelLowering.h:567
llvm::X86TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: X86ISelLowering.cpp:55834
llvm::X86TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Definition: X86ISelLowering.cpp:2446
llvm::X86::rmDownward
@ rmDownward
Definition: X86ISelLowering.h:886
MachineFunction.h
llvm::X86ISD::EXP2_SAE
@ EXP2_SAE
Definition: X86ISelLowering.h:702
llvm::X86ISD::UCOMI
@ UCOMI
Definition: X86ISelLowering.h:88
llvm::X86ISD::VFMULCSH
@ VFMULCSH
Definition: X86ISelLowering.h:582
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::X86ISD::FGETEXPS
@ FGETEXPS
Definition: X86ISelLowering.h:239
llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const override
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
Definition: X86ISelLowering.cpp:41551
llvm::X86TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: X86ISelLowering.cpp:54413
llvm::X86ISD::MCVTUI2P
@ MCVTUI2P
Definition: X86ISelLowering.h:635
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::X86TargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower interleaved store(s) into target specific instructions/intrinsics.
Definition: X86InterleavedAccess.cpp:827
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: X86ISelLowering.cpp:36595
llvm::X86ISD::VPCOM
@ VPCOM
Definition: X86ISelLowering.h:520
llvm::X86ISD::PINSRB
@ PINSRB
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
Definition: X86ISelLowering.h:185
llvm::X86ISD::STRICT_FCMP
@ STRICT_FCMP
X86 strict FP compare instructions.
Definition: X86ISelLowering.h:736
llvm::X86ISD::TLSBASEADDR
@ TLSBASEADDR
Definition: X86ISelLowering.h:292
llvm::X86ISD::VRANGE_SAE
@ VRANGE_SAE
Definition: X86ISelLowering.h:486
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:139
llvm::X86ISD::PMULUDQ
@ PMULUDQ
Definition: X86ISelLowering.h:528
llvm::X86ISD::AESENC128KL
@ AESENC128KL
Definition: X86ISelLowering.h:861
llvm::X86ISD::MMX_MOVD2W
@ MMX_MOVD2W
Copies a 32-bit value from the low word of a MMX vector to a GPR.
Definition: X86ISelLowering.h:165
llvm::X86ISD::STRICT_CVTPS2PH
@ STRICT_CVTPS2PH
Definition: X86ISelLowering.h:771
llvm::X86ISD::VSHRD
@ VSHRD
Definition: X86ISelLowering.h:449
llvm::X86TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: X86ISelLowering.cpp:33490
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Definition: X86ISelLowering.cpp:5681
llvm::X86ISD::TC_RETURN
@ TC_RETURN
Tail call return.
Definition: X86ISelLowering.h:312
llvm::X86ISD::VFCMADDCSH
@ VFCMADDCSH
Definition: X86ISelLowering.h:579
llvm::X86MaskedScatterSDNode::classof
static bool classof(const SDNode *N)
Definition: X86ISelLowering.h:1754
llvm::X86TargetLowering::isNarrowingProfitable
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
Definition: X86ISelLowering.cpp:33666
llvm::X86ISD::RCP28S
@ RCP28S
Definition: X86ISelLowering.h:699
llvm::X86ISD::NodeType
NodeType
Definition: X86ISelLowering.h:26
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1168
llvm::X86ISD::STRICT_CVTTP2UI
@ STRICT_CVTTP2UI
Definition: X86ISelLowering.h:748
llvm::X86ISD::VMTRUNC
@ VMTRUNC
Definition: X86ISelLowering.h:327
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::X86TargetLowering::reduceSelectOfFPConstantLoads
bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
Definition: X86ISelLowering.cpp:5568