Go to the documentation of this file.
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
22 class X86TargetMachine;
901 bool hasSymbolicDisplacement);
906 bool is64Bit,
bool IsVarArg,
bool GuaranteeTCO);
913 bool AllowPartialUndefs =
true);
918 bool AssumeSingleUse =
false);
923 const X86Subtarget &Subtarget,
924 bool AssumeSingleUse =
false);
962 unsigned JTI,
MCContext &Ctx)
const override;
986 bool *Fast)
const override;
1016 bool LegalOperations,
bool ForCodeSize,
1018 unsigned Depth)
const override;
1070 unsigned OldShiftOpcode,
unsigned NewShiftOpcode,
1080 unsigned KeptBits)
const override {
1085 auto VTIsOk = [](
EVT VT) ->
bool {
1093 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
1115 EVT VT)
const override;
1118 const APInt &DemandedElts,
1119 TargetLoweringOpt &TLO)
const override;
1125 const APInt &DemandedElts,
1127 unsigned Depth = 0)
const override;
1131 const APInt &DemandedElts,
1133 unsigned Depth)
const override;
1136 const APInt &DemandedElts,
1139 TargetLoweringOpt &TLO,
1140 unsigned Depth)
const override;
1143 const APInt &DemandedElts,
1145 TargetLoweringOpt &TLO,
1146 unsigned Depth)
const;
1150 const APInt &DemandedElts,
1152 TargetLoweringOpt &TLO,
1153 unsigned Depth)
const override;
1161 unsigned Depth)
const override;
1177 const char *constraint)
const override;
1185 std::string &Constraint,
1186 std::vector<SDValue> &Ops,
1191 if (ConstraintCode ==
"v")
1199 const AsmOperandInfo &Constraint,
1206 std::pair<unsigned, const TargetRegisterClass *>
1213 Type *Ty,
unsigned AS,
1237 unsigned AS)
const override;
1244 bool isBinOp(
unsigned Opcode)
const override;
1281 EVT VT)
const override;
1289 EVT VT)
const override;
1297 unsigned Intrinsic)
const override;
1303 bool ForCodeSize)
const override;
1320 EVT ConditionVT)
const override;
1330 EVT NewVT)
const override;
1339 Type *Ty)
const override;
1351 unsigned Index)
const override;
1368 bool MathUsed)
const override;
1371 unsigned AddrSpace)
const override {
1416 const SDLoc &
DL)
const override;
1436 EVT VT)
const override;
1440 EVT VT)
const override;
1444 unsigned &NumIntermediates,
MVT &RegisterVT)
const override;
1465 unsigned Factor)
const override;
1470 unsigned Factor)
const override;
1479 std::pair<const TargetRegisterClass *, uint8_t>
1481 MVT VT)
const override;
1489 std::vector<APFloat> LegalFPImmediates;
1493 void addLegalFPImmediate(
const APFloat& Imm) {
1494 LegalFPImmediates.push_back(Imm);
1497 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1499 const SmallVectorImpl<ISD::InputArg> &
Ins,
1500 const SDLoc &dl, SelectionDAG &DAG,
1501 SmallVectorImpl<SDValue> &InVals,
1504 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1505 const SDLoc &dl, SelectionDAG &DAG,
1506 const CCValAssign &VA, MachineFrameInfo &MFI,
1508 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue
Arg,
1509 const SDLoc &dl, SelectionDAG &DAG,
1510 const CCValAssign &VA,
1511 ISD::ArgFlagsTy Flags,
bool isByval)
const;
1517 bool IsEligibleForTailCallOptimization(
1518 SDValue Callee,
CallingConv::ID CalleeCC,
bool IsCalleeStackStructRet,
1519 bool isVarArg, Type *RetTy,
const SmallVectorImpl<ISD::OutputArg> &Outs,
1520 const SmallVectorImpl<SDValue> &OutVals,
1521 const SmallVectorImpl<ISD::InputArg> &
Ins, SelectionDAG &DAG)
const;
1522 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1523 SDValue Chain,
bool IsTailCall,
1524 bool Is64Bit,
int FPDiff,
1525 const SDLoc &dl)
const;
1527 unsigned GetAlignedArgumentStackSize(
unsigned StackSize,
1528 SelectionDAG &DAG)
const;
1530 unsigned getAddressSpace()
const;
1532 SDValue FP_TO_INTHelper(SDValue
Op, SelectionDAG &DAG,
bool IsSigned,
1533 SDValue &Chain)
const;
1534 SDValue LRINT_LLRINTHelper(SDNode *
N, SelectionDAG &DAG)
const;
1536 SDValue LowerBUILD_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1537 SDValue LowerVSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1538 SDValue LowerEXTRACT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1539 SDValue LowerINSERT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1541 unsigned getGlobalWrapperKind(
const GlobalValue *GV =
nullptr,
1542 const unsigned char OpFlags = 0)
const;
1543 SDValue LowerConstantPool(SDValue
Op, SelectionDAG &DAG)
const;
1544 SDValue LowerBlockAddress(SDValue
Op, SelectionDAG &DAG)
const;
1545 SDValue LowerGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
1546 SDValue LowerGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1547 SDValue LowerExternalSymbol(SDValue
Op, SelectionDAG &DAG)
const;
1551 SDValue LowerGlobalOrExternal(SDValue
Op, SelectionDAG &DAG,
1552 bool ForCall)
const;
1554 SDValue LowerSINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1555 SDValue LowerUINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1556 SDValue LowerTRUNCATE(SDValue
Op, SelectionDAG &DAG)
const;
1557 SDValue LowerFP_TO_INT(SDValue
Op, SelectionDAG &DAG)
const;
1558 SDValue LowerFP_TO_INT_SAT(SDValue
Op, SelectionDAG &DAG)
const;
1559 SDValue LowerLRINT_LLRINT(SDValue
Op, SelectionDAG &DAG)
const;
1560 SDValue LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const;
1561 SDValue LowerSETCCCARRY(SDValue
Op, SelectionDAG &DAG)
const;
1562 SDValue LowerSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1563 SDValue LowerBRCOND(SDValue
Op, SelectionDAG &DAG)
const;
1564 SDValue LowerJumpTable(SDValue
Op, SelectionDAG &DAG)
const;
1565 SDValue LowerDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1566 SDValue LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const;
1567 SDValue LowerVAARG(SDValue
Op, SelectionDAG &DAG)
const;
1568 SDValue LowerRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1569 SDValue LowerADDROFRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1570 SDValue LowerFRAMEADDR(SDValue
Op, SelectionDAG &DAG)
const;
1571 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue
Op, SelectionDAG &DAG)
const;
1572 SDValue LowerEH_RETURN(SDValue
Op, SelectionDAG &DAG)
const;
1573 SDValue lowerEH_SJLJ_SETJMP(SDValue
Op, SelectionDAG &DAG)
const;
1574 SDValue lowerEH_SJLJ_LONGJMP(SDValue
Op, SelectionDAG &DAG)
const;
1575 SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue
Op, SelectionDAG &DAG)
const;
1576 SDValue LowerINIT_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1577 SDValue LowerFLT_ROUNDS_(SDValue
Op, SelectionDAG &DAG)
const;
1578 SDValue LowerSET_ROUNDING(SDValue
Op, SelectionDAG &DAG)
const;
1579 SDValue LowerWin64_i128OP(SDValue
Op, SelectionDAG &DAG)
const;
1580 SDValue LowerWin64_FP_TO_INT128(SDValue
Op, SelectionDAG &DAG,
1581 SDValue &Chain)
const;
1582 SDValue LowerWin64_INT128_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1583 SDValue LowerGC_TRANSITION(SDValue
Op, SelectionDAG &DAG)
const;
1584 SDValue LowerINTRINSIC_WO_CHAIN(SDValue
Op, SelectionDAG &DAG)
const;
1585 SDValue lowerFaddFsub(SDValue
Op, SelectionDAG &DAG)
const;
1586 SDValue LowerFP_EXTEND(SDValue
Op, SelectionDAG &DAG)
const;
1587 SDValue LowerFP_ROUND(SDValue
Op, SelectionDAG &DAG)
const;
1590 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1591 const SmallVectorImpl<ISD::InputArg> &
Ins,
1592 const SDLoc &dl, SelectionDAG &DAG,
1593 SmallVectorImpl<SDValue> &InVals)
const override;
1594 SDValue LowerCall(CallLoweringInfo &CLI,
1595 SmallVectorImpl<SDValue> &InVals)
const override;
1597 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1598 const SmallVectorImpl<ISD::OutputArg> &Outs,
1599 const SmallVectorImpl<SDValue> &OutVals,
1600 const SDLoc &dl, SelectionDAG &DAG)
const override;
1602 bool supportSplitCSR(MachineFunction *MF)
const override {
1604 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1606 void initializeSplitCSR(MachineBasicBlock *Entry)
const override;
1607 void insertCopiesSplitCSR(
1608 MachineBasicBlock *Entry,
1609 const SmallVectorImpl<MachineBasicBlock *> &Exits)
const override;
1611 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
1613 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
1615 EVT getTypeForExtReturn(LLVMContext &
Context, EVT VT,
1620 const SmallVectorImpl<ISD::OutputArg> &Outs,
1621 LLVMContext &
Context)
const override;
1626 shouldExpandAtomicLoadInIR(LoadInst *LI)
const override;
1628 shouldExpandAtomicStoreInIR(StoreInst *
SI)
const override;
1630 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI)
const override;
1632 shouldExpandLogicAtomicRMWInIR(AtomicRMWInst *AI)
const;
1633 void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI)
const override;
1636 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI)
const override;
1638 bool lowerAtomicStoreAsStoreSDNode(
const StoreInst &
SI)
const override;
1639 bool lowerAtomicLoadAsLoadSDNode(
const LoadInst &LI)
const override;
1641 bool needsCmpXchgNb(Type *MemType)
const;
1643 void SetupEntryBlockForSjLj(MachineInstr &
MI, MachineBasicBlock *
MBB,
1644 MachineBasicBlock *DispatchBB,
int FI)
const;
1648 EmitVAARGWithCustomInserter(MachineInstr &
MI, MachineBasicBlock *
MBB)
const;
1651 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1653 MachineBasicBlock *
BB)
const;
1655 MachineBasicBlock *EmitLoweredSelect(MachineInstr &
I,
1656 MachineBasicBlock *
BB)
const;
1658 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &
MI,
1659 MachineBasicBlock *
BB)
const;
1661 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &
MI,
1662 MachineBasicBlock *
BB)
const;
1664 MachineBasicBlock *EmitLoweredProbedAlloca(MachineInstr &
MI,
1665 MachineBasicBlock *
BB)
const;
1667 MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &
MI,
1668 MachineBasicBlock *
BB)
const;
1670 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &
MI,
1671 MachineBasicBlock *
BB)
const;
1673 MachineBasicBlock *EmitLoweredIndirectThunk(MachineInstr &
MI,
1674 MachineBasicBlock *
BB)
const;
1676 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &
MI,
1677 MachineBasicBlock *
MBB)
const;
1679 void emitSetJmpShadowStackFix(MachineInstr &
MI,
1680 MachineBasicBlock *
MBB)
const;
1682 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &
MI,
1683 MachineBasicBlock *
MBB)
const;
1685 MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &
MI,
1686 MachineBasicBlock *
MBB)
const;
1688 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &
MI,
1689 MachineBasicBlock *
MBB)
const;
1693 SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1,
ISD::CondCode CC,
1694 const SDLoc &dl, SelectionDAG &DAG,
1695 SDValue &X86CC)
const;
1698 bool isFsqrtCheap(SDValue
Op, SelectionDAG &DAG)
const override;
1701 SDValue getSqrtEstimate(SDValue
Op, SelectionDAG &DAG,
int Enabled,
1702 int &RefinementSteps,
bool &UseOneConstNR,
1703 bool Reciprocal)
const override;
1706 SDValue getRecipEstimate(SDValue
Op, SelectionDAG &DAG,
int Enabled,
1707 int &RefinementSteps)
const override;
1710 unsigned combineRepeatedFPDivisors()
const override;
1712 SDValue BuildSDIVPow2(SDNode *
N,
const APInt &Divisor, SelectionDAG &DAG,
1713 SmallVectorImpl<SDNode *> &Created)
const override;
1718 const TargetLibraryInfo *libInfo);
1771 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
const SDValue & getIndex() const
This is an optimization pass for GlobalISel generic memory operations.
@ PEXTRW
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
bool hasStackProbeSymbol(MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Return true if sinking I's operands to the same basic block as I is profitable, e....
A parsed version of the target data layout string in and methods for querying it.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool mayFoldLoadIntoBroadcastFromMem(SDValue Op, MVT EltVT, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into a vector splat instruction as a memory oper...
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
@ LADD
LOCK-prefixed arithmetic read-modify-write instructions.
Context object for machine code objects.
static bool is64Bit(const char *name)
@ FSETCC
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
@ FMAX
Floating point max and min.
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
bool isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
@ FXOR
Bitwise logical XOR of floating point values.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
@ BRCOND
X86 conditional branches.
Represents one node in the SelectionDAG.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
This class is used to represent ISD::LOAD nodes.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
@ FST
This instruction implements a truncating store from FP stack slots.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
@ BLENDV
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
unsigned getStackProbeSize(MachineFunction &MF) const
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
The instances of the Type class are immutable: once they are created, they are never changed.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
A description of a memory reference used in the backend.
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
@ ANDNP
Bitwise Logical AND NOT of Packed FP values.
bool useSoftFloat() const override
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement)
Returns true of the given offset can be fit into displacement field of the instruction.
X86MaskedGatherScatterSDNode()=delete
Function Alias Analysis Results
bool mayFoldLoad(SDValue Op, const X86Subtarget &Subtarget, bool AssumeSingleUse=false)
Check if Op is a load operation that could be folded into some other x86 instruction as a memory oper...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
@ FMAXC
Commutative FMIN and FMAX.
unsigned const TargetRegisterInfo * TRI
bool SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) const
bool shouldScalarizeBinop(SDValue) const override
Scalar ops always have equal or better analysis/performance/power than the vector equivalent,...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
@ FSETCCM
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE.
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth) const override
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
@ CALL
These operations represent an abstract X86 call instruction, which includes a bunch of information.
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const override
Handle Lowering flag assembly outputs.
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
@ CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
@ PINSRW
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
@ STRICT_CMPM
Vector comparison generating mask bits for fp and integer signed and unsigned data types.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool useStackGuardXorFP() const override
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
@ PSHUFB
Shuffle 16 8-bit values within a vector.
@ CMOV
X86 conditional moves.
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
@ BT
X86 bit-test instructions.
(vector float) vec_cmpeq(*A, *B) C
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs)
If Op is a constant whose elements are all the same constant or undefined, return true and return the...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
@ NT_CALL
Same as call except it adds the NoTrack prefix.
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
@ FILD
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override
void createSplat2ShuffleMask(MVT VT, SmallVectorImpl< int > &Mask, bool Lo)
Similar to unpacklo/unpackhi, but without the 128-bit lane limitation imposed by AVX and specific to ...
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
bool isInteger() const
Return true if this is an integer or a vector integer type.
virtual bool needsFixedCatchObjects() const override
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const SDValue & getMask() const
bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const override
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
@ PEXTRB
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
@ VAARG_64
These instructions grab the address of the next argument from a va_list.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
@ IRET
Return from interrupt. Operand 0 is the number of bytes to pop.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
@ FMAXS
Scalar intrinsic floating point max and min.
Analysis containing CSE Info
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool areJTsAllowed(const Function *Fn) const override
Returns true if lowering to a jump table is allowed.
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isVectorShiftByScalarCheap(Type *Ty) const override
This is used to enable splatted operand transforms for vector shifts and vector funnel shifts.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
@ GlobalBaseReg
On Darwin, this node represents the result of the popl at function entry, used for PIC code.
@ EXTRQI
SSE4A Extraction and Insertion.
const SDValue & getScale() const
~X86MaskedGatherScatterSDNode()=delete
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code.
bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
An instruction for storing to memory.
This is an important base class in LLVM.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
@ MOVQ2DQ
Copies a 64-bit value from an MMX vector to the low word of an XMM vector, with the high word zero fi...
void createUnpackShuffleMask(EVT VT, SmallVectorImpl< int > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Customize the preferred legalization strategy for certain types.
Representation of each machine instruction.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
@ FSHL
X86 funnel/double shift i16 instructions.
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
@ FOR
Bitwise logical OR of floating point values.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
const SDValue & getOperand(unsigned Num) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
@ INSERTPS
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
NegatibleCost
Enum that specifies when a float negation is beneficial.
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
const SDValue & getValue() const
Flags
Flags values. These may be or'd together.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
RoundingMode
Current rounding mode is represented in bits 11:10 of FPSR.
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
@ FRSQRT
Floating point reciprocal-sqrt and reciprocal approximation.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
@ MOVDQ2Q
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
StandardInstrumentations SI(Debug, VerifyEach)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ DBPSADBW
Compute Double Block Packed Sum-Absolute-Differences.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
A Module instance is used to store all the information related to an LLVM module.
@ NT_BRIND
BRIND node with NoTrack prefix.
SDValue unwrapAddress(SDValue N) const override
bool mayFoldIntoZeroExtend(SDValue Op)
Check if Op is an operation that could be folded into a zero extend x86 instruction.
Class for arbitrary precision integers.
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
bool isVector() const
Return true if this is a vector value type.
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
@ PSADBW
Compute Sum of Absolute Differences.
StringRef - Represent a constant reference to a string, i.e.
@ FP_TO_INT_IN_MEM
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source.
static bool classof(const SDNode *N)
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
@ FLD
This instruction implements an extending load to FP stack slots.
@ BLENDI
Blend where the selector is an immediate.
Common base class shared among various IRBuilders.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const SDValue & getPassThru() const
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const override
Expands target specific indirect branch for the case of JumpTable expanasion.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
An instruction for reading from memory.
@ Wrapper
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress,...
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
Wrapper class representing virtual and physical registers.
std::vector< ArgListEntry > ArgListTy
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
const SDValue & getBasePtr() const
@ FHADD
Floating point horizontal add/sub.
@ MMX_MOVW2D
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool shouldConvertPhiType(Type *From, Type *To) const override
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To',...
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
static bool classof(const SDNode *N)
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool mergeStoresAfterLegalization(EVT MemVT) const override
Do not merge vector stores after legalization because that may conflict with x86-specific store split...
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
@ FAND
Bitwise logical AND of floating point values.
MVT hasFastEqualityCompare(unsigned NumBits) const override
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Provides information about what library functions are available for the current target.
@ RET_FLAG
Return with a flag operand.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
@ HADD
Integer horizontal add/sub.
bool isBinOp(unsigned Opcode) const override
Add x86-specific opcodes to the default list.
bool mayFoldIntoStore(SDValue Op)
Check if Op is a value that could be used to fold a store into some other x86 instruction as a memory...
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
bool isCommutativeBinOp(unsigned Opcode) const override
Returns true if the opcode is a commutative binary operation.
This instruction constructs a fixed permutation of two input vectors.
std::pair< SDValue, SDValue > BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) const
bool shouldSplatInsEltVarIndex(EVT VT) const override
Return true if inserting a scalar into a variable element of an undef vector is more efficiently hand...
bool isLegalStoreImmediate(int64_t Imm) const override
Return true if the specified immediate is legal for the value input of a store instruction.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
@ ADDSUB
Combined add and sub on an FP vector.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
@ LCMPXCHG16_SAVE_RBX_DAG
@ CMP
X86 compare and logical compare instructions.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating exp...
MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const override
Returns preferred type for switch condition.
@ FANDN
Bitwise logical ANDNOT of floating point values.
const char LLVMTargetMachineRef TM
This class represents a function call, abstracting a target machine's calling convention.
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
bool softPromoteHalfType() const override
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
BlockVerifier::State From
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
@ WrapperRIP
Special wrapper used under X86-64 PIC mode for RIP relative displacements.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
@ FIST
This instruction implements a fp->int store from FP stack slots.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
SDValue SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const override
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower interleaved store(s) into target specific instructions/intrinsics.
LLVM Value Representation.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
@ PINSRB
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
@ STRICT_FCMP
X86 strict FP compare instructions.
Base class for the full range of assembler expressions which are needed for parsing.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
@ MMX_MOVD2W
Copies a 32-bit value from the low word of a MMX vector to a GPR.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
@ TC_RETURN
Tail call return.
static bool classof(const SDNode *N)
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
static MVT getIntegerVT(unsigned BitWidth)
bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const override
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...