X86TargetTransformInfo.cpp

Go to the documentation of this file.

//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// X86 target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
/// About Cost Model numbers used below it's necessary to say the following:
/// the numbers correspond to some "generic" X86 CPU instead of usage of a
/// specific CPU model. Usually the numbers correspond to the CPU where the
/// feature first appeared. For example, if we do Subtarget.hasSSE42() in
/// the lookups below the cost is based on Nehalem as that was the first CPU
/// to support that feature level and thus has most likely the worst case cost,
/// although we may discard an outlying worst cost from one CPU (e.g. Atom).
///
/// Some examples of other technologies/CPUs:
///   SSE 3   - Pentium4 / Athlon64
///   SSE 4.1 - Penryn
///   SSE 4.2 - Nehalem / Silvermont
///   AVX     - Sandy Bridge / Jaguar / Bulldozer
///   AVX2    - Haswell / Ryzen
///   AVX-512 - Xeon Phi / Skylake
///
/// And some examples of instruction target dependent costs (latency)
///                   divss     sqrtss          rsqrtss
///   AMD K7          11-16     19              3
///   Piledriver      9-24      13-15           5
///   Jaguar          14        16              2
///   Pentium II,III  18        30              2
///   Nehalem         7-14      7-18            3
///   Haswell         10-13     11              5
///
/// Interpreting the 4 TargetCostKind types:
/// TCK_RecipThroughput and TCK_Latency should try to match the worst case
/// values reported by the CPU scheduler models (and llvm-mca).
/// TCK_CodeSize should match the instruction count (e.g. divss = 1), NOT the
/// actual encoding size of the instruction.
/// TCK_SizeAndLatency should match the worst case micro-op counts reported by
/// by the CPU scheduler models (and llvm-mca), to ensure that they are
/// compatible with the MicroOpBufferSize and LoopMicroOpBufferSize values which are
/// often used as the cost thresholds where TCK_SizeAndLatency is requested.
//===----------------------------------------------------------------------===//
 
#include "X86TargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/CostTable.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/InstIterator.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/Support/Debug.h"
#include <optional>
 
using namespace llvm;
 
#define DEBUG_TYPE "x86tti"
 
//===----------------------------------------------------------------------===//
//
// X86 cost model.
//
//===----------------------------------------------------------------------===//
 
// Helper struct to store/access costs for each cost kind.
// TODO: Move this to allow other targets to use it?
struct CostKindCosts {
  unsigned RecipThroughputCost = ~0U;
  unsigned LatencyCost = ~0U;
  unsigned CodeSizeCost = ~0U;
  unsigned SizeAndLatencyCost = ~0U;
 
  std::optional<unsigned>
  operator[](TargetTransformInfo::TargetCostKind Kind) const {
    unsigned Cost = ~0U;
    switch (Kind) {
    case TargetTransformInfo::TCK_RecipThroughput:
      Cost = RecipThroughputCost;
      break;
    case TargetTransformInfo::TCK_Latency:
      Cost = LatencyCost;
      break;
    case TargetTransformInfo::TCK_CodeSize:
      Cost = CodeSizeCost;
      break;
    case TargetTransformInfo::TCK_SizeAndLatency:
      Cost = SizeAndLatencyCost;
      break;
    }
    if (Cost == ~0U)
      return std::nullopt;
    return Cost;
  }
};
using CostKindTblEntry = CostTblEntryT<CostKindCosts>;
 
TargetTransformInfo::PopcntSupportKind
X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
  // TODO: Currently the __builtin_popcount() implementation using SSE3
  //   instructions is inefficient. Once the problem is fixed, we should
  //   call ST->hasSSE3() instead of ST->hasPOPCNT().
  return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
}
 
std::optional<unsigned> X86TTIImpl::getCacheSize(
  TargetTransformInfo::CacheLevel Level) const {
  switch (Level) {
  case TargetTransformInfo::CacheLevel::L1D:
    //   - Penryn
    //   - Nehalem
    //   - Westmere
    //   - Sandy Bridge
    //   - Ivy Bridge
    //   - Haswell
    //   - Broadwell
    //   - Skylake
    //   - Kabylake
    return 32 * 1024;  //  32 KByte
  case TargetTransformInfo::CacheLevel::L2D:
    //   - Penryn
    //   - Nehalem
    //   - Westmere
    //   - Sandy Bridge
    //   - Ivy Bridge
    //   - Haswell
    //   - Broadwell
    //   - Skylake
    //   - Kabylake
    return 256 * 1024; // 256 KByte
  }
 
  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
}
 
std::optional<unsigned> X86TTIImpl::getCacheAssociativity(
  TargetTransformInfo::CacheLevel Level) const {
  //   - Penryn
  //   - Nehalem
  //   - Westmere
  //   - Sandy Bridge
  //   - Ivy Bridge
  //   - Haswell
  //   - Broadwell
  //   - Skylake
  //   - Kabylake
  switch (Level) {
  case TargetTransformInfo::CacheLevel::L1D:
    [[fallthrough]];
  case TargetTransformInfo::CacheLevel::L2D:
    return 8;
  }
 
  llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
}
 
unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const {
  bool Vector = (ClassID == 1);
  if (Vector && !ST->hasSSE1())
    return 0;
 
  if (ST->is64Bit()) {
    if (Vector && ST->hasAVX512())
      return 32;
    return 16;
  }
  return 8;
}
 
TypeSize
X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
  unsigned PreferVectorWidth = ST->getPreferVectorWidth();
  switch (K) {
  case TargetTransformInfo::RGK_Scalar:
    return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
  case TargetTransformInfo::RGK_FixedWidthVector:
    if (ST->hasAVX512() && PreferVectorWidth >= 512)
      return TypeSize::getFixed(512);
    if (ST->hasAVX() && PreferVectorWidth >= 256)
      return TypeSize::getFixed(256);
    if (ST->hasSSE1() && PreferVectorWidth >= 128)
      return TypeSize::getFixed(128);
    return TypeSize::getFixed(0);
  case TargetTransformInfo::RGK_ScalableVector:
    return TypeSize::getScalable(0);
  }
 
  llvm_unreachable("Unsupported register kind");
}
 
unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
  return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
      .getFixedValue();
}
 
unsigned X86TTIImpl::getMaxInterleaveFactor(ElementCount VF) {
  // If the loop will not be vectorized, don't interleave the loop.
  // Let regular unroll to unroll the loop, which saves the overflow
  // check and memory check cost.
  if (VF.isScalar())
    return 1;
 
  if (ST->isAtom())
    return 1;
 
  // Sandybridge and Haswell have multiple execution ports and pipelined
  // vector units.
  if (ST->hasAVX())
    return 4;
 
  return 2;
}
 
InstructionCost X86TTIImpl::getArithmeticInstrCost(
    unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
    TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
    ArrayRef<const Value *> Args,
    const Instruction *CxtI) {
 
  // vXi8 multiplications are always promoted to vXi16.
  // Sub-128-bit types can be extended/packed more efficiently.
  if (Opcode == Instruction::Mul && Ty->isVectorTy() &&
      Ty->getPrimitiveSizeInBits() <= 64 && Ty->getScalarSizeInBits() == 8) {
    Type *WideVecTy =
        VectorType::getExtendedElementVectorType(cast<VectorType>(Ty));
    return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty,
                            TargetTransformInfo::CastContextHint::None,
                            CostKind) +
           getCastInstrCost(Instruction::Trunc, Ty, WideVecTy,
                            TargetTransformInfo::CastContextHint::None,
                            CostKind) +
           getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info);
  }
 
  // Legalize the type.
  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
 
  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Invalid opcode");
 
  if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
      LT.second.getScalarType() == MVT::i32) {
    // Check if the operands can be represented as a smaller datatype.
    bool Op1Signed = false, Op2Signed = false;
    unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
    unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
    unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
    bool SignedMode = Op1Signed || Op2Signed;
 
    // If both are representable as i15 and at least one is constant,
    // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we
    // can treat this as PMADDWD which has the same costs as a vXi16 multiply.
    if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) {
      bool Op1Constant =
          isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]);
      bool Op2Constant =
          isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]);
      bool Op1Sext = isa<SExtInst>(Args[0]) &&
                     (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41()));
      bool Op2Sext = isa<SExtInst>(Args[1]) &&
                     (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41()));
 
      bool IsZeroExtended = !Op1Signed || !Op2Signed;
      bool IsConstant = Op1Constant || Op2Constant;
      bool IsSext = Op1Sext || Op2Sext;
      if (IsConstant || IsZeroExtended || IsSext)
        LT.second =
            MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements());
    }
 
    // Check if the vXi32 operands can be shrunk into a smaller datatype.
    // This should match the codegen from reduceVMULWidth.
    // TODO: Make this generic (!ST->SSE41 || ST->isPMULLDSlow()).
    if (ST->useSLMArithCosts() && LT.second == MVT::v4i32) {
      if (OpMinSize <= 7)
        return LT.first * 3; // pmullw/sext
      if (!SignedMode && OpMinSize <= 8)
        return LT.first * 3; // pmullw/zext
      if (OpMinSize <= 15)
        return LT.first * 5; // pmullw/pmulhw/pshuf
      if (!SignedMode && OpMinSize <= 16)
        return LT.first * 5; // pmullw/pmulhw/pshuf
    }
  }
 
  // Vector multiply by pow2 will be simplified to shifts.
  // Vector multiply by -pow2 will be simplified to shifts/negates.
  if (ISD == ISD::MUL && Op2Info.isConstant() &&
      (Op2Info.isPowerOf2() || Op2Info.isNegatedPowerOf2())) {
    InstructionCost Cost =
        getArithmeticInstrCost(Instruction::Shl, Ty, CostKind,
                               Op1Info.getNoProps(), Op2Info.getNoProps());
    if (Op2Info.isNegatedPowerOf2())
      Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind);
    return Cost;
  }
 
  // On X86, vector signed division by constants power-of-two are
  // normally expanded to the sequence SRA + SRL + ADD + SRA.
  // The OperandValue properties may not be the same as that of the previous
  // operation; conservatively assume OP_None.
  if ((ISD == ISD::SDIV || ISD == ISD::SREM) &&
      Op2Info.isConstant() && Op2Info.isPowerOf2()) {
    InstructionCost Cost =
        2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind,
                                   Op1Info.getNoProps(), Op2Info.getNoProps());
    Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
                                   Op1Info.getNoProps(), Op2Info.getNoProps());
    Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind,
                                   Op1Info.getNoProps(), Op2Info.getNoProps());
 
    if (ISD == ISD::SREM) {
      // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
      Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info.getNoProps(),
                                     Op2Info.getNoProps());
      Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info.getNoProps(),
                                     Op2Info.getNoProps());
    }
 
    return Cost;
  }
 
  // Vector unsigned division/remainder will be simplified to shifts/masks.
  if ((ISD == ISD::UDIV || ISD == ISD::UREM) &&
      Op2Info.isConstant() && Op2Info.isPowerOf2()) {
    if (ISD == ISD::UDIV)
      return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
                                    Op1Info.getNoProps(), Op2Info.getNoProps());
    // UREM
    return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
                                  Op1Info.getNoProps(), Op2Info.getNoProps());
  }
 
  static const CostKindTblEntry AVX512BWUniformConstCostTable[] = {
    { ISD::SHL,  MVT::v16i8,  { 1, 7, 2, 3 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8,  { 1, 7, 2, 3 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8,  { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v32i8,  { 1, 8, 2, 3 } }, // psllw + pand.
    { ISD::SRL,  MVT::v32i8,  { 1, 8, 2, 3 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v32i8,  { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v64i8,  { 1, 8, 2, 3 } }, // psllw + pand.
    { ISD::SRL,  MVT::v64i8,  { 1, 8, 2, 3 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v64i8,  { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb.
 
    { ISD::SHL,  MVT::v16i16, { 1, 1, 1, 1 } }, // psllw
    { ISD::SRL,  MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
    { ISD::SRA,  MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
    { ISD::SHL,  MVT::v32i16, { 1, 1, 1, 1 } }, // psllw
    { ISD::SRL,  MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
    { ISD::SRA,  MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
  };
 
  if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasBWI())
    if (const auto *Entry =
            CostTableLookup(AVX512BWUniformConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512UniformConstCostTable[] = {
    { ISD::SHL,  MVT::v64i8,  {  2, 12,  5,  6 } }, // psllw + pand.
    { ISD::SRL,  MVT::v64i8,  {  2, 12,  5,  6 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v64i8,  {  3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb.
 
    { ISD::SHL,  MVT::v16i16, {  2,  7,  4,  4 } }, // psllw + split.
    { ISD::SRL,  MVT::v16i16, {  2,  7,  4,  4 } }, // psrlw + split.
    { ISD::SRA,  MVT::v16i16, {  2,  7,  4,  4 } }, // psraw + split.
 
    { ISD::SHL,  MVT::v8i32,  {  1,  1,  1,  1 } }, // pslld
    { ISD::SRL,  MVT::v8i32,  {  1,  1,  1,  1 } }, // psrld
    { ISD::SRA,  MVT::v8i32,  {  1,  1,  1,  1 } }, // psrad
    { ISD::SHL,  MVT::v16i32, {  1,  1,  1,  1 } }, // pslld
    { ISD::SRL,  MVT::v16i32, {  1,  1,  1,  1 } }, // psrld
    { ISD::SRA,  MVT::v16i32, {  1,  1,  1,  1 } }, // psrad
 
    { ISD::SRA,  MVT::v2i64,  {  1,  1,  1,  1 } }, // psraq
    { ISD::SHL,  MVT::v4i64,  {  1,  1,  1,  1 } }, // psllq
    { ISD::SRL,  MVT::v4i64,  {  1,  1,  1,  1 } }, // psrlq
    { ISD::SRA,  MVT::v4i64,  {  1,  1,  1,  1 } }, // psraq
    { ISD::SHL,  MVT::v8i64,  {  1,  1,  1,  1 } }, // psllq
    { ISD::SRL,  MVT::v8i64,  {  1,  1,  1,  1 } }, // psrlq
    { ISD::SRA,  MVT::v8i64,  {  1,  1,  1,  1 } }, // psraq
 
    { ISD::SDIV, MVT::v16i32, {  6 } }, // pmuludq sequence
    { ISD::SREM, MVT::v16i32, {  8 } }, // pmuludq+mul+sub sequence
    { ISD::UDIV, MVT::v16i32, {  5 } }, // pmuludq sequence
    { ISD::UREM, MVT::v16i32, {  7 } }, // pmuludq+mul+sub sequence
  };
 
  if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX512())
    if (const auto *Entry =
            CostTableLookup(AVX512UniformConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX2UniformConstCostTable[] = {
    { ISD::SHL,  MVT::v16i8, {  1,  8,  2,  3 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8, {  1,  8,  2,  3 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8, {  2, 10,  5,  6 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v32i8, {  2,  8,  2,  4 } }, // psllw + pand.
    { ISD::SRL,  MVT::v32i8, {  2,  8,  2,  4 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v32i8, {  3, 10,  5,  9 } }, // psrlw, pand, pxor, psubb.
 
    { ISD::SHL,  MVT::v8i16, {  1,  1,  1,  1 } }, // psllw
    { ISD::SRL,  MVT::v8i16, {  1,  1,  1,  1 } }, // psrlw
    { ISD::SRA,  MVT::v8i16, {  1,  1,  1,  1 } }, // psraw
    { ISD::SHL,  MVT::v16i16,{  2,  2,  1,  2 } }, // psllw
    { ISD::SRL,  MVT::v16i16,{  2,  2,  1,  2 } }, // psrlw
    { ISD::SRA,  MVT::v16i16,{  2,  2,  1,  2 } }, // psraw
 
    { ISD::SHL,  MVT::v4i32, {  1,  1,  1,  1 } }, // pslld
    { ISD::SRL,  MVT::v4i32, {  1,  1,  1,  1 } }, // psrld
    { ISD::SRA,  MVT::v4i32, {  1,  1,  1,  1 } }, // psrad
    { ISD::SHL,  MVT::v8i32, {  2,  2,  1,  2 } }, // pslld
    { ISD::SRL,  MVT::v8i32, {  2,  2,  1,  2 } }, // psrld
    { ISD::SRA,  MVT::v8i32, {  2,  2,  1,  2 } }, // psrad
 
    { ISD::SHL,  MVT::v2i64, {  1,  1,  1,  1 } }, // psllq
    { ISD::SRL,  MVT::v2i64, {  1,  1,  1,  1 } }, // psrlq
    { ISD::SRA,  MVT::v2i64, {  2,  3,  3,  3 } }, // psrad + shuffle.
    { ISD::SHL,  MVT::v4i64, {  2,  2,  1,  2 } }, // psllq
    { ISD::SRL,  MVT::v4i64, {  2,  2,  1,  2 } }, // psrlq
    { ISD::SRA,  MVT::v4i64, {  4,  4,  3,  6 } }, // psrad + shuffle + split.
 
    { ISD::SDIV, MVT::v8i32, {  6 } }, // pmuludq sequence
    { ISD::SREM, MVT::v8i32, {  8 } }, // pmuludq+mul+sub sequence
    { ISD::UDIV, MVT::v8i32, {  5 } }, // pmuludq sequence
    { ISD::UREM, MVT::v8i32, {  7 } }, // pmuludq+mul+sub sequence
  };
 
  if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX2())
    if (const auto *Entry =
            CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVXUniformConstCostTable[] = {
    { ISD::SHL,  MVT::v16i8, {  2,  7,  2,  3 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8, {  2,  7,  2,  3 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8, {  3,  9,  5,  6 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v32i8, {  4,  7,  7,  8 } }, // 2*(psllw + pand) + split.
    { ISD::SRL,  MVT::v32i8, {  4,  7,  7,  8 } }, // 2*(psrlw + pand) + split.
    { ISD::SRA,  MVT::v32i8, {  7,  7, 12, 13 } }, // 2*(psrlw, pand, pxor, psubb) + split.
 
    { ISD::SHL,  MVT::v8i16, {  1,  2,  1,  1 } }, // psllw.
    { ISD::SRL,  MVT::v8i16, {  1,  2,  1,  1 } }, // psrlw.
    { ISD::SRA,  MVT::v8i16, {  1,  2,  1,  1 } }, // psraw.
    { ISD::SHL,  MVT::v16i16,{  3,  6,  4,  5 } }, // psllw + split.
    { ISD::SRL,  MVT::v16i16,{  3,  6,  4,  5 } }, // psrlw + split.
    { ISD::SRA,  MVT::v16i16,{  3,  6,  4,  5 } }, // psraw + split.
 
    { ISD::SHL,  MVT::v4i32, {  1,  2,  1,  1 } }, // pslld.
    { ISD::SRL,  MVT::v4i32, {  1,  2,  1,  1 } }, // psrld.
    { ISD::SRA,  MVT::v4i32, {  1,  2,  1,  1 } }, // psrad.
    { ISD::SHL,  MVT::v8i32, {  3,  6,  4,  5 } }, // pslld + split.
    { ISD::SRL,  MVT::v8i32, {  3,  6,  4,  5 } }, // psrld + split.
    { ISD::SRA,  MVT::v8i32, {  3,  6,  4,  5 } }, // psrad + split.
 
    { ISD::SHL,  MVT::v2i64, {  1,  2,  1,  1 } }, // psllq.
    { ISD::SRL,  MVT::v2i64, {  1,  2,  1,  1 } }, // psrlq.
    { ISD::SRA,  MVT::v2i64, {  2,  3,  3,  3 } }, // psrad + shuffle.
    { ISD::SHL,  MVT::v4i64, {  3,  6,  4,  5 } }, // 2 x psllq + split.
    { ISD::SRL,  MVT::v4i64, {  3,  6,  4,  5 } }, // 2 x psllq + split.
    { ISD::SRA,  MVT::v4i64, {  5,  7,  8,  9 } }, // 2 x psrad + shuffle + split.
 
    { ISD::SDIV, MVT::v8i32, { 14 } }, // 2*pmuludq sequence + split.
    { ISD::SREM, MVT::v8i32, { 18 } }, // 2*pmuludq+mul+sub sequence + split.
    { ISD::UDIV, MVT::v8i32, { 12 } }, // 2*pmuludq sequence + split.
    { ISD::UREM, MVT::v8i32, { 16 } }, // 2*pmuludq+mul+sub sequence + split.
  };
 
  // XOP has faster vXi8 shifts.
  if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX() &&
      (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
    if (const auto *Entry =
            CostTableLookup(AVXUniformConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE2UniformConstCostTable[] = {
    { ISD::SHL,  MVT::v16i8, {  1,  7,  2,  3 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8, {  1,  7,  2,  3 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8, {  3,  9,  5,  6 } }, // psrlw, pand, pxor, psubb.
 
    { ISD::SHL,  MVT::v8i16, {  1,  1,  1,  1 } }, // psllw.
    { ISD::SRL,  MVT::v8i16, {  1,  1,  1,  1 } }, // psrlw.
    { ISD::SRA,  MVT::v8i16, {  1,  1,  1,  1 } }, // psraw.
 
    { ISD::SHL,  MVT::v4i32, {  1,  1,  1,  1 } }, // pslld
    { ISD::SRL,  MVT::v4i32, {  1,  1,  1,  1 } }, // psrld.
    { ISD::SRA,  MVT::v4i32, {  1,  1,  1,  1 } }, // psrad.
 
    { ISD::SHL,  MVT::v2i64, {  1,  1,  1,  1 } }, // psllq.
    { ISD::SRL,  MVT::v2i64, {  1,  1,  1,  1 } }, // psrlq.
    { ISD::SRA,  MVT::v2i64, {  3,  5,  6,  6 } }, // 2 x psrad + shuffle.
 
    { ISD::SDIV, MVT::v4i32, {  6 } }, // pmuludq sequence
    { ISD::SREM, MVT::v4i32, {  8 } }, // pmuludq+mul+sub sequence
    { ISD::UDIV, MVT::v4i32, {  5 } }, // pmuludq sequence
    { ISD::UREM, MVT::v4i32, {  7 } }, // pmuludq+mul+sub sequence
  };
 
  // XOP has faster vXi8 shifts.
  if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasSSE2() &&
      (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
    if (const auto *Entry =
            CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512BWConstCostTable[] = {
    { ISD::SDIV, MVT::v64i8,  { 14 } }, // 2*ext+2*pmulhw sequence
    { ISD::SREM, MVT::v64i8,  { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v64i8,  { 14 } }, // 2*ext+2*pmulhw sequence
    { ISD::UREM, MVT::v64i8,  { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
 
    { ISD::SDIV, MVT::v32i16, {  6 } }, // vpmulhw sequence
    { ISD::SREM, MVT::v32i16, {  8 } }, // vpmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v32i16, {  6 } }, // vpmulhuw sequence
    { ISD::UREM, MVT::v32i16, {  8 } }, // vpmulhuw+mul+sub sequence
  };
 
  if (Op2Info.isConstant() && ST->hasBWI())
    if (const auto *Entry =
            CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512ConstCostTable[] = {
    { ISD::SDIV, MVT::v64i8,  { 28 } }, // 4*ext+4*pmulhw sequence
    { ISD::SREM, MVT::v64i8,  { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v64i8,  { 28 } }, // 4*ext+4*pmulhw sequence
    { ISD::UREM, MVT::v64i8,  { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
 
    { ISD::SDIV, MVT::v32i16, { 12 } }, // 2*vpmulhw sequence
    { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v32i16, { 12 } }, // 2*vpmulhuw sequence
    { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence
 
    { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence
    { ISD::SREM, MVT::v16i32, { 17 } }, // vpmuldq+mul+sub sequence
    { ISD::UDIV, MVT::v16i32, { 15 } }, // vpmuludq sequence
    { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence
  };
 
  if (Op2Info.isConstant() && ST->hasAVX512())
    if (const auto *Entry =
            CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX2ConstCostTable[] = {
    { ISD::SDIV, MVT::v32i8,  { 14 } }, // 2*ext+2*pmulhw sequence
    { ISD::SREM, MVT::v32i8,  { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v32i8,  { 14 } }, // 2*ext+2*pmulhw sequence
    { ISD::UREM, MVT::v32i8,  { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
 
    { ISD::SDIV, MVT::v16i16, {  6 } }, // vpmulhw sequence
    { ISD::SREM, MVT::v16i16, {  8 } }, // vpmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v16i16, {  6 } }, // vpmulhuw sequence
    { ISD::UREM, MVT::v16i16, {  8 } }, // vpmulhuw+mul+sub sequence
 
    { ISD::SDIV, MVT::v8i32,  { 15 } }, // vpmuldq sequence
    { ISD::SREM, MVT::v8i32,  { 19 } }, // vpmuldq+mul+sub sequence
    { ISD::UDIV, MVT::v8i32,  { 15 } }, // vpmuludq sequence
    { ISD::UREM, MVT::v8i32,  { 19 } }, // vpmuludq+mul+sub sequence
  };
 
  if (Op2Info.isConstant() && ST->hasAVX2())
    if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVXConstCostTable[] = {
    { ISD::SDIV, MVT::v32i8,  { 30 } }, // 4*ext+4*pmulhw sequence + split.
    { ISD::SREM, MVT::v32i8,  { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
    { ISD::UDIV, MVT::v32i8,  { 30 } }, // 4*ext+4*pmulhw sequence + split.
    { ISD::UREM, MVT::v32i8,  { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
 
    { ISD::SDIV, MVT::v16i16, { 14 } }, // 2*pmulhw sequence + split.
    { ISD::SREM, MVT::v16i16, { 18 } }, // 2*pmulhw+mul+sub sequence + split.
    { ISD::UDIV, MVT::v16i16, { 14 } }, // 2*pmulhuw sequence + split.
    { ISD::UREM, MVT::v16i16, { 18 } }, // 2*pmulhuw+mul+sub sequence + split.
 
    { ISD::SDIV, MVT::v8i32,  { 32 } }, // vpmuludq sequence
    { ISD::SREM, MVT::v8i32,  { 38 } }, // vpmuludq+mul+sub sequence
    { ISD::UDIV, MVT::v8i32,  { 32 } }, // 2*pmuludq sequence + split.
    { ISD::UREM, MVT::v8i32,  { 42 } }, // 2*pmuludq+mul+sub sequence + split.
  };
 
  if (Op2Info.isConstant() && ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVXConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE41ConstCostTable[] = {
    { ISD::SDIV, MVT::v4i32,  { 15 } }, // vpmuludq sequence
    { ISD::SREM, MVT::v4i32,  { 20 } }, // vpmuludq+mul+sub sequence
  };
 
  if (Op2Info.isConstant() && ST->hasSSE41())
    if (const auto *Entry =
            CostTableLookup(SSE41ConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE2ConstCostTable[] = {
    { ISD::SDIV, MVT::v16i8,  { 14 } }, // 2*ext+2*pmulhw sequence
    { ISD::SREM, MVT::v16i8,  { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v16i8,  { 14 } }, // 2*ext+2*pmulhw sequence
    { ISD::UREM, MVT::v16i8,  { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
 
    { ISD::SDIV, MVT::v8i16,  {  6 } }, // pmulhw sequence
    { ISD::SREM, MVT::v8i16,  {  8 } }, // pmulhw+mul+sub sequence
    { ISD::UDIV, MVT::v8i16,  {  6 } }, // pmulhuw sequence
    { ISD::UREM, MVT::v8i16,  {  8 } }, // pmulhuw+mul+sub sequence
 
    { ISD::SDIV, MVT::v4i32,  { 19 } }, // pmuludq sequence
    { ISD::SREM, MVT::v4i32,  { 24 } }, // pmuludq+mul+sub sequence
    { ISD::UDIV, MVT::v4i32,  { 15 } }, // pmuludq sequence
    { ISD::UREM, MVT::v4i32,  { 20 } }, // pmuludq+mul+sub sequence
  };
 
  if (Op2Info.isConstant() && ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512BWUniformCostTable[] = {
    { ISD::SHL,  MVT::v16i8,  { 3, 5, 5, 7 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8,  { 3,10, 5, 8 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8,  { 4,12, 8,12 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v32i8,  { 4, 7, 6, 8 } }, // psllw + pand.
    { ISD::SRL,  MVT::v32i8,  { 4, 8, 7, 9 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v32i8,  { 5,10,10,13 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v64i8,  { 4, 7, 6, 8 } }, // psllw + pand.
    { ISD::SRL,  MVT::v64i8,  { 4, 8, 7,10 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v64i8,  { 5,10,10,15 } }, // psrlw, pand, pxor, psubb.
 
    { ISD::SHL,  MVT::v32i16, { 2, 4, 2, 3 } }, // psllw
    { ISD::SRL,  MVT::v32i16, { 2, 4, 2, 3 } }, // psrlw
    { ISD::SRA,  MVT::v32i16, { 2, 4, 2, 3 } }, // psrqw
  };
 
  if (ST->hasBWI() && Op2Info.isUniform())
    if (const auto *Entry =
            CostTableLookup(AVX512BWUniformCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512UniformCostTable[] = {
    { ISD::SHL,  MVT::v32i16, { 5,10, 5, 7 } }, // psllw + split.
    { ISD::SRL,  MVT::v32i16, { 5,10, 5, 7 } }, // psrlw + split.
    { ISD::SRA,  MVT::v32i16, { 5,10, 5, 7 } }, // psraw + split.
 
    { ISD::SHL,  MVT::v16i32, { 2, 4, 2, 3 } }, // pslld
    { ISD::SRL,  MVT::v16i32, { 2, 4, 2, 3 } }, // psrld
    { ISD::SRA,  MVT::v16i32, { 2, 4, 2, 3 } }, // psrad
 
    { ISD::SRA,  MVT::v2i64,  { 1, 2, 1, 2 } }, // psraq
    { ISD::SHL,  MVT::v4i64,  { 1, 4, 1, 2 } }, // psllq
    { ISD::SRL,  MVT::v4i64,  { 1, 4, 1, 2 } }, // psrlq
    { ISD::SRA,  MVT::v4i64,  { 1, 4, 1, 2 } }, // psraq
    { ISD::SHL,  MVT::v8i64,  { 1, 4, 1, 2 } }, // psllq
    { ISD::SRL,  MVT::v8i64,  { 1, 4, 1, 2 } }, // psrlq
    { ISD::SRA,  MVT::v8i64,  { 1, 4, 1, 2 } }, // psraq
  };
 
  if (ST->hasAVX512() && Op2Info.isUniform())
    if (const auto *Entry =
            CostTableLookup(AVX512UniformCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX2UniformCostTable[] = {
    // Uniform splats are cheaper for the following instructions.
    { ISD::SHL,  MVT::v16i8,  { 3, 5, 5, 7 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8,  { 3, 9, 5, 8 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8,  { 4, 5, 9,13 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v32i8,  { 4, 7, 6, 8 } }, // psllw + pand.
    { ISD::SRL,  MVT::v32i8,  { 4, 8, 7, 9 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v32i8,  { 6, 9,11,16 } }, // psrlw, pand, pxor, psubb.
 
    { ISD::SHL,  MVT::v8i16,  { 1, 2, 1, 2 } }, // psllw.
    { ISD::SRL,  MVT::v8i16,  { 1, 2, 1, 2 } }, // psrlw.
    { ISD::SRA,  MVT::v8i16,  { 1, 2, 1, 2 } }, // psraw.
    { ISD::SHL,  MVT::v16i16, { 2, 4, 2, 3 } }, // psllw.
    { ISD::SRL,  MVT::v16i16, { 2, 4, 2, 3 } }, // psrlw.
    { ISD::SRA,  MVT::v16i16, { 2, 4, 2, 3 } }, // psraw.
 
    { ISD::SHL,  MVT::v4i32,  { 1, 2, 1, 2 } }, // pslld
    { ISD::SRL,  MVT::v4i32,  { 1, 2, 1, 2 } }, // psrld
    { ISD::SRA,  MVT::v4i32,  { 1, 2, 1, 2 } }, // psrad
    { ISD::SHL,  MVT::v8i32,  { 2, 4, 2, 3 } }, // pslld
    { ISD::SRL,  MVT::v8i32,  { 2, 4, 2, 3 } }, // psrld
    { ISD::SRA,  MVT::v8i32,  { 2, 4, 2, 3 } }, // psrad
 
    { ISD::SHL,  MVT::v2i64,  { 1, 2, 1, 2 } }, // psllq
    { ISD::SRL,  MVT::v2i64,  { 1, 2, 1, 2 } }, // psrlq
    { ISD::SRA,  MVT::v2i64,  { 2, 4, 5, 7 } }, // 2 x psrad + shuffle.
    { ISD::SHL,  MVT::v4i64,  { 2, 4, 1, 2 } }, // psllq
    { ISD::SRL,  MVT::v4i64,  { 2, 4, 1, 2 } }, // psrlq
    { ISD::SRA,  MVT::v4i64,  { 4, 6, 5, 9 } }, // 2 x psrad + shuffle.
  };
 
  if (ST->hasAVX2() && Op2Info.isUniform())
    if (const auto *Entry =
            CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVXUniformCostTable[] = {
    { ISD::SHL,  MVT::v16i8,  {  4, 4, 6, 8 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8,  {  4, 8, 5, 8 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8,  {  6, 6, 9,13 } }, // psrlw, pand, pxor, psubb.
    { ISD::SHL,  MVT::v32i8,  {  7, 8,11,14 } }, // psllw + pand + split.
    { ISD::SRL,  MVT::v32i8,  {  7, 9,10,14 } }, // psrlw + pand + split.
    { ISD::SRA,  MVT::v32i8,  { 10,11,16,21 } }, // psrlw, pand, pxor, psubb + split.
 
    { ISD::SHL,  MVT::v8i16,  {  1, 3, 1, 2 } }, // psllw.
    { ISD::SRL,  MVT::v8i16,  {  1, 3, 1, 2 } }, // psrlw.
    { ISD::SRA,  MVT::v8i16,  {  1, 3, 1, 2 } }, // psraw.
    { ISD::SHL,  MVT::v16i16, {  3, 7, 5, 7 } }, // psllw + split.
    { ISD::SRL,  MVT::v16i16, {  3, 7, 5, 7 } }, // psrlw + split.
    { ISD::SRA,  MVT::v16i16, {  3, 7, 5, 7 } }, // psraw + split.
 
    { ISD::SHL,  MVT::v4i32,  {  1, 3, 1, 2 } }, // pslld.
    { ISD::SRL,  MVT::v4i32,  {  1, 3, 1, 2 } }, // psrld.
    { ISD::SRA,  MVT::v4i32,  {  1, 3, 1, 2 } }, // psrad.
    { ISD::SHL,  MVT::v8i32,  {  3, 7, 5, 7 } }, // pslld + split.
    { ISD::SRL,  MVT::v8i32,  {  3, 7, 5, 7 } }, // psrld + split.
    { ISD::SRA,  MVT::v8i32,  {  3, 7, 5, 7 } }, // psrad + split.
 
    { ISD::SHL,  MVT::v2i64,  {  1, 3, 1, 2 } }, // psllq.
    { ISD::SRL,  MVT::v2i64,  {  1, 3, 1, 2 } }, // psrlq.
    { ISD::SRA,  MVT::v2i64,  {  3, 4, 5, 7 } }, // 2 x psrad + shuffle.
    { ISD::SHL,  MVT::v4i64,  {  3, 7, 4, 6 } }, // psllq + split.
    { ISD::SRL,  MVT::v4i64,  {  3, 7, 4, 6 } }, // psrlq + split.
    { ISD::SRA,  MVT::v4i64,  {  6, 7,10,13 } }, // 2 x (2 x psrad + shuffle) + split.
  };
 
  // XOP has faster vXi8 shifts.
  if (ST->hasAVX() && Op2Info.isUniform() &&
      (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
    if (const auto *Entry =
            CostTableLookup(AVXUniformCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE2UniformCostTable[] = {
    // Uniform splats are cheaper for the following instructions.
    { ISD::SHL,  MVT::v16i8, {  9, 10, 6, 9 } }, // psllw + pand.
    { ISD::SRL,  MVT::v16i8, {  9, 13, 5, 9 } }, // psrlw + pand.
    { ISD::SRA,  MVT::v16i8, { 11, 15, 9,13 } }, // pcmpgtb sequence.
 
    { ISD::SHL,  MVT::v8i16, {  2, 2, 1, 2 } }, // psllw.
    { ISD::SRL,  MVT::v8i16, {  2, 2, 1, 2 } }, // psrlw.
    { ISD::SRA,  MVT::v8i16, {  2, 2, 1, 2 } }, // psraw.
 
    { ISD::SHL,  MVT::v4i32, {  2, 2, 1, 2 } }, // pslld
    { ISD::SRL,  MVT::v4i32, {  2, 2, 1, 2 } }, // psrld.
    { ISD::SRA,  MVT::v4i32, {  2, 2, 1, 2 } }, // psrad.
 
    { ISD::SHL,  MVT::v2i64, {  2, 2, 1, 2 } }, // psllq.
    { ISD::SRL,  MVT::v2i64, {  2, 2, 1, 2 } }, // psrlq.
    { ISD::SRA,  MVT::v2i64, {  5, 9, 5, 7 } }, // 2*psrlq + xor + sub.
  };
 
  if (ST->hasSSE2() && Op2Info.isUniform() &&
      (!ST->hasXOP() || LT.second.getScalarSizeInBits() != 8))
    if (const auto *Entry =
            CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512DQCostTable[] = {
    { ISD::MUL,  MVT::v2i64, { 2, 15, 1, 3 } }, // pmullq
    { ISD::MUL,  MVT::v4i64, { 2, 15, 1, 3 } }, // pmullq
    { ISD::MUL,  MVT::v8i64, { 3, 15, 1, 3 } }  // pmullq
  };
 
  // Look for AVX512DQ lowering tricks for custom cases.
  if (ST->hasDQI())
    if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512BWCostTable[] = {
    { ISD::SHL,   MVT::v16i8,   {  4,  8, 4, 5 } }, // extend/vpsllvw/pack sequence.
    { ISD::SRL,   MVT::v16i8,   {  4,  8, 4, 5 } }, // extend/vpsrlvw/pack sequence.
    { ISD::SRA,   MVT::v16i8,   {  4,  8, 4, 5 } }, // extend/vpsravw/pack sequence.
    { ISD::SHL,   MVT::v32i8,   {  4, 23,11,16 } }, // extend/vpsllvw/pack sequence.
    { ISD::SRL,   MVT::v32i8,   {  4, 30,12,18 } }, // extend/vpsrlvw/pack sequence.
    { ISD::SRA,   MVT::v32i8,   {  6, 13,24,30 } }, // extend/vpsravw/pack sequence.
    { ISD::SHL,   MVT::v64i8,   {  6, 19,13,15 } }, // extend/vpsllvw/pack sequence.
    { ISD::SRL,   MVT::v64i8,   {  7, 27,15,18 } }, // extend/vpsrlvw/pack sequence.
    { ISD::SRA,   MVT::v64i8,   { 15, 15,30,30 } }, // extend/vpsravw/pack sequence.
 
    { ISD::SHL,   MVT::v8i16,   {  1,  1, 1, 1 } }, // vpsllvw
    { ISD::SRL,   MVT::v8i16,   {  1,  1, 1, 1 } }, // vpsrlvw
    { ISD::SRA,   MVT::v8i16,   {  1,  1, 1, 1 } }, // vpsravw
    { ISD::SHL,   MVT::v16i16,  {  1,  1, 1, 1 } }, // vpsllvw
    { ISD::SRL,   MVT::v16i16,  {  1,  1, 1, 1 } }, // vpsrlvw
    { ISD::SRA,   MVT::v16i16,  {  1,  1, 1, 1 } }, // vpsravw
    { ISD::SHL,   MVT::v32i16,  {  1,  1, 1, 1 } }, // vpsllvw
    { ISD::SRL,   MVT::v32i16,  {  1,  1, 1, 1 } }, // vpsrlvw
    { ISD::SRA,   MVT::v32i16,  {  1,  1, 1, 1 } }, // vpsravw
 
    { ISD::ADD,   MVT::v64i8,   {  1,  1, 1, 1 } }, // paddb
    { ISD::ADD,   MVT::v32i16,  {  1,  1, 1, 1 } }, // paddw
 
    { ISD::ADD,   MVT::v32i8,   {  1,  1, 1, 1 } }, // paddb
    { ISD::ADD,   MVT::v16i16,  {  1,  1, 1, 1 } }, // paddw
    { ISD::ADD,   MVT::v8i32,   {  1,  1, 1, 1 } }, // paddd
    { ISD::ADD,   MVT::v4i64,   {  1,  1, 1, 1 } }, // paddq
 
    { ISD::SUB,   MVT::v64i8,   {  1,  1, 1, 1 } }, // psubb
    { ISD::SUB,   MVT::v32i16,  {  1,  1, 1, 1 } }, // psubw
 
    { ISD::MUL,   MVT::v64i8,   {  5, 10,10,11 } },
    { ISD::MUL,   MVT::v32i16,  {  1,  5, 1, 1 } }, // pmullw
 
    { ISD::SUB,   MVT::v32i8,   {  1,  1, 1, 1 } }, // psubb
    { ISD::SUB,   MVT::v16i16,  {  1,  1, 1, 1 } }, // psubw
    { ISD::SUB,   MVT::v8i32,   {  1,  1, 1, 1 } }, // psubd
    { ISD::SUB,   MVT::v4i64,   {  1,  1, 1, 1 } }, // psubq
  };
 
  // Look for AVX512BW lowering tricks for custom cases.
  if (ST->hasBWI())
    if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX512CostTable[] = {
    { ISD::SHL,     MVT::v64i8,   { 15, 19,27,33 } }, // vpblendv+split sequence.
    { ISD::SRL,     MVT::v64i8,   { 15, 19,30,36 } }, // vpblendv+split sequence.
    { ISD::SRA,     MVT::v64i8,   { 37, 37,51,63 } }, // vpblendv+split sequence.
 
    { ISD::SHL,     MVT::v32i16,  { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
    { ISD::SRL,     MVT::v32i16,  { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
    { ISD::SRA,     MVT::v32i16,  { 11, 16,11,15 } }, // 2*extend/vpsravd/pack sequence.
 
    { ISD::SHL,     MVT::v4i32,   {  1,  1, 1, 1 } },
    { ISD::SRL,     MVT::v4i32,   {  1,  1, 1, 1 } },
    { ISD::SRA,     MVT::v4i32,   {  1,  1, 1, 1 } },
    { ISD::SHL,     MVT::v8i32,   {  1,  1, 1, 1 } },
    { ISD::SRL,     MVT::v8i32,   {  1,  1, 1, 1 } },
    { ISD::SRA,     MVT::v8i32,   {  1,  1, 1, 1 } },
    { ISD::SHL,     MVT::v16i32,  {  1,  1, 1, 1 } },
    { ISD::SRL,     MVT::v16i32,  {  1,  1, 1, 1 } },
    { ISD::SRA,     MVT::v16i32,  {  1,  1, 1, 1 } },
 
    { ISD::SHL,     MVT::v2i64,   {  1,  1, 1, 1 } },
    { ISD::SRL,     MVT::v2i64,   {  1,  1, 1, 1 } },
    { ISD::SRA,     MVT::v2i64,   {  1,  1, 1, 1 } },
    { ISD::SHL,     MVT::v4i64,   {  1,  1, 1, 1 } },
    { ISD::SRL,     MVT::v4i64,   {  1,  1, 1, 1 } },
    { ISD::SRA,     MVT::v4i64,   {  1,  1, 1, 1 } },
    { ISD::SHL,     MVT::v8i64,   {  1,  1, 1, 1 } },
    { ISD::SRL,     MVT::v8i64,   {  1,  1, 1, 1 } },
    { ISD::SRA,     MVT::v8i64,   {  1,  1, 1, 1 } },
 
    { ISD::ADD,     MVT::v64i8,   {  3,  7, 5, 5 } }, // 2*paddb + split
    { ISD::ADD,     MVT::v32i16,  {  3,  7, 5, 5 } }, // 2*paddw + split
 
    { ISD::SUB,     MVT::v64i8,   {  3,  7, 5, 5 } }, // 2*psubb + split
    { ISD::SUB,     MVT::v32i16,  {  3,  7, 5, 5 } }, // 2*psubw + split
 
    { ISD::AND,     MVT::v32i8,   {  1,  1, 1, 1 } },
    { ISD::AND,     MVT::v16i16,  {  1,  1, 1, 1 } },
    { ISD::AND,     MVT::v8i32,   {  1,  1, 1, 1 } },
    { ISD::AND,     MVT::v4i64,   {  1,  1, 1, 1 } },
 
    { ISD::OR,      MVT::v32i8,   {  1,  1, 1, 1 } },
    { ISD::OR,      MVT::v16i16,  {  1,  1, 1, 1 } },
    { ISD::OR,      MVT::v8i32,   {  1,  1, 1, 1 } },
    { ISD::OR,      MVT::v4i64,   {  1,  1, 1, 1 } },
 
    { ISD::XOR,     MVT::v32i8,   {  1,  1, 1, 1 } },
    { ISD::XOR,     MVT::v16i16,  {  1,  1, 1, 1 } },
    { ISD::XOR,     MVT::v8i32,   {  1,  1, 1, 1 } },
    { ISD::XOR,     MVT::v4i64,   {  1,  1, 1, 1 } },
 
    { ISD::MUL,     MVT::v16i32,  {  1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
    { ISD::MUL,     MVT::v8i32,   {  1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
    { ISD::MUL,     MVT::v4i32,   {  1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
    { ISD::MUL,     MVT::v8i64,   {  6,  9, 8, 8 } }, // 3*pmuludq/3*shift/2*add
    { ISD::MUL,     MVT::i64,     {  1 } }, // Skylake from http://www.agner.org/
 
    { ISD::FNEG,    MVT::v8f64,   {  1,  1, 1, 2 } }, // Skylake from http://www.agner.org/
    { ISD::FADD,    MVT::v8f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FADD,    MVT::v4f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FSUB,    MVT::v8f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FSUB,    MVT::v4f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::v8f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::v4f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::v2f64,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::f64,     {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
 
    { ISD::FDIV,    MVT::f64,     {  4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FDIV,    MVT::v2f64,   {  4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FDIV,    MVT::v4f64,   {  8, 14, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FDIV,    MVT::v8f64,   { 16, 23, 1, 3 } }, // Skylake from http://www.agner.org/
 
    { ISD::FNEG,    MVT::v16f32,  {  1,  1, 1, 2 } }, // Skylake from http://www.agner.org/
    { ISD::FADD,    MVT::v16f32,  {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FADD,    MVT::v8f32,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FSUB,    MVT::v16f32,  {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FSUB,    MVT::v8f32,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::v16f32,  {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::v8f32,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::v4f32,   {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FMUL,    MVT::f32,     {  1,  4, 1, 1 } }, // Skylake from http://www.agner.org/
 
    { ISD::FDIV,    MVT::f32,     {  3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FDIV,    MVT::v4f32,   {  3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FDIV,    MVT::v8f32,   {  5, 11, 1, 1 } }, // Skylake from http://www.agner.org/
    { ISD::FDIV,    MVT::v16f32,  { 10, 18, 1, 3 } }, // Skylake from http://www.agner.org/
  };
 
  if (ST->hasAVX512())
    if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX2ShiftCostTable[] = {
    // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to
    // customize them to detect the cases where shift amount is a scalar one.
    { ISD::SHL,     MVT::v4i32,  { 2, 3, 1, 3 } }, // vpsllvd (Haswell from agner.org)
    { ISD::SRL,     MVT::v4i32,  { 2, 3, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
    { ISD::SRA,     MVT::v4i32,  { 2, 3, 1, 3 } }, // vpsravd (Haswell from agner.org)
    { ISD::SHL,     MVT::v8i32,  { 4, 4, 1, 3 } }, // vpsllvd (Haswell from agner.org)
    { ISD::SRL,     MVT::v8i32,  { 4, 4, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
    { ISD::SRA,     MVT::v8i32,  { 4, 4, 1, 3 } }, // vpsravd (Haswell from agner.org)
    { ISD::SHL,     MVT::v2i64,  { 2, 3, 1, 1 } }, // vpsllvq (Haswell from agner.org)
    { ISD::SRL,     MVT::v2i64,  { 2, 3, 1, 1 } }, // vpsrlvq (Haswell from agner.org)
    { ISD::SHL,     MVT::v4i64,  { 4, 4, 1, 2 } }, // vpsllvq (Haswell from agner.org)
    { ISD::SRL,     MVT::v4i64,  { 4, 4, 1, 2 } }, // vpsrlvq (Haswell from agner.org)
  };
 
  if (ST->hasAVX512()) {
    if (ISD == ISD::SHL && LT.second == MVT::v32i16 && Op2Info.isConstant())
      // On AVX512, a packed v32i16 shift left by a constant build_vector
      // is lowered into a vector multiply (vpmullw).
      return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
                                    Op1Info.getNoProps(), Op2Info.getNoProps());
  }
 
  // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts).
  if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) {
    if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
        Op2Info.isConstant())
      // On AVX2, a packed v16i16 shift left by a constant build_vector
      // is lowered into a vector multiply (vpmullw).
      return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
                                    Op1Info.getNoProps(), Op2Info.getNoProps());
 
    if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
  }
 
  static const CostKindTblEntry XOPShiftCostTable[] = {
    // 128bit shifts take 1cy, but right shifts require negation beforehand.
    { ISD::SHL,     MVT::v16i8,  { 1, 3, 1, 1 } },
    { ISD::SRL,     MVT::v16i8,  { 2, 3, 1, 1 } },
    { ISD::SRA,     MVT::v16i8,  { 2, 3, 1, 1 } },
    { ISD::SHL,     MVT::v8i16,  { 1, 3, 1, 1 } },
    { ISD::SRL,     MVT::v8i16,  { 2, 3, 1, 1 } },
    { ISD::SRA,     MVT::v8i16,  { 2, 3, 1, 1 } },
    { ISD::SHL,     MVT::v4i32,  { 1, 3, 1, 1 } },
    { ISD::SRL,     MVT::v4i32,  { 2, 3, 1, 1 } },
    { ISD::SRA,     MVT::v4i32,  { 2, 3, 1, 1 } },
    { ISD::SHL,     MVT::v2i64,  { 1, 3, 1, 1 } },
    { ISD::SRL,     MVT::v2i64,  { 2, 3, 1, 1 } },
    { ISD::SRA,     MVT::v2i64,  { 2, 3, 1, 1 } },
    // 256bit shifts require splitting if AVX2 didn't catch them above.
    { ISD::SHL,     MVT::v32i8,  { 4, 7, 5, 6 } },
    { ISD::SRL,     MVT::v32i8,  { 6, 7, 5, 6 } },
    { ISD::SRA,     MVT::v32i8,  { 6, 7, 5, 6 } },
    { ISD::SHL,     MVT::v16i16, { 4, 7, 5, 6 } },
    { ISD::SRL,     MVT::v16i16, { 6, 7, 5, 6 } },
    { ISD::SRA,     MVT::v16i16, { 6, 7, 5, 6 } },
    { ISD::SHL,     MVT::v8i32,  { 4, 7, 5, 6 } },
    { ISD::SRL,     MVT::v8i32,  { 6, 7, 5, 6 } },
    { ISD::SRA,     MVT::v8i32,  { 6, 7, 5, 6 } },
    { ISD::SHL,     MVT::v4i64,  { 4, 7, 5, 6 } },
    { ISD::SRL,     MVT::v4i64,  { 6, 7, 5, 6 } },
    { ISD::SRA,     MVT::v4i64,  { 6, 7, 5, 6 } },
  };
 
  // Look for XOP lowering tricks.
  if (ST->hasXOP()) {
    // If the right shift is constant then we'll fold the negation so
    // it's as cheap as a left shift.
    int ShiftISD = ISD;
    if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant())
      ShiftISD = ISD::SHL;
    if (const auto *Entry =
            CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
  }
 
  if (ISD == ISD::SHL && !Op2Info.isUniform() && Op2Info.isConstant()) {
    MVT VT = LT.second;
    // Vector shift left by non uniform constant can be lowered
    // into vector multiply.
    if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
        ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
      ISD = ISD::MUL;
  }
 
  static const CostKindTblEntry GLMCostTable[] = {
    { ISD::FDIV,  MVT::f32,   { 18, 19, 1, 1 } }, // divss
    { ISD::FDIV,  MVT::v4f32, { 35, 36, 1, 1 } }, // divps
    { ISD::FDIV,  MVT::f64,   { 33, 34, 1, 1 } }, // divsd
    { ISD::FDIV,  MVT::v2f64, { 65, 66, 1, 1 } }, // divpd
  };
 
  if (ST->useGLMDivSqrtCosts())
    if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SLMCostTable[] = {
    { ISD::MUL,   MVT::v4i32, { 11, 11, 1, 7 } }, // pmulld
    { ISD::MUL,   MVT::v8i16, {  2,  5, 1, 1 } }, // pmullw
    { ISD::FMUL,  MVT::f64,   {  2,  5, 1, 1 } }, // mulsd
    { ISD::FMUL,  MVT::f32,   {  1,  4, 1, 1 } }, // mulss
    { ISD::FMUL,  MVT::v2f64, {  4,  7, 1, 1 } }, // mulpd
    { ISD::FMUL,  MVT::v4f32, {  2,  5, 1, 1 } }, // mulps
    { ISD::FDIV,  MVT::f32,   { 17, 19, 1, 1 } }, // divss
    { ISD::FDIV,  MVT::v4f32, { 39, 39, 1, 6 } }, // divps
    { ISD::FDIV,  MVT::f64,   { 32, 34, 1, 1 } }, // divsd
    { ISD::FDIV,  MVT::v2f64, { 69, 69, 1, 6 } }, // divpd
    { ISD::FADD,  MVT::v2f64, {  2,  4, 1, 1 } }, // addpd
    { ISD::FSUB,  MVT::v2f64, {  2,  4, 1, 1 } }, // subpd
    // v2i64/v4i64 mul is custom lowered as a series of long:
    // multiplies(3), shifts(3) and adds(2)
    // slm muldq version throughput is 2 and addq throughput 4
    // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
    //       3X4 (addq throughput) = 17
    { ISD::MUL,   MVT::v2i64, { 17, 22, 9, 9 } },
    // slm addq\subq throughput is 4
    { ISD::ADD,   MVT::v2i64, {  4,  2, 1, 2 } },
    { ISD::SUB,   MVT::v2i64, {  4,  2, 1, 2 } },
  };
 
  if (ST->useSLMArithCosts())
    if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX2CostTable[] = {
    { ISD::SHL,  MVT::v16i8,   {  6, 21,11,16 } }, // vpblendvb sequence.
    { ISD::SHL,  MVT::v32i8,   {  6, 23,11,22 } }, // vpblendvb sequence.
    { ISD::SHL,  MVT::v8i16,   {  5, 18, 5,10 } }, // extend/vpsrlvd/pack sequence.
    { ISD::SHL,  MVT::v16i16,  {  8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
 
    { ISD::SRL,  MVT::v16i8,   {  6, 27,12,18 } }, // vpblendvb sequence.
    { ISD::SRL,  MVT::v32i8,   {  8, 30,12,24 } }, // vpblendvb sequence.
    { ISD::SRL,  MVT::v8i16,   {  5, 11, 5,10 } }, // extend/vpsrlvd/pack sequence.
    { ISD::SRL,  MVT::v16i16,  {  8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
 
    { ISD::SRA,  MVT::v16i8,   { 17, 17,24,30 } }, // vpblendvb sequence.
    { ISD::SRA,  MVT::v32i8,   { 18, 20,24,43 } }, // vpblendvb sequence.
    { ISD::SRA,  MVT::v8i16,   {  5, 11, 5,10 } }, // extend/vpsravd/pack sequence.
    { ISD::SRA,  MVT::v16i16,  {  8, 10,10,14 } }, // extend/vpsravd/pack sequence.
    { ISD::SRA,  MVT::v2i64,   {  4,  5, 5, 5 } }, // srl/xor/sub sequence.
    { ISD::SRA,  MVT::v4i64,   {  8,  8, 5, 9 } }, // srl/xor/sub sequence.
 
    { ISD::SUB,  MVT::v32i8,   {  1,  1, 1, 2 } }, // psubb
    { ISD::ADD,  MVT::v32i8,   {  1,  1, 1, 2 } }, // paddb
    { ISD::SUB,  MVT::v16i16,  {  1,  1, 1, 2 } }, // psubw
    { ISD::ADD,  MVT::v16i16,  {  1,  1, 1, 2 } }, // paddw
    { ISD::SUB,  MVT::v8i32,   {  1,  1, 1, 2 } }, // psubd
    { ISD::ADD,  MVT::v8i32,   {  1,  1, 1, 2 } }, // paddd
    { ISD::SUB,  MVT::v4i64,   {  1,  1, 1, 2 } }, // psubq
    { ISD::ADD,  MVT::v4i64,   {  1,  1, 1, 2 } }, // paddq
 
    { ISD::MUL,  MVT::v16i8,   {  5, 18, 6,12 } }, // extend/pmullw/pack
    { ISD::MUL,  MVT::v32i8,   {  6, 11,10,19 } }, // unpack/pmullw
    { ISD::MUL,  MVT::v16i16,  {  2,  5, 1, 2 } }, // pmullw
    { ISD::MUL,  MVT::v8i32,   {  4, 10, 1, 2 } }, // pmulld
    { ISD::MUL,  MVT::v4i32,   {  2, 10, 1, 2 } }, // pmulld
    { ISD::MUL,  MVT::v4i64,   {  6, 10, 8,13 } }, // 3*pmuludq/3*shift/2*add
    { ISD::MUL,  MVT::v2i64,   {  6, 10, 8, 8 } }, // 3*pmuludq/3*shift/2*add
 
    { ISD::FNEG, MVT::v4f64,   {  1,  1, 1, 2 } }, // vxorpd
    { ISD::FNEG, MVT::v8f32,   {  1,  1, 1, 2 } }, // vxorps
 
    { ISD::FADD, MVT::f64,     {  1,  4, 1, 1 } }, // vaddsd
    { ISD::FADD, MVT::f32,     {  1,  4, 1, 1 } }, // vaddss
    { ISD::FADD, MVT::v2f64,   {  1,  4, 1, 1 } }, // vaddpd
    { ISD::FADD, MVT::v4f32,   {  1,  4, 1, 1 } }, // vaddps
    { ISD::FADD, MVT::v4f64,   {  1,  4, 1, 2 } }, // vaddpd
    { ISD::FADD, MVT::v8f32,   {  1,  4, 1, 2 } }, // vaddps
 
    { ISD::FSUB, MVT::f64,     {  1,  4, 1, 1 } }, // vsubsd
    { ISD::FSUB, MVT::f32,     {  1,  4, 1, 1 } }, // vsubss
    { ISD::FSUB, MVT::v2f64,   {  1,  4, 1, 1 } }, // vsubpd
    { ISD::FSUB, MVT::v4f32,   {  1,  4, 1, 1 } }, // vsubps
    { ISD::FSUB, MVT::v4f64,   {  1,  4, 1, 2 } }, // vsubpd
    { ISD::FSUB, MVT::v8f32,   {  1,  4, 1, 2 } }, // vsubps
 
    { ISD::FMUL, MVT::f64,     {  1,  5, 1, 1 } }, // vmulsd
    { ISD::FMUL, MVT::f32,     {  1,  5, 1, 1 } }, // vmulss
    { ISD::FMUL, MVT::v2f64,   {  1,  5, 1, 1 } }, // vmulpd
    { ISD::FMUL, MVT::v4f32,   {  1,  5, 1, 1 } }, // vmulps
    { ISD::FMUL, MVT::v4f64,   {  1,  5, 1, 2 } }, // vmulpd
    { ISD::FMUL, MVT::v8f32,   {  1,  5, 1, 2 } }, // vmulps
 
    { ISD::FDIV, MVT::f32,     {  7, 13, 1, 1 } }, // vdivss
    { ISD::FDIV, MVT::v4f32,   {  7, 13, 1, 1 } }, // vdivps
    { ISD::FDIV, MVT::v8f32,   { 14, 21, 1, 3 } }, // vdivps
    { ISD::FDIV, MVT::f64,     { 14, 20, 1, 1 } }, // vdivsd
    { ISD::FDIV, MVT::v2f64,   { 14, 20, 1, 1 } }, // vdivpd
    { ISD::FDIV, MVT::v4f64,   { 28, 35, 1, 3 } }, // vdivpd
  };
 
  // Look for AVX2 lowering tricks for custom cases.
  if (ST->hasAVX2())
    if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry AVX1CostTable[] = {
    // We don't have to scalarize unsupported ops. We can issue two half-sized
    // operations and we only need to extract the upper YMM half.
    // Two ops + 1 extract + 1 insert = 4.
    { ISD::MUL,     MVT::v32i8,   { 12, 13, 22, 23 } }, // unpack/pmullw + split
    { ISD::MUL,     MVT::v16i16,  {  4,  8,  5,  6 } }, // pmullw + split
    { ISD::MUL,     MVT::v8i32,   {  5,  8,  5, 10 } }, // pmulld + split
    { ISD::MUL,     MVT::v4i32,   {  2,  5,  1,  3 } }, // pmulld
    { ISD::MUL,     MVT::v4i64,   { 12, 15, 19, 20 } },
 
    { ISD::AND,     MVT::v32i8,   {  1,  1, 1, 2 } }, // vandps
    { ISD::AND,     MVT::v16i16,  {  1,  1, 1, 2 } }, // vandps
    { ISD::AND,     MVT::v8i32,   {  1,  1, 1, 2 } }, // vandps
    { ISD::AND,     MVT::v4i64,   {  1,  1, 1, 2 } }, // vandps
 
    { ISD::OR,      MVT::v32i8,   {  1,  1, 1, 2 } }, // vorps
    { ISD::OR,      MVT::v16i16,  {  1,  1, 1, 2 } }, // vorps
    { ISD::OR,      MVT::v8i32,   {  1,  1, 1, 2 } }, // vorps
    { ISD::OR,      MVT::v4i64,   {  1,  1, 1, 2 } }, // vorps
 
    { ISD::XOR,     MVT::v32i8,   {  1,  1, 1, 2 } }, // vxorps
    { ISD::XOR,     MVT::v16i16,  {  1,  1, 1, 2 } }, // vxorps
    { ISD::XOR,     MVT::v8i32,   {  1,  1, 1, 2 } }, // vxorps
    { ISD::XOR,     MVT::v4i64,   {  1,  1, 1, 2 } }, // vxorps
 
    { ISD::SUB,     MVT::v32i8,   {  4,  2, 5, 6 } }, // psubb + split
    { ISD::ADD,     MVT::v32i8,   {  4,  2, 5, 6 } }, // paddb + split
    { ISD::SUB,     MVT::v16i16,  {  4,  2, 5, 6 } }, // psubw + split
    { ISD::ADD,     MVT::v16i16,  {  4,  2, 5, 6 } }, // paddw + split
    { ISD::SUB,     MVT::v8i32,   {  4,  2, 5, 6 } }, // psubd + split
    { ISD::ADD,     MVT::v8i32,   {  4,  2, 5, 6 } }, // paddd + split
    { ISD::SUB,     MVT::v4i64,   {  4,  2, 5, 6 } }, // psubq + split
    { ISD::ADD,     MVT::v4i64,   {  4,  2, 5, 6 } }, // paddq + split
    { ISD::SUB,     MVT::v2i64,   {  1,  1, 1, 1 } }, // psubq
    { ISD::ADD,     MVT::v2i64,   {  1,  1, 1, 1 } }, // paddq
 
    { ISD::SHL,     MVT::v16i8,   { 10, 21,11,17 } }, // pblendvb sequence.
    { ISD::SHL,     MVT::v32i8,   { 22, 22,27,40 } }, // pblendvb sequence + split.
    { ISD::SHL,     MVT::v8i16,   {  6,  9,11,11 } }, // pblendvb sequence.
    { ISD::SHL,     MVT::v16i16,  { 13, 16,24,25 } }, // pblendvb sequence + split.
    { ISD::SHL,     MVT::v4i32,   {  3, 11, 4, 6 } }, // pslld/paddd/cvttps2dq/pmulld
    { ISD::SHL,     MVT::v8i32,   {  9, 11,12,17 } }, // pslld/paddd/cvttps2dq/pmulld + split
    { ISD::SHL,     MVT::v2i64,   {  2,  4, 4, 6 } }, // Shift each lane + blend.
    { ISD::SHL,     MVT::v4i64,   {  6,  7,11,15 } }, // Shift each lane + blend + split.
 
    { ISD::SRL,     MVT::v16i8,   { 11, 27,12,18 } }, // pblendvb sequence.
    { ISD::SRL,     MVT::v32i8,   { 23, 23,30,43 } }, // pblendvb sequence + split.
    { ISD::SRL,     MVT::v8i16,   { 13, 16,14,22 } }, // pblendvb sequence.
    { ISD::SRL,     MVT::v16i16,  { 28, 30,31,48 } }, // pblendvb sequence + split.
    { ISD::SRL,     MVT::v4i32,   {  6,  7,12,16 } }, // Shift each lane + blend.
    { ISD::SRL,     MVT::v8i32,   { 14, 14,26,34 } }, // Shift each lane + blend + split.
    { ISD::SRL,     MVT::v2i64,   {  2,  4, 4, 6 } }, // Shift each lane + blend.
    { ISD::SRL,     MVT::v4i64,   {  6,  7,11,15 } }, // Shift each lane + blend + split.
 
    { ISD::SRA,     MVT::v16i8,   { 21, 22,24,36 } }, // pblendvb sequence.
    { ISD::SRA,     MVT::v32i8,   { 44, 45,51,76 } }, // pblendvb sequence + split.
    { ISD::SRA,     MVT::v8i16,   { 13, 16,14,22 } }, // pblendvb sequence.
    { ISD::SRA,     MVT::v16i16,  { 28, 30,31,48 } }, // pblendvb sequence + split.
    { ISD::SRA,     MVT::v4i32,   {  6,  7,12,16 } }, // Shift each lane + blend.
    { ISD::SRA,     MVT::v8i32,   { 14, 14,26,34 } }, // Shift each lane + blend + split.
    { ISD::SRA,     MVT::v2i64,   {  5,  6,10,14 } }, // Shift each lane + blend.
    { ISD::SRA,     MVT::v4i64,   { 12, 12,22,30 } }, // Shift each lane + blend + split.
 
    { ISD::FNEG,    MVT::v4f64,   {  2,  2, 1, 2 } }, // BTVER2 from http://www.agner.org/
    { ISD::FNEG,    MVT::v8f32,   {  2,  2, 1, 2 } }, // BTVER2 from http://www.agner.org/
 
    { ISD::FADD,    MVT::f64,     {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FADD,    MVT::f32,     {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FADD,    MVT::v2f64,   {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FADD,    MVT::v4f32,   {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FADD,    MVT::v4f64,   {  2,  5, 1, 2 } }, // BDVER2 from http://www.agner.org/
    { ISD::FADD,    MVT::v8f32,   {  2,  5, 1, 2 } }, // BDVER2 from http://www.agner.org/
 
    { ISD::FSUB,    MVT::f64,     {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FSUB,    MVT::f32,     {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FSUB,    MVT::v2f64,   {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FSUB,    MVT::v4f32,   {  1,  5, 1, 1 } }, // BDVER2 from http://www.agner.org/
    { ISD::FSUB,    MVT::v4f64,   {  2,  5, 1, 2 } }, // BDVER2 from http://www.agner.org/
    { ISD::FSUB,    MVT::v8f32,   {  2,  5, 1, 2 } }, // BDVER2 from http://www.agner.org/
 
    { ISD::FMUL,    MVT::f64,     {  2,  5, 1, 1 } }, // BTVER2 from http://www.agner.org/
    { ISD::FMUL,    MVT::f32,     {  1,  5, 1, 1 } }, // BTVER2 from http://www.agner.org/
    { ISD::FMUL,    MVT::v2f64,   {  2,  5, 1, 1 } }, // BTVER2 from http://www.agner.org/
    { ISD::FMUL,    MVT::v4f32,   {  1,  5, 1, 1 } }, // BTVER2 from http://www.agner.org/
    { ISD::FMUL,    MVT::v4f64,   {  4,  5, 1, 2 } }, // BTVER2 from http://www.agner.org/
    { ISD::FMUL,    MVT::v8f32,   {  2,  5, 1, 2 } }, // BTVER2 from http://www.agner.org/
 
    { ISD::FDIV,    MVT::f32,     { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
    { ISD::FDIV,    MVT::v4f32,   { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
    { ISD::FDIV,    MVT::v8f32,   { 28, 29, 1, 3 } }, // SNB from http://www.agner.org/
    { ISD::FDIV,    MVT::f64,     { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
    { ISD::FDIV,    MVT::v2f64,   { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
    { ISD::FDIV,    MVT::v4f64,   { 44, 45, 1, 3 } }, // SNB from http://www.agner.org/
  };
 
  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE42CostTable[] = {
    { ISD::FADD, MVT::f64,    {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FADD, MVT::f32,    {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FADD, MVT::v2f64,  {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FADD, MVT::v4f32,  {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
 
    { ISD::FSUB, MVT::f64,    {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FSUB, MVT::f32 ,   {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FSUB, MVT::v2f64,  {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FSUB, MVT::v4f32,  {  1,  3, 1, 1 } }, // Nehalem from http://www.agner.org/
 
    { ISD::FMUL, MVT::f64,    {  1,  5, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FMUL, MVT::f32,    {  1,  5, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FMUL, MVT::v2f64,  {  1,  5, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FMUL, MVT::v4f32,  {  1,  5, 1, 1 } }, // Nehalem from http://www.agner.org/
 
    { ISD::FDIV,  MVT::f32,   { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FDIV,  MVT::v4f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FDIV,  MVT::f64,   { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
    { ISD::FDIV,  MVT::v2f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
 
    { ISD::MUL,   MVT::v2i64, {  6, 10,10,10 } }  // 3*pmuludq/3*shift/2*add
  };
 
  if (ST->hasSSE42())
    if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE41CostTable[] = {
    { ISD::SHL,  MVT::v16i8,  { 15, 24,17,22 } }, // pblendvb sequence.
    { ISD::SHL,  MVT::v8i16,  { 11, 14,11,11 } }, // pblendvb sequence.
    { ISD::SHL,  MVT::v4i32,  { 14, 20, 4,10 } }, // pslld/paddd/cvttps2dq/pmulld
 
    { ISD::SRL,  MVT::v16i8,  { 16, 27,18,24 } }, // pblendvb sequence.
    { ISD::SRL,  MVT::v8i16,  { 22, 26,23,27 } }, // pblendvb sequence.
    { ISD::SRL,  MVT::v4i32,  { 16, 17,15,19 } }, // Shift each lane + blend.
    { ISD::SRL,  MVT::v2i64,  {  4,  6, 5, 7 } }, // splat+shuffle sequence.
 
    { ISD::SRA,  MVT::v16i8,  { 38, 41,30,36 } }, // pblendvb sequence.
    { ISD::SRA,  MVT::v8i16,  { 22, 26,23,27 } }, // pblendvb sequence.
    { ISD::SRA,  MVT::v4i32,  { 16, 17,15,19 } }, // Shift each lane + blend.
    { ISD::SRA,  MVT::v2i64,  {  8, 17, 5, 7 } }, // splat+shuffle sequence.
 
    { ISD::MUL,  MVT::v16i8,  {  5, 18,10,12 } }, // 2*unpack/2*pmullw/2*and/pack
    { ISD::MUL,  MVT::v4i32,  {  2, 11, 1, 1 } }  // pmulld (Nehalem from agner.org)
  };
 
  if (ST->hasSSE41())
    if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE2CostTable[] = {
    // We don't correctly identify costs of casts because they are marked as
    // custom.
    { ISD::SHL,  MVT::v16i8,  { 13, 21,26,28 } }, // cmpgtb sequence.
    { ISD::SHL,  MVT::v8i16,  { 24, 27,16,20 } }, // cmpgtw sequence.
    { ISD::SHL,  MVT::v4i32,  { 17, 19,10,12 } }, // pslld/paddd/cvttps2dq/pmuludq.
    { ISD::SHL,  MVT::v2i64,  {  4,  6, 5, 7 } }, // splat+shuffle sequence.
 
    { ISD::SRL,  MVT::v16i8,  { 14, 28,27,30 } }, // cmpgtb sequence.
    { ISD::SRL,  MVT::v8i16,  { 16, 19,31,31 } }, // cmpgtw sequence.
    { ISD::SRL,  MVT::v4i32,  { 12, 12,15,19 } }, // Shift each lane + blend.
    { ISD::SRL,  MVT::v2i64,  {  4,  6, 5, 7 } }, // splat+shuffle sequence.
 
    { ISD::SRA,  MVT::v16i8,  { 27, 30,54,54 } }, // unpacked cmpgtb sequence.
    { ISD::SRA,  MVT::v8i16,  { 16, 19,31,31 } }, // cmpgtw sequence.
    { ISD::SRA,  MVT::v4i32,  { 12, 12,15,19 } }, // Shift each lane + blend.
    { ISD::SRA,  MVT::v2i64,  {  8, 11,12,16 } }, // srl/xor/sub splat+shuffle sequence.
 
    { ISD::AND,  MVT::v16i8,  {  1,  1, 1, 1 } }, // pand
    { ISD::AND,  MVT::v8i16,  {  1,  1, 1, 1 } }, // pand
    { ISD::AND,  MVT::v4i32,  {  1,  1, 1, 1 } }, // pand
    { ISD::AND,  MVT::v2i64,  {  1,  1, 1, 1 } }, // pand
 
    { ISD::OR,   MVT::v16i8,  {  1,  1, 1, 1 } }, // por
    { ISD::OR,   MVT::v8i16,  {  1,  1, 1, 1 } }, // por
    { ISD::OR,   MVT::v4i32,  {  1,  1, 1, 1 } }, // por
    { ISD::OR,   MVT::v2i64,  {  1,  1, 1, 1 } }, // por
 
    { ISD::XOR,  MVT::v16i8,  {  1,  1, 1, 1 } }, // pxor
    { ISD::XOR,  MVT::v8i16,  {  1,  1, 1, 1 } }, // pxor
    { ISD::XOR,  MVT::v4i32,  {  1,  1, 1, 1 } }, // pxor
    { ISD::XOR,  MVT::v2i64,  {  1,  1, 1, 1 } }, // pxor
 
    { ISD::ADD,  MVT::v2i64,  {  1,  2, 1, 2 } }, // paddq
    { ISD::SUB,  MVT::v2i64,  {  1,  2, 1, 2 } }, // psubq
 
    { ISD::MUL,  MVT::v16i8,  {  5, 18,12,12 } }, // 2*unpack/2*pmullw/2*and/pack
    { ISD::MUL,  MVT::v8i16,  {  1,  5, 1, 1 } }, // pmullw
    { ISD::MUL,  MVT::v4i32,  {  6,  8, 7, 7 } }, // 3*pmuludq/4*shuffle
    { ISD::MUL,  MVT::v2i64,  {  8, 10, 8, 8 } }, // 3*pmuludq/3*shift/2*add
 
    { ISD::FDIV, MVT::f32,    { 23, 23, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FDIV, MVT::v4f32,  { 39, 39, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FDIV, MVT::f64,    { 38, 38, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FDIV, MVT::v2f64,  { 69, 69, 1, 1 } }, // Pentium IV from http://www.agner.org/
 
    { ISD::FNEG, MVT::f32,    {  1,  1, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FNEG, MVT::f64,    {  1,  1, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FNEG, MVT::v4f32,  {  1,  1, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FNEG, MVT::v2f64,  {  1,  1, 1, 1 } }, // Pentium IV from http://www.agner.org/
 
    { ISD::FADD, MVT::f32,    {  2,  3, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FADD, MVT::f64,    {  2,  3, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FADD, MVT::v2f64,  {  2,  3, 1, 1 } }, // Pentium IV from http://www.agner.org/
 
    { ISD::FSUB, MVT::f32,    {  2,  3, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FSUB, MVT::f64,    {  2,  3, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FSUB, MVT::v2f64,  {  2,  3, 1, 1 } }, // Pentium IV from http://www.agner.org/
 
    { ISD::FMUL, MVT::f64,    {  2,  5, 1, 1 } }, // Pentium IV from http://www.agner.org/
    { ISD::FMUL, MVT::v2f64,  {  2,  5, 1, 1 } }, // Pentium IV from http://www.agner.org/
  };
 
  if (ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry SSE1CostTable[] = {
    { ISD::FDIV, MVT::f32,   { 17, 18, 1, 1 } }, // Pentium III from http://www.agner.org/
    { ISD::FDIV, MVT::v4f32, { 34, 48, 1, 1 } }, // Pentium III from http://www.agner.org/
 
    { ISD::FNEG, MVT::f32,   {  2,  2, 1, 2 } }, // Pentium III from http://www.agner.org/
    { ISD::FNEG, MVT::v4f32, {  2,  2, 1, 2 } }, // Pentium III from http://www.agner.org/
 
    { ISD::FADD, MVT::f32,   {  1,  3, 1, 1 } }, // Pentium III from http://www.agner.org/
    { ISD::FADD, MVT::v4f32, {  2,  3, 1, 1 } }, // Pentium III from http://www.agner.org/
 
    { ISD::FSUB, MVT::f32,   {  1,  3, 1, 1 } }, // Pentium III from http://www.agner.org/
    { ISD::FSUB, MVT::v4f32, {  2,  3, 1, 1 } }, // Pentium III from http://www.agner.org/
 
    { ISD::FMUL, MVT::f32,   {  2,  5, 1, 1 } }, // Pentium III from http://www.agner.org/
    { ISD::FMUL, MVT::v4f32, {  2,  5, 1, 1 } }, // Pentium III from http://www.agner.org/
  };
 
  if (ST->hasSSE1())
    if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
    { ISD::ADD,  MVT::i64,  {  1 } }, // Core (Merom) from http://www.agner.org/
    { ISD::SUB,  MVT::i64,  {  1 } }, // Core (Merom) from http://www.agner.org/
    { ISD::MUL,  MVT::i64,  {  2,  6,  1,  2 } },
  };
 
  if (ST->is64Bit())
    if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostKindTblEntry X86CostTbl[] = { // 32 or 64-bit targets
    { ISD::ADD,  MVT::i8,  {  1 } }, // Pentium III from http://www.agner.org/
    { ISD::ADD,  MVT::i16, {  1 } }, // Pentium III from http://www.agner.org/
    { ISD::ADD,  MVT::i32, {  1 } }, // Pentium III from http://www.agner.org/
 
    { ISD::SUB,  MVT::i8,  {  1 } }, // Pentium III from http://www.agner.org/
    { ISD::SUB,  MVT::i16, {  1 } }, // Pentium III from http://www.agner.org/
    { ISD::SUB,  MVT::i32, {  1 } }, // Pentium III from http://www.agner.org/
 
    { ISD::MUL,  MVT::i8,  {  3,  4, 1, 1 } },
    { ISD::MUL,  MVT::i16, {  2,  4, 1, 1 } },
    { ISD::MUL,  MVT::i32, {  1,  4, 1, 1 } },
 
    { ISD::FNEG, MVT::f64, {  2,  2, 1, 3 } }, // (x87)
    { ISD::FADD, MVT::f64, {  2,  3, 1, 1 } }, // (x87)
    { ISD::FSUB, MVT::f64, {  2,  3, 1, 1 } }, // (x87)
    { ISD::FMUL, MVT::f64, {  2,  5, 1, 1 } }, // (x87)
    { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // (x87)
  };
 
  if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second))
    if (auto KindCost = Entry->Cost[CostKind])
      return LT.first * *KindCost;
 
  // It is not a good idea to vectorize division. We have to scalarize it and
  // in the process we will often end up having to spilling regular
  // registers. The overhead of division is going to dominate most kernels
  // anyways so try hard to prevent vectorization of division - it is
  // generally a bad idea. Assume somewhat arbitrarily that we have to be able
  // to hide "20 cycles" for each lane.
  if (CostKind == TTI::TCK_RecipThroughput && LT.second.isVector() &&
      (ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
       ISD == ISD::UREM)) {
    InstructionCost ScalarCost =
        getArithmeticInstrCost(Opcode, Ty->getScalarType(), CostKind,
                               Op1Info.getNoProps(), Op2Info.getNoProps());
    return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost;
  }
 
  // Handle some basic single instruction code size cases.
  if (CostKind == TTI::TCK_CodeSize) {
    switch (ISD) {
    case ISD::FADD:
    case ISD::FSUB:
    case ISD::FMUL:
    case ISD::FDIV:
    case ISD::FNEG:
    case ISD::AND:
    case ISD::OR:
    case ISD::XOR:
      return LT.first;
      break;
    }
  }
 
  // Fallback to the default implementation.
  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
                                       Args, CxtI);
}
 
InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
                                           VectorType *BaseTp,
                                           ArrayRef<int> Mask,
                                           TTI::TargetCostKind CostKind,
                                           int Index, VectorType *SubTp,
                                           ArrayRef<const Value *> Args) {
  // 64-bit packed float vectors (v2f32) are widened to type v4f32.
  // 64-bit packed integer vectors (v2i32) are widened to type v4i32.
  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(BaseTp);
 
  Kind = improveShuffleKindFromMask(Kind, Mask);
 
  // Treat Transpose as 2-op shuffles - there's no difference in lowering.
  if (Kind == TTI::SK_Transpose)
    Kind = TTI::SK_PermuteTwoSrc;
 
  // For Broadcasts we are splatting the first element from the first input
  // register, so only need to reference that input and all the output
  // registers are the same.
  if (Kind == TTI::SK_Broadcast)
    LT.first = 1;
 
  // Subvector extractions are free if they start at the beginning of a
  // vector and cheap if the subvectors are aligned.
  if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) {
    int NumElts = LT.second.getVectorNumElements();
    if ((Index % NumElts) == 0)
      return 0;
    std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
    if (SubLT.second.isVector()) {
      int NumSubElts = SubLT.second.getVectorNumElements();
      if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
        return SubLT.first;
      // Handle some cases for widening legalization. For now we only handle
      // cases where the original subvector was naturally aligned and evenly
      // fit in its legalized subvector type.
      // FIXME: Remove some of the alignment restrictions.
      // FIXME: We can use permq for 64-bit or larger extracts from 256-bit
      // vectors.
      int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements();
      if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 &&
          (NumSubElts % OrigSubElts) == 0 &&
          LT.second.getVectorElementType() ==
              SubLT.second.getVectorElementType() &&
          LT.second.getVectorElementType().getSizeInBits() ==
              BaseTp->getElementType()->getPrimitiveSizeInBits()) {
        assert(NumElts >= NumSubElts && NumElts > OrigSubElts &&
               "Unexpected number of elements!");
        auto *VecTy = FixedVectorType::get(BaseTp->getElementType(),
                                           LT.second.getVectorNumElements());
        auto *SubTy = FixedVectorType::get(BaseTp->getElementType(),
                                           SubLT.second.getVectorNumElements());
        int ExtractIndex = alignDown((Index % NumElts), NumSubElts);
        InstructionCost ExtractCost =
            getShuffleCost(TTI::SK_ExtractSubvector, VecTy, std::nullopt,
                           CostKind, ExtractIndex, SubTy);
 
        // If the original size is 32-bits or more, we can use pshufd. Otherwise
        // if we have SSSE3 we can use pshufb.
        if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3())
          return ExtractCost + 1; // pshufd or pshufb
 
        assert(SubTp->getPrimitiveSizeInBits() == 16 &&
               "Unexpected vector size");
 
        return ExtractCost + 2; // worst case pshufhw + pshufd
      }
    }
  }
 
  // Subvector insertions are cheap if the subvectors are aligned.
  // Note that in general, the insertion starting at the beginning of a vector
  // isn't free, because we need to preserve the rest of the wide vector.
  if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) {
    int NumElts = LT.second.getVectorNumElements();
    std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
    if (SubLT.second.isVector()) {
      int NumSubElts = SubLT.second.getVectorNumElements();
      if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
        return SubLT.first;
    }
 
    // If the insertion isn't aligned, treat it like a 2-op shuffle.
    Kind = TTI::SK_PermuteTwoSrc;
  }
 
  // Handle some common (illegal) sub-vector types as they are often very cheap
  // to shuffle even on targets without PSHUFB.
  EVT VT = TLI->getValueType(DL, BaseTp);
  if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 &&
      !ST->hasSSSE3()) {
     static const CostTblEntry SSE2SubVectorShuffleTbl[] = {
      {TTI::SK_Broadcast,        MVT::v4i16, 1}, // pshuflw
      {TTI::SK_Broadcast,        MVT::v2i16, 1}, // pshuflw
      {TTI::SK_Broadcast,        MVT::v8i8,  2}, // punpck/pshuflw
      {TTI::SK_Broadcast,        MVT::v4i8,  2}, // punpck/pshuflw
      {TTI::SK_Broadcast,        MVT::v2i8,  1}, // punpck
 
      {TTI::SK_Reverse,          MVT::v4i16, 1}, // pshuflw
      {TTI::SK_Reverse,          MVT::v2i16, 1}, // pshuflw
      {TTI::SK_Reverse,          MVT::v4i8,  3}, // punpck/pshuflw/packus
      {TTI::SK_Reverse,          MVT::v2i8,  1}, // punpck
 
      {TTI::SK_Splice,           MVT::v4i16, 2}, // punpck+psrldq
      {TTI::SK_Splice,           MVT::v2i16, 2}, // punpck+psrldq
      {TTI::SK_Splice,           MVT::v4i8,  2}, // punpck+psrldq
      {TTI::SK_Splice,           MVT::v2i8,  2}, // punpck+psrldq
 
      {TTI::SK_PermuteTwoSrc,    MVT::v4i16, 2}, // punpck/pshuflw
      {TTI::SK_PermuteTwoSrc,    MVT::v2i16, 2}, // punpck/pshuflw
      {TTI::SK_PermuteTwoSrc,    MVT::v8i8,  7}, // punpck/pshuflw
      {TTI::SK_PermuteTwoSrc,    MVT::v4i8,  4}, // punpck/pshuflw
      {TTI::SK_PermuteTwoSrc,    MVT::v2i8,  2}, // punpck
 
      {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw
      {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw
      {TTI::SK_PermuteSingleSrc, MVT::v8i8,  5}, // punpck/pshuflw
      {TTI::SK_PermuteSingleSrc, MVT::v4i8,  3}, // punpck/pshuflw
      {TTI::SK_PermuteSingleSrc, MVT::v2i8,  1}, // punpck
    };
 
    if (ST->hasSSE2())
      if (const auto *Entry =
              CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT()))
        return Entry->Cost;
  }
 
  // We are going to permute multiple sources and the result will be in multiple
  // destinations. Providing an accurate cost only for splits where the element
  // type remains the same.
  if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
    MVT LegalVT = LT.second;
    if (LegalVT.isVector() &&
        LegalVT.getVectorElementType().getSizeInBits() ==
            BaseTp->getElementType()->getPrimitiveSizeInBits() &&
        LegalVT.getVectorNumElements() <
            cast<FixedVectorType>(BaseTp)->getNumElements()) {
 
      unsigned VecTySize = DL.getTypeStoreSize(BaseTp);
      unsigned LegalVTSize = LegalVT.getStoreSize();
      // Number of source vectors after legalization:
      unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
      // Number of destination vectors after legalization:
      InstructionCost NumOfDests = LT.first;
 
      auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(),
                                              LegalVT.getVectorNumElements());
 
      if (!Mask.empty() && NumOfDests.isValid()) {
        // Try to perform better estimation of the permutation.
        // 1. Split the source/destination vectors into real registers.
        // 2. Do the mask analysis to identify which real registers are
        // permuted. If more than 1 source registers are used for the
        // destination register building, the cost for this destination register
        // is (Number_of_source_register - 1) * Cost_PermuteTwoSrc. If only one
        // source register is used, build mask and calculate the cost as a cost
        // of PermuteSingleSrc.
        // Also, for the single register permute we try to identify if the
        // destination register is just a copy of the source register or the
        // copy of the previous destination register (the cost is
        // TTI::TCC_Basic). If the source register is just reused, the cost for
        // this operation is 0.
        unsigned E = *NumOfDests.getValue();
        unsigned NormalizedVF =
            LegalVT.getVectorNumElements() * std::max(NumOfSrcs, E);
        unsigned NumOfSrcRegs = NormalizedVF / LegalVT.getVectorNumElements();
        unsigned NumOfDestRegs = NormalizedVF / LegalVT.getVectorNumElements();
        SmallVector<int> NormalizedMask(NormalizedVF, PoisonMaskElem);
        copy(Mask, NormalizedMask.begin());
        unsigned PrevSrcReg = 0;
        ArrayRef<int> PrevRegMask;
        InstructionCost Cost = 0;
        processShuffleMasks(
            NormalizedMask, NumOfSrcRegs, NumOfDestRegs, NumOfDestRegs, []() {},
            [this, SingleOpTy, CostKind, &PrevSrcReg, &PrevRegMask,
             &Cost](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) {
              if (!ShuffleVectorInst::isIdentityMask(RegMask)) {
                // Check if the previous register can be just copied to the next
                // one.
                if (PrevRegMask.empty() || PrevSrcReg != SrcReg ||
                    PrevRegMask != RegMask)
                  Cost += getShuffleCost(TTI::SK_PermuteSingleSrc, SingleOpTy,
                                         RegMask, CostKind, 0, nullptr);
                else
                  // Just a copy of previous destination register.
                  Cost += TTI::TCC_Basic;
                return;
              }
              if (SrcReg != DestReg &&
                  any_of(RegMask, [](int I) { return I != PoisonMaskElem; })) {
                // Just a copy of the source register.
                Cost += TTI::TCC_Basic;
              }
              PrevSrcReg = SrcReg;
              PrevRegMask = RegMask;
            },
            [this, SingleOpTy, CostKind, &Cost](ArrayRef<int> RegMask,
                                                unsigned /*Unused*/,
                                                unsigned /*Unused*/) {
              Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, RegMask,
                                     CostKind, 0, nullptr);
            });
        return Cost;
      }
 
      InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
      return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy,
                                            std::nullopt, CostKind, 0, nullptr);
    }
 
    return BaseT::getShuffleCost(Kind, BaseTp, Mask, CostKind, Index, SubTp);
  }
 
  // For 2-input shuffles, we must account for splitting the 2 inputs into many.
  if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
    // We assume that source and destination have the same vector type.
    InstructionCost NumOfDests = LT.first;
    InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1;
    LT.first = NumOfDests * NumOfShufflesPerDest;
  }
 
  static const CostTblEntry AVX512VBMIShuffleTbl[] = {
      {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb
      {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb
 
      {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb
      {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb
 
      {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b
      {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b
      {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2}  // vpermt2b
  };
 
  if (ST->hasVBMI())
    if (const auto *Entry =
            CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostTblEntry AVX512BWShuffleTbl[] = {
      {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
      {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw
      {TTI::SK_Broadcast, MVT::v64i8, 1},  // vpbroadcastb
 
      {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw
      {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw
      {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw
      {TTI::SK_Reverse, MVT::v64i8, 2},  // pshufb + vshufi64x2
 
      {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw
      {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw
      {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw
      {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw
      {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8},  // extend to v32i16
 
      {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w
      {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w
      {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w
      {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2},  // vpermt2w
      {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1
 
      {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw
      {TTI::SK_Select, MVT::v64i8,  1}, // vblendmb
 
      {TTI::SK_Splice, MVT::v32i16, 2}, // vshufi64x2 + palignr
      {TTI::SK_Splice, MVT::v32f16, 2}, // vshufi64x2 + palignr
      {TTI::SK_Splice, MVT::v64i8,  2}, // vshufi64x2 + palignr
  };
 
  if (ST->hasBWI())
    if (const auto *Entry =
            CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostKindTblEntry AVX512ShuffleTbl[] = {
      {TTI::SK_Broadcast, MVT::v8f64,  { 1, 1, 1, 1 } }, // vbroadcastsd
      {TTI::SK_Broadcast, MVT::v16f32, { 1, 1, 1, 1 } }, // vbroadcastss
      {TTI::SK_Broadcast, MVT::v8i64,  { 1, 1, 1, 1 } }, // vpbroadcastq
      {TTI::SK_Broadcast, MVT::v16i32, { 1, 1, 1, 1 } }, // vpbroadcastd
      {TTI::SK_Broadcast, MVT::v32i16, { 1, 1, 1, 1 } }, // vpbroadcastw
      {TTI::SK_Broadcast, MVT::v32f16, { 1, 1, 1, 1 } }, // vpbroadcastw
      {TTI::SK_Broadcast, MVT::v64i8,  { 1, 1, 1, 1 } }, // vpbroadcastb
 
      {TTI::SK_Reverse, MVT::v8f64,  { 1, 3, 1, 1 } }, // vpermpd
      {TTI::SK_Reverse, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermps
      {TTI::SK_Reverse, MVT::v8i64,  { 1, 3, 1, 1 } }, // vpermq
      {TTI::SK_Reverse, MVT::v16i32, { 1, 3, 1, 1 } }, // vpermd
      {TTI::SK_Reverse, MVT::v32i16, { 7, 7, 7, 7 } }, // per mca
      {TTI::SK_Reverse, MVT::v32f16, { 7, 7, 7, 7 } }, // per mca
      {TTI::SK_Reverse, MVT::v64i8,  { 7, 7, 7, 7 } }, // per mca
 
      {TTI::SK_Splice, MVT::v8f64,  { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v4f64,  { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v16f32, { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v8f32,  { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v8i64,  { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v4i64,  { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v16i32, { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v8i32,  { 1, 1, 1, 1 } }, // vpalignd
      {TTI::SK_Splice, MVT::v32i16, { 4, 4, 4, 4 } }, // split + palignr
      {TTI::SK_Splice, MVT::v32f16, { 4, 4, 4, 4 } }, // split + palignr
      {TTI::SK_Splice, MVT::v64i8,  { 4, 4, 4, 4 } }, // split + palignr
 
      {TTI::SK_PermuteSingleSrc, MVT::v8f64,  { 1, 3, 1, 1 } }, // vpermpd
      {TTI::SK_PermuteSingleSrc, MVT::v4f64,  { 1, 3, 1, 1 } }, // vpermpd
      {TTI::SK_PermuteSingleSrc, MVT::v2f64,  { 1, 3, 1, 1 } }, // vpermpd
      {TTI::SK_PermuteSingleSrc, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermps
      {TTI::SK_PermuteSingleSrc, MVT::v8f32,  { 1, 3, 1, 1 } }, // vpermps
      {TTI::SK_PermuteSingleSrc, MVT::v4f32,  { 1, 3, 1, 1 } }, // vpermps
      {TTI::SK_PermuteSingleSrc, MVT::v8i64,  { 1, 3, 1, 1 } }, // vpermq
      {TTI::SK_PermuteSingleSrc, MVT::v4i64,  { 1, 3, 1, 1 } }, // vpermq
      {TTI::SK_PermuteSingleSrc, MVT::v2i64,  { 1, 3, 1, 1 } }, // vpermq
      {TTI::SK_PermuteSingleSrc, MVT::v16i32, { 1, 3, 1, 1 } }, // vpermd
      {TTI::SK_PermuteSingleSrc, MVT::v8i32,  { 1, 3, 1, 1 } }, // vpermd
      {TTI::SK_PermuteSingleSrc, MVT::v4i32,  { 1, 3, 1, 1 } }, // vpermd
      {TTI::SK_PermuteSingleSrc, MVT::v16i8,  { 1, 3, 1, 1 } }, // pshufb
 
      {TTI::SK_PermuteTwoSrc, MVT::v8f64,  { 1, 3, 1, 1 } }, // vpermt2pd
      {TTI::SK_PermuteTwoSrc, MVT::v16f32, { 1, 3, 1, 1 } }, // vpermt2ps
      {TTI::SK_PermuteTwoSrc, MVT::v8i64,  { 1, 3, 1, 1 } }, // vpermt2q
      {TTI::SK_PermuteTwoSrc, MVT::v16i32, { 1, 3, 1, 1 } }, // vpermt2d
      {TTI::SK_PermuteTwoSrc, MVT::v4f64,  { 1, 3, 1, 1 } }, // vpermt2pd
      {TTI::SK_PermuteTwoSrc, MVT::v8f32,  { 1, 3, 1, 1 } }, // vpermt2ps
      {TTI::SK_PermuteTwoSrc, MVT::v4i64,  { 1, 3, 1, 1 } }, // vpermt2q
      {TTI::SK_PermuteTwoSrc, MVT::v8i32,  { 1, 3, 1, 1 } }, // vpermt2d
      {TTI::SK_PermuteTwoSrc, MVT::v2f64,  { 1, 3, 1, 1 } }, // vpermt2pd
      {TTI::SK_PermuteTwoSrc, MVT::v4f32,  { 1, 3, 1, 1 } }, // vpermt2ps
      {TTI::SK_PermuteTwoSrc, MVT::v2i64,  { 1, 3, 1, 1 } }, // vpermt2q
      {TTI::SK_PermuteTwoSrc, MVT::v4i32,  { 1, 3, 1, 1 } }, // vpermt2d
 
      // FIXME: This just applies the type legalization cost rules above
      // assuming these completely split.
      {TTI::SK_PermuteSingleSrc, MVT::v32i16, { 14, 14, 14, 14 } },
      {TTI::SK_PermuteSingleSrc, MVT::v32f16, { 14, 14, 14, 14 } },
      {TTI::SK_PermuteSingleSrc, MVT::v64i8,  { 14, 14, 14, 14 } },
      {TTI::SK_PermuteTwoSrc,    MVT::v32i16, { 42, 42, 42, 42 } },
      {TTI::SK_PermuteTwoSrc,    MVT::v32f16, { 42, 42, 42, 42 } },
      {TTI::SK_PermuteTwoSrc,    MVT::v64i8,  { 42, 42, 42, 42 } },
 
      {TTI::SK_Select, MVT::v32i16, { 1, 1, 1, 1 } }, // vpternlogq
      {TTI::SK_Select, MVT::v32f16, { 1, 1, 1, 1 } }, // vpternlogq
      {TTI::SK_Select, MVT::v64i8,  { 1, 1, 1, 1 } }, // vpternlogq
      {TTI::SK_Select, MVT::v8f64,  { 1, 1, 1, 1 } }, // vblendmpd
      {TTI::SK_Select, MVT::v16f32, { 1, 1, 1, 1 } }, // vblendmps
      {TTI::SK_Select, MVT::v8i64,  { 1, 1, 1, 1 } }, // vblendmq
      {TTI::SK_Select, MVT::v16i32, { 1, 1, 1, 1 } }, // vblendmd
  };
 
  if (ST->hasAVX512())
    if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * *KindCost;
 
  static const CostTblEntry AVX2ShuffleTbl[] = {
      {TTI::SK_Broadcast, MVT::v4f64, 1},  // vbroadcastpd
      {TTI::SK_Broadcast, MVT::v8f32, 1},  // vbroadcastps
      {TTI::SK_Broadcast, MVT::v4i64, 1},  // vpbroadcastq
      {TTI::SK_Broadcast, MVT::v8i32, 1},  // vpbroadcastd
      {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
      {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw
      {TTI::SK_Broadcast, MVT::v32i8, 1},  // vpbroadcastb
 
      {TTI::SK_Reverse, MVT::v4f64, 1},  // vpermpd
      {TTI::SK_Reverse, MVT::v8f32, 1},  // vpermps
      {TTI::SK_Reverse, MVT::v4i64, 1},  // vpermq
      {TTI::SK_Reverse, MVT::v8i32, 1},  // vpermd
      {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
      {TTI::SK_Reverse, MVT::v16f16, 2}, // vperm2i128 + pshufb
      {TTI::SK_Reverse, MVT::v32i8, 2},  // vperm2i128 + pshufb
 
      {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
      {TTI::SK_Select, MVT::v16f16, 1}, // vpblendvb
      {TTI::SK_Select, MVT::v32i8,  1}, // vpblendvb
 
      {TTI::SK_Splice, MVT::v8i32,  2}, // vperm2i128 + vpalignr
      {TTI::SK_Splice, MVT::v8f32,  2}, // vperm2i128 + vpalignr
      {TTI::SK_Splice, MVT::v16i16, 2}, // vperm2i128 + vpalignr
      {TTI::SK_Splice, MVT::v16f16, 2}, // vperm2i128 + vpalignr
      {TTI::SK_Splice, MVT::v32i8,  2}, // vperm2i128 + vpalignr
 
      {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1},  // vpermpd
      {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1},  // vpermps
      {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1},  // vpermq
      {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1},  // vpermd
      {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
                                                  // + vpblendvb
      {TTI::SK_PermuteSingleSrc, MVT::v16f16, 4}, // vperm2i128 + 2*vpshufb
                                                  // + vpblendvb
      {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4},  // vperm2i128 + 2*vpshufb
                                                  // + vpblendvb
 
      {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3},  // 2*vpermpd + vblendpd
      {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3},  // 2*vpermps + vblendps
      {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3},  // 2*vpermq + vpblendd
      {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3},  // 2*vpermd + vpblendd
      {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
                                               // + vpblendvb
      {TTI::SK_PermuteTwoSrc, MVT::v16f16, 7}, // 2*vperm2i128 + 4*vpshufb
                                               // + vpblendvb
      {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7},  // 2*vperm2i128 + 4*vpshufb
                                               // + vpblendvb
  };
 
  if (ST->hasAVX2())
    if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostTblEntry XOPShuffleTbl[] = {
      {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2},  // vperm2f128 + vpermil2pd
      {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2},  // vperm2f128 + vpermil2ps
      {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2},  // vperm2f128 + vpermil2pd
      {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2},  // vperm2f128 + vpermil2ps
      {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
                                                  // + vinsertf128
      {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4},  // vextractf128 + 2*vpperm
                                                  // + vinsertf128
 
      {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
                                               // + vinsertf128
      {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1},  // vpperm
      {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9},  // 2*vextractf128 + 6*vpperm
                                               // + vinsertf128
      {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1},  // vpperm
  };
 
  if (ST->hasXOP())
    if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostTblEntry AVX1ShuffleTbl[] = {
      {TTI::SK_Broadcast, MVT::v4f64, 2},  // vperm2f128 + vpermilpd
      {TTI::SK_Broadcast, MVT::v8f32, 2},  // vperm2f128 + vpermilps
      {TTI::SK_Broadcast, MVT::v4i64, 2},  // vperm2f128 + vpermilpd
      {TTI::SK_Broadcast, MVT::v8i32, 2},  // vperm2f128 + vpermilps
      {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
      {TTI::SK_Broadcast, MVT::v16f16, 3}, // vpshuflw + vpshufd + vinsertf128
      {TTI::SK_Broadcast, MVT::v32i8, 2},  // vpshufb + vinsertf128
 
      {TTI::SK_Reverse, MVT::v4f64, 2},  // vperm2f128 + vpermilpd
      {TTI::SK_Reverse, MVT::v8f32, 2},  // vperm2f128 + vpermilps
      {TTI::SK_Reverse, MVT::v4i64, 2},  // vperm2f128 + vpermilpd
      {TTI::SK_Reverse, MVT::v8i32, 2},  // vperm2f128 + vpermilps
      {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
                                         // + vinsertf128
      {TTI::SK_Reverse, MVT::v16f16, 4}, // vextractf128 + 2*pshufb
                                         // + vinsertf128
      {TTI::SK_Reverse, MVT::v32i8, 4},  // vextractf128 + 2*pshufb
                                         // + vinsertf128
 
      {TTI::SK_Select, MVT::v4i64, 1},  // vblendpd
      {TTI::SK_Select, MVT::v4f64, 1},  // vblendpd
      {TTI::SK_Select, MVT::v8i32, 1},  // vblendps
      {TTI::SK_Select, MVT::v8f32, 1},  // vblendps
      {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
      {TTI::SK_Select, MVT::v16f16, 3}, // vpand + vpandn + vpor
      {TTI::SK_Select, MVT::v32i8, 3},  // vpand + vpandn + vpor
 
      {TTI::SK_Splice, MVT::v4i64,  2}, // vperm2f128 + shufpd
      {TTI::SK_Splice, MVT::v4f64,  2}, // vperm2f128 + shufpd
      {TTI::SK_Splice, MVT::v8i32,  4}, // 2*vperm2f128 + 2*vshufps
      {TTI::SK_Splice, MVT::v8f32,  4}, // 2*vperm2f128 + 2*vshufps
      {TTI::SK_Splice, MVT::v16i16, 5}, // 2*vperm2f128 + 2*vpalignr + vinsertf128
      {TTI::SK_Splice, MVT::v16f16, 5}, // 2*vperm2f128 + 2*vpalignr + vinsertf128
      {TTI::SK_Splice, MVT::v32i8,  5}, // 2*vperm2f128 + 2*vpalignr + vinsertf128
 
      {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2},  // vperm2f128 + vshufpd
      {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2},  // vperm2f128 + vshufpd
      {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4},  // 2*vperm2f128 + 2*vshufps
      {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4},  // 2*vperm2f128 + 2*vshufps
      {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
                                                  // + 2*por + vinsertf128
      {TTI::SK_PermuteSingleSrc, MVT::v16f16, 8}, // vextractf128 + 4*pshufb
                                                  // + 2*por + vinsertf128
      {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8},  // vextractf128 + 4*pshufb
                                                  // + 2*por + vinsertf128
 
      {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3},   // 2*vperm2f128 + vshufpd
      {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3},   // 2*vperm2f128 + vshufpd
      {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4},   // 2*vperm2f128 + 2*vshufps
      {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4},   // 2*vperm2f128 + 2*vshufps
      {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
                                                // + 4*por + vinsertf128
      {TTI::SK_PermuteTwoSrc, MVT::v16f16, 15}, // 2*vextractf128 + 8*pshufb
                                                // + 4*por + vinsertf128
      {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15},  // 2*vextractf128 + 8*pshufb
                                                // + 4*por + vinsertf128
  };
 
  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostTblEntry SSE41ShuffleTbl[] = {
      {TTI::SK_Select, MVT::v2i64, 1}, // pblendw
      {TTI::SK_Select, MVT::v2f64, 1}, // movsd
      {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
      {TTI::SK_Select, MVT::v4f32, 1}, // blendps
      {TTI::SK_Select, MVT::v8i16, 1}, // pblendw
      {TTI::SK_Select, MVT::v8f16, 1}, // pblendw
      {TTI::SK_Select, MVT::v16i8, 1}  // pblendvb
  };
 
  if (ST->hasSSE41())
    if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostTblEntry SSSE3ShuffleTbl[] = {
      {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb
      {TTI::SK_Broadcast, MVT::v8f16, 1}, // pshufb
      {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb
 
      {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb
      {TTI::SK_Reverse, MVT::v8f16, 1}, // pshufb
      {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb
 
      {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por
      {TTI::SK_Select, MVT::v8f16, 3}, // 2*pshufb + por
      {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por
 
      {TTI::SK_Splice, MVT::v4i32, 1}, // palignr
      {TTI::SK_Splice, MVT::v4f32, 1}, // palignr
      {TTI::SK_Splice, MVT::v8i16, 1}, // palignr
      {TTI::SK_Splice, MVT::v8f16, 1}, // palignr
      {TTI::SK_Splice, MVT::v16i8, 1}, // palignr
 
      {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb
      {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // pshufb
      {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
 
      {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por
      {TTI::SK_PermuteTwoSrc, MVT::v8f16, 3}, // 2*pshufb + por
      {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por
  };
 
  if (ST->hasSSSE3())
    if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  static const CostTblEntry SSE2ShuffleTbl[] = {
      {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd
      {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd
      {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
      {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd
      {TTI::SK_Broadcast, MVT::v8f16, 2}, // pshuflw + pshufd
      {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd
 
      {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd
      {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd
      {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
      {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd
      {TTI::SK_Reverse, MVT::v8f16, 3}, // pshuflw + pshufhw + pshufd
      {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw
                                        // + 2*pshufd + 2*unpck + packus
 
      {TTI::SK_Select, MVT::v2i64, 1}, // movsd
      {TTI::SK_Select, MVT::v2f64, 1}, // movsd
      {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
      {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por
      {TTI::SK_Select, MVT::v8f16, 3}, // pand + pandn + por
      {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por
 
      {TTI::SK_Splice, MVT::v2i64, 1}, // shufpd
      {TTI::SK_Splice, MVT::v2f64, 1}, // shufpd
      {TTI::SK_Splice, MVT::v4i32, 2}, // 2*{unpck,movsd,pshufd}
      {TTI::SK_Splice, MVT::v8i16, 3}, // psrldq + psrlldq + por
      {TTI::SK_Splice, MVT::v8f16, 3}, // psrldq + psrlldq + por
      {TTI::SK_Splice, MVT::v16i8, 3}, // psrldq + psrlldq + por
 
      {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd
      {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd
      {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
      {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
                                                  // + pshufd/unpck
      {TTI::SK_PermuteSingleSrc, MVT::v8f16, 5}, // 2*pshuflw + 2*pshufhw
                                                  // + pshufd/unpck
    { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
                                                  // + 2*pshufd + 2*unpck + 2*packus
 
    { TTI::SK_PermuteTwoSrc,    MVT::v2f64,  1 }, // shufpd
    { TTI::SK_PermuteTwoSrc,    MVT::v2i64,  1 }, // shufpd
    { TTI::SK_PermuteTwoSrc,    MVT::v4i32,  2 }, // 2*{unpck,movsd,pshufd}
    { TTI::SK_PermuteTwoSrc,    MVT::v8i16,  8 }, // blend+permute
    { TTI::SK_PermuteTwoSrc,    MVT::v8f16,  8 }, // blend+permute
    { TTI::SK_PermuteTwoSrc,    MVT::v16i8, 13 }, // blend+permute
  };
 
  static const CostTblEntry SSE3BroadcastLoadTbl[] = {
      {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup
  };
 
  if (ST->hasSSE2()) {
    bool IsLoad =
        llvm::any_of(Args, [](const auto &V) { return isa<LoadInst>(V); });
    if (ST->hasSSE3() && IsLoad)
      if (const auto *Entry =
              CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) {
        assert(isLegalBroadcastLoad(BaseTp->getElementType(),
                                    LT.second.getVectorElementCount()) &&
               "Table entry missing from isLegalBroadcastLoad()");
        return LT.first * Entry->Cost;
      }
 
    if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
  }
 
  static const CostTblEntry SSE1ShuffleTbl[] = {
    { TTI::SK_Broadcast,        MVT::v4f32, 1 }, // shufps
    { TTI::SK_Reverse,          MVT::v4f32, 1 }, // shufps
    { TTI::SK_Select,           MVT::v4f32, 2 }, // 2*shufps
    { TTI::SK_Splice,           MVT::v4f32, 2 }, // 2*shufps
    { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
    { TTI::SK_PermuteTwoSrc,    MVT::v4f32, 2 }, // 2*shufps
  };
 
  if (ST->hasSSE1())
    if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
      return LT.first * Entry->Cost;
 
  return BaseT::getShuffleCost(Kind, BaseTp, Mask, CostKind, Index, SubTp);
}
 
InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
                                             Type *Src,
                                             TTI::CastContextHint CCH,
                                             TTI::TargetCostKind CostKind,
                                             const Instruction *I) {
  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Invalid opcode");
 
  // TODO: Allow non-throughput costs that aren't binary.
  auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost {
    if (CostKind != TTI::TCK_RecipThroughput)
      return Cost == 0 ? 0 : 1;
    return Cost;
  };
 
  // The cost tables include both specific, custom (non-legal) src/dst type
  // conversions and generic, legalized types. We test for customs first, before
  // falling back to legalization.
  // FIXME: Need a better design of the cost table to handle non-simple types of
  // potential massive combinations (elem_num x src_type x dst_type).
  static const TypeConversionCostTblEntry AVX512BWConversionTbl[] {
    { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
    { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
 
    // Mask sign extend has an instruction.
    { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v64i8,  MVT::v64i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1,  1 },
 
    // Mask zero extend is a sext + shift.
    { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v64i8,  MVT::v64i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1,  2 },
 
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v8i16,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v8i16,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i16,  2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 },
    { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 },
    { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i16, 2 },
    { ISD::TRUNCATE,    MVT::v64i1,  MVT::v64i8,  2 },
    { ISD::TRUNCATE,    MVT::v64i1,  MVT::v32i16, 2 },
 
    { ISD::TRUNCATE,    MVT::v32i8,  MVT::v32i16, 2 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 }, // widen to zmm
    { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i16,  2 }, // vpmovwb
    { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i16,  2 }, // vpmovwb
    { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i16,  2 }, // vpmovwb
  };
 
  static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
    // Mask sign extend has an instruction.
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1,  1 },
 
    // Mask zero extend is a sext + shift.
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1,  2 },
 
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i64,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v4i32,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i32,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i64,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i64,  2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i32, 2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v8i64,  2 },
 
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i64,  1 },
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  1 },
 
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i64,  1 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  1 },
 
    { ISD::FP_TO_SINT,  MVT::v8i64,  MVT::v8f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v8i64,  MVT::v8f64,  1 },
 
    { ISD::FP_TO_UINT,  MVT::v8i64,  MVT::v8f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v8i64,  MVT::v8f64,  1 },
  };
 
  // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
  // 256-bit wide vectors.
 
  static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
    { ISD::FP_EXTEND, MVT::v8f64,   MVT::v8f32,  1 },
    { ISD::FP_EXTEND, MVT::v8f64,   MVT::v16f32, 3 },
    { ISD::FP_ROUND,  MVT::v8f32,   MVT::v8f64,  1 },
 
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i8,   3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i8,   3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i8,   3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i8,  3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i16,  3 }, // sext+vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i16,  3 }, // sext+vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i16,  3 }, // sext+vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i16, 3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i32,  2 }, // zmm vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i32,  2 }, // zmm vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i32,  2 }, // zmm vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i32, 2 }, // vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i64,  2 }, // zmm vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i64,  2 }, // zmm vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i64,  2 }, // vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v2i8,    MVT::v2i32,  2 }, // vpmovdb
    { ISD::TRUNCATE,  MVT::v4i8,    MVT::v4i32,  2 }, // vpmovdb
    { ISD::TRUNCATE,  MVT::v16i8,   MVT::v16i32, 2 }, // vpmovdb
    { ISD::TRUNCATE,  MVT::v32i8,   MVT::v16i32, 2 }, // vpmovdb
    { ISD::TRUNCATE,  MVT::v64i8,   MVT::v16i32, 2 }, // vpmovdb
    { ISD::TRUNCATE,  MVT::v16i16,  MVT::v16i32, 2 }, // vpmovdw
    { ISD::TRUNCATE,  MVT::v32i16,  MVT::v16i32, 2 }, // vpmovdw
    { ISD::TRUNCATE,  MVT::v2i8,    MVT::v2i64,  2 }, // vpmovqb
    { ISD::TRUNCATE,  MVT::v2i16,   MVT::v2i64,  1 }, // vpshufb
    { ISD::TRUNCATE,  MVT::v8i8,    MVT::v8i64,  2 }, // vpmovqb
    { ISD::TRUNCATE,  MVT::v16i8,   MVT::v8i64,  2 }, // vpmovqb
    { ISD::TRUNCATE,  MVT::v32i8,   MVT::v8i64,  2 }, // vpmovqb
    { ISD::TRUNCATE,  MVT::v64i8,   MVT::v8i64,  2 }, // vpmovqb
    { ISD::TRUNCATE,  MVT::v8i16,   MVT::v8i64,  2 }, // vpmovqw
    { ISD::TRUNCATE,  MVT::v16i16,  MVT::v8i64,  2 }, // vpmovqw
    { ISD::TRUNCATE,  MVT::v32i16,  MVT::v8i64,  2 }, // vpmovqw
    { ISD::TRUNCATE,  MVT::v8i32,   MVT::v8i64,  1 }, // vpmovqd
    { ISD::TRUNCATE,  MVT::v4i32,   MVT::v4i64,  1 }, // zmm vpmovqd
    { ISD::TRUNCATE,  MVT::v16i8,   MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb
 
    { ISD::TRUNCATE,  MVT::v16i8,  MVT::v16i16,  3 }, // extend to v16i32
    { ISD::TRUNCATE,  MVT::v32i8,  MVT::v32i16,  8 },
    { ISD::TRUNCATE,  MVT::v64i8,  MVT::v32i16,  8 },
 
    // Sign extend is zmm vpternlogd+vptruncdb.
    // Zero extend is zmm broadcast load+vptruncdw.
    { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1,  3 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1,  4 },
 
    // Sign extend is zmm vpternlogd+vptruncdw.
    // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw.
    { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  3 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  4 },
 
    { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i1,   1 }, // zmm vpternlogd
    { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i1,   2 }, // zmm vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 }, // zmm vpternlogd
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 }, // zmm vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 }, // zmm vpternlogd
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 }, // zmm vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 }, // zmm vpternlogq
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 }, // zmm vpternlogq+psrlq
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 }, // zmm vpternlogq
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 }, // zmm vpternlogq+psrlq
 
    { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1,  1 }, // vpternlogd
    { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1,  2 }, // vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i1,   1 }, // vpternlogq
    { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i1,   2 }, // vpternlogq+psrlq
 
    { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  1 },
    { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  1 },
    { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
    { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
    { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i8,   1 },
    { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i8,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i16,  1 },
    { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i16,  1 },
    { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i32,  1 },
    { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i32,  1 },
 
    { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8,  3 }, // FIXME: May not be right
    { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8,  3 }, // FIXME: May not be right
 
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i1,   4 },
    { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i1,  3 },
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v16i8,  2 },
    { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i8,  1 },
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i16,  2 },
    { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i16, 1 },
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  1 },
    { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i32, 1 },
 
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i1,   4 },
    { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i1,  3 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v16i8,  2 },
    { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i8,  1 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i16,  2 },
    { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i16, 1 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  1 },
    { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i32, 1 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i64, 26 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  5 },
 
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f32, 2 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f64, 7 },
    { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v32f64,15 },
    { ISD::FP_TO_SINT,  MVT::v64i8,  MVT::v64f32,11 },
    { ISD::FP_TO_SINT,  MVT::v64i8,  MVT::v64f64,31 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v8f64,  3 },
    { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v16f64, 7 },
    { ISD::FP_TO_SINT,  MVT::v32i16, MVT::v32f32, 5 },
    { ISD::FP_TO_SINT,  MVT::v32i16, MVT::v32f64,15 },
    { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f64,  1 },
    { ISD::FP_TO_SINT,  MVT::v16i32, MVT::v16f64, 3 },
 
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f64,  1 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v8f64,  3 },
    { ISD::FP_TO_UINT,  MVT::v8i8,   MVT::v8f64,  3 },
    { ISD::FP_TO_UINT,  MVT::v16i32, MVT::v16f32, 1 },
    { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v16f32, 3 },
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v16f32, 3 },
  };
 
  static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] {
    // Mask sign extend has an instruction.
    { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v64i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1,  1 },
 
    // Mask zero extend is a sext + shift.
    { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v64i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1,  2 },
 
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v8i16,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v8i16,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i16,  2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i8,  2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 },
    { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 },
    { ISD::TRUNCATE,    MVT::v32i1,  MVT::v16i16, 2 },
    { ISD::TRUNCATE,    MVT::v64i1,  MVT::v32i8,  2 },
    { ISD::TRUNCATE,    MVT::v64i1,  MVT::v16i16, 2 },
 
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 },
  };
 
  static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = {
    // Mask sign extend has an instruction.
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v2i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i1,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i1,  1 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 },
 
    // Mask zero extend is a sext + shift.
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v2i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i1,   2 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i1,  2 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 },
 
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v4i64,  2 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v8i32,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i64,  2 },
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v4i32,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i32,  2 },
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i64,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v4i64,  2 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  2 },
 
    { ISD::SINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  1 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  1 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  1 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  1 },
 
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  1 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  1 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  1 },
 
    { ISD::FP_TO_SINT,  MVT::v2i64,  MVT::v4f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v4i64,  MVT::v4f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v2i64,  MVT::v2f64,  1 },
    { ISD::FP_TO_SINT,  MVT::v4i64,  MVT::v4f64,  1 },
 
    { ISD::FP_TO_UINT,  MVT::v2i64,  MVT::v4f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v4i64,  MVT::v4f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v2i64,  MVT::v2f64,  1 },
    { ISD::FP_TO_UINT,  MVT::v4i64,  MVT::v4f64,  1 },
  };
 
  static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = {
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i8,   3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i8,   3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i8,   3 }, // sext+vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i8,  8 }, // split+2*v8i8
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i16,  3 }, // sext+vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i16,  3 }, // sext+vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i16,  3 }, // sext+vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i16, 8 }, // split+2*v8i16
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i32,  2 }, // vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i32,  2 }, // vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i32,  2 }, // vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v16i1,   MVT::v8i32,  2 }, // vpslld+vptestmd
    { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i64,  2 }, // vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i64,  2 }, // vpsllq+vptestmq
    { ISD::TRUNCATE,  MVT::v4i32,   MVT::v4i64,  1 }, // vpmovqd
    { ISD::TRUNCATE,  MVT::v4i8,    MVT::v4i64,  2 }, // vpmovqb
    { ISD::TRUNCATE,  MVT::v4i16,   MVT::v4i64,  2 }, // vpmovqw
    { ISD::TRUNCATE,  MVT::v8i8,    MVT::v8i32,  2 }, // vpmovwb
 
    // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb
    // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb
    { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   5 },
    { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   6 },
    { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   5 },
    { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   6 },
    { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   5 },
    { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   6 },
    { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 10 },
    { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 12 },
 
    // sign extend is vpcmpeq+maskedmove+vpmovdw
    // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw
    { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   4 },
    { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   5 },
    { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   4 },
    { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   5 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   4 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   5 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 },
 
    { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i1,   1 }, // vpternlogd
    { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i1,   2 }, // vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 }, // vpternlogd
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 }, // vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 }, // vpternlogd
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 }, // vpternlogd+psrld
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i1,  1 }, // vpternlogd
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i1,  2 }, // vpternlogd+psrld
 
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 }, // vpternlogq
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 }, // vpternlogq+psrlq
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 }, // vpternlogq
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 }, // vpternlogq+psrlq
 
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i8,  1 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i8,  1 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i8,  1 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i8,  1 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  1 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  1 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i16,  1 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i16,  1 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  1 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  1 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  1 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  1 },
 
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  1 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  1 },
 
    { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    1 },
    { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    1 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  1 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  1 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  1 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  5 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  5 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  5 },
 
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v8f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f32, 2 },
    { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v32f32, 5 },
 
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    1 },
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    1 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  1 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  1 },
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f64,  1 },
  };
 
  static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   3 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   3 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   3 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
 
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i8,  2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i8,  2 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i8,  2 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i8,  2 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  2 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  2 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i16,  2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i16,  2 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
    { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
    { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  2 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  2 },
 
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  2 },
 
    { ISD::TRUNCATE,    MVT::v16i16, MVT::v16i32, 4 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i32, 4 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i16,  1 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i32,  1 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v2i64,  1 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i32,  4 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i64,  4 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i32,  1 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v2i64,  1 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i64,  5 },
    { ISD::TRUNCATE,    MVT::v4i32,  MVT::v4i64,  1 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  2 },
 
    { ISD::FP_EXTEND,   MVT::v8f64,  MVT::v8f32,  3 },
    { ISD::FP_ROUND,    MVT::v8f32,  MVT::v8f64,  3 },
 
    { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v8f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f64,  1 },
    { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f64,  3 },
 
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    3 },
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    3 },
    { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v8f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  3 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  4 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  4 },
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  3 },
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v4f64,  4 },
 
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  2 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  2 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  2 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  2 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  1 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  1 },
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  3 },
 
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  2 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  2 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  2 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  2 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  2 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i32,  1 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  2 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  2 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  2 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  4 },
  };
 
  static const TypeConversionCostTblEntry AVXConversionTbl[] = {
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   6 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   7 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   4 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  4 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  4 },
 
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i8,  3 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i8,  3 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i8,  3 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i8,  3 },
    { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  3 },
    { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  3 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i16,  3 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i16,  3 },
    { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  3 },
    { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  3 },
    { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  3 },
    { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  3 },
 
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i64,  4 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  5 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 4 },
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i64,  9 },
    { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i64, 11 },
 
    { ISD::TRUNCATE,    MVT::v16i16, MVT::v16i32, 6 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i32, 6 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 }, // and+extract+packuswb
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i32,  5 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  5 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i64,  5 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i64,  3 }, // and+extract+2*packusdw
    { ISD::TRUNCATE,    MVT::v4i32,  MVT::v4i64,  2 },
 
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i1,   3 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i1,   3 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i1,   8 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  4 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v16i8,  2 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  4 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v8i16,  2 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  2 },
    { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  2 },
    { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  4 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v2i64,  5 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  8 },
 
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i1,   7 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i1,   7 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i1,   6 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  4 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v16i8,  2 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  4 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v8i16,  2 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  4 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i32,  4 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  5 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  6 },
    { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  8 },
    { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32, 10 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64, 10 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64, 18 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  5 },
    { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64, 10 },
 
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v8f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v4f64,  2 },
    { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v8f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v4f64,  2 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v8f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v4f64,  2 },
    { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v8f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v4f64,  2 },
    { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f64,  2 },
    { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f64,  5 },
 
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v8f32,  2 },
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v4f64,  2 },
    { ISD::FP_TO_UINT,  MVT::v32i8,  MVT::v8f32,  2 },
    { ISD::FP_TO_UINT,  MVT::v32i8,  MVT::v4f64,  2 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v8f32,  2 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v4f64,  2 },
    { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v8f32,  2 },
    { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v4f64,  2 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  3 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  4 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  6 },
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  7 },
    { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v4f64,  7 },
 
    { ISD::FP_EXTEND,   MVT::v4f64,  MVT::v4f32,  1 },
    { ISD::FP_ROUND,    MVT::v4f32,  MVT::v4f64,  1 },
  };
 
  static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
    { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8,   1 },
    { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8,   1 },
    { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8,   1 },
    { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8,   1 },
    { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8,   1 },
    { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16,   1 },
    { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16,   1 },
    { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16,   1 },
    { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16,   1 },
    { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32,   1 },
    { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32,   1 },
 
    // These truncates end up widening elements.
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   1 }, // PMOVXZBQ
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  1 }, // PMOVXZWQ
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   1 }, // PMOVXZBD
 
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i32,  2 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i32,  2 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v2i64,  2 },
 
    { ISD::SINT_TO_FP,  MVT::f32,    MVT::i32,    1 },
    { ISD::SINT_TO_FP,  MVT::f64,    MVT::i32,    1 },
    { ISD::SINT_TO_FP,  MVT::f32,    MVT::i64,    1 },
    { ISD::SINT_TO_FP,  MVT::f64,    MVT::i64,    1 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  1 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  1 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  1 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  1 },
    { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  2 },
 
    { ISD::UINT_TO_FP,  MVT::f32,    MVT::i32,    1 },
    { ISD::UINT_TO_FP,  MVT::f64,    MVT::i32,    1 },
    { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    4 },
    { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    4 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  3 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  3 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  2 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v2i64, 12 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64, 22 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  4 },
 
    { ISD::FP_TO_SINT,  MVT::i32,    MVT::f32,    1 },
    { ISD::FP_TO_SINT,  MVT::i64,    MVT::f32,    1 },
    { ISD::FP_TO_SINT,  MVT::i32,    MVT::f64,    1 },
    { ISD::FP_TO_SINT,  MVT::i64,    MVT::f64,    1 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v4f32,  2 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v2f64,  2 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v4f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v2f64,  1 },
    { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f32,  1 },
    { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v2f64,  1 },
 
    { ISD::FP_TO_UINT,  MVT::i32,    MVT::f32,    1 },
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    4 },
    { ISD::FP_TO_UINT,  MVT::i32,    MVT::f64,    1 },
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    4 },
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v4f32,  2 },
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v2f64,  2 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v4f32,  1 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v2f64,  1 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  4 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  4 },
  };
 
  static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
    // These are somewhat magic numbers justified by comparing the
    // output of llvm-mca for our various supported scheduler models
    // and basing it off the worst case scenario.
    { ISD::SINT_TO_FP,  MVT::f32,    MVT::i32,    3 },
    { ISD::SINT_TO_FP,  MVT::f64,    MVT::i32,    3 },
    { ISD::SINT_TO_FP,  MVT::f32,    MVT::i64,    3 },
    { ISD::SINT_TO_FP,  MVT::f64,    MVT::i64,    3 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  3 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  4 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  3 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  4 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  3 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  4 },
    { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v2i64,  8 },
    { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  8 },
 
    { ISD::UINT_TO_FP,  MVT::f32,    MVT::i32,    3 },
    { ISD::UINT_TO_FP,  MVT::f64,    MVT::i32,    3 },
    { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    8 },
    { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    9 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  4 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  4 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  4 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  4 },
    { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  7 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  7 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  5 },
    { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64, 15 },
    { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v2i64, 18 },
 
    { ISD::FP_TO_SINT,  MVT::i32,    MVT::f32,    4 },
    { ISD::FP_TO_SINT,  MVT::i64,    MVT::f32,    4 },
    { ISD::FP_TO_SINT,  MVT::i32,    MVT::f64,    4 },
    { ISD::FP_TO_SINT,  MVT::i64,    MVT::f64,    4 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v4f32,  6 },
    { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v2f64,  6 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v4f32,  5 },
    { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v2f64,  5 },
    { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f32,  4 },
    { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v2f64,  4 },
 
    { ISD::FP_TO_UINT,  MVT::i32,    MVT::f32,    4 },
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    4 },
    { ISD::FP_TO_UINT,  MVT::i32,    MVT::f64,    4 },
    { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,   15 },
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v4f32,  6 },
    { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v2f64,  6 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v4f32,  5 },
    { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v2f64,  5 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  8 },
    { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  8 },
 
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v16i8,  4 },
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v16i8,  4 },
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v16i8,  2 },
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v16i8,  3 },
    { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v16i8,  1 },
    { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v16i8,  2 },
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v8i16,  2 },
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v8i16,  3 },
    { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v8i16,  1 },
    { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v8i16,  2 },
    { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v4i32,  1 },
    { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v4i32,  2 },
 
    // These truncates are really widening elements.
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i32,  1 }, // PSHUFD
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // PUNPCKLWD+DQ
    { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   3 }, // PUNPCKLBW+WD+PSHUFD
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  1 }, // PUNPCKLWD
    { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // PUNPCKLBW+WD
    { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   1 }, // PUNPCKLBW
 
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i16,  2 }, // PAND+PACKUSWB
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 3 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i32,  3 }, // PAND+2*PACKUSWB
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i32, 7 },
    { ISD::TRUNCATE,    MVT::v2i16,  MVT::v2i32,  1 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i32,  3 },
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  5 },
    { ISD::TRUNCATE,    MVT::v16i16, MVT::v16i32,10 },
    { ISD::TRUNCATE,    MVT::v16i8,  MVT::v2i64,  4 }, // PAND+3*PACKUSWB
    { ISD::TRUNCATE,    MVT::v8i16,  MVT::v2i64,  2 }, // PSHUFD+PSHUFLW
    { ISD::TRUNCATE,    MVT::v4i32,  MVT::v2i64,  1 }, // PSHUFD
  };
 
  // Attempt to map directly to (simple) MVT types to let us match custom entries.
  EVT SrcTy = TLI->getValueType(DL, Src);
  EVT DstTy = TLI->getValueType(DL, Dst);
 
  // The function getSimpleVT only handles simple value types.
  if (SrcTy.isSimple() && DstTy.isSimple()) {
    MVT SimpleSrcTy = SrcTy.getSimpleVT();
    MVT SimpleDstTy = DstTy.getSimpleVT();
 
    if (ST->useAVX512Regs()) {
      if (ST->hasBWI())
        if (const auto *Entry = ConvertCostTableLookup(
                AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
          return AdjustCost(Entry->Cost);
 
      if (ST->hasDQI())
        if (const auto *Entry = ConvertCostTableLookup(
                AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
          return AdjustCost(Entry->Cost);
 
      if (ST->hasAVX512())
        if (const auto *Entry = ConvertCostTableLookup(
                AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
          return AdjustCost(Entry->Cost);
    }
 
    if (ST->hasBWI())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
 
    if (ST->hasDQI())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
 
    if (ST->hasAVX512())
      if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
                                                     SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
 
    if (ST->hasAVX2()) {
      if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
                                                     SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
    }
 
    if (ST->hasAVX()) {
      if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
                                                     SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
    }
 
    if (ST->hasSSE41()) {
      if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
                                                     SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
    }
 
    if (ST->hasSSE2()) {
      if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
                                                     SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
    }
  }
 
  // Fall back to legalized types.
  std::pair<InstructionCost, MVT> LTSrc = getTypeLegalizationCost(Src);
  std::pair<InstructionCost, MVT> LTDest = getTypeLegalizationCost(Dst);
 
  // If we're truncating to the same legalized type - just assume its free.
  if (ISD == ISD::TRUNCATE && LTSrc.second == LTDest.second)
    return TTI::TCC_Free;
 
  if (ST->useAVX512Regs()) {
    if (ST->hasBWI())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second))
        return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
    if (ST->hasDQI())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second))
        return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
    if (ST->hasAVX512())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second))
        return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
  }
 
  if (ST->hasBWI())
    if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  if (ST->hasDQI())
    if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  if (ST->hasAVX512())
    if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  if (ST->hasAVX2())
    if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  if (ST->hasAVX())
    if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  if (ST->hasSSE41())
    if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  if (ST->hasSSE2())
    if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
                                                   LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
 
  // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for
  // sitofp.
  if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) &&
      1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) {
    Type *ExtSrc = Src->getWithNewBitWidth(32);
    unsigned ExtOpc =
        (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt;
 
    // For scalar loads the extend would be free.
    InstructionCost ExtCost = 0;
    if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0))))
      ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind);
 
    return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc,
                                      TTI::CastContextHint::None, CostKind);
  }
 
  // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi
  // i32.
  if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) &&
      1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) {
    Type *TruncDst = Dst->getWithNewBitWidth(32);
    return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) +
           getCastInstrCost(Instruction::Trunc, Dst, TruncDst,
                            TTI::CastContextHint::None, CostKind);
  }
 
  return AdjustCost(
      BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
}
 
InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
                                               Type *CondTy,
                                               CmpInst::Predicate VecPred,
                                               TTI::TargetCostKind CostKind,
                                               const Instruction *I) {
  // Early out if this type isn't scalar/vector integer/float.
  if (!(ValTy->isIntOrIntVectorTy() || ValTy->isFPOrFPVectorTy()))
    return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind,
                                     I);
 
  // Legalize the type.
  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
 
  MVT MTy = LT.second;
 
  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Invalid opcode");
 
  InstructionCost ExtraCost = 0;
  if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) {
    // Some vector comparison predicates cost extra instructions.
    // TODO: Should we invert this and assume worst case cmp costs
    // and reduce for particular predicates?
    if (MTy.isVector() &&
        !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) ||
          (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) ||
          ST->hasBWI())) {
      // Fallback to I if a specific predicate wasn't specified.
      CmpInst::Predicate Pred = VecPred;
      if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE ||
                Pred == CmpInst::BAD_FCMP_PREDICATE))
        Pred = cast<CmpInst>(I)->getPredicate();
 
      switch (Pred) {
      case CmpInst::Predicate::ICMP_NE:
        // xor(cmpeq(x,y),-1)
        ExtraCost = 1;
        break;
      case CmpInst::Predicate::ICMP_SGE:
      case CmpInst::Predicate::ICMP_SLE:
        // xor(cmpgt(x,y),-1)
        ExtraCost = 1;
        break;
      case CmpInst::Predicate::ICMP_ULT:
      case CmpInst::Predicate::ICMP_UGT:
        // cmpgt(xor(x,signbit),xor(y,signbit))
        // xor(cmpeq(pmaxu(x,y),x),-1)
        ExtraCost = 2;
        break;
      case CmpInst::Predicate::ICMP_ULE:
      case CmpInst::Predicate::ICMP_UGE:
        if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) ||
            (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) {
          // cmpeq(psubus(x,y),0)
          // cmpeq(pminu(x,y),x)
          ExtraCost = 1;
        } else {
          // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1)
          ExtraCost = 3;
        }
        break;
      case CmpInst::Predicate::FCMP_ONE:
      case CmpInst::Predicate::FCMP_UEQ:
        // Without AVX we need to expand FCMP_ONE/FCMP_UEQ cases.
        // Use FCMP_UEQ expansion - FCMP_ONE should be the same.
        if (CondTy && !ST->hasAVX())
          return getCmpSelInstrCost(Opcode, ValTy, CondTy,
                                    CmpInst::Predicate::FCMP_UNO, CostKind) +
                 getCmpSelInstrCost(Opcode, ValTy, CondTy,
                                    CmpInst::Predicate::FCMP_OEQ, CostKind) +
                 getArithmeticInstrCost(Instruction::Or, CondTy, CostKind);
 
        break;
      case CmpInst::Predicate::BAD_ICMP_PREDICATE:
      case CmpInst::Predicate::BAD_FCMP_PREDICATE:
        // Assume worst case scenario and add the maximum extra cost.
        ExtraCost = 3;
        break;
      default:
        break;
      }
    }
  }
 
  static const CostKindTblEntry SLMCostTbl[] = {
    // slm pcmpeq/pcmpgt throughput is 2
    { ISD::SETCC,   MVT::v2i64,   { 2, 5, 1, 2 } },
    // slm pblendvb/blendvpd/blendvps throughput is 4
    { ISD::SELECT,  MVT::v2f64,   { 4, 4, 1, 3 } }, // vblendvpd
    { ISD::SELECT,  MVT::v4f32,   { 4, 4, 1, 3 } }, // vblendvps
    { ISD::SELECT,  MVT::v2i64,   { 4, 4, 1, 3 } }, // pblendvb
    { ISD::SELECT,  MVT::v8i32,   { 4, 4, 1, 3 } }, // pblendvb
    { ISD::SELECT,  MVT::v8i16,   { 4, 4, 1, 3 } }, // pblendvb
    { ISD::SELECT,  MVT::v16i8,   { 4, 4, 1, 3 } }, // pblendvb
  };
 
  static const CostKindTblEntry AVX512BWCostTbl[] = {
    { ISD::SETCC,   MVT::v32i16,  { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v16i16,  { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v64i8,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v32i8,   { 1, 1, 1, 1 } },
 
    { ISD::SELECT,  MVT::v32i16,  { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v64i8,   { 1, 1, 1, 1 } },
  };
 
  static const CostKindTblEntry AVX512CostTbl[] = {
    { ISD::SETCC,   MVT::v8f64,   { 1, 4, 1, 1 } },
    { ISD::SETCC,   MVT::v4f64,   { 1, 4, 1, 1 } },
    { ISD::SETCC,   MVT::v16f32,  { 1, 4, 1, 1 } },
    { ISD::SETCC,   MVT::v8f32,   { 1, 4, 1, 1 } },
 
    { ISD::SETCC,   MVT::v8i64,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v4i64,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v2i64,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v16i32,  { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v8i32,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v32i16,  { 3, 7, 5, 5 } },
    { ISD::SETCC,   MVT::v64i8,   { 3, 7, 5, 5 } },
 
    { ISD::SELECT,  MVT::v8i64,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v4i64,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v2i64,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v16i32,  { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v8i32,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v4i32,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v8f64,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v4f64,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v2f64,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::f64,     { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v16f32,  { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v8f32 ,  { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v4f32,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::f32  ,   { 1, 1, 1, 1 } },
 
    { ISD::SELECT,  MVT::v32i16,  { 2, 2, 4, 4 } },
    { ISD::SELECT,  MVT::v16i16,  { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v8i16,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v64i8,   { 2, 2, 4, 4 } },
    { ISD::SELECT,  MVT::v32i8,   { 1, 1, 1, 1 } },
    { ISD::SELECT,  MVT::v16i8,   { 1, 1, 1, 1 } },
  };
 
  static const CostKindTblEntry AVX2CostTbl[] = {
    { ISD::SETCC,   MVT::v4f64,   { 1, 4, 1, 2 } },
    { ISD::SETCC,   MVT::v2f64,   { 1, 4, 1, 1 } },
    { ISD::SETCC,   MVT::f64,     { 1, 4, 1, 1 } },
    { ISD::SETCC,   MVT::v8f32,   { 1, 4, 1, 2 } },
    { ISD::SETCC,   MVT::v4f32,   { 1, 4, 1, 1 } },
    { ISD::SETCC,   MVT::f32,     { 1, 4, 1, 1 } },
 
    { ISD::SETCC,   MVT::v4i64,   { 1, 1, 1, 2 } },
    { ISD::SETCC,   MVT::v8i32,   { 1, 1, 1, 2 } },
    { ISD::SETCC,   MVT::v16i16,  { 1, 1, 1, 2 } },
    { ISD::SETCC,   MVT::v32i8,   { 1, 1, 1, 2 } },
 
    { ISD::SELECT,  MVT::v4f64,   { 2, 2, 1, 2 } }, // vblendvpd
    { ISD::SELECT,  MVT::v8f32,   { 2, 2, 1, 2 } }, // vblendvps
    { ISD::SELECT,  MVT::v4i64,   { 2, 2, 1, 2 } }, // pblendvb
    { ISD::SELECT,  MVT::v8i32,   { 2, 2, 1, 2 } }, // pblendvb
    { ISD::SELECT,  MVT::v16i16,  { 2, 2, 1, 2 } }, // pblendvb
    { ISD::SELECT,  MVT::v32i8,   { 2, 2, 1, 2 } }, // pblendvb
  };
 
  static const CostKindTblEntry XOPCostTbl[] = {
    { ISD::SETCC,   MVT::v4i64,   { 4, 2, 5, 6 } },
    { ISD::SETCC,   MVT::v2i64,   { 1, 1, 1, 1 } },
  };
 
  static const CostKindTblEntry AVX1CostTbl[] = {
    { ISD::SETCC,   MVT::v4f64,   { 2, 3, 1, 2 } },
    { ISD::SETCC,   MVT::v2f64,   { 1, 3, 1, 1 } },
    { ISD::SETCC,   MVT::f64,     { 1, 3, 1, 1 } },
    { ISD::SETCC,   MVT::v8f32,   { 2, 3, 1, 2 } },
    { ISD::SETCC,   MVT::v4f32,   { 1, 3, 1, 1 } },
    { ISD::SETCC,   MVT::f32,     { 1, 3, 1, 1 } },
 
    // AVX1 does not support 8-wide integer compare.
    { ISD::SETCC,   MVT::v4i64,   { 4, 2, 5, 6 } },
    { ISD::SETCC,   MVT::v8i32,   { 4, 2, 5, 6 } },
    { ISD::SETCC,   MVT::v16i16,  { 4, 2, 5, 6 } },
    { ISD::SETCC,   MVT::v32i8,   { 4, 2, 5, 6 } },
 
    { ISD::SELECT,  MVT::v4f64,   { 3, 3, 1, 2 } }, // vblendvpd
    { ISD::SELECT,  MVT::v8f32,   { 3, 3, 1, 2 } }, // vblendvps
    { ISD::SELECT,  MVT::v4i64,   { 3, 3, 1, 2 } }, // vblendvpd
    { ISD::SELECT,  MVT::v8i32,   { 3, 3, 1, 2 } }, // vblendvps
    { ISD::SELECT,  MVT::v16i16,  { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
    { ISD::SELECT,  MVT::v32i8,   { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
  };
 
  static const CostKindTblEntry SSE42CostTbl[] = {
    { ISD::SETCC,   MVT::v2i64,   { 1, 2, 1, 2 } },
  };
 
  static const CostKindTblEntry SSE41CostTbl[] = {
    { ISD::SETCC,   MVT::v2f64,   { 1, 5, 1, 1 } },
    { ISD::SETCC,   MVT::v4f32,   { 1, 5, 1, 1 } },
 
    { ISD::SELECT,  MVT::v2f64,   { 2, 2, 1, 2 } }, // blendvpd
    { ISD::SELECT,  MVT::f64,     { 2, 2, 1, 2 } }, // blendvpd
    { ISD::SELECT,  MVT::v4f32,   { 2, 2, 1, 2 } }, // blendvps
    { ISD::SELECT,  MVT::f32  ,   { 2, 2, 1, 2 } }, // blendvps
    { ISD::SELECT,  MVT::v2i64,   { 2, 2, 1, 2 } }, // pblendvb
    { ISD::SELECT,  MVT::v4i32,   { 2, 2, 1, 2 } }, // pblendvb
    { ISD::SELECT,  MVT::v8i16,   { 2, 2, 1, 2 } }, // pblendvb
    { ISD::SELECT,  MVT::v16i8,   { 2, 2, 1, 2 } }, // pblendvb
  };
 
  static const CostKindTblEntry SSE2CostTbl[] = {
    { ISD::SETCC,   MVT::v2f64,   { 2, 5, 1, 1 } },
    { ISD::SETCC,   MVT::f64,     { 1, 5, 1, 1 } },
 
    { ISD::SETCC,   MVT::v2i64,   { 5, 4, 5, 5 } }, // pcmpeqd/pcmpgtd expansion
    { ISD::SETCC,   MVT::v4i32,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v8i16,   { 1, 1, 1, 1 } },
    { ISD::SETCC,   MVT::v16i8,   { 1, 1, 1, 1 } },
 
    { ISD::SELECT,  MVT::v2f64,   { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
    { ISD::SELECT,  MVT::f64,     { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
    { ISD::SELECT,  MVT::v2i64,   { 2, 2, 3, 3 } }, // pand + pandn + por
    { ISD::SELECT,  MVT::v4i32,   { 2, 2, 3, 3 } }, // pand + pandn + por
    { ISD::SELECT,  MVT::v8i16,   { 2, 2, 3, 3 } }, // pand + pandn + por
    { ISD::SELECT,  MVT::v16i8,   { 2, 2, 3, 3 } }, // pand + pandn + por
  };
 
  static const CostKindTblEntry SSE1CostTbl[] = {
    { ISD::SETCC,   MVT::v4f32,   { 2, 5, 1, 1 } },
    { ISD::SETCC,   MVT::f32,     { 1, 5, 1, 1 } },
 
    { ISD::SELECT,  MVT::v4f32,   { 2, 2, 3, 3 } }, // andps + andnps + orps
    { ISD::SELECT,  MVT::f32,     { 2, 2, 3, 3 } }, // andps + andnps + orps
  };
 
  if (ST->useSLMArithCosts())
    if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasBWI())
    if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasAVX512())
    if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasAVX2())
    if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasXOP())
    if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasSSE42())
    if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasSSE41())
    if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  if (ST->hasSSE1())
    if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
      if (auto KindCost = Entry->Cost[CostKind])
        return LT.first * (ExtraCost + *KindCost);
 
  // Assume a 3cy latency for fp select ops.
  if (CostKind == TTI::TCK_Latency && Opcode == Instruction::Select)
    if (ValTy->getScalarType()->isFloatingPointTy())
      return 3;
 
  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
}
 
unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
 
InstructionCost
X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                  TTI::TargetCostKind CostKind) {
  // Costs should match the codegen from:
  // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
  // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
  // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
  // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
  // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
 
  // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not
  //       specialized in these tables yet.
  static const CostKindTblEntry AVX512VBMI2CostTbl[] = {
    { ISD::FSHL,       MVT::v8i64,   {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v4i64,   {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v2i64,   {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v8i32,   {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v16i16,  {  1,  1,  1,  1 } },
    { ISD::FSHL,       MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v16i16,  {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v16i16,  {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v8i16,   {  1,  1,  1,  1 } },
  };
  static const CostKindTblEntry AVX512BITALGCostTbl[] = {
    { ISD::CTPOP,      MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v64i8,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v16i16,  {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v32i8,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v16i8,   {  1,  1,  1,  1 } },
  };
  static const CostKindTblEntry AVX512VPOPCNTDQCostTbl[] = {
    { ISD::CTPOP,      MVT::v8i64,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v4i64,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v8i32,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v2i64,   {  1,  1,  1,  1 } },
    { ISD::CTPOP,      MVT::v4i32,   {  1,  1,  1,  1 } },
  };
  static const CostKindTblEntry AVX512CDCostTbl[] = {
    { ISD::CTLZ,       MVT::v8i64,   {  1,  5,  1,  1 } },
    { ISD::CTLZ,       MVT::v16i32,  {  1,  5,  1,  1 } },
    { ISD::CTLZ,       MVT::v32i16,  { 18, 27, 23, 27 } },
    { ISD::CTLZ,       MVT::v64i8,   {  3, 16,  9, 11 } },
    { ISD::CTLZ,       MVT::v4i64,   {  1,  5,  1,  1 } },
    { ISD::CTLZ,       MVT::v8i32,   {  1,  5,  1,  1 } },
    { ISD::CTLZ,       MVT::v16i16,  {  8, 19, 11, 13 } },
    { ISD::CTLZ,       MVT::v32i8,   {  2, 11,  9, 10 } },
    { ISD::CTLZ,       MVT::v2i64,   {  1,  5,  1,  1 } },
    { ISD::CTLZ,       MVT::v4i32,   {  1,  5,  1,  1 } },
    { ISD::CTLZ,       MVT::v8i16,   {  3, 15,  4,  6 } },
    { ISD::CTLZ,       MVT::v16i8,   {  2, 10,  9, 10 } },
 
    { ISD::CTTZ,       MVT::v8i64,   {  2,  8,  6,  7 } },
    { ISD::CTTZ,       MVT::v16i32,  {  2,  8,  6,  7 } },
    { ISD::CTTZ,       MVT::v4i64,   {  1,  8,  6,  6 } },
    { ISD::CTTZ,       MVT::v8i32,   {  1,  8,  6,  6 } },
    { ISD::CTTZ,       MVT::v2i64,   {  1,  8,  6,  6 } },
    { ISD::CTTZ,       MVT::v4i32,   {  1,  8,  6,  6 } },
  };
  static const CostKindTblEntry AVX512BWCostTbl[] = {
    { ISD::ABS,        MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v64i8,   {  1,  1,  1,  1 } },
    { ISD::BITREVERSE, MVT::v2i64,   {  3, 10, 10, 11 } },
    { ISD::BITREVERSE, MVT::v4i64,   {  3, 11, 10, 11 } },
    { ISD::BITREVERSE, MVT::v8i64,   {  3, 12, 10, 14 } },
    { ISD::BITREVERSE, MVT::v4i32,   {  3, 10, 10, 11 } },
    { ISD::BITREVERSE, MVT::v8i32,   {  3, 11, 10, 11 } },
    { ISD::BITREVERSE, MVT::v16i32,  {  3, 12, 10, 14 } },
    { ISD::BITREVERSE, MVT::v8i16,   {  3, 10, 10, 11 } },
    { ISD::BITREVERSE, MVT::v16i16,  {  3, 11, 10, 11 } },
    { ISD::BITREVERSE, MVT::v32i16,  {  3, 12, 10, 14 } },
    { ISD::BITREVERSE, MVT::v16i8,   {  2,  5,  9,  9 } },
    { ISD::BITREVERSE, MVT::v32i8,   {  2,  5,  9,  9 } },
    { ISD::BITREVERSE, MVT::v64i8,   {  2,  5,  9, 12 } },
    { ISD::BSWAP,      MVT::v2i64,   {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v4i64,   {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v8i64,   {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v4i32,   {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v8i32,   {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v16i32,  {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v8i16,   {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v16i16,  {  1,  1,  1,  2 } },
    { ISD::BSWAP,      MVT::v32i16,  {  1,  1,  1,  2 } },
    { ISD::CTLZ,       MVT::v8i64,   {  8, 22, 23, 23 } },
    { ISD::CTLZ,       MVT::v16i32,  {  8, 23, 25, 25 } },
    { ISD::CTLZ,       MVT::v32i16,  {  4, 15, 15, 16 } },
    { ISD::CTLZ,       MVT::v64i8,   {  3, 12, 10,  9 } },
    { ISD::CTPOP,      MVT::v2i64,   {  3,  7, 10, 10 } },
    { ISD::CTPOP,      MVT::v4i64,   {  3,  7, 10, 10 } },
    { ISD::CTPOP,      MVT::v8i64,   {  3,  8, 10, 12 } },
    { ISD::CTPOP,      MVT::v4i32,   {  7, 11, 14, 14 } },
    { ISD::CTPOP,      MVT::v8i32,   {  7, 11, 14, 14 } },
    { ISD::CTPOP,      MVT::v16i32,  {  7, 12, 14, 16 } },
    { ISD::CTPOP,      MVT::v8i16,   {  2,  7, 11, 11 } },
    { ISD::CTPOP,      MVT::v16i16,  {  2,  7, 11, 11 } },
    { ISD::CTPOP,      MVT::v32i16,  {  3,  7, 11, 13 } },
    { ISD::CTPOP,      MVT::v16i8,   {  2,  4,  8,  8 } },
    { ISD::CTPOP,      MVT::v32i8,   {  2,  4,  8,  8 } },
    { ISD::CTPOP,      MVT::v64i8,   {  2,  5,  8, 10 } },
    { ISD::CTTZ,       MVT::v8i16,   {  3,  9, 14, 14 } },
    { ISD::CTTZ,       MVT::v16i16,  {  3,  9, 14, 14 } },
    { ISD::CTTZ,       MVT::v32i16,  {  3, 10, 14, 16 } },
    { ISD::CTTZ,       MVT::v16i8,   {  2,  6, 11, 11 } },
    { ISD::CTTZ,       MVT::v32i8,   {  2,  6, 11, 11 } },
    { ISD::CTTZ,       MVT::v64i8,   {  3,  7, 11, 13 } },
    { ISD::ROTL,       MVT::v32i16,  {  2,  8,  6,  8 } },
    { ISD::ROTL,       MVT::v16i16,  {  2,  8,  6,  7 } },
    { ISD::ROTL,       MVT::v8i16,   {  2,  7,  6,  7 } },
    { ISD::ROTL,       MVT::v64i8,   {  5,  6, 11, 12 } },
    { ISD::ROTL,       MVT::v32i8,   {  5, 15,  7, 10 } },
    { ISD::ROTL,       MVT::v16i8,   {  5, 15,  7, 10 } },
    { ISD::ROTR,       MVT::v32i16,  {  2,  8,  6,  8 } },
    { ISD::ROTR,       MVT::v16i16,  {  2,  8,  6,  7 } },
    { ISD::ROTR,       MVT::v8i16,   {  2,  7,  6,  7 } },
    { ISD::ROTR,       MVT::v64i8,   {  5,  6, 12, 14 } },
    { ISD::ROTR,       MVT::v32i8,   {  5, 14,  6,  9 } },
    { ISD::ROTR,       MVT::v16i8,   {  5, 14,  6,  9 } },
    { ISD::SADDSAT,    MVT::v32i16,  {  1 } },
    { ISD::SADDSAT,    MVT::v64i8,   {  1 } },
    { ISD::SMAX,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::SMAX,       MVT::v64i8,   {  1,  1,  1,  1 } },
    { ISD::SMIN,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::SMIN,       MVT::v64i8,   {  1,  1,  1,  1 } },
    { ISD::SSUBSAT,    MVT::v32i16,  {  1 } },
    { ISD::SSUBSAT,    MVT::v64i8,   {  1 } },
    { ISD::UADDSAT,    MVT::v32i16,  {  1 } },
    { ISD::UADDSAT,    MVT::v64i8,   {  1 } },
    { ISD::UMAX,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::UMAX,       MVT::v64i8,   {  1,  1,  1,  1 } },
    { ISD::UMIN,       MVT::v32i16,  {  1,  1,  1,  1 } },
    { ISD::UMIN,       MVT::v64i8,   {  1,  1,  1,  1 } },
    { ISD::USUBSAT,    MVT::v32i16,  {  1 } },
    { ISD::USUBSAT,    MVT::v64i8,   {  1 } },
  };
  static const CostKindTblEntry AVX512CostTbl[] = {
    { ISD::ABS,        MVT::v8i64,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v4i64,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v2i64,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v8i32,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v32i16,  {  2,  7,  4,  4 } },
    { ISD::ABS,        MVT::v16i16,  {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v64i8,   {  2,  7,  4,  4 } },
    { ISD::ABS,        MVT::v32i8,   {  1,  1,  1,  1 } },
    { ISD::BITREVERSE, MVT::v8i64,   {  9, 13, 20, 20 } },
    { ISD::BITREVERSE, MVT::v16i32,  {  9, 13, 20, 20 } },
    { ISD::BITREVERSE, MVT::v32i16,  {  9, 13, 20, 20 } },
    { ISD::BITREVERSE, MVT::v64i8,   {  6, 11, 17, 17 } },
    { ISD::BSWAP,      MVT::v8i64,   {  4,  7,  5,  5 } },
    { ISD::BSWAP,      MVT::v16i32,  {  4,  7,  5,  5 } },
    { ISD::BSWAP,      MVT::v32i16,  {  4,  7,  5,  5 } },
    { ISD::CTLZ,       MVT::v8i64,   { 10, 28, 32, 32 } },
    { ISD::CTLZ,       MVT::v16i32,  { 12, 30, 38, 38 } },
    { ISD::CTLZ,       MVT::v32i16,  {  8, 15, 29, 29 } },
    { ISD::CTLZ,       MVT::v64i8,   {  6, 11, 19, 19 } },
    { ISD::CTPOP,      MVT::v8i64,   { 16, 16, 19, 19 } },
    { ISD::CTPOP,      MVT::v16i32,  { 24, 19, 27, 27 } },
    { ISD::CTPOP,      MVT::v32i16,  { 18, 15, 22, 22 } },
    { ISD::CTPOP,      MVT::v64i8,   { 12, 11, 16, 16 } },
    { ISD::CTTZ,       MVT::v8i64,   {  2,  8,  6,  7 } },
    { ISD::CTTZ,       MVT::v16i32,  {  2,  8,  6,  7 } },
    { ISD::CTTZ,       MVT::v32i16,  {  7, 17, 27, 27 } },
    { ISD::CTTZ,       MVT::v64i8,   {  6, 13, 21, 21 } },
    { ISD::ROTL,       MVT::v8i64,   {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v4i64,   {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v2i64,   {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v8i32,   {  1,  1,  1,  1 } },
    { ISD::ROTL,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v8i64,   {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v4i64,   {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v2i64,   {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v8i32,   {  1,  1,  1,  1 } },
    { ISD::ROTR,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::SMAX,       MVT::v8i64,   {  1,  3,  1,  1 } },
    { ISD::SMAX,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::SMAX,       MVT::v32i16,  {  3,  7,  5,  5 } },
    { ISD::SMAX,       MVT::v64i8,   {  3,  7,  5,  5 } },
    { ISD::SMAX,       MVT::v4i64,   {  1,  3,  1,  1 } },
    { ISD::SMAX,       MVT::v2i64,   {  1,  3,  1,  1 } },
    { ISD::SMIN,       MVT::v8i64,   {  1,  3,  1,  1 } },
    { ISD::SMIN,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::SMIN,       MVT::v32i16,  {  3,  7,  5,  5 } },
    { ISD::SMIN,       MVT::v64i8,   {  3,  7,  5,  5 } },
    { ISD::SMIN,       MVT::v4i64,   {  1,  3,  1,  1 } },
    { ISD::SMIN,       MVT::v2i64,   {  1,  3,  1,  1 } },
    { ISD::UMAX,       MVT::v8i64,   {  1,  3,  1,  1 } },
    { ISD::UMAX,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::UMAX,       MVT::v32i16,  {  3,  7,  5,  5 } },
    { ISD::UMAX,       MVT::v64i8,   {  3,  7,  5,  5 } },
    { ISD::UMAX,       MVT::v4i64,   {  1,  3,  1,  1 } },
    { ISD::UMAX,       MVT::v2i64,   {  1,  3,  1,  1 } },
    { ISD::UMIN,       MVT::v8i64,   {  1,  3,  1,  1 } },
    { ISD::UMIN,       MVT::v16i32,  {  1,  1,  1,  1 } },
    { ISD::UMIN,       MVT::v32i16,  {  3,  7,  5,  5 } },
    { ISD::UMIN,       MVT::v64i8,   {  3,  7,  5,  5 } },
    { ISD::UMIN,       MVT::v4i64,   {  1,  3,  1,  1 } },
    { ISD::UMIN,       MVT::v2i64,   {  1,  3,  1,  1 } },
    { ISD::USUBSAT,    MVT::v16i32,  {  2 } }, // pmaxud + psubd
    { ISD::USUBSAT,    MVT::v2i64,   {  2 } }, // pmaxuq + psubq
    { ISD::USUBSAT,    MVT::v4i64,   {  2 } }, // pmaxuq + psubq
    { ISD::USUBSAT,    MVT::v8i64,   {  2 } }, // pmaxuq + psubq
    { ISD::UADDSAT,    MVT::v16i32,  {  3 } }, // not + pminud + paddd
    { ISD::UADDSAT,    MVT::v2i64,   {  3 } }, // not + pminuq + paddq
    { ISD::UADDSAT,    MVT::v4i64,   {  3 } }, // not + pminuq + paddq
    { ISD::UADDSAT,    MVT::v8i64,   {  3 } }, // not + pminuq + paddq
    { ISD::SADDSAT,    MVT::v32i16,  {  2 } },
    { ISD::SADDSAT,    MVT::v64i8,   {  2 } },
    { ISD::SSUBSAT,    MVT::v32i16,  {  2 } },
    { ISD::SSUBSAT,    MVT::v64i8,   {  2 } },
    { ISD::UADDSAT,    MVT::v32i16,  {  2 } },
    { ISD::UADDSAT,    MVT::v64i8,   {  2 } },
    { ISD::USUBSAT,    MVT::v32i16,  {  2 } },
    { ISD::USUBSAT,    MVT::v64i8,   {  2 } },
    { ISD::FMAXNUM,    MVT::f32,     {  2,  2,  3,  3 } },
    { ISD::FMAXNUM,    MVT::v4f32,   {  1,  1,  3,  3 } },
    { ISD::FMAXNUM,    MVT::v8f32,   {  2,  2,  3,  3 } },
    { ISD::FMAXNUM,    MVT::v16f32,  {  4,  4,  3,  3 } },
    { ISD::FMAXNUM,    MVT::f64,     {  2,  2,  3,  3 } },
    { ISD::FMAXNUM,    MVT::v2f64,   {  1,  1,  3,  3 } },
    { ISD::FMAXNUM,    MVT::v4f64,   {  2,  2,  3,  3 } },
    { ISD::FMAXNUM,    MVT::v8f64,   {  3,  3,  3,  3 } },
    { ISD::FSQRT,      MVT::f32,     {  3, 12,  1,  1 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::v4f32,   {  3, 12,  1,  1 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::v8f32,   {  6, 12,  1,  1 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::v16f32,  { 12, 20,  1,  3 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::f64,     {  6, 18,  1,  1 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::v2f64,   {  6, 18,  1,  1 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::v4f64,   { 12, 18,  1,  1 } }, // Skylake from http://www.agner.org/
    { ISD::FSQRT,      MVT::v8f64,   { 24, 32,  1,  3 } }, // Skylake from http://www.agner.org/
  };
  static const CostKindTblEntry XOPCostTbl[] = {
    { ISD::BITREVERSE, MVT::v4i64,   {  3,  6,  5,  6 } },
    { ISD::BITREVERSE, MVT::v8i32,   {  3,  6,  5,  6 } },
    { ISD::BITREVERSE, MVT::v16i16,  {  3,  6,  5,  6 } },
    { ISD::BITREVERSE, MVT::v32i8,   {  3,  6,  5,  6 } },
    { ISD::BITREVERSE, MVT::v2i64,   {  2,  7,  1,  1 } },
    { ISD::BITREVERSE, MVT::v4i32,   {  2,  7,  1,  1 } },
    { ISD::BITREVERSE, MVT::v8i16,   {  2,  7,  1,  1 } },
    { ISD::BITREVERSE, MVT::v16i8,   {  2,  7,  1,  1 } },
    { ISD::BITREVERSE, MVT::i64,     {  2,  2,  3,  4 } },
    { ISD::BITREVERSE, MVT::i32,     {  2,  2,  3,  4 } },
    { ISD::BITREVERSE, MVT::i16,     {  2,  2,  3,  4 } },
    { ISD::BITREVERSE, MVT::i8,      {  2,  2,  3,  4 } },
    // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
    { ISD::ROTL,       MVT::v4i64,   {  4,  7,  5,  6 } },
    { ISD::ROTL,       MVT::v8i32,   {  4,  7,  5,  6 } },
    { ISD::ROTL,       MVT::v16i16,  {  4,  7,  5,  6 } },
    { ISD::ROTL,       MVT::v32i8,   {  4,  7,  5,  6 } },
    { ISD::ROTL,       MVT::v2i64,   {  1,  3,  1,  1 } },
    { ISD::ROTL,       MVT::v4i32,   {  1,  3,  1,  1 } },
    { ISD::ROTL,       MVT::v8i16,   {  1,  3,  1,  1 } },
    { ISD::ROTL,       MVT::v16i8,   {  1,  3,  1,  1 } },
    { ISD::ROTR,       MVT::v4i64,   {  4,  7,  8,  9 } },
    { ISD::ROTR,       MVT::v8i32,   {  4,  7,  8,  9 } },
    { ISD::ROTR,       MVT::v16i16,  {  4,  7,  8,  9 } },
    { ISD::ROTR,       MVT::v32i8,   {  4,  7,  8,  9 } },
    { ISD::ROTR,       MVT::v2i64,   {  1,  3,  3,  3 } },
    { ISD::ROTR,       MVT::v4i32,   {  1,  3,  3,  3 } },
    { ISD::ROTR,       MVT::v8i16,   {  1,  3,  3,  3 } },
    { ISD::ROTR,       MVT::v16i8,   {  1,  3,  3,  3 } }
  };
  static const CostKindTblEntry AVX2CostTbl[] = {
    { ISD::ABS,        MVT::v2i64,   {  2,  4,  3,  5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
    { ISD::ABS,        MVT::v4i64,   {  2,  4,  3,  5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
    { ISD::ABS,        MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v8i32,   {  1,  1,  1,  2 } },
    { ISD::ABS,        MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v16i16,  {  1,  1,  1,  2 } },
    { ISD::ABS,        MVT::v16i8,   {  1,  1,  1,  1 } },
    { ISD::ABS,        MVT::v32i8,   {  1,  1,  1,  2 } },
    { ISD::BITREVERSE, MVT::v2i64,   {  3, 11, 10, 11 } },
    { ISD::BITREVERSE, MVT::v4i64,   {  5, 11, 10, 17 } },
    { ISD::BITREVERSE, MVT::v4i32,   {  3, 11, 10, 11 } },
    { ISD::BITREVERSE, MVT::v8i32,   {  5, 11, 10, 17 } },
    { ISD::BITREVERSE, MVT::v8i16,   {  3, 11, 10, 11 } },
    { ISD::BITREVERSE, MVT::v16i16,  {  5, 11, 10, 17 } },
    { ISD::BITREVERSE, MVT::v16i8,   {  3,  6,  9,  9 } },
    { ISD::BITREVERSE, MVT::v32i8,   {  4,  5,  9, 15 } },
    { ISD::BSWAP,      MVT::v2i64,   {  1,  2,  1,  2 } },
    { ISD::BSWAP,      MVT::v4i64,   {  1,  3,  1,  2 } },
    { ISD::BSWAP,      MVT::v4i32,   {  1,  2,  1,  2 } },
    { ISD::BSWAP,      MVT::v8i32,   {  1,  3,  1,  2 } },
    { ISD::BSWAP,      MVT::v8i16,   {  1,  2,  1,  2 } },
    { ISD::BSWAP,      MVT::v16i16,  {  1,  3,  1,  2 } },
    { ISD::CTLZ,       MVT::v2i64,   {  7, 18, 24, 25 } },
    { ISD::CTLZ,       MVT::v4i64,   { 14, 18, 24, 44 } },
    { ISD::CTLZ,       MVT::v4i32,   {  5, 16, 19, 20 } },
    { ISD::CTLZ,       MVT::v8i32,   { 10, 16, 19, 34 } },
    { ISD::CTLZ,       MVT::v8i16,   {  4, 13, 14, 15 } },
    { ISD::CTLZ,       MVT::v16i16,  {  6, 14, 14, 24 } },
    { ISD::CTLZ,       MVT::v16i8,   {  3, 12,  9, 10 } },
    { ISD::CTLZ,       MVT::v32i8,   {  4, 12,  9, 14 } },
    { ISD::CTPOP,      MVT::v2i64,   {  3,  9, 10, 10 } },
    { ISD::CTPOP,      MVT::v4i64,   {  4,  9, 10, 14 } },
    { ISD::CTPOP,      MVT::v4i32,   {  7, 12, 14, 14 } },
    { ISD::CTPOP,      MVT::v8i32,   {  7, 12, 14, 18 } },
    { ISD::CTPOP,      MVT::v8i16,   {  3,  7, 11, 11 } },
    { ISD::CTPOP,      MVT::v16i16,  {  6,  8, 11, 18 } },
    { ISD::CTPOP,      MVT::v16i8,   {  2,  5,  8,  8 } },
    { ISD::CTPOP,      MVT::v32i8,   {  3,  5,  8, 12 } },
    { ISD::CTTZ,       MVT::v2i64,   {  4, 11, 13, 13 } },
    { ISD::CTTZ,       MVT::v4i64,   {  5, 11, 13, 20 } },
    { ISD::CTTZ,       MVT::v4i32,   {  7, 14, 17, 17 } },
    { ISD::CTTZ,       MVT::v8i32,   {  7, 15, 17, 24 } },
    { ISD::CTTZ,       MVT::v8i16,   {  4,  9, 14, 14 } },
    { ISD::CTTZ,       MVT::v16i16,  {  6,  9, 14, 24 } },
    { ISD::CTTZ,       MVT::v16i8,   {  3,  7, 11, 11 } },
    { ISD::CTTZ,       MVT::v32i8,   {  5,  7, 11, 18 } },
    { ISD::SADDSAT,    MVT::v16i16,  {  1 } },
    { ISD::SADDSAT,    MVT::v32i8,   {  1 } },
    { ISD::SMAX,       MVT::v2i64,   {  2,  7,  2,  3 } },
    { ISD::SMAX,       MVT::v4i64,   {  2,  7,  2,  3 } },
    { ISD::SMAX,       MVT::v8i32,   {  1,  1,  1,  2 } },
    { ISD::SMAX,       MVT::v16i16,  {  1,  1,  1,  2 } },
    { ISD::SMAX,       MVT::v32i8,   {  1,  1,  1,  2 } },
    { ISD::SMIN,       MVT::v2i64,   {  2,  7,  2,  3 } },
    { ISD::SMIN,       MVT::v4i64,   {  2,  7,  2,  3 } },
    { ISD::SMIN,       MVT::v8i32,   {  1,  1,  1,  2 } },
    { ISD::SMIN,       MVT::v16i16,  {  1,  1,  1,  2 } },
    { ISD::SMIN,       MVT::v32i8,   {  1,  1,  1,  2 } },
    { ISD::SSUBSAT,    MVT::v16i16,  {  1 } },
    { ISD::SSUBSAT,    MVT::v32i8,   {  1 } },
    { ISD::UADDSAT,    MVT::v16i16,  {  1 } },
    { ISD::UADDSAT,    MVT::v32i8,   {  1 } },
    { ISD::UADDSAT,    MVT::v8i32,   {  3 } }, // not + pminud + paddd
    { ISD::UMAX,       MVT::v2i64,   {  2,  8,  5,  6 } },
    { ISD::UMAX,       MVT::v4i64,   {  2,  8,  5,  8 } },
    { ISD::UMAX,       MVT::v8i32,   {  1,  1,  1,  2 } },
    { ISD::UMAX,       MVT::v16i16,  {  1,  1,  1,  2 } },
    { ISD::UMAX,       MVT::v32i8,   {  1,  1,  1,  2 } },
    { ISD::UMIN,       MVT::v2i64,   {  2,  8,  5,  6 } },
    { ISD::UMIN,       MVT::v4i64,   {  2,  8,  5,  8 } },
    { ISD::UMIN,       MVT::v8i32,   {  1,  1,  1,  2 } },
    { ISD::UMIN,       MVT::v16i16,  {  1,  1,  1,  2 } },
    { ISD::UMIN,       MVT::v32i8,   {  1,  1,  1,  2 } },
    { ISD::USUBSAT,    MVT::v16i16,  {  1 } },
    { ISD::USUBSAT,    MVT::v32i8,   {  1 } },
    { ISD::USUBSAT,    MVT::v8i32,   {  2 } }, // pmaxud + psubd
    { ISD::FMAXNUM,    MVT::f32,     {  2,  7,  3,  5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
    { ISD::FMAXNUM,    MVT::v4f32,   {  2,  7,  3,  5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
    { ISD::FMAXNUM,    MVT::v8f32,   {  3,  7,  3,  6 } }, // MAXPS + CMPUNORDPS + BLENDVPS
    { ISD::FMAXNUM,    MVT::f64,     {  2,  7,  3,  5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
    { ISD::FMAXNUM,    MVT::v2f64,   {  2,  7,  3,  5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
    { ISD::FMAXNUM,    MVT::v4f64,   {  3,  7,  3,  6 } }, // MAXPD + CMPUNORDPD + BLENDVPD
    { ISD::FSQRT,      MVT::f32,     {  7, 15,  1,  1 } }, // vsqrtss
    { ISD::FSQRT,      MVT::v4f32,   {  7, 15,  1,  1 } }, // vsqrtps
    { ISD::FSQRT,      MVT::v8f32,   { 14, 21,  1,  3 } }, // vsqrtps
    { ISD::FSQRT,      MVT::f64,     { 14, 21,  1,  1 } }, // vsqrtsd
    { ISD::FSQRT,      MVT::v2f64,   { 14, 21,  1,  1 } }, // vsqrtpd
    { ISD::FSQRT,      MVT::v4f64,   { 28, 35,  1,  3 } }, // vsqrtpd
  };
  static const CostKindTblEntry AVX1CostTbl[] = {
    { ISD::ABS,        MVT::v4i64,   {  6,  8,  6, 12 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
    { ISD::ABS,        MVT::v8i32,   {  3,  6,  4,  5 } },
    { ISD::ABS,        MVT::v16i16,  {  3,  6,  4,  5 } },
    { ISD::ABS,        MVT::v32i8,   {  3,  6,  4,  5 } },
    { ISD::BITREVERSE, MVT::v4i64,   { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
    { ISD::BITREVERSE, MVT::v2i64,   {  8, 13, 10, 16 } },
    { ISD::BITREVERSE, MVT::v8i32,   { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
    { ISD::BITREVERSE, MVT::v4i32,   {  8, 13, 10, 16 } },
    { ISD::BITREVERSE, MVT::v16i16,  { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
    { ISD::BITREVERSE, MVT::v8i16,   {  8, 13, 10, 16 } },
    { ISD::BITREVERSE, MVT::v32i8,   { 13, 15, 17, 26 } }, // 2 x 128-bit Op + extract/insert
    { ISD::BITREVERSE, MVT::v16i8,   {  7,  7,  9, 13 } },
    { ISD::BSWAP,      MVT::v4i64,   {  5,  7,  5, 10 } },
    { ISD::BSWAP,      MVT::v2i64,   {  2,  3,  1,  3 } },
    { ISD::BSWAP,      MVT::v8i32,   {  5,  7,  5, 10 } },
    { ISD::BSWAP,      MVT::v4i32,   {  2,  3,  1,  3 } },
    { ISD::BSWAP,      MVT::v16i16,  {  5,  6,  5, 10 } },
    { ISD::BSWAP,      MVT::v8i16,   {  2,  2,  1,  3 } },
    { ISD::CTLZ,       MVT::v4i64,   { 29, 33, 49, 58 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTLZ,       MVT::v2i64,   { 14, 24, 24, 28 } },
    { ISD::CTLZ,       MVT::v8i32,   { 24, 28, 39, 48 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTLZ,       MVT::v4i32,   { 12, 20, 19, 23 } },
    { ISD::CTLZ,       MVT::v16i16,  { 19, 22, 29, 38 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTLZ,       MVT::v8i16,   {  9, 16, 14, 18 } },
    { ISD::CTLZ,       MVT::v32i8,   { 14, 15, 19, 28 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTLZ,       MVT::v16i8,   {  7, 12,  9, 13 } },
    { ISD::CTPOP,      MVT::v4i64,   { 14, 18, 19, 28 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTPOP,      MVT::v2i64,   {  7, 14, 10, 14 } },
    { ISD::CTPOP,      MVT::v8i32,   { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTPOP,      MVT::v4i32,   {  9, 20, 14, 18 } },
    { ISD::CTPOP,      MVT::v16i16,  { 16, 21, 22, 31 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTPOP,      MVT::v8i16,   {  8, 18, 11, 15 } },
    { ISD::CTPOP,      MVT::v32i8,   { 13, 15, 16, 25 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTPOP,      MVT::v16i8,   {  6, 12,  8, 12 } },
    { ISD::CTTZ,       MVT::v4i64,   { 17, 22, 24, 33 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTTZ,       MVT::v2i64,   {  9, 19, 13, 17 } },
    { ISD::CTTZ,       MVT::v8i32,   { 21, 27, 32, 41 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTTZ,       MVT::v4i32,   { 11, 24, 17, 21 } },
    { ISD::CTTZ,       MVT::v16i16,  { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTTZ,       MVT::v8i16,   {  9, 21, 14, 18 } },
    { ISD::CTTZ,       MVT::v32i8,   { 15, 18, 21, 30 } }, // 2 x 128-bit Op + extract/insert
    { ISD::CTTZ,       MVT::v16i8,   {  8, 16, 11, 15 } },
    { ISD::SADDSAT,    MVT::v16i16,  {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SADDSAT,    MVT::v32i8,   {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMAX,       MVT::v4i64,   {  6,  9,  6, 12 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMAX,       MVT::v2i64,   {  3,  7,  2,  4 } },
    { ISD::SMAX,       MVT::v8i32,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMAX,       MVT::v16i16,  {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMAX,       MVT::v32i8,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMIN,       MVT::v4i64,   {  6,  9,  6, 12 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMIN,       MVT::v2i64,   {  3,  7,  2,  3 } },
    { ISD::SMIN,       MVT::v8i32,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMIN,       MVT::v16i16,  {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SMIN,       MVT::v32i8,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SSUBSAT,    MVT::v16i16,  {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::SSUBSAT,    MVT::v32i8,   {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UADDSAT,    MVT::v16i16,  {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UADDSAT,    MVT::v32i8,   {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UADDSAT,    MVT::v8i32,   {  8 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMAX,       MVT::v4i64,   {  9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMAX,       MVT::v2i64,   {  4,  8,  5,  7 } },
    { ISD::UMAX,       MVT::v8i32,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMAX,       MVT::v16i16,  {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMAX,       MVT::v32i8,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMIN,       MVT::v4i64,   {  9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMIN,       MVT::v2i64,   {  4,  8,  5,  7 } },
    { ISD::UMIN,       MVT::v8i32,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMIN,       MVT::v16i16,  {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::UMIN,       MVT::v32i8,   {  4,  6,  5,  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::USUBSAT,    MVT::v16i16,  {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::USUBSAT,    MVT::v32i8,   {  4 } }, // 2 x 128-bit Op + extract/insert
    { ISD::USUBSAT,    MVT::v8i32,   {  6 } }, // 2 x 128-bit Op + extract/insert
    { ISD::FMAXNUM,    MVT::f32,     {  3,  6,  3,  5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
    { ISD::FMAXNUM,    MVT::v4f32,   {  3,  6,  3,  5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
    { ISD::FMAXNUM,    MVT::v8f32,   {  5,  7,  3, 10 } }, // MAXPS + CMPUNORDPS + BLENDVPS
    { ISD::FMAXNUM,    MVT::f64,     {  3,  6,  3,  5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
    { ISD::FMAXNUM,    MVT::v2f64,   {  3,  6,  3,  5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
    { ISD::FMAXNUM,    MVT::v4f64,   {  5,  7,  3, 10 } }, // MAXPD + CMPUNORDPD + BLENDVPD
    { ISD::FSQRT,      MVT::f32,     { 21, 21,  1,  1 } }, // vsqrtss
    { ISD::FSQRT,      MVT::v4f32,   { 21, 21,  1,  1 } }, // vsqrtps
    { ISD::FSQRT,      MVT::v8f32,   { 42, 42,  1,  3 } }, // vsqrtps
    { ISD::FSQRT,      MVT::f64,     { 27, 27,  1,  1 } }, // vsqrtsd
    { ISD::FSQRT,      MVT::v2f64,   { 27, 27,  1,  1 } }, // vsqrtpd
    { ISD::FSQRT,      MVT::v4f64,   { 54, 54,  1,  3 } }, // vsqrtpd
  };
  static const CostKindTblEntry GLMCostTbl[] = {
    { ISD::FSQRT,      MVT::f32,     { 19, 20, 1, 1 } }, // sqrtss
    { ISD::FSQRT,      MVT::v4f32,   { 37, 41, 1, 5 } }, // sqrtps
    { ISD::FSQRT,      MVT::f64,     { 34, 35, 1, 1 } }, // sqrtsd
    { ISD::FSQRT,      MVT::v2f64,   { 67, 71, 1, 5 } }, // sqrtpd
  };
  static const CostKindTblEntry SLMCostTbl[] = {
    { ISD::FSQRT,      MVT::f32,     { 20, 20, 1, 1 } }, // sqrtss
    { ISD::FSQRT,      MVT::v4f32,   { 40, 41, 1, 5 } }, // sqrtps
    { ISD::FSQRT,      MVT::f64,     { 35, 35, 1, 1 } }, // sqrtsd
    { ISD::FSQRT,      MVT::v2f64,   { 70, 71, 1, 5 } }, // sqrtpd
  };
  static const CostKindTblEntry SSE42CostTbl[] = {
    { ISD::USUBSAT,    MVT::v4i32,   {  2 } }, // pmaxud + psubd
    { ISD::UADDSAT,    MVT::v4i32,   {  3 } }, // not + pminud + paddd
    { ISD::FMAXNUM,    MVT::f32,     {  5,  5,  7,  7 } }, // MAXSS + CMPUNORDSS + BLENDVPS
    { ISD::FMAXNUM,    MVT::v4f32,   {  4,  4,  4,  5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
    { ISD::FMAXNUM,    MVT::f64,     {  5,  5,  7,  7 } }, // MAXSD + CMPUNORDSD + BLENDVPD
    { ISD::FMAXNUM,    MVT::v2f64,   {  4,  4,  4,  5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
    { ISD::FSQRT,      MVT::f32,     { 18, 18,  1,  1 } }, // Nehalem from http://www.agner.org/
    { ISD::FSQRT,      MVT::v4f32,   { 18, 18,  1,  1 } }, // Nehalem from http://www.agner.org/
  };
  static const CostKindTblEntry SSE41CostTbl[] = {
    { ISD::ABS,        MVT::v2i64,   {  3,  4,  3,  5 } }, // BLENDVPD(X,PSUBQ(0,X),X)
    { ISD::SMAX,       MVT::v2i64,   {  3,  7,  2,  3 } },
    { ISD::SMAX,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::SMAX,       MVT::v16i8,   {  1,  1,  1,  1 } },
    { ISD::SMIN,       MVT::v2i64,   {  3,  7,  2,  3 } },
    { ISD::SMIN,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::SMIN,       MVT::v16i8,   {  1,  1,  1,  1 } },
    { ISD::UMAX,       MVT::v2i64,   {  2, 11,  6,  7 } },
    { ISD::UMAX,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::UMAX,       MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::UMIN,       MVT::v2i64,   {  2, 11,  6,  7 } },
    { ISD::UMIN,       MVT::v4i32,   {  1,  1,  1,  1 } },
    { ISD::UMIN,       MVT::v8i16,   {  1,  1,  1,  1 } },
  };
  static const CostKindTblEntry SSSE3CostTbl[] = {
    { ISD::ABS,        MVT::v4i32,   {  1,  2,  1,  1 } },
    { ISD::ABS,        MVT::v8i16,   {  1,  2,  1,  1 } },
    { ISD::ABS,        MVT::v16i8,   {  1,  2,  1,  1 } },
    { ISD::BITREVERSE, MVT::v2i64,   { 16, 20, 11, 21 } },
    { ISD::BITREVERSE, MVT::v4i32,   { 16, 20, 11, 21 } },
    { ISD::BITREVERSE, MVT::v8i16,   { 16, 20, 11, 21 } },
    { ISD::BITREVERSE, MVT::v16i8,   { 11, 12, 10, 16 } },
    { ISD::BSWAP,      MVT::v2i64,   {  5,  5,  1,  5 } },
    { ISD::BSWAP,      MVT::v4i32,   {  5,  5,  1,  5 } },
    { ISD::BSWAP,      MVT::v8i16,   {  5,  5,  1,  5 } },
    { ISD::CTLZ,       MVT::v2i64,   { 18, 28, 28, 35 } },
    { ISD::CTLZ,       MVT::v4i32,   { 15, 20, 22, 28 } },
    { ISD::CTLZ,       MVT::v8i16,   { 13, 17, 16, 22 } },
    { ISD::CTLZ,       MVT::v16i8,   { 11, 15, 10, 16 } },
    { ISD::CTPOP,      MVT::v2i64,   { 13, 19, 12, 18 } },
    { ISD::CTPOP,      MVT::v4i32,   { 18, 24, 16, 22 } },
    { ISD::CTPOP,      MVT::v8i16,   { 13, 18, 14, 20 } },
    { ISD::CTPOP,      MVT::v16i8,   { 11, 12, 10, 16 } },
    { ISD::CTTZ,       MVT::v2i64,   { 13, 25, 15, 22 } },
    { ISD::CTTZ,       MVT::v4i32,   { 18, 26, 19, 25 } },
    { ISD::CTTZ,       MVT::v8i16,   { 13, 20, 17, 23 } },
    { ISD::CTTZ,       MVT::v16i8,   { 11, 16, 13, 19 } }
  };
  static const CostKindTblEntry SSE2CostTbl[] = {
    { ISD::ABS,        MVT::v2i64,   {  3,  6,  5,  5 } },
    { ISD::ABS,        MVT::v4i32,   {  1,  4,  4,  4 } },
    { ISD::ABS,        MVT::v8i16,   {  1,  2,  3,  3 } },
    { ISD::ABS,        MVT::v16i8,   {  1,  2,  3,  3 } },
    { ISD::BITREVERSE, MVT::v2i64,   { 16, 20, 32, 32 } },
    { ISD::BITREVERSE, MVT::v4i32,   { 16, 20, 30, 30 } },
    { ISD::BITREVERSE, MVT::v8i16,   { 16, 20, 25, 25 } },
    { ISD::BITREVERSE, MVT::v16i8,   { 11, 12, 21, 21 } },
    { ISD::BSWAP,      MVT::v2i64,   {  5,  6, 11, 11 } },
    { ISD::BSWAP,      MVT::v4i32,   {  5,  5,  9,  9 } },
    { ISD::BSWAP,      MVT::v8i16,   {  5,  5,  4,  5 } },
    { ISD::CTLZ,       MVT::v2i64,   { 10, 45, 36, 38 } },
    { ISD::CTLZ,       MVT::v4i32,   { 10, 45, 38, 40 } },
    { ISD::CTLZ,       MVT::v8i16,   {  9, 38, 32, 34 } },
    { ISD::CTLZ,       MVT::v16i8,   {  8, 39, 29, 32 } },
    { ISD::CTPOP,      MVT::v2i64,   { 12, 26, 16, 18 } },
    { ISD::CTPOP,      MVT::v4i32,   { 15, 29, 21, 23 } },
    { ISD::CTPOP,      MVT::v8i16,   { 13, 25, 18, 20 } },
    { ISD::CTPOP,      MVT::v16i8,   { 10, 21, 14, 16 } },
    { ISD::CTTZ,       MVT::v2i64,   { 14, 28, 19, 21 } },
    { ISD::CTTZ,       MVT::v4i32,   { 18, 31, 24, 26 } },
    { ISD::CTTZ,       MVT::v8i16,   { 16, 27, 21, 23 } },
    { ISD::CTTZ,       MVT::v16i8,   { 13, 23, 17, 19 } },
    { ISD::SADDSAT,    MVT::v8i16,   {  1 } },
    { ISD::SADDSAT,    MVT::v16i8,   {  1 } },
    { ISD::SMAX,       MVT::v2i64,   {  4,  8, 15, 15 } },
    { ISD::SMAX,       MVT::v4i32,   {  2,  4,  5,  5 } },
    { ISD::SMAX,       MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::SMAX,       MVT::v16i8,   {  2,  4,  5,  5 } },
    { ISD::SMIN,       MVT::v2i64,   {  4,  8, 15, 15 } },
    { ISD::SMIN,       MVT::v4i32,   {  2,  4,  5,  5 } },
    { ISD::SMIN,       MVT::v8i16,   {  1,  1,  1,  1 } },
    { ISD::SMIN,       MVT::v16i8,   {  2,  4,  5,  5 } },
    { ISD::SSUBSAT,    MVT::v8i16,   {  1 } },
    { ISD::SSUBSAT,    MVT::v16i8,   {  1 } },
    { ISD::UADDSAT,    MVT::v8i16,   {  1 } },
    { ISD::UADDSAT,    MVT::v16i8,   {  1 } },
    { ISD::UMAX,       MVT::v2i64,   {  4,  8, 15, 15 } },
    { ISD::UMAX,       MVT::v4i32,   {  2,  5,  8,  8 } },
    { ISD::UMAX,       MVT::v8i16,   {  1,  3,  3,  3 } },
    { ISD::UMAX,       MVT::v16i8,   {  1,  1,  1,  1 } },
    { ISD::UMIN,       MVT::v2i64,   {  4,  8, 15, 15 } },
    { ISD::UMIN,       MVT::v4i32,   {  2,  5,  8,  8 } },
    { ISD::UMIN,       MVT::v8i16,   {  1,  3,  3,  3 } },
    { ISD::UMIN,       MVT::v16i8,   {  1,  1,  1,  1 } },
    { ISD::USUBSAT,    MVT::v8i16,   {  1 } },
    { ISD::USUBSAT,    MVT::v16i8,   {  1 } },
    { ISD::FMAXNUM,    MVT::f64,     {  5,  5,  7,  7 } },
    { ISD::FMAXNUM,    MVT::v2f64,   {  4,  6,  6,  6 } },
    { ISD::FSQRT,      MVT::f64,     { 32, 32,  1,  1 } }, // Nehalem from http://www.agner.org/
    { ISD::FSQRT,      MVT::v2f64,   { 32, 32,  1,  1 } }, // Nehalem from http://www.agner.org/
  };
  static const CostKindTblEntry SSE1CostTbl[] = {
    { ISD::FMAXNUM,    MVT::f32,     {  5,  5,  7,  7 } },
    { ISD::FMAXNUM,    MVT::v4f32,   {  4,  6,  6,  6 } },
    { ISD::FSQRT,      MVT::f32,     { 28, 30,  1,  2 } }, // Pentium III from http://www.agner.org/
    { ISD::FSQRT,      MVT::v4f32,   { 56, 56,  1,  2 } }, // Pentium III from http://www.agner.org/
  };
  static const CostKindTblEntry BMI64CostTbl[] = { // 64-bit targets
    { ISD::CTTZ,       MVT::i64,     {  1 } },
  };
  static const CostKindTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets
    { ISD::CTTZ,       MVT::i32,     {  1 } },
    { ISD::CTTZ,       MVT::i16,     {  1 } },
    { ISD::CTTZ,       MVT::i8,      {  1 } },
  };
  static const CostKindTblEntry LZCNT64CostTbl[] = { // 64-bit targets
    { ISD::CTLZ,       MVT::i64,     {  1 } },
  };
  static const CostKindTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets
    { ISD::CTLZ,       MVT::i32,     {  1 } },
    { ISD::CTLZ,       MVT::i16,     {  2 } },
    { ISD::CTLZ,       MVT::i8,      {  2 } },
  };
  static const CostKindTblEntry POPCNT64CostTbl[] = { // 64-bit targets
    { ISD::CTPOP,      MVT::i64,     {  1, 1, 1, 1 } }, // popcnt
  };
  static const CostKindTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets
    { ISD::CTPOP,      MVT::i32,     {  1, 1, 1, 1 } }, // popcnt
    { ISD::CTPOP,      MVT::i16,     {  1, 1, 2, 2 } }, // popcnt(zext())
    { ISD::CTPOP,      MVT::i8,      {  1, 1, 2, 2 } }, // popcnt(zext())
  };
  static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
    { ISD::ABS,        MVT::i64,     {  1,  2,  3,  4 } }, // SUB+CMOV
    { ISD::BITREVERSE, MVT::i64,     { 10, 12, 20, 22 } },
    { ISD::BSWAP,      MVT::i64,     {  1,  2,  1,  2 } },
    { ISD::CTLZ,       MVT::i64,     {  4 } }, // BSR+XOR or BSR+XOR+CMOV
    { ISD::CTLZ_ZERO_UNDEF, MVT::i64,{  1,  1,  1,  1 } }, // BSR+XOR
    { ISD::CTTZ,       MVT::i64,     {  3 } }, // TEST+BSF+CMOV/BRANCH
    { ISD::CTTZ_ZERO_UNDEF, MVT::i64,{  1,  1,  1,  1 } }, // BSR
    { ISD::CTPOP,      MVT::i64,     { 10,  6, 19, 19 } },
    { ISD::ROTL,       MVT::i64,     {  2, 3, 1, 3 } },
    { ISD::ROTR,       MVT::i64,     {  2, 3, 1, 3 } },
    { ISD::FSHL,       MVT::i64,     {  4, 4, 1, 4 } },
    { ISD::SMAX,       MVT::i64,     {  1,  3,  2,  3 } },
    { ISD::SMIN,       MVT::i64,     {  1,  3,  2,  3 } },
    { ISD::UMAX,       MVT::i64,     {  1,  3,  2,  3 } },
    { ISD::UMIN,       MVT::i64,     {  1,  3,  2,  3 } },
    { ISD::SADDO,      MVT::i64,     {  1 } },
    { ISD::UADDO,      MVT::i64,     {  1 } },
    { ISD::UMULO,      MVT::i64,     {  2 } }, // mulq + seto
  };
  static const CostKindTblEntry X86CostTbl[] = { // 32 or 64-bit targets
    { ISD::ABS,        MVT::i32,     {  1,  2,  3,  4 } }, // SUB+XOR+SRA or SUB+CMOV
    { ISD::ABS,        MVT::i16,     {  2,  2,  3,  4 } }, // SUB+XOR+SRA or SUB+CMOV
    { ISD::ABS,        MVT::i8,      {  2,  4,  4,  4 } }, // SUB+XOR+SRA
    { ISD::BITREVERSE, MVT::i32,     {  9, 12, 17, 19 } },
    { ISD::BITREVERSE, MVT::i16,     {  9, 12, 17, 19 } },
    { ISD::BITREVERSE, MVT::i8,      {  7,  9, 13, 14 } },
    { ISD::BSWAP,      MVT::i32,     {  1,  1,  1,  1 } },
    { ISD::BSWAP,      MVT::i16,     {  1,  2,  1,  2 } }, // ROL
    { ISD::CTLZ,       MVT::i32,     {  4 } }, // BSR+XOR or BSR+XOR+CMOV
    { ISD::CTLZ,       MVT::i16,     {  4 } }, // BSR+XOR or BSR+XOR+CMOV
    { ISD::CTLZ,       MVT::i8,      {  4 } }, // BSR+XOR or BSR+XOR+CMOV
    { ISD::CTLZ_ZERO_UNDEF, MVT::i32,{  1,  1,  1,  1 } }, // BSR+XOR
    { ISD::CTLZ_ZERO_UNDEF, MVT::i16,{  2,  2,  3,  3 } }, // BSR+XOR
    { ISD::CTLZ_ZERO_UNDEF, MVT::i8, {  2,  2,  3,  3 } }, // BSR+XOR
    { ISD::CTTZ,       MVT::i32,     {  3 } }, // TEST+BSF+CMOV/BRANCH
    { ISD::CTTZ,       MVT::i16,     {  3 } }, // TEST+BSF+CMOV/BRANCH
    { ISD::CTTZ,       MVT::i8,      {  3 } }, // TEST+BSF+CMOV/BRANCH
    { ISD::CTTZ_ZERO_UNDEF, MVT::i32,{  1,  1,  1,  1 } }, // BSF
    { ISD::CTTZ_ZERO_UNDEF, MVT::i16,{  2,  2,  1,  1 } }, // BSF
    { ISD::CTTZ_ZERO_UNDEF, MVT::i8, {  2,  2,  1,  1 } }, // BSF
    { ISD::CTPOP,      MVT::i32,     {  8,  7, 15, 15 } },
    { ISD::CTPOP,      MVT::i16,     {  9,  8, 17, 17 } },
    { ISD::CTPOP,      MVT::i8,      {  7,  6, 13, 13 } },
    { ISD::ROTL,       MVT::i32,     {  2,  3,  1,  3 } },
    { ISD::ROTL,       MVT::i16,     {  2,  3,  1,  3 } },
    { ISD::ROTL,       MVT::i8,      {  2,  3,  1,  3 } },
    { ISD::ROTR,       MVT::i32,     {  2,  3,  1,  3 } },
    { ISD::ROTR,       MVT::i16,     {  2,  3,  1,  3 } },
    { ISD::ROTR,       MVT::i8,      {  2,  3,  1,  3 } },
    { ISD::FSHL,       MVT::i32,     {  4,  4,  1,  4 } },
    { ISD::FSHL,       MVT::i16,     {  4,  4,  2,  5 } },
    { ISD::FSHL,       MVT::i8,      {  4,  4,  2,  5 } },
    { ISD::SMAX,       MVT::i32,     {  1,  2,  2,  3 } },
    { ISD::SMAX,       MVT::i16,     {  1,  4,  2,  4 } },
    { ISD::SMAX,       MVT::i8,      {  1,  4,  2,  4 } },
    { ISD::SMIN,       MVT::i32,     {  1,  2,  2,  3 } },
    { ISD::SMIN,       MVT::i16,     {  1,  4,  2,  4 } },
    { ISD::SMIN,       MVT::i8,      {  1,  4,  2,  4 } },
    { ISD::UMAX,       MVT::i32,     {  1,  2,  2,  3 } },
    { ISD::UMAX,       MVT::i16,     {  1,  4,  2,  4 } },
    { ISD::UMAX,       MVT::i8,      {  1,  4,  2,  4 } },
    { ISD::UMIN,       MVT::i32,     {  1,  2,  2,  3 } },
    { ISD::UMIN,       MVT::i16,     {  1,  4,  2,  4 } },
    { ISD::UMIN,       MVT::i8,      {  1,  4,  2,  4 } },
    { ISD::SADDO,      MVT::i32,     {  1 } },
    { ISD::SADDO,      MVT::i16,     {  1 } },
    { ISD::SADDO,      MVT::i8,      {  1 } },
    { ISD::UADDO,      MVT::i32,     {  1 } },
    { ISD::UADDO,      MVT::i16,     {  1 } },
    { ISD::UADDO,      MVT::i8,      {  1 } },
    { ISD::UMULO,      MVT::i32,     {  2 } }, // mul + seto
    { ISD::UMULO,      MVT::i16,     {  2 } },
    { ISD::UMULO,      MVT::i8,      {  2 } },
  };
 
  Type *RetTy = ICA.getReturnType();
  Type *OpTy = RetTy;
  Intrinsic::ID IID = ICA.getID();
  unsigned ISD = ISD::DELETED_NODE;
  switch (IID) {
  default:
    break;
  case Intrinsic::abs:
    ISD = ISD::ABS;
    break;
  case Intrinsic::bitreverse:
    ISD = ISD::BITREVERSE;
    break;
  case Intrinsic::bswap:
    ISD = ISD::BSWAP;
    break;
  case Intrinsic::ctlz:
    ISD = ISD::CTLZ;
    break;
  case Intrinsic::ctpop:
    ISD = ISD::CTPOP;
    break;
  case Intrinsic::cttz:
    ISD = ISD::CTTZ;
    break;
  case Intrinsic::fshl:
    ISD = ISD::FSHL;
    if (!ICA.isTypeBasedOnly()) {
      const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
      if (Args[0] == Args[1])
        ISD = ISD::ROTL;
    }
    break;
  case Intrinsic::fshr:
    // FSHR has same costs so don't duplicate.
    ISD = ISD::FSHL;
    if (!ICA.isTypeBasedOnly()) {
      const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
      if (Args[0] == Args[1])
        ISD = ISD::ROTR;
    }
    break;
  case Intrinsic::maxnum:
  case Intrinsic::minnum:
    // FMINNUM has same costs so don't duplicate.
    ISD = ISD::FMAXNUM;
    break;
  case Intrinsic::sadd_sat:
    ISD = ISD::SADDSAT;
    break;
  case Intrinsic::smax:
    ISD = ISD::SMAX;
    break;
  case Intrinsic::smin:
    ISD = ISD::SMIN;
    break;
  case Intrinsic::ssub_sat:
    ISD = ISD::SSUBSAT;
    break;
  case Intrinsic::uadd_sat:
    ISD = ISD::UADDSAT;
    break;
  case Intrinsic::umax:
    ISD = ISD::UMAX;
    break;
  case Intrinsic::umin:
    ISD = ISD::UMIN;
    break;
  case Intrinsic::usub_sat:
    ISD = ISD::USUBSAT;
    break;
  case Intrinsic::sqrt:
    ISD = ISD::FSQRT;
    break;
  case Intrinsic::sadd_with_overflow:
  case Intrinsic::ssub_with_overflow:
    // SSUBO has same costs so don't duplicate.
    ISD = ISD::SADDO;
    OpTy = RetTy->getContainedType(0);
    break;
  case Intrinsic::uadd_with_overflow:
  case Intrinsic::usub_with_overflow:
    // USUBO has same costs so don't duplicate.
    ISD = ISD::UADDO;
    OpTy = RetTy->getContainedType(0);
    break;
  case Intrinsic::umul_with_overflow:
  case Intrinsic::smul_with_overflow:
    // SMULO has same costs so don't duplicate.
    ISD = ISD::UMULO;
    OpTy = RetTy->getContainedType(0);
    break;
  }
 
  if (ISD != ISD::DELETED_NODE) {
    // Legalize the type.
    std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(OpTy);
    MVT MTy = LT.second;
 
    // Attempt to lookup cost.
    if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() &&
        MTy.isVector()) {
      // With PSHUFB the code is very similar for all types. If we have integer
      // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types
      // we also need a PSHUFB.
      unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2;
 
      // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB
      // instructions. We also need an extract and an insert.
      if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) ||
            (ST->hasBWI() && MTy.is512BitVector())))
        Cost = Cost * 2 + 2;
 
      return LT.first * Cost;
    }
 
    // Without BMI/LZCNT see if we're only looking for a *_ZERO_UNDEF cost.
    if (((ISD == ISD::CTTZ && !ST->hasBMI()) ||
         (ISD == ISD::CTLZ && !ST->hasLZCNT())) &&
        !MTy.isVector() && !ICA.isTypeBasedOnly()) {
      const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
      if (auto *Cst = dyn_cast<ConstantInt>(Args[1]))
        if (Cst->isAllOnesValue())
          ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_UNDEF : ISD::CTLZ_ZERO_UNDEF;
    }
 
    // FSQRT is a single instruction.
    if (ISD == ISD::FSQRT && CostKind == TTI::TCK_CodeSize)
      return LT.first;
 
    auto adjustTableCost = [](int ISD, unsigned Cost,
                              InstructionCost LegalizationCost,
                              FastMathFlags FMF) {
      // If there are no NANs to d