LLVM  14.0.0git
X86ISelLowering.cpp
Go to the documentation of this file.
1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
16 #include "X86.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86IntrinsicsInfo.h"
21 #include "X86MachineFunctionInfo.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DerivedTypes.h"
47 #include "llvm/IR/DiagnosticInfo.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalAlias.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/IRBuilder.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/Intrinsics.h"
54 #include "llvm/IR/PatternMatch.h"
55 #include "llvm/MC/MCAsmInfo.h"
56 #include "llvm/MC/MCContext.h"
57 #include "llvm/MC/MCExpr.h"
58 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/KnownBits.h"
65 #include <algorithm>
66 #include <bitset>
67 #include <cctype>
68 #include <numeric>
69 using namespace llvm;
70 
71 #define DEBUG_TYPE "x86-isel"
72 
73 STATISTIC(NumTailCalls, "Number of tail calls");
74 
76  "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77  cl::desc(
78  "Sets the preferable loop alignment for experiments (as log2 bytes) "
79  "for innermost loops only. If specified, this option overrides "
80  "alignment set by x86-experimental-pref-loop-alignment."),
81  cl::Hidden);
82 
84  "mul-constant-optimization", cl::init(true),
85  cl::desc("Replace 'mul x, Const' with more effective instructions like "
86  "SHIFT, LEA, etc."),
87  cl::Hidden);
88 
90  "x86-experimental-unordered-atomic-isel", cl::init(false),
91  cl::desc("Use LoadSDNode and StoreSDNode instead of "
92  "AtomicSDNode for unordered atomic loads and "
93  "stores respectively."),
94  cl::Hidden);
95 
96 /// Call this when the user attempts to do something unsupported, like
97 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98 /// report_fatal_error, so calling code should attempt to recover without
99 /// crashing.
100 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101  const char *Msg) {
103  DAG.getContext()->diagnose(
105 }
106 
108  const X86Subtarget &STI)
109  : TargetLowering(TM), Subtarget(STI) {
110  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111  X86ScalarSSEf64 = Subtarget.hasSSE2();
112  X86ScalarSSEf32 = Subtarget.hasSSE1();
113  X86ScalarSSEf16 = Subtarget.hasFP16();
114  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
115 
116  // Set up the TargetLowering object.
117 
118  // X86 is weird. It always uses i8 for shift amounts and setcc results.
120  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
122 
123  // For 64-bit, since we have so many registers, use the ILP scheduler.
124  // For 32-bit, use the register pressure specific scheduling.
125  // For Atom, always use ILP scheduling.
126  if (Subtarget.isAtom())
128  else if (Subtarget.is64Bit())
130  else
132  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
134 
135  // Bypass expensive divides and use cheaper ones.
136  if (TM.getOptLevel() >= CodeGenOpt::Default) {
137  if (Subtarget.hasSlowDivide32())
138  addBypassSlowDiv(32, 8);
139  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
140  addBypassSlowDiv(64, 32);
141  }
142 
143  // Setup Windows compiler runtime calls.
144  if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
145  static const struct {
146  const RTLIB::Libcall Op;
147  const char * const Name;
148  const CallingConv::ID CC;
149  } LibraryCalls[] = {
150  { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
151  { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
152  { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
153  { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
154  { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
155  };
156 
157  for (const auto &LC : LibraryCalls) {
158  setLibcallName(LC.Op, LC.Name);
159  setLibcallCallingConv(LC.Op, LC.CC);
160  }
161  }
162 
163  if (Subtarget.getTargetTriple().isOSMSVCRT()) {
164  // MSVCRT doesn't have powi; fall back to pow
165  setLibcallName(RTLIB::POWI_F32, nullptr);
166  setLibcallName(RTLIB::POWI_F64, nullptr);
167  }
168 
169  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
170  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
171  // FIXME: Should we be limiting the atomic size on other configs? Default is
172  // 1024.
173  if (!Subtarget.hasCmpxchg8b())
175 
176  // Set up the register classes.
177  addRegisterClass(MVT::i8, &X86::GR8RegClass);
178  addRegisterClass(MVT::i16, &X86::GR16RegClass);
179  addRegisterClass(MVT::i32, &X86::GR32RegClass);
180  if (Subtarget.is64Bit())
181  addRegisterClass(MVT::i64, &X86::GR64RegClass);
182 
183  for (MVT VT : MVT::integer_valuetypes())
185 
186  // We don't accept any truncstore of integer registers.
193 
195 
196  // SETOEQ and SETUNE require checking two conditions.
197  for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
200  }
201 
202  // Integer absolute.
203  if (Subtarget.hasCMov()) {
206  if (Subtarget.is64Bit())
208  }
209 
210  // Signed saturation subtraction.
214  if (Subtarget.is64Bit())
216 
217  // Funnel shifts.
218  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
219  // For slow shld targets we only lower for code size.
220  LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
221 
222  setOperationAction(ShiftOp , MVT::i8 , Custom);
223  setOperationAction(ShiftOp , MVT::i16 , Custom);
224  setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
225  if (Subtarget.is64Bit())
226  setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
227  }
228 
229  if (!Subtarget.useSoftFloat()) {
230  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
231  // operation.
236  // We have an algorithm for SSE2, and we turn this into a 64-bit
237  // FILD or VCVTUSI2SS/SD for other targets.
240  // We have an algorithm for SSE2->double, and we turn this into a
241  // 64-bit FILD followed by conditional FADD for other targets.
244 
245  // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
246  // this operation.
249  // SSE has no i16 to fp conversion, only i32. We promote in the handler
250  // to allow f80 to use i16 and f64 to use i16 with sse1 only
253  // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
256  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
257  // are Legal, f80 is custom lowered.
260 
261  // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
262  // this operation.
264  // FIXME: This doesn't generate invalid exception when it should. PR44019.
270  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
271  // are Legal, f80 is custom lowered.
274 
275  // Handle FP_TO_UINT by promoting the destination to a larger signed
276  // conversion.
278  // FIXME: This doesn't generate invalid exception when it should. PR44019.
281  // FIXME: This doesn't generate invalid exception when it should. PR44019.
287 
292 
293  if (!Subtarget.is64Bit()) {
296  }
297  }
298 
299  if (Subtarget.hasSSE2()) {
300  // Custom lowering for saturating float to int conversions.
301  // We handle promotion to larger result types manually.
302  for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
305  }
306  if (Subtarget.is64Bit()) {
309  }
310  }
311 
312  // Handle address space casts between mixed sized pointers.
315 
316  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
317  if (!X86ScalarSSEf64) {
320  if (Subtarget.is64Bit()) {
322  // Without SSE, i64->f64 goes through memory.
324  }
325  } else if (!Subtarget.is64Bit())
327 
328  // Scalar integer divide and remainder are lowered to use operations that
329  // produce two results, to match the available instructions. This exposes
330  // the two-result form to trivial CSE, which is able to combine x/y and x%y
331  // into a single instruction.
332  //
333  // Scalar integer multiply-high is also lowered to use two-result
334  // operations, to match the available instructions. However, plain multiply
335  // (low) operations are left as Legal, as there are single-result
336  // instructions for this in x86. Using the two-result multiply instructions
337  // when both high and low results are needed must be arranged by dagcombine.
338  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
345  }
346 
349  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
353  }
354  if (Subtarget.is64Bit())
359 
364 
365  if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
368  }
369 
370  // Promote the i8 variants and force them on up to i32 which has a shorter
371  // encoding.
374 
375  if (Subtarget.hasBMI()) {
376  // Promote the i16 zero undef variant and force it on up to i32 when tzcnt
377  // is enabled.
379  } else {
384  if (Subtarget.is64Bit()) {
387  }
388  }
389 
390  if (Subtarget.hasLZCNT()) {
391  // When promoting the i8 variants, force them to i32 for a shorter
392  // encoding.
395  } else {
396  for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
397  if (VT == MVT::i64 && !Subtarget.is64Bit())
398  continue;
401  }
402  }
403 
406  // Special handling for half-precision floating point conversions.
407  // If we don't have F16C support, then lower half float conversions
408  // into library calls.
410  Op, MVT::f32,
411  (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
412  // There's never any support for operations beyond MVT::f32.
416  }
417 
426 
428  if (Subtarget.hasPOPCNT()) {
430  } else {
434  if (Subtarget.is64Bit())
436  else
438 
441  if (Subtarget.is64Bit())
443  }
444 
446 
447  if (!Subtarget.hasMOVBE())
449 
450  // X86 wants to expand cmov itself.
451  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
456  }
457  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
458  if (VT == MVT::i64 && !Subtarget.is64Bit())
459  continue;
462  }
463 
464  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
467 
469  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
470  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
474  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
475  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
476 
477  // Darwin ABI issue.
478  for (auto VT : { MVT::i32, MVT::i64 }) {
479  if (VT == MVT::i64 && !Subtarget.is64Bit())
480  continue;
487  }
488 
489  // 64-bit shl, sra, srl (iff 32-bit x86)
490  for (auto VT : { MVT::i32, MVT::i64 }) {
491  if (VT == MVT::i64 && !Subtarget.is64Bit())
492  continue;
496  }
497 
498  if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
500 
502 
503  // Expand certain atomics
504  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
512  }
513 
514  if (!Subtarget.is64Bit())
516 
517  if (Subtarget.hasCmpxchg16b()) {
519  }
520 
521  // FIXME - use subtarget debug flags
522  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
523  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
524  TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
526  }
527 
530 
533 
537 
538  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
541  bool Is64Bit = Subtarget.is64Bit();
544 
547 
549 
550  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
553 
554  if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
555  // f32 and f64 use SSE.
556  // Set up the FP register classes.
557  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
558  : &X86::FR32RegClass);
559  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
560  : &X86::FR64RegClass);
561 
562  // Disable f32->f64 extload as we can only generate this in one instruction
563  // under optsize. So its easier to pattern match (fpext (load)) for that
564  // case instead of needing to emit 2 instructions for extload in the
565  // non-optsize case.
567 
568  for (auto VT : { MVT::f32, MVT::f64 }) {
569  // Use ANDPD to simulate FABS.
571 
572  // Use XORP to simulate FNEG.
574 
575  // Use ANDPD and ORPD to simulate FCOPYSIGN.
577 
578  // These might be better off as horizontal vector ops.
581 
582  // We don't support sin/cos/fmod
586  }
587 
588  // Lower this to MOVMSK plus an AND.
591 
592  } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32 &&
593  (UseX87 || Is64Bit)) {
594  // Use SSE for f32, x87 for f64.
595  // Set up the FP register classes.
596  addRegisterClass(MVT::f32, &X86::FR32RegClass);
597  if (UseX87)
598  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
599 
600  // Use ANDPS to simulate FABS.
602 
603  // Use XORP to simulate FNEG.
605 
606  if (UseX87)
608 
609  // Use ANDPS and ORPS to simulate FCOPYSIGN.
610  if (UseX87)
613 
614  // We don't support sin/cos/fmod
618 
619  if (UseX87) {
620  // Always expand sin/cos functions even though x87 has an instruction.
624  }
625  } else if (UseX87) {
626  // f32 and f64 in x87.
627  // Set up the FP register classes.
628  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
629  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
630 
631  for (auto VT : { MVT::f32, MVT::f64 }) {
634 
635  // Always expand sin/cos functions even though x87 has an instruction.
639  }
640  }
641 
642  // Expand FP32 immediates into loads from the stack, save special cases.
643  if (isTypeLegal(MVT::f32)) {
644  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
645  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
646  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
647  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
648  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
649  } else // SSE immediates.
650  addLegalFPImmediate(APFloat(+0.0f)); // xorps
651  }
652  // Expand FP64 immediates into loads from the stack, save special cases.
653  if (isTypeLegal(MVT::f64)) {
654  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
655  addLegalFPImmediate(APFloat(+0.0)); // FLD0
656  addLegalFPImmediate(APFloat(+1.0)); // FLD1
657  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
658  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
659  } else // SSE immediates.
660  addLegalFPImmediate(APFloat(+0.0)); // xorpd
661  }
662  // Handle constrained floating-point operations of scalar.
676 
677  // We don't support FMA.
680 
681  // f80 always uses X87.
682  if (UseX87) {
683  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
686  {
688  addLegalFPImmediate(TmpFlt); // FLD0
689  TmpFlt.changeSign();
690  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
691 
692  bool ignored;
693  APFloat TmpFlt2(+1.0);
695  &ignored);
696  addLegalFPImmediate(TmpFlt2); // FLD1
697  TmpFlt2.changeSign();
698  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
699  }
700 
701  // Always expand sin/cos functions even though x87 has an instruction.
705 
716 
717  // Handle constrained floating-point operations of scalar.
724  // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
725  // as Custom.
727  }
728 
729  // f128 uses xmm registers, but most operations require libcalls.
730  if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
731  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
732  : &X86::VR128RegClass);
733 
734  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
735 
746 
750 
756  // No STRICT_FSINCOS
759 
762  // We need to custom handle any FP_ROUND with an f128 input, but
763  // LegalizeDAG uses the result type to know when to run a custom handler.
764  // So we have to list all legal floating point result types here.
765  if (isTypeLegal(MVT::f32)) {
768  }
769  if (isTypeLegal(MVT::f64)) {
772  }
773  if (isTypeLegal(MVT::f80)) {
776  }
777 
779 
786  }
787 
788  // Always use a library call for pow.
793 
801 
802  // Some FP actions are always expanded for vector types.
803  for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
816  }
817 
818  // First set operation action for all vector types to either promote
819  // (for widening) or expand (for scalarization). Then we will selectively
820  // turn on ones that can be effectively codegen'd.
821  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
859  for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
860  setTruncStoreAction(InnerVT, VT, Expand);
861 
862  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
863  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
864 
865  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
866  // types, we have to deal with them whether we ask for Expansion or not.
867  // Setting Expand causes its own optimisation problems though, so leave
868  // them legal.
869  if (VT.getVectorElementType() == MVT::i1)
870  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
871 
872  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
873  // split/scalarized right now.
874  if (VT.getVectorElementType() == MVT::f16)
875  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
876  }
877  }
878 
879  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
880  // with -msoft-float, disable use of MMX as well.
881  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
882  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
883  // No operations on x86mmx supported, everything uses intrinsics.
884  }
885 
886  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
887  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
888  : &X86::VR128RegClass);
889 
898 
901 
907  }
908 
909  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
910  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
911  : &X86::VR128RegClass);
912 
913  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
914  // registers cannot be used even for integer operations.
915  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
916  : &X86::VR128RegClass);
917  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
918  : &X86::VR128RegClass);
919  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
920  : &X86::VR128RegClass);
921  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
922  : &X86::VR128RegClass);
923 
924  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
930  }
931 
935 
946 
949 
953 
954  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
959  }
960 
971 
976 
977  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
983 
984  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
985  // setcc all the way to isel and prefer SETGT in some isel patterns.
988  }
989 
990  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
996  }
997 
998  for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1002 
1003  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1004  continue;
1005 
1008  }
1009 
1010  // Custom lower v2i64 and v2f64 selects.
1016 
1023 
1024  // Custom legalize these to avoid over promotion or custom promotion.
1025  for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1030  }
1031 
1036 
1039 
1042 
1043  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1048 
1053 
1054  // We want to legalize this to an f64 load rather than an i64 load on
1055  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1056  // store.
1063 
1067  if (!Subtarget.hasAVX512())
1069 
1073 
1075 
1082 
1083  // In the customized shift lowering, the legal v4i32/v2i64 cases
1084  // in AVX2 will be recognized.
1085  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1089  }
1090 
1093 
1094  // With 512-bit registers or AVX512VL+BW, expanding (and promoting the
1095  // shifts) is better.
1096  if (!Subtarget.useAVX512Regs() &&
1097  !(Subtarget.hasBWI() && Subtarget.hasVLX()))
1099 
1105  }
1106 
1107  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1116 
1117  // These might be better off as horizontal vector ops.
1122  }
1123 
1124  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1125  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1126  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1128  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1130  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1132  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1138 
1139  setOperationAction(ISD::FROUND, RoundedTy, Custom);
1140  }
1141 
1150 
1154 
1155  // FIXME: Do we need to handle scalar-to-vector here?
1157 
1158  // We directly match byte blends in the backend as they match the VSELECT
1159  // condition form.
1161 
1162  // SSE41 brings specific instructions for doing vector sign extend even in
1163  // cases where we don't have SRA.
1164  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1167  }
1168 
1169  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1170  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1177  }
1178 
1179  if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1180  // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1181  // do the pre and post work in the vector domain.
1184  // We need to mark SINT_TO_FP as Custom even though we want to expand it
1185  // so that DAG combine doesn't try to turn it into uint_to_fp.
1188  }
1189  }
1190 
1191  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1193  }
1194 
1195  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1196  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1199 
1200  // XOP can efficiently perform BITREVERSE with VPPERM.
1201  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1203 
1204  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1207  }
1208 
1209  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1210  bool HasInt256 = Subtarget.hasInt256();
1211 
1212  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1213  : &X86::VR256RegClass);
1214  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1215  : &X86::VR256RegClass);
1216  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1217  : &X86::VR256RegClass);
1218  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1219  : &X86::VR256RegClass);
1220  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1221  : &X86::VR256RegClass);
1222  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1223  : &X86::VR256RegClass);
1224 
1225  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1238 
1240 
1244  }
1245 
1246  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1247  // even though v8i16 is a legal type.
1255 
1258 
1271 
1272  if (!Subtarget.hasAVX512())
1274 
1275  // In the customized shift lowering, the legal v8i32/v4i64 cases
1276  // in AVX2 will be recognized.
1277  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1281  }
1282 
1283  // These types need custom splitting if their input is a 128-bit vector.
1288 
1291 
1292  // With BWI, expanding (and promoting the shifts) is the better.
1293  if (!Subtarget.useBWIRegs())
1295 
1302 
1303  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1307  }
1308 
1313 
1314  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1320 
1321  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1322  // setcc all the way to isel and prefer SETGT in some isel patterns.
1325  }
1326 
1327  if (Subtarget.hasAnyFMA()) {
1328  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1329  MVT::v2f64, MVT::v4f64 }) {
1332  }
1333  }
1334 
1335  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1336  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1337  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1338  }
1339 
1344 
1351 
1354 
1360 
1373 
1374  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1375  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1376  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1377  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1378  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1379  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1380  }
1381 
1382  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1385  }
1386 
1387  if (HasInt256) {
1388  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1389  // when we have a 256bit-wide blend with immediate.
1392 
1393  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1394  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1401  }
1402  }
1403 
1404  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1406  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1408  }
1409 
1410  // Extract subvector is special because the value type
1411  // (result) is 128-bit but the source is 256-bit wide.
1412  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1413  MVT::v4f32, MVT::v2f64 }) {
1415  }
1416 
1417  // Custom lower several nodes for 256-bit types.
1419  MVT::v8f32, MVT::v4f64 }) {
1429  }
1430 
1431  if (HasInt256) {
1433 
1434  // Custom legalize 2x32 to get a little better code.
1437 
1438  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1441  }
1442  }
1443 
1444  // This block controls legalization of the mask vector sizes that are
1445  // available with AVX512. 512-bit vectors are in a separate block controlled
1446  // by useAVX512Regs.
1447  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1448  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1449  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1450  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1451  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1452  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1453 
1457 
1470 
1471  // There is no byte sized k-register load or store without AVX512DQ.
1472  if (!Subtarget.hasDQI()) {
1477 
1482  }
1483 
1484  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1485  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1489  }
1490 
1491  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1493 
1494  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1500 
1507  }
1508 
1509  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1511  }
1512 
1513  // This block controls legalization for 512-bit operations with 32/64 bit
1514  // elements. 512-bits can be disabled based on prefer-vector-width and
1515  // required-vector-width function attributes.
1516  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1517  bool HasBWI = Subtarget.hasBWI();
1518 
1519  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1520  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1521  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1522  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1523  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1524  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1525 
1526  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1532  if (HasBWI)
1534  }
1535 
1536  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1542  }
1543 
1544  for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1549  }
1558 
1571 
1577  if (HasBWI)
1579 
1580  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1581  // to 512-bit rather than use the AVX2 instructions so that we can use
1582  // k-masks.
1583  if (!Subtarget.hasVLX()) {
1584  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1588  }
1589  }
1590 
1604 
1605  if (HasBWI) {
1606  // Extends from v64i1 masks to 512-bit vectors.
1610  }
1611 
1612  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1625 
1627  }
1628 
1629  for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1632  }
1633 
1638 
1643 
1650 
1653 
1655 
1656  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1661 
1662  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1663  // setcc all the way to isel and prefer SETGT in some isel patterns.
1666  }
1667  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1678  }
1679 
1680  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1681  setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1682  setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1684  setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1685  setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1686  setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1687  setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1688  setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1689  setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1690  setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1691  setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1692  }
1693 
1694  if (Subtarget.hasDQI()) {
1703 
1705  }
1706 
1707  if (Subtarget.hasCDI()) {
1708  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1709  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1711  }
1712  } // Subtarget.hasCDI()
1713 
1714  if (Subtarget.hasVPOPCNTDQ()) {
1715  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1717  }
1718 
1719  // Extract subvector is special because the value type
1720  // (result) is 256-bit but the source is 512-bit wide.
1721  // 128-bit was made Legal under AVX1.
1722  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1725 
1726  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1727  MVT::v16f32, MVT::v8f64 }) {
1737  }
1738 
1739  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1744  }
1745  if (HasBWI) {
1746  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1749  }
1750  } else {
1753  }
1754 
1755  if (Subtarget.hasVBMI2()) {
1756  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1761  }
1762 
1767  }
1768  }// useAVX512Regs
1769 
1770  // This block controls legalization for operations that don't have
1771  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1772  // narrower widths.
1773  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1774  // These operations are handled on non-VLX by artificially widening in
1775  // isel patterns.
1776 
1778  Subtarget.hasVLX() ? Legal : Custom);
1780  Subtarget.hasVLX() ? Legal : Custom);
1782  Subtarget.hasVLX() ? Legal : Custom);
1784  Subtarget.hasVLX() ? Legal : Custom);
1787  Subtarget.hasVLX() ? Legal : Custom);
1789  Subtarget.hasVLX() ? Legal : Custom);
1791  Subtarget.hasVLX() ? Legal : Custom);
1793  Subtarget.hasVLX() ? Legal : Custom);
1794 
1795  if (Subtarget.hasDQI()) {
1796  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1797  // v2f32 UINT_TO_FP is already custom under SSE2.
1800  "Unexpected operation action!");
1801  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1806  }
1807 
1808  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1814  }
1815 
1816  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1819  }
1820 
1821  // Custom legalize 2x32 to get a little better code.
1824 
1825  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1828 
1829  if (Subtarget.hasDQI()) {
1830  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1832  Subtarget.hasVLX() ? Legal : Custom);
1834  Subtarget.hasVLX() ? Legal : Custom);
1836  Subtarget.hasVLX() ? Legal : Custom);
1838  Subtarget.hasVLX() ? Legal : Custom);
1840  Subtarget.hasVLX() ? Legal : Custom);
1842  Subtarget.hasVLX() ? Legal : Custom);
1844  Subtarget.hasVLX() ? Legal : Custom);
1846  Subtarget.hasVLX() ? Legal : Custom);
1848  }
1849  }
1850 
1851  if (Subtarget.hasCDI()) {
1852  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1854  }
1855  } // Subtarget.hasCDI()
1856 
1857  if (Subtarget.hasVPOPCNTDQ()) {
1858  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1860  }
1861  }
1862 
1863  // This block control legalization of v32i1/v64i1 which are available with
1864  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1865  // useBWIRegs.
1866  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1867  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1868  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1869 
1870  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1881  }
1882 
1883  for (auto VT : { MVT::v16i1, MVT::v32i1 })
1885 
1886  // Extends from v32i1 masks to 256-bit vectors.
1890 
1891  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1892  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1893  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1894  }
1895 
1896  // These operations are handled on non-VLX by artificially widening in
1897  // isel patterns.
1898  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1899 
1900  if (Subtarget.hasBITALG()) {
1901  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1903  }
1904  }
1905 
1906  if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
1907  auto setGroup = [&] (MVT VT) {
1918 
1929 
1932 
1938 
1944  };
1945 
1946  // AVX512_FP16 scalar operations
1947  setGroup(MVT::f16);
1948  addRegisterClass(MVT::f16, &X86::FR16XRegClass);
1957  if (isTypeLegal(MVT::f80)) {
1960  }
1961 
1964 
1965  if (Subtarget.useAVX512Regs()) {
1966  setGroup(MVT::v32f16);
1967  addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
1976 
1983  MVT::v32i16);
1986  MVT::v32i16);
1989  MVT::v32i16);
1992  MVT::v32i16);
1993 
1997 
2000 
2003  }
2004 
2005  if (Subtarget.hasVLX()) {
2006  addRegisterClass(MVT::v8f16, &X86::VR128XRegClass);
2007  addRegisterClass(MVT::v16f16, &X86::VR256XRegClass);
2008  setGroup(MVT::v8f16);
2009  setGroup(MVT::v16f16);
2010 
2021 
2028 
2029  // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2032 
2036 
2041 
2042  // Need to custom widen these to prevent scalarization.
2045  }
2046 
2047  // Support fp16 0 immediate
2048  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
2049  }
2050 
2051  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2057 
2063 
2064  if (Subtarget.hasBWI()) {
2067  }
2068 
2069  if (Subtarget.hasFP16()) {
2070  // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2079  // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2088  // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2093  // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2098  }
2099 
2103  }
2104 
2105  if (Subtarget.hasAMXTILE()) {
2106  addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2107  }
2108 
2109  // We want to custom lower some of our intrinsics.
2113  if (!Subtarget.is64Bit()) {
2115  }
2116 
2117  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2118  // handle type legalization for these operations here.
2119  //
2120  // FIXME: We really should do custom legalization for addition and
2121  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2122  // than generic legalization for 64-bit multiplication-with-overflow, though.
2123  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2124  if (VT == MVT::i64 && !Subtarget.is64Bit())
2125  continue;
2126  // Add/Sub/Mul with overflow operations are custom lowered.
2133 
2134  // Support carry in as value rather than glue.
2140  }
2141 
2142  if (!Subtarget.is64Bit()) {
2143  // These libcalls are not available in 32-bit.
2144  setLibcallName(RTLIB::SHL_I128, nullptr);
2145  setLibcallName(RTLIB::SRL_I128, nullptr);
2146  setLibcallName(RTLIB::SRA_I128, nullptr);
2147  setLibcallName(RTLIB::MUL_I128, nullptr);
2148  // The MULO libcall is not part of libgcc, only compiler-rt.
2149  setLibcallName(RTLIB::MULO_I64, nullptr);
2150  }
2151  // The MULO libcall is not part of libgcc, only compiler-rt.
2152  setLibcallName(RTLIB::MULO_I128, nullptr);
2153 
2154  // Combine sin / cos into _sincos_stret if it is available.
2155  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2156  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2159  }
2160 
2161  if (Subtarget.isTargetWin64()) {
2166  }
2167 
2168  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2169  // is. We should promote the value to 64-bits to solve this.
2170  // This is what the CRT headers do - `fmodf` is an inline header
2171  // function casting to f64 and calling `fmod`.
2172  if (Subtarget.is32Bit() &&
2173  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2174  for (ISD::NodeType Op :
2186 
2187  // We have target-specific dag combine patterns for the following nodes:
2237 
2239 
2240  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2242  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2244  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2246 
2247  // TODO: These control memcmp expansion in CGP and could be raised higher, but
2248  // that needs to benchmarked and balanced with the potential use of vector
2249  // load/store types (PR33329, PR33914).
2250  MaxLoadsPerMemcmp = 2;
2252 
2253  // Default loop alignment, which can be overridden by -align-loops.
2255 
2256  // An out-of-order CPU can speculatively execute past a predictable branch,
2257  // but a conditional move could be stalled by an expensive earlier operation.
2258  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2259  EnableExtLdPromotion = true;
2261 
2263 
2264  // Default to having -disable-strictnode-mutation on
2265  IsStrictFPEnabled = true;
2266 }
2267 
2268 // This has so far only been implemented for 64-bit MachO.
2270  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2271 }
2272 
2274  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2275  return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2276 }
2277 
2279  const SDLoc &DL) const {
2280  EVT PtrTy = getPointerTy(DAG.getDataLayout());
2281  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2282  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2283  return SDValue(Node, 0);
2284 }
2285 
2288  if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2289  !Subtarget.hasBWI())
2290  return TypeSplitVector;
2291 
2292  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2293  VT.getVectorElementType() != MVT::i1)
2294  return TypeWidenVector;
2295 
2297 }
2298 
2299 static std::pair<MVT, unsigned>
2301  const X86Subtarget &Subtarget) {
2302  // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2303  // convention is one that uses k registers.
2304  if (NumElts == 2)
2305  return {MVT::v2i64, 1};
2306  if (NumElts == 4)
2307  return {MVT::v4i32, 1};
2308  if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2310  return {MVT::v8i16, 1};
2311  if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2313  return {MVT::v16i8, 1};
2314  // v32i1 passes in ymm unless we have BWI and the calling convention is
2315  // regcall.
2316  if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2317  return {MVT::v32i8, 1};
2318  // Split v64i1 vectors if we don't have v64i8 available.
2319  if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2320  if (Subtarget.useAVX512Regs())
2321  return {MVT::v64i8, 1};
2322  return {MVT::v32i8, 2};
2323  }
2324 
2325  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2326  if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2327  NumElts > 64)
2328  return {MVT::i8, NumElts};
2329 
2330  return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2331 }
2332 
2334  CallingConv::ID CC,
2335  EVT VT) const {
2336  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2337  Subtarget.hasAVX512()) {
2338  unsigned NumElts = VT.getVectorNumElements();
2339 
2340  MVT RegisterVT;
2341  unsigned NumRegisters;
2342  std::tie(RegisterVT, NumRegisters) =
2343  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2344  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2345  return RegisterVT;
2346  }
2347 
2348  // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2349  // So its default register type is f16. We override the type to v8f16 here.
2350  if (VT == MVT::v3f16 && Subtarget.hasFP16())
2351  return MVT::v8f16;
2352 
2354 }
2355 
2357  CallingConv::ID CC,
2358  EVT VT) const {
2359  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2360  Subtarget.hasAVX512()) {
2361  unsigned NumElts = VT.getVectorNumElements();
2362 
2363  MVT RegisterVT;
2364  unsigned NumRegisters;
2365  std::tie(RegisterVT, NumRegisters) =
2366  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2367  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2368  return NumRegisters;
2369  }
2370 
2371  // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2372  // So its default register number is 3. We override the number to 1 here.
2373  if (VT == MVT::v3f16 && Subtarget.hasFP16())
2374  return 1;
2375 
2377 }
2378 
2380  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2381  unsigned &NumIntermediates, MVT &RegisterVT) const {
2382  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2383  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2384  Subtarget.hasAVX512() &&
2386  (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2387  VT.getVectorNumElements() > 64)) {
2388  RegisterVT = MVT::i8;
2389  IntermediateVT = MVT::i1;
2390  NumIntermediates = VT.getVectorNumElements();
2391  return NumIntermediates;
2392  }
2393 
2394  // Split v64i1 vectors if we don't have v64i8 available.
2395  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2396  CC != CallingConv::X86_RegCall) {
2397  RegisterVT = MVT::v32i8;
2398  IntermediateVT = MVT::v32i1;
2399  NumIntermediates = 2;
2400  return 2;
2401  }
2402 
2403  return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2404  NumIntermediates, RegisterVT);
2405 }
2406 
2409  EVT VT) const {
2410  if (!VT.isVector())
2411  return MVT::i8;
2412 
2413  if (Subtarget.hasAVX512()) {
2414  // Figure out what this type will be legalized to.
2415  EVT LegalVT = VT;
2416  while (getTypeAction(Context, LegalVT) != TypeLegal)
2417  LegalVT = getTypeToTransformTo(Context, LegalVT);
2418 
2419  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2420  if (LegalVT.getSimpleVT().is512BitVector())
2422 
2423  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2424  // If we legalized to less than a 512-bit vector, then we will use a vXi1
2425  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2426  // vXi16/vXi8.
2427  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2428  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2430  }
2431  }
2432 
2434 }
2435 
2436 /// Helper for getByValTypeAlignment to determine
2437 /// the desired ByVal argument alignment.
2438 static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2439  if (MaxAlign == 16)
2440  return;
2441  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2442  if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2443  MaxAlign = Align(16);
2444  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2445  Align EltAlign;
2446  getMaxByValAlign(ATy->getElementType(), EltAlign);
2447  if (EltAlign > MaxAlign)
2448  MaxAlign = EltAlign;
2449  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2450  for (auto *EltTy : STy->elements()) {
2451  Align EltAlign;
2452  getMaxByValAlign(EltTy, EltAlign);
2453  if (EltAlign > MaxAlign)
2454  MaxAlign = EltAlign;
2455  if (MaxAlign == 16)
2456  break;
2457  }
2458  }
2459 }
2460 
2461 /// Return the desired alignment for ByVal aggregate
2462 /// function arguments in the caller parameter area. For X86, aggregates
2463 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2464 /// are at 4-byte boundaries.
2466  const DataLayout &DL) const {
2467  if (Subtarget.is64Bit()) {
2468  // Max of 8 and alignment of type.
2469  Align TyAlign = DL.getABITypeAlign(Ty);
2470  if (TyAlign > 8)
2471  return TyAlign.value();
2472  return 8;
2473  }
2474 
2475  Align Alignment(4);
2476  if (Subtarget.hasSSE1())
2477  getMaxByValAlign(Ty, Alignment);
2478  return Alignment.value();
2479 }
2480 
2481 /// It returns EVT::Other if the type should be determined using generic
2482 /// target-independent logic.
2483 /// For vector ops we check that the overall size isn't larger than our
2484 /// preferred vector width.
2486  const MemOp &Op, const AttributeList &FuncAttributes) const {
2487  if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2488  if (Op.size() >= 16 &&
2489  (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2490  // FIXME: Check if unaligned 64-byte accesses are slow.
2491  if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2492  (Subtarget.getPreferVectorWidth() >= 512)) {
2493  return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2494  }
2495  // FIXME: Check if unaligned 32-byte accesses are slow.
2496  if (Op.size() >= 32 && Subtarget.hasAVX() &&
2497  (Subtarget.getPreferVectorWidth() >= 256)) {
2498  // Although this isn't a well-supported type for AVX1, we'll let
2499  // legalization and shuffle lowering produce the optimal codegen. If we
2500  // choose an optimal type with a vector element larger than a byte,
2501  // getMemsetStores() may create an intermediate splat (using an integer
2502  // multiply) before we splat as a vector.
2503  return MVT::v32i8;
2504  }
2505  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2506  return MVT::v16i8;
2507  // TODO: Can SSE1 handle a byte vector?
2508  // If we have SSE1 registers we should be able to use them.
2509  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2510  (Subtarget.getPreferVectorWidth() >= 128))
2511  return MVT::v4f32;
2512  } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2513  Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2514  // Do not use f64 to lower memcpy if source is string constant. It's
2515  // better to use i32 to avoid the loads.
2516  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2517  // The gymnastics of splatting a byte value into an XMM register and then
2518  // only using 8-byte stores (because this is a CPU with slow unaligned
2519  // 16-byte accesses) makes that a loser.
2520  return MVT::f64;
2521  }
2522  }
2523  // This is a compromise. If we reach here, unaligned accesses may be slow on
2524  // this target. However, creating smaller, aligned accesses could be even
2525  // slower and would certainly be a lot more code.
2526  if (Subtarget.is64Bit() && Op.size() >= 8)
2527  return MVT::i64;
2528  return MVT::i32;
2529 }
2530 
2532  if (VT == MVT::f32)
2533  return X86ScalarSSEf32;
2534  if (VT == MVT::f64)
2535  return X86ScalarSSEf64;
2536  return true;
2537 }
2538 
2540  EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2541  bool *Fast) const {
2542  if (Fast) {
2543  switch (VT.getSizeInBits()) {
2544  default:
2545  // 8-byte and under are always assumed to be fast.
2546  *Fast = true;
2547  break;
2548  case 128:
2549  *Fast = !Subtarget.isUnalignedMem16Slow();
2550  break;
2551  case 256:
2552  *Fast = !Subtarget.isUnalignedMem32Slow();
2553  break;
2554  // TODO: What about AVX-512 (512-bit) accesses?
2555  }
2556  }
2557  // NonTemporal vector memory ops must be aligned.
2558  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2559  // NT loads can only be vector aligned, so if its less aligned than the
2560  // minimum vector size (which we can split the vector down to), we might as
2561  // well use a regular unaligned vector load.
2562  // We don't have any NT loads pre-SSE41.
2563  if (!!(Flags & MachineMemOperand::MOLoad))
2564  return (Alignment < 16 || !Subtarget.hasSSE41());
2565  return false;
2566  }
2567  // Misaligned accesses of any size are always allowed.
2568  return true;
2569 }
2570 
2571 /// Return the entry encoding for a jump table in the
2572 /// current function. The returned value is a member of the
2573 /// MachineJumpTableInfo::JTEntryKind enum.
2575  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2576  // symbol.
2577  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2579 
2580  // Otherwise, use the normal jump table encoding heuristics.
2582 }
2583 
2585  return Subtarget.useSoftFloat();
2586 }
2587 
2589  ArgListTy &Args) const {
2590 
2591  // Only relabel X86-32 for C / Stdcall CCs.
2592  if (Subtarget.is64Bit())
2593  return;
2594  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2595  return;
2596  unsigned ParamRegs = 0;
2597  if (auto *M = MF->getFunction().getParent())
2598  ParamRegs = M->getNumberRegisterParameters();
2599 
2600  // Mark the first N int arguments as having reg
2601  for (auto &Arg : Args) {
2602  Type *T = Arg.Ty;
2603  if (T->isIntOrPtrTy())
2604  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2605  unsigned numRegs = 1;
2606  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2607  numRegs = 2;
2608  if (ParamRegs < numRegs)
2609  return;
2610  ParamRegs -= numRegs;
2611  Arg.IsInReg = true;
2612  }
2613  }
2614 }
2615 
2616 const MCExpr *
2618  const MachineBasicBlock *MBB,
2619  unsigned uid,MCContext &Ctx) const{
2620  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2621  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2622  // entries.
2625 }
2626 
2627 /// Returns relocation base for the given PIC jumptable.
2629  SelectionDAG &DAG) const {
2630  if (!Subtarget.is64Bit())
2631  // This doesn't have SDLoc associated with it, but is not really the
2632  // same as a Register.
2633  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2634  getPointerTy(DAG.getDataLayout()));
2635  return Table;
2636 }
2637 
2638 /// This returns the relocation base for the given PIC jumptable,
2639 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2642  MCContext &Ctx) const {
2643  // X86-64 uses RIP relative addressing based on the jump table label.
2644  if (Subtarget.isPICStyleRIPRel())
2645  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2646 
2647  // Otherwise, the reference is relative to the PIC base.
2648  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2649 }
2650 
2651 std::pair<const TargetRegisterClass *, uint8_t>
2653  MVT VT) const {
2654  const TargetRegisterClass *RRC = nullptr;
2655  uint8_t Cost = 1;
2656  switch (VT.SimpleTy) {
2657  default:
2659  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2660  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2661  break;
2662  case MVT::x86mmx:
2663  RRC = &X86::VR64RegClass;
2664  break;
2665  case MVT::f32: case MVT::f64:
2666  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2667  case MVT::v4f32: case MVT::v2f64:
2668  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2669  case MVT::v8f32: case MVT::v4f64:
2670  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2671  case MVT::v16f32: case MVT::v8f64:
2672  RRC = &X86::VR128XRegClass;
2673  break;
2674  }
2675  return std::make_pair(RRC, Cost);
2676 }
2677 
2678 unsigned X86TargetLowering::getAddressSpace() const {
2679  if (Subtarget.is64Bit())
2680  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2681  return 256;
2682 }
2683 
2684 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2685  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2686  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2687 }
2688 
2690  int Offset, unsigned AddressSpace) {
2694 }
2695 
2697  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2698  // tcbhead_t; use it instead of the usual global variable (see
2699  // sysdeps/{i386,x86_64}/nptl/tls.h)
2700  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2701  if (Subtarget.isTargetFuchsia()) {
2702  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2703  return SegmentOffset(IRB, 0x10, getAddressSpace());
2704  } else {
2705  unsigned AddressSpace = getAddressSpace();
2706  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2707  // Specially, some users may customize the base reg and offset.
2708  int Offset = M->getStackProtectorGuardOffset();
2709  // If we don't set -stack-protector-guard-offset value:
2710  // %fs:0x28, unless we're using a Kernel code model, in which case
2711  // it's %gs:0x28. gs:0x14 on i386.
2712  if (Offset == INT_MAX)
2713  Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2714 
2715  StringRef GuardReg = M->getStackProtectorGuardReg();
2716  if (GuardReg == "fs")
2718  else if (GuardReg == "gs")
2720  return SegmentOffset(IRB, Offset, AddressSpace);
2721  }
2722  }
2723  return TargetLowering::getIRStackGuard(IRB);
2724 }
2725 
2727  // MSVC CRT provides functionalities for stack protection.
2728  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2730  // MSVC CRT has a global variable holding security cookie.
2731  M.getOrInsertGlobal("__security_cookie",
2732  Type::getInt8PtrTy(M.getContext()));
2733 
2734  // MSVC CRT has a function to validate security cookie.
2735  FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2736  "__security_check_cookie", Type::getVoidTy(M.getContext()),
2737  Type::getInt8PtrTy(M.getContext()));
2738  if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2739  F->setCallingConv(CallingConv::X86_FastCall);
2740  F->addParamAttr(0, Attribute::AttrKind::InReg);
2741  }
2742  return;
2743  }
2744 
2745  StringRef GuardMode = M.getStackProtectorGuard();
2746 
2747  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2748  if ((GuardMode == "tls" || GuardMode.empty()) &&
2750  return;
2752 }
2753 
2755  // MSVC CRT has a global variable holding security cookie.
2756  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2758  return M.getGlobalVariable("__security_cookie");
2759  }
2761 }
2762 
2764  // MSVC CRT has a function to validate security cookie.
2765  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2767  return M.getFunction("__security_check_cookie");
2768  }
2770 }
2771 
2772 Value *
2774  if (Subtarget.getTargetTriple().isOSContiki())
2775  return getDefaultSafeStackPointerLocation(IRB, false);
2776 
2777  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2778  // definition of TLS_SLOT_SAFESTACK in
2779  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2780  if (Subtarget.isTargetAndroid()) {
2781  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2782  // %gs:0x24 on i386
2783  int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2784  return SegmentOffset(IRB, Offset, getAddressSpace());
2785  }
2786 
2787  // Fuchsia is similar.
2788  if (Subtarget.isTargetFuchsia()) {
2789  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2790  return SegmentOffset(IRB, 0x18, getAddressSpace());
2791  }
2792 
2794 }
2795 
2796 //===----------------------------------------------------------------------===//
2797 // Return Value Calling Convention Implementation
2798 //===----------------------------------------------------------------------===//
2799 
2800 bool X86TargetLowering::CanLowerReturn(
2801  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2802  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2804  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2805  return CCInfo.CheckReturn(Outs, RetCC_X86);
2806 }
2807 
2808 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2809  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2810  return ScratchRegs;
2811 }
2812 
2813 /// Lowers masks values (v*i1) to the local register values
2814 /// \returns DAG node after lowering to register type
2815 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2816  const SDLoc &Dl, SelectionDAG &DAG) {
2817  EVT ValVT = ValArg.getValueType();
2818 
2819  if (ValVT == MVT::v1i1)
2820  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2821  DAG.getIntPtrConstant(0, Dl));
2822 
2823  if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2824  (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2825  // Two stage lowering might be required
2826  // bitcast: v8i1 -> i8 / v16i1 -> i16
2827  // anyextend: i8 -> i32 / i16 -> i32
2828  EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2829  SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2830  if (ValLoc == MVT::i32)
2831  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2832  return ValToCopy;
2833  }
2834 
2835  if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2836  (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2837  // One stage lowering is required
2838  // bitcast: v32i1 -> i32 / v64i1 -> i64
2839  return DAG.getBitcast(ValLoc, ValArg);
2840  }
2841 
2842  return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2843 }
2844 
2845 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2847  const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2848  SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2849  CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2850  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
2851  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2852  assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
2853  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2854  "The value should reside in two registers");
2855 
2856  // Before splitting the value we cast it to i64
2857  Arg = DAG.getBitcast(MVT::i64, Arg);
2858 
2859  // Splitting the value into two i32 types
2860  SDValue Lo, Hi;
2862  DAG.getConstant(0, Dl, MVT::i32));
2864  DAG.getConstant(1, Dl, MVT::i32));
2865 
2866  // Attach the two i32 types into corresponding registers
2867  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2868  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2869 }
2870 
2871 SDValue
2872 X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2873  bool isVarArg,
2874  const SmallVectorImpl<ISD::OutputArg> &Outs,
2875  const SmallVectorImpl<SDValue> &OutVals,
2876  const SDLoc &dl, SelectionDAG &DAG) const {
2877  MachineFunction &MF = DAG.getMachineFunction();
2879 
2880  // In some cases we need to disable registers from the default CSR list.
2881  // For example, when they are used for argument passing.
2882  bool ShouldDisableCalleeSavedRegister =
2883  CallConv == CallingConv::X86_RegCall ||
2884  MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2885 
2886  if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2887  report_fatal_error("X86 interrupts may not return any value");
2888 
2890  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2891  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2892 
2894  for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2895  ++I, ++OutsIndex) {
2896  CCValAssign &VA = RVLocs[I];
2897  assert(VA.isRegLoc() && "Can only return in registers!");
2898 
2899  // Add the register to the CalleeSaveDisableRegs list.
2900  if (ShouldDisableCalleeSavedRegister)
2902 
2903  SDValue ValToCopy = OutVals[OutsIndex];
2904  EVT ValVT = ValToCopy.getValueType();
2905 
2906  // Promote values to the appropriate types.
2907  if (VA.getLocInfo() == CCValAssign::SExt)
2908  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2909  else if (VA.getLocInfo() == CCValAssign::ZExt)
2910  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2911  else if (VA.getLocInfo() == CCValAssign::AExt) {
2912  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2913  ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2914  else
2915  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2916  }
2917  else if (VA.getLocInfo() == CCValAssign::BCvt)
2918  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2919 
2921  "Unexpected FP-extend for return value.");
2922 
2923  // Report an error if we have attempted to return a value via an XMM
2924  // register and SSE was disabled.
2925  if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
2926  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2927  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2928  } else if (!Subtarget.hasSSE2() &&
2929  X86::FR64XRegClass.contains(VA.getLocReg()) &&
2930  ValVT == MVT::f64) {
2931  // When returning a double via an XMM register, report an error if SSE2 is
2932  // not enabled.
2933  errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2934  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2935  }
2936 
2937  // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2938  // the RET instruction and handled by the FP Stackifier.
2939  if (VA.getLocReg() == X86::FP0 ||
2940  VA.getLocReg() == X86::FP1) {
2941  // If this is a copy from an xmm register to ST(0), use an FPExtend to
2942  // change the value to the FP stack register class.
2943  if (isScalarFPTypeInSSEReg(VA.getValVT()))
2944  ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2945  RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2946  // Don't emit a copytoreg.
2947  continue;
2948  }
2949 
2950  // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2951  // which is returned in RAX / RDX.
2952  if (Subtarget.is64Bit()) {
2953  if (ValVT == MVT::x86mmx) {
2954  if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2955  ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2956  ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2957  ValToCopy);
2958  // If we don't have SSE2 available, convert to v4f32 so the generated
2959  // register is legal.
2960  if (!Subtarget.hasSSE2())
2961  ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2962  }
2963  }
2964  }
2965 
2966  if (VA.needsCustom()) {
2967  assert(VA.getValVT() == MVT::v64i1 &&
2968  "Currently the only custom case is when we split v64i1 to 2 regs");
2969 
2970  Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I],
2971  Subtarget);
2972 
2973  // Add the second register to the CalleeSaveDisableRegs list.
2974  if (ShouldDisableCalleeSavedRegister)
2975  MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2976  } else {
2977  RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy));
2978  }
2979  }
2980 
2981  SDValue Flag;
2982  SmallVector<SDValue, 6> RetOps;
2983  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2984  // Operand #1 = Bytes To Pop
2985  RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2986  MVT::i32));
2987 
2988  // Copy the result values into the output registers.
2989  for (auto &RetVal : RetVals) {
2990  if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
2991  RetOps.push_back(RetVal.second);
2992  continue; // Don't emit a copytoreg.
2993  }
2994 
2995  Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Flag);
2996  Flag = Chain.getValue(1);
2997  RetOps.push_back(
2998  DAG.getRegister(RetVal.first, RetVal.second.getValueType()));
2999  }
3000 
3001  // Swift calling convention does not require we copy the sret argument
3002  // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
3003 
3004  // All x86 ABIs require that for returning structs by value we copy
3005  // the sret argument into %rax/%eax (depending on ABI) for the return.
3006  // We saved the argument into a virtual register in the entry block,
3007  // so now we copy the value out and into %rax/%eax.
3008  //
3009  // Checking Function.hasStructRetAttr() here is insufficient because the IR
3010  // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
3011  // false, then an sret argument may be implicitly inserted in the SelDAG. In
3012  // either case FuncInfo->setSRetReturnReg() will have been called.
3013  if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
3014  // When we have both sret and another return value, we should use the
3015  // original Chain stored in RetOps[0], instead of the current Chain updated
3016  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
3017 
3018  // For the case of sret and another return value, we have
3019  // Chain_0 at the function entry
3020  // Chain_1 = getCopyToReg(Chain_0) in the above loop
3021  // If we use Chain_1 in getCopyFromReg, we will have
3022  // Val = getCopyFromReg(Chain_1)
3023  // Chain_2 = getCopyToReg(Chain_1, Val) from below
3024 
3025  // getCopyToReg(Chain_0) will be glued together with
3026  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
3027  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
3028  // Data dependency from Unit B to Unit A due to usage of Val in
3029  // getCopyToReg(Chain_1, Val)
3030  // Chain dependency from Unit A to Unit B
3031 
3032  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
3033  SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg,
3034  getPointerTy(MF.getDataLayout()));
3035 
3036  Register RetValReg
3037  = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
3038  X86::RAX :