LLVM  15.0.0git
X86ISelLowering.cpp
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1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
16 #include "X86.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86IntrinsicsInfo.h"
21 #include "X86MachineFunctionInfo.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DerivedTypes.h"
47 #include "llvm/IR/DiagnosticInfo.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalAlias.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/IRBuilder.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/Intrinsics.h"
54 #include "llvm/IR/PatternMatch.h"
55 #include "llvm/MC/MCAsmInfo.h"
56 #include "llvm/MC/MCContext.h"
57 #include "llvm/MC/MCExpr.h"
58 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/KnownBits.h"
65 #include <algorithm>
66 #include <bitset>
67 #include <cctype>
68 #include <numeric>
69 using namespace llvm;
70 
71 #define DEBUG_TYPE "x86-isel"
72 
73 STATISTIC(NumTailCalls, "Number of tail calls");
74 
76  "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77  cl::desc(
78  "Sets the preferable loop alignment for experiments (as log2 bytes) "
79  "for innermost loops only. If specified, this option overrides "
80  "alignment set by x86-experimental-pref-loop-alignment."),
81  cl::Hidden);
82 
84  "mul-constant-optimization", cl::init(true),
85  cl::desc("Replace 'mul x, Const' with more effective instructions like "
86  "SHIFT, LEA, etc."),
87  cl::Hidden);
88 
90  "x86-experimental-unordered-atomic-isel", cl::init(false),
91  cl::desc("Use LoadSDNode and StoreSDNode instead of "
92  "AtomicSDNode for unordered atomic loads and "
93  "stores respectively."),
94  cl::Hidden);
95 
96 /// Call this when the user attempts to do something unsupported, like
97 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98 /// report_fatal_error, so calling code should attempt to recover without
99 /// crashing.
100 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101  const char *Msg) {
103  DAG.getContext()->diagnose(
105 }
106 
108  const X86Subtarget &STI)
109  : TargetLowering(TM), Subtarget(STI) {
110  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
112 
113  // Set up the TargetLowering object.
114 
115  // X86 is weird. It always uses i8 for shift amounts and setcc results.
117  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
119 
120  // For 64-bit, since we have so many registers, use the ILP scheduler.
121  // For 32-bit, use the register pressure specific scheduling.
122  // For Atom, always use ILP scheduling.
123  if (Subtarget.isAtom())
125  else if (Subtarget.is64Bit())
127  else
129  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
131 
132  // Bypass expensive divides and use cheaper ones.
133  if (TM.getOptLevel() >= CodeGenOpt::Default) {
134  if (Subtarget.hasSlowDivide32())
135  addBypassSlowDiv(32, 8);
136  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
137  addBypassSlowDiv(64, 32);
138  }
139 
140  // Setup Windows compiler runtime calls.
141  if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
142  static const struct {
143  const RTLIB::Libcall Op;
144  const char * const Name;
145  const CallingConv::ID CC;
146  } LibraryCalls[] = {
147  { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
148  { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
149  { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
150  { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
151  { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
152  };
153 
154  for (const auto &LC : LibraryCalls) {
155  setLibcallName(LC.Op, LC.Name);
156  setLibcallCallingConv(LC.Op, LC.CC);
157  }
158  }
159 
160  if (Subtarget.getTargetTriple().isOSMSVCRT()) {
161  // MSVCRT doesn't have powi; fall back to pow
162  setLibcallName(RTLIB::POWI_F32, nullptr);
163  setLibcallName(RTLIB::POWI_F64, nullptr);
164  }
165 
166  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
167  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
168  // FIXME: Should we be limiting the atomic size on other configs? Default is
169  // 1024.
170  if (!Subtarget.canUseCMPXCHG8B())
172 
173  // Set up the register classes.
174  addRegisterClass(MVT::i8, &X86::GR8RegClass);
175  addRegisterClass(MVT::i16, &X86::GR16RegClass);
176  addRegisterClass(MVT::i32, &X86::GR32RegClass);
177  if (Subtarget.is64Bit())
178  addRegisterClass(MVT::i64, &X86::GR64RegClass);
179 
180  for (MVT VT : MVT::integer_valuetypes())
182 
183  // We don't accept any truncstore of integer registers.
190 
192 
193  // SETOEQ and SETUNE require checking two conditions.
194  for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
197  }
198 
199  // Integer absolute.
200  if (Subtarget.canUseCMOV()) {
203  if (Subtarget.is64Bit())
205  }
206 
207  // Signed saturation subtraction.
211  if (Subtarget.is64Bit())
213 
214  // Funnel shifts.
215  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
216  // For slow shld targets we only lower for code size.
217  LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
218 
219  setOperationAction(ShiftOp , MVT::i8 , Custom);
220  setOperationAction(ShiftOp , MVT::i16 , Custom);
221  setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
222  if (Subtarget.is64Bit())
223  setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
224  }
225 
226  if (!Subtarget.useSoftFloat()) {
227  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
228  // operation.
233  // We have an algorithm for SSE2, and we turn this into a 64-bit
234  // FILD or VCVTUSI2SS/SD for other targets.
237  // We have an algorithm for SSE2->double, and we turn this into a
238  // 64-bit FILD followed by conditional FADD for other targets.
241 
242  // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
243  // this operation.
246  // SSE has no i16 to fp conversion, only i32. We promote in the handler
247  // to allow f80 to use i16 and f64 to use i16 with sse1 only
250  // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
253  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
254  // are Legal, f80 is custom lowered.
257 
258  // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
259  // this operation.
261  // FIXME: This doesn't generate invalid exception when it should. PR44019.
267  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
268  // are Legal, f80 is custom lowered.
271 
272  // Handle FP_TO_UINT by promoting the destination to a larger signed
273  // conversion.
275  // FIXME: This doesn't generate invalid exception when it should. PR44019.
278  // FIXME: This doesn't generate invalid exception when it should. PR44019.
284 
289 
290  if (!Subtarget.is64Bit()) {
293  }
294  }
295 
296  if (Subtarget.hasSSE2()) {
297  // Custom lowering for saturating float to int conversions.
298  // We handle promotion to larger result types manually.
299  for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
302  }
303  if (Subtarget.is64Bit()) {
306  }
307  }
308 
309  // Handle address space casts between mixed sized pointers.
312 
313  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
314  if (!Subtarget.hasSSE2()) {
317  if (Subtarget.is64Bit()) {
319  // Without SSE, i64->f64 goes through memory.
321  }
322  } else if (!Subtarget.is64Bit())
324 
325  // Scalar integer divide and remainder are lowered to use operations that
326  // produce two results, to match the available instructions. This exposes
327  // the two-result form to trivial CSE, which is able to combine x/y and x%y
328  // into a single instruction.
329  //
330  // Scalar integer multiply-high is also lowered to use two-result
331  // operations, to match the available instructions. However, plain multiply
332  // (low) operations are left as Legal, as there are single-result
333  // instructions for this in x86. Using the two-result multiply instructions
334  // when both high and low results are needed must be arranged by dagcombine.
335  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
342  }
343 
346  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
350  }
351  if (Subtarget.is64Bit())
356 
361 
362  if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
365  }
366 
367  // Promote the i8 variants and force them on up to i32 which has a shorter
368  // encoding.
371 
372  if (Subtarget.hasBMI()) {
373  // Promote the i16 zero undef variant and force it on up to i32 when tzcnt
374  // is enabled.
376  } else {
381  if (Subtarget.is64Bit()) {
384  }
385  }
386 
387  if (Subtarget.hasLZCNT()) {
388  // When promoting the i8 variants, force them to i32 for a shorter
389  // encoding.
392  } else {
393  for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
394  if (VT == MVT::i64 && !Subtarget.is64Bit())
395  continue;
398  }
399  }
400 
403  // Special handling for half-precision floating point conversions.
404  // If we don't have F16C support, then lower half float conversions
405  // into library calls.
407  Op, MVT::f32,
408  (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
409  // There's never any support for operations beyond MVT::f32.
413  }
414 
415  for (MVT VT : {MVT::f32, MVT::f64, MVT::f80, MVT::f128}) {
420 
423  }
424 
428  if (Subtarget.is64Bit())
430  if (Subtarget.hasPOPCNT()) {
432  // popcntw is longer to encode than popcntl and also has a false dependency
433  // on the dest that popcntl hasn't had since Cannon Lake.
435  } else {
439  if (Subtarget.is64Bit())
441  else
443  }
444 
446 
447  if (!Subtarget.hasMOVBE())
449 
450  // X86 wants to expand cmov itself.
451  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
456  }
457  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
458  if (VT == MVT::i64 && !Subtarget.is64Bit())
459  continue;
462  }
463 
464  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
467 
469  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
470  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
474  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
475  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
476 
477  // Darwin ABI issue.
478  for (auto VT : { MVT::i32, MVT::i64 }) {
479  if (VT == MVT::i64 && !Subtarget.is64Bit())
480  continue;
487  }
488 
489  // 64-bit shl, sra, srl (iff 32-bit x86)
490  for (auto VT : { MVT::i32, MVT::i64 }) {
491  if (VT == MVT::i64 && !Subtarget.is64Bit())
492  continue;
496  }
497 
498  if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
500 
502 
503  // Expand certain atomics
504  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
512  }
513 
514  if (!Subtarget.is64Bit())
516 
517  if (Subtarget.canUseCMPXCHG16B())
519 
520  // FIXME - use subtarget debug flags
521  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
522  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
523  TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
525  }
526 
529 
532 
535  if (Subtarget.isTargetPS())
537  else
539 
540  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
543  bool Is64Bit = Subtarget.is64Bit();
546 
549 
551 
552  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
555 
557 
558  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
559  // f16, f32 and f64 use SSE.
560  // Set up the FP register classes.
561  addRegisterClass(MVT::f16, Subtarget.hasAVX512() ? &X86::FR16XRegClass
562  : &X86::FR16RegClass);
563  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
564  : &X86::FR32RegClass);
565  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
566  : &X86::FR64RegClass);
567 
568  // Disable f32->f64 extload as we can only generate this in one instruction
569  // under optsize. So its easier to pattern match (fpext (load)) for that
570  // case instead of needing to emit 2 instructions for extload in the
571  // non-optsize case.
573 
574  for (auto VT : { MVT::f32, MVT::f64 }) {
575  // Use ANDPD to simulate FABS.
577 
578  // Use XORP to simulate FNEG.
580 
581  // Use ANDPD and ORPD to simulate FCOPYSIGN.
583 
584  // These might be better off as horizontal vector ops.
587 
588  // We don't support sin/cos/fmod
592  }
593 
594  // Half type will be promoted by default.
633 
634  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
635  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
636 
637  // Lower this to MOVMSK plus an AND.
640 
641  } else if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1() &&
642  (UseX87 || Is64Bit)) {
643  // Use SSE for f32, x87 for f64.
644  // Set up the FP register classes.
645  addRegisterClass(MVT::f32, &X86::FR32RegClass);
646  if (UseX87)
647  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
648 
649  // Use ANDPS to simulate FABS.
651 
652  // Use XORP to simulate FNEG.
654 
655  if (UseX87)
657 
658  // Use ANDPS and ORPS to simulate FCOPYSIGN.
659  if (UseX87)
662 
663  // We don't support sin/cos/fmod
667 
668  if (UseX87) {
669  // Always expand sin/cos functions even though x87 has an instruction.
673  }
674  } else if (UseX87) {
675  // f32 and f64 in x87.
676  // Set up the FP register classes.
677  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
678  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
679 
680  for (auto VT : { MVT::f32, MVT::f64 }) {
683 
684  // Always expand sin/cos functions even though x87 has an instruction.
688  }
689  }
690 
691  // Expand FP32 immediates into loads from the stack, save special cases.
692  if (isTypeLegal(MVT::f32)) {
693  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
694  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
695  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
696  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
697  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
698  } else // SSE immediates.
699  addLegalFPImmediate(APFloat(+0.0f)); // xorps
700  }
701  // Expand FP64 immediates into loads from the stack, save special cases.
702  if (isTypeLegal(MVT::f64)) {
703  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
704  addLegalFPImmediate(APFloat(+0.0)); // FLD0
705  addLegalFPImmediate(APFloat(+1.0)); // FLD1
706  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708  } else // SSE immediates.
709  addLegalFPImmediate(APFloat(+0.0)); // xorpd
710  }
711  // Support fp16 0 immediate.
712  if (isTypeLegal(MVT::f16))
713  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
714 
715  // Handle constrained floating-point operations of scalar.
728 
729  // We don't support FMA.
732 
733  // f80 always uses X87.
734  if (UseX87) {
735  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
738  {
740  addLegalFPImmediate(TmpFlt); // FLD0
741  TmpFlt.changeSign();
742  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
743 
744  bool ignored;
745  APFloat TmpFlt2(+1.0);
747  &ignored);
748  addLegalFPImmediate(TmpFlt2); // FLD1
749  TmpFlt2.changeSign();
750  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
751  }
752 
753  // Always expand sin/cos functions even though x87 has an instruction.
757 
768 
769  // Handle constrained floating-point operations of scalar.
775  if (isTypeLegal(MVT::f16)) {
778  } else {
780  }
781  // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
782  // as Custom.
784  }
785 
786  // f128 uses xmm registers, but most operations require libcalls.
787  if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
788  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
789  : &X86::VR128RegClass);
790 
791  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
792 
803 
807 
813  // No STRICT_FSINCOS
816 
819  // We need to custom handle any FP_ROUND with an f128 input, but
820  // LegalizeDAG uses the result type to know when to run a custom handler.
821  // So we have to list all legal floating point result types here.
822  if (isTypeLegal(MVT::f32)) {
825  }
826  if (isTypeLegal(MVT::f64)) {
829  }
830  if (isTypeLegal(MVT::f80)) {
833  }
834 
836 
843  }
844 
845  // Always use a library call for pow.
850 
858 
859  // Some FP actions are always expanded for vector types.
860  for (auto VT : { MVT::v8f16, MVT::v16f16, MVT::v32f16,
874  }
875 
876  // First set operation action for all vector types to either promote
877  // (for widening) or expand (for scalarization). Then we will selectively
878  // turn on ones that can be effectively codegen'd.
879  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
917  for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
918  setTruncStoreAction(InnerVT, VT, Expand);
919 
920  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
921  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
922 
923  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
924  // types, we have to deal with them whether we ask for Expansion or not.
925  // Setting Expand causes its own optimisation problems though, so leave
926  // them legal.
927  if (VT.getVectorElementType() == MVT::i1)
928  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
929 
930  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
931  // split/scalarized right now.
932  if (VT.getVectorElementType() == MVT::f16 ||
933  VT.getVectorElementType() == MVT::bf16)
934  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
935  }
936  }
937 
938  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
939  // with -msoft-float, disable use of MMX as well.
940  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
941  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
942  // No operations on x86mmx supported, everything uses intrinsics.
943  }
944 
945  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
946  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
947  : &X86::VR128RegClass);
948 
957 
960 
966  }
967 
968  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
969  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
970  : &X86::VR128RegClass);
971 
972  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
973  // registers cannot be used even for integer operations.
974  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
975  : &X86::VR128RegClass);
976  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
977  : &X86::VR128RegClass);
978  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
979  : &X86::VR128RegClass);
980  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
981  : &X86::VR128RegClass);
982 
983  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
989  }
990 
994 
1007 
1010 
1014 
1015  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1020  }
1021 
1032 
1037 
1038  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1044 
1045  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1046  // setcc all the way to isel and prefer SETGT in some isel patterns.
1049  }
1050 
1051  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1057  }
1058 
1059  for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1063 
1064  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1065  continue;
1066 
1069  }
1070 
1071  // Custom lower v2i64 and v2f64 selects.
1077 
1084 
1085  // Custom legalize these to avoid over promotion or custom promotion.
1086  for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1091  }
1092 
1097 
1100 
1103 
1104  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1109 
1114 
1115  // We want to legalize this to an f64 load rather than an i64 load on
1116  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1117  // store.
1124 
1128  if (!Subtarget.hasAVX512())
1130 
1134 
1136 
1143 
1144  // In the customized shift lowering, the legal v4i32/v2i64 cases
1145  // in AVX2 will be recognized.
1146  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1150  if (VT == MVT::v2i64) continue;
1155  }
1156 
1162  }
1163 
1164  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1173 
1174  // These might be better off as horizontal vector ops.
1179  }
1180 
1181  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1182  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1183  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1185  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1187  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1189  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1195 
1196  setOperationAction(ISD::FROUND, RoundedTy, Custom);
1197  }
1198 
1207 
1211 
1212  // FIXME: Do we need to handle scalar-to-vector here?
1214 
1215  // We directly match byte blends in the backend as they match the VSELECT
1216  // condition form.
1218 
1219  // SSE41 brings specific instructions for doing vector sign extend even in
1220  // cases where we don't have SRA.
1221  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1224  }
1225 
1226  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1227  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1234  }
1235 
1236  if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1237  // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1238  // do the pre and post work in the vector domain.
1241  // We need to mark SINT_TO_FP as Custom even though we want to expand it
1242  // so that DAG combine doesn't try to turn it into uint_to_fp.
1245  }
1246  }
1247 
1248  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1250  }
1251 
1252  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1253  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1257  }
1258 
1259  // XOP can efficiently perform BITREVERSE with VPPERM.
1260  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1262 
1263  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1266  }
1267 
1268  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1269  bool HasInt256 = Subtarget.hasInt256();
1270 
1271  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1272  : &X86::VR256RegClass);
1273  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1274  : &X86::VR256RegClass);
1275  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1276  : &X86::VR256RegClass);
1277  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1278  : &X86::VR256RegClass);
1279  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1280  : &X86::VR256RegClass);
1281  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1282  : &X86::VR256RegClass);
1283 
1284  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1297 
1299 
1303  }
1304 
1305  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1306  // even though v8i16 is a legal type.
1314 
1317 
1330 
1331  if (!Subtarget.hasAVX512())
1333 
1334  // In the customized shift lowering, the legal v8i32/v4i64 cases
1335  // in AVX2 will be recognized.
1336  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1340  if (VT == MVT::v4i64) continue;
1345  }
1346 
1347  // These types need custom splitting if their input is a 128-bit vector.
1352 
1359 
1360  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1364  }
1365 
1370 
1371  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1377 
1378  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1379  // setcc all the way to isel and prefer SETGT in some isel patterns.
1382  }
1383 
1384  if (Subtarget.hasAnyFMA()) {
1385  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1386  MVT::v2f64, MVT::v4f64 }) {
1389  }
1390  }
1391 
1392  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1393  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1394  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1395  }
1396 
1401 
1410 
1413 
1419 
1432 
1433  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1434  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1435  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1436  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1437  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1438  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1439  }
1440 
1441  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1444  }
1445 
1446  if (HasInt256) {
1447  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1448  // when we have a 256bit-wide blend with immediate.
1451 
1452  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1453  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1460  }
1461  }
1462 
1463  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1465  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1467  }
1468 
1469  // Extract subvector is special because the value type
1470  // (result) is 128-bit but the source is 256-bit wide.
1471  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1472  MVT::v4f32, MVT::v2f64 }) {
1474  }
1475 
1476  // Custom lower several nodes for 256-bit types.
1478  MVT::v8f32, MVT::v4f64 }) {
1488  }
1489 
1490  if (HasInt256) {
1492 
1493  // Custom legalize 2x32 to get a little better code.
1496 
1497  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1500  }
1501  }
1502 
1503  if (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) {
1508  }
1509 
1510  // This block controls legalization of the mask vector sizes that are
1511  // available with AVX512. 512-bit vectors are in a separate block controlled
1512  // by useAVX512Regs.
1513  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1514  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1515  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1516  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1517  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1518  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1519 
1523 
1536 
1537  // There is no byte sized k-register load or store without AVX512DQ.
1538  if (!Subtarget.hasDQI()) {
1543 
1548  }
1549 
1550  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1551  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1555  }
1556 
1557  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1559 
1560  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1566 
1573  }
1574 
1575  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1577  }
1578 
1579  // This block controls legalization for 512-bit operations with 32/64 bit
1580  // elements. 512-bits can be disabled based on prefer-vector-width and
1581  // required-vector-width function attributes.
1582  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1583  bool HasBWI = Subtarget.hasBWI();
1584 
1585  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1586  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1587  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1588  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1589  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1591 
1592  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1598  if (HasBWI)
1600  }
1601 
1602  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1608  }
1609 
1610  for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1615  }
1624 
1637 
1643  if (HasBWI)
1645 
1646  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1647  // to 512-bit rather than use the AVX2 instructions so that we can use
1648  // k-masks.
1649  if (!Subtarget.hasVLX()) {
1650  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1654  }
1655  }
1656 
1670 
1671  if (HasBWI) {
1672  // Extends from v64i1 masks to 512-bit vectors.
1676  }
1677 
1678  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1691 
1693  }
1694 
1695  for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1698  }
1699 
1704 
1709 
1718 
1721 
1723 
1724  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1731 
1732  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1733  // setcc all the way to isel and prefer SETGT in some isel patterns.
1736  }
1737  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1746  }
1747 
1748  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1749  setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1750  setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1752  setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1753  setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1754  setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1755  setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1756  setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1757  setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1758  setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1759  setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1760  }
1761 
1768 
1769  if (Subtarget.hasDQI()) {
1778 
1780  }
1781 
1782  if (Subtarget.hasCDI()) {
1783  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1784  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1786  }
1787  } // Subtarget.hasCDI()
1788 
1789  if (Subtarget.hasVPOPCNTDQ()) {
1790  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1792  }
1793 
1794  // Extract subvector is special because the value type
1795  // (result) is 256-bit but the source is 512-bit wide.
1796  // 128-bit was made Legal under AVX1.
1797  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1800 
1801  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1802  MVT::v16f32, MVT::v8f64 }) {
1812  }
1813 
1814  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1819  }
1820  if (HasBWI) {
1821  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1824  }
1825  } else {
1828  }
1829 
1830  if (Subtarget.hasVBMI2()) {
1831  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1836  }
1837 
1842  }
1843  }// useAVX512Regs
1844 
1845  // This block controls legalization for operations that don't have
1846  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1847  // narrower widths.
1848  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1849  // These operations are handled on non-VLX by artificially widening in
1850  // isel patterns.
1851 
1853  Subtarget.hasVLX() ? Legal : Custom);
1855  Subtarget.hasVLX() ? Legal : Custom);
1857  Subtarget.hasVLX() ? Legal : Custom);
1859  Subtarget.hasVLX() ? Legal : Custom);
1862  Subtarget.hasVLX() ? Legal : Custom);
1864  Subtarget.hasVLX() ? Legal : Custom);
1866  Subtarget.hasVLX() ? Legal : Custom);
1868  Subtarget.hasVLX() ? Legal : Custom);
1869 
1870  if (Subtarget.hasDQI()) {
1871  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1872  // v2f32 UINT_TO_FP is already custom under SSE2.
1875  "Unexpected operation action!");
1876  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1881  }
1882 
1883  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1889  }
1890 
1891  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1894  }
1895 
1896  // Custom legalize 2x32 to get a little better code.
1899 
1900  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1903 
1904  if (Subtarget.hasDQI()) {
1905  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1907  Subtarget.hasVLX() ? Legal : Custom);
1909  Subtarget.hasVLX() ? Legal : Custom);
1911  Subtarget.hasVLX() ? Legal : Custom);
1913  Subtarget.hasVLX() ? Legal : Custom);
1915  Subtarget.hasVLX() ? Legal : Custom);
1917  Subtarget.hasVLX() ? Legal : Custom);
1919  Subtarget.hasVLX() ? Legal : Custom);
1921  Subtarget.hasVLX() ? Legal : Custom);
1923  }
1924  }
1925 
1926  if (Subtarget.hasCDI()) {
1927  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1929  }
1930  } // Subtarget.hasCDI()
1931 
1932  if (Subtarget.hasVPOPCNTDQ()) {
1933  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1935  }
1936  }
1937 
1938  // This block control legalization of v32i1/v64i1 which are available with
1939  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1940  // useBWIRegs.
1941  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1942  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1943  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1944 
1945  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1956  }
1957 
1958  for (auto VT : { MVT::v16i1, MVT::v32i1 })
1960 
1961  // Extends from v32i1 masks to 256-bit vectors.
1965 
1966  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1967  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1968  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1969  }
1970 
1971  // These operations are handled on non-VLX by artificially widening in
1972  // isel patterns.
1973  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1974 
1975  if (Subtarget.hasBITALG()) {
1976  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1978  }
1979  }
1980 
1981  if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
1982  auto setGroup = [&] (MVT VT) {
1993 
2004 
2007 
2013 
2019  };
2020 
2021  // AVX512_FP16 scalar operations
2022  setGroup(MVT::f16);
2023  addRegisterClass(MVT::f16, &X86::FR16XRegClass);
2038 
2041 
2042  if (Subtarget.useAVX512Regs()) {
2043  setGroup(MVT::v32f16);
2044  addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
2053 
2060  MVT::v32i16);
2063  MVT::v32i16);
2066  MVT::v32i16);
2069  MVT::v32i16);
2070 
2074 
2077 
2080  }
2081 
2082  if (Subtarget.hasVLX()) {
2083  addRegisterClass(MVT::v8f16, &X86::VR128XRegClass);
2084  addRegisterClass(MVT::v16f16, &X86::VR256XRegClass);
2085  setGroup(MVT::v8f16);
2086  setGroup(MVT::v16f16);
2087 
2098 
2105 
2106  // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2109 
2113 
2118 
2119  // Need to custom widen these to prevent scalarization.
2122  }
2123  }
2124 
2125  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2131 
2137 
2138  if (Subtarget.hasBWI()) {
2141  }
2142 
2143  if (Subtarget.hasFP16()) {
2144  // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2153  // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2162  // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2167  // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2172  }
2173 
2177  }
2178 
2179  if (Subtarget.hasAMXTILE()) {
2180  addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2181  }
2182 
2183  // We want to custom lower some of our intrinsics.
2187  if (!Subtarget.is64Bit()) {
2189  }
2190 
2191  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2192  // handle type legalization for these operations here.
2193  //
2194  // FIXME: We really should do custom legalization for addition and
2195  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2196  // than generic legalization for 64-bit multiplication-with-overflow, though.
2197  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2198  if (VT == MVT::i64 && !Subtarget.is64Bit())
2199  continue;
2200  // Add/Sub/Mul with overflow operations are custom lowered.
2207 
2208  // Support carry in as value rather than glue.
2214  }
2215 
2216  if (!Subtarget.is64Bit()) {
2217  // These libcalls are not available in 32-bit.
2218  setLibcallName(RTLIB::SHL_I128, nullptr);
2219  setLibcallName(RTLIB::SRL_I128, nullptr);
2220  setLibcallName(RTLIB::SRA_I128, nullptr);
2221  setLibcallName(RTLIB::MUL_I128, nullptr);
2222  // The MULO libcall is not part of libgcc, only compiler-rt.
2223  setLibcallName(RTLIB::MULO_I64, nullptr);
2224  }
2225  // The MULO libcall is not part of libgcc, only compiler-rt.
2226  setLibcallName(RTLIB::MULO_I128, nullptr);
2227 
2228  // Combine sin / cos into _sincos_stret if it is available.
2229  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2230  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2233  }
2234 
2235  if (Subtarget.isTargetWin64()) {
2248  }
2249 
2250  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2251  // is. We should promote the value to 64-bits to solve this.
2252  // This is what the CRT headers do - `fmodf` is an inline header
2253  // function casting to f64 and calling `fmod`.
2254  if (Subtarget.is32Bit() &&
2255  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2256  for (ISD::NodeType Op :
2268 
2269  // We have target-specific dag combine patterns for the following nodes:
2277  ISD::BITCAST,
2278  ISD::VSELECT,
2279  ISD::SELECT,
2280  ISD::SHL,
2281  ISD::SRA,
2282  ISD::SRL,
2283  ISD::OR,
2284  ISD::AND,
2285  ISD::ADD,
2286  ISD::FADD,
2287  ISD::FSUB,
2288  ISD::FNEG,
2289  ISD::FMA,
2291  ISD::FMINNUM,
2292  ISD::FMAXNUM,
2293  ISD::SUB,
2294  ISD::LOAD,
2295  ISD::MLOAD,
2296  ISD::STORE,
2297  ISD::MSTORE,
2298  ISD::TRUNCATE,
2310  ISD::SETCC,
2311  ISD::MUL,
2312  ISD::XOR,
2313  ISD::MSCATTER,
2314  ISD::MGATHER,
2318  ISD::FP_ROUND});
2319 
2321 
2322  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2324  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2326  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2328 
2329  // TODO: These control memcmp expansion in CGP and could be raised higher, but
2330  // that needs to benchmarked and balanced with the potential use of vector
2331  // load/store types (PR33329, PR33914).
2332  MaxLoadsPerMemcmp = 2;
2334 
2335  // Default loop alignment, which can be overridden by -align-loops.
2337 
2338  // An out-of-order CPU can speculatively execute past a predictable branch,
2339  // but a conditional move could be stalled by an expensive earlier operation.
2340  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2341  EnableExtLdPromotion = true;
2343 
2345 
2346  // Default to having -disable-strictnode-mutation on
2347  IsStrictFPEnabled = true;
2348 }
2349 
2350 // This has so far only been implemented for 64-bit MachO.
2352  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2353 }
2354 
2356  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2357  return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2358 }
2359 
2361  const SDLoc &DL) const {
2362  EVT PtrTy = getPointerTy(DAG.getDataLayout());
2363  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2364  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2365  return SDValue(Node, 0);
2366 }
2367 
2370  if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2371  !Subtarget.hasBWI())
2372  return TypeSplitVector;
2373 
2374  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2375  VT.getVectorElementType() != MVT::i1)
2376  return TypeWidenVector;
2377 
2379 }
2380 
2381 static std::pair<MVT, unsigned>
2383  const X86Subtarget &Subtarget) {
2384  // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2385  // convention is one that uses k registers.
2386  if (NumElts == 2)
2387  return {MVT::v2i64, 1};
2388  if (NumElts == 4)
2389  return {MVT::v4i32, 1};
2390  if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2392  return {MVT::v8i16, 1};
2393  if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2395  return {MVT::v16i8, 1};
2396  // v32i1 passes in ymm unless we have BWI and the calling convention is
2397  // regcall.
2398  if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2399  return {MVT::v32i8, 1};
2400  // Split v64i1 vectors if we don't have v64i8 available.
2401  if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2402  if (Subtarget.useAVX512Regs())
2403  return {MVT::v64i8, 1};
2404  return {MVT::v32i8, 2};
2405  }
2406 
2407  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2408  if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2409  NumElts > 64)
2410  return {MVT::i8, NumElts};
2411 
2412  return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2413 }
2414 
2416  CallingConv::ID CC,
2417  EVT VT) const {
2418  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2419  Subtarget.hasAVX512()) {
2420  unsigned NumElts = VT.getVectorNumElements();
2421 
2422  MVT RegisterVT;
2423  unsigned NumRegisters;
2424  std::tie(RegisterVT, NumRegisters) =
2425  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2426  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2427  return RegisterVT;
2428  }
2429 
2430  // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2431  // So its default register type is f16. We override the type to v8f16 here.
2432  if (VT == MVT::v3f16 && Subtarget.hasFP16())
2433  return MVT::v8f16;
2434 
2435  // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
2436  if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
2437  !Subtarget.hasX87())
2438  return MVT::i32;
2439 
2441 }
2442 
2444  CallingConv::ID CC,
2445  EVT VT) const {
2446  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2447  Subtarget.hasAVX512()) {
2448  unsigned NumElts = VT.getVectorNumElements();
2449 
2450  MVT RegisterVT;
2451  unsigned NumRegisters;
2452  std::tie(RegisterVT, NumRegisters) =
2453  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2454  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2455  return NumRegisters;
2456  }
2457 
2458  // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2459  // So its default register number is 3. We override the number to 1 here.
2460  if (VT == MVT::v3f16 && Subtarget.hasFP16())
2461  return 1;
2462 
2463  // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
2464  // x87 is disabled.
2465  if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
2466  if (VT == MVT::f64)
2467  return 2;
2468  if (VT == MVT::f80)
2469  return 3;
2470  }
2471 
2473 }
2474 
2476  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2477  unsigned &NumIntermediates, MVT &RegisterVT) const {
2478  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2479  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2480  Subtarget.hasAVX512() &&
2482  (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2483  VT.getVectorNumElements() > 64)) {
2484  RegisterVT = MVT::i8;
2485  IntermediateVT = MVT::i1;
2486  NumIntermediates = VT.getVectorNumElements();
2487  return NumIntermediates;
2488  }
2489 
2490  // Split v64i1 vectors if we don't have v64i8 available.
2491  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2492  CC != CallingConv::X86_RegCall) {
2493  RegisterVT = MVT::v32i8;
2494  IntermediateVT = MVT::v32i1;
2495  NumIntermediates = 2;
2496  return 2;
2497  }
2498 
2499  return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2500  NumIntermediates, RegisterVT);
2501 }
2502 
2505  EVT VT) const {
2506  if (!VT.isVector())
2507  return MVT::i8;
2508 
2509  if (Subtarget.hasAVX512()) {
2510  // Figure out what this type will be legalized to.
2511  EVT LegalVT = VT;
2512  while (getTypeAction(Context, LegalVT) != TypeLegal)
2513  LegalVT = getTypeToTransformTo(Context, LegalVT);
2514 
2515  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2516  if (LegalVT.getSimpleVT().is512BitVector())
2518 
2519  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2520  // If we legalized to less than a 512-bit vector, then we will use a vXi1
2521  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2522  // vXi16/vXi8.
2523  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2524  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2526  }
2527  }
2528 
2530 }
2531 
2532 /// Helper for getByValTypeAlignment to determine
2533 /// the desired ByVal argument alignment.
2534 static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2535  if (MaxAlign == 16)
2536  return;
2537  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2538  if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2539  MaxAlign = Align(16);
2540  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2541  Align EltAlign;
2542  getMaxByValAlign(ATy->getElementType(), EltAlign);
2543  if (EltAlign > MaxAlign)
2544  MaxAlign = EltAlign;
2545  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2546  for (auto *EltTy : STy->elements()) {
2547  Align EltAlign;
2548  getMaxByValAlign(EltTy, EltAlign);
2549  if (EltAlign > MaxAlign)
2550  MaxAlign = EltAlign;
2551  if (MaxAlign == 16)
2552  break;
2553  }
2554  }
2555 }
2556 
2557 /// Return the desired alignment for ByVal aggregate
2558 /// function arguments in the caller parameter area. For X86, aggregates
2559 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2560 /// are at 4-byte boundaries.
2562  const DataLayout &DL) const {
2563  if (Subtarget.is64Bit()) {
2564  // Max of 8 and alignment of type.
2565  Align TyAlign = DL.getABITypeAlign(Ty);
2566  if (TyAlign > 8)
2567  return TyAlign.value();
2568  return 8;
2569  }
2570 
2571  Align Alignment(4);
2572  if (Subtarget.hasSSE1())
2573  getMaxByValAlign(Ty, Alignment);
2574  return Alignment.value();
2575 }
2576 
2577 /// It returns EVT::Other if the type should be determined using generic
2578 /// target-independent logic.
2579 /// For vector ops we check that the overall size isn't larger than our
2580 /// preferred vector width.
2582  const MemOp &Op, const AttributeList &FuncAttributes) const {
2583  if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2584  if (Op.size() >= 16 &&
2585  (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2586  // FIXME: Check if unaligned 64-byte accesses are slow.
2587  if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2588  (Subtarget.getPreferVectorWidth() >= 512)) {
2589  return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2590  }
2591  // FIXME: Check if unaligned 32-byte accesses are slow.
2592  if (Op.size() >= 32 && Subtarget.hasAVX() &&
2593  (Subtarget.getPreferVectorWidth() >= 256)) {
2594  // Although this isn't a well-supported type for AVX1, we'll let
2595  // legalization and shuffle lowering produce the optimal codegen. If we
2596  // choose an optimal type with a vector element larger than a byte,
2597  // getMemsetStores() may create an intermediate splat (using an integer
2598  // multiply) before we splat as a vector.
2599  return MVT::v32i8;
2600  }
2601  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2602  return MVT::v16i8;
2603  // TODO: Can SSE1 handle a byte vector?
2604  // If we have SSE1 registers we should be able to use them.
2605  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2606  (Subtarget.getPreferVectorWidth() >= 128))
2607  return MVT::v4f32;
2608  } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2609  Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2610  // Do not use f64 to lower memcpy if source is string constant. It's
2611  // better to use i32 to avoid the loads.
2612  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2613  // The gymnastics of splatting a byte value into an XMM register and then
2614  // only using 8-byte stores (because this is a CPU with slow unaligned
2615  // 16-byte accesses) makes that a loser.
2616  return MVT::f64;
2617  }
2618  }
2619  // This is a compromise. If we reach here, unaligned accesses may be slow on
2620  // this target. However, creating smaller, aligned accesses could be even
2621  // slower and would certainly be a lot more code.
2622  if (Subtarget.is64Bit() && Op.size() >= 8)
2623  return MVT::i64;
2624  return MVT::i32;
2625 }
2626 
2628  if (VT == MVT::f32)
2629  return Subtarget.hasSSE1();
2630  if (VT == MVT::f64)
2631  return Subtarget.hasSSE2();
2632  return true;
2633 }
2634 
2636  EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2637  bool *Fast) const {
2638  if (Fast) {
2639  switch (VT.getSizeInBits()) {
2640  default:
2641  // 8-byte and under are always assumed to be fast.
2642  *Fast = true;
2643  break;
2644  case 128:
2645  *Fast = !Subtarget.isUnalignedMem16Slow();
2646  break;
2647  case 256:
2648  *Fast = !Subtarget.isUnalignedMem32Slow();
2649  break;
2650  // TODO: What about AVX-512 (512-bit) accesses?
2651  }
2652  }
2653  // NonTemporal vector memory ops must be aligned.
2654  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2655  // NT loads can only be vector aligned, so if its less aligned than the
2656  // minimum vector size (which we can split the vector down to), we might as
2657  // well use a regular unaligned vector load.
2658  // We don't have any NT loads pre-SSE41.
2659  if (!!(Flags & MachineMemOperand::MOLoad))
2660  return (Alignment < 16 || !Subtarget.hasSSE41());
2661  return false;
2662  }
2663  // Misaligned accesses of any size are always allowed.
2664  return true;
2665 }
2666 
2667 /// Return the entry encoding for a jump table in the
2668 /// current function. The returned value is a member of the
2669 /// MachineJumpTableInfo::JTEntryKind enum.
2671  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2672  // symbol.
2673  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2675 
2676  // Otherwise, use the normal jump table encoding heuristics.
2678 }
2679 
2681  return Subtarget.useSoftFloat();
2682 }
2683 
2685  ArgListTy &Args) const {
2686 
2687  // Only relabel X86-32 for C / Stdcall CCs.
2688  if (Subtarget.is64Bit())
2689  return;
2690  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2691  return;
2692  unsigned ParamRegs = 0;
2693  if (auto *M = MF->getFunction().getParent())
2694  ParamRegs = M->getNumberRegisterParameters();
2695 
2696  // Mark the first N int arguments as having reg
2697  for (auto &Arg : Args) {
2698  Type *T = Arg.Ty;
2699  if (T->isIntOrPtrTy())
2700  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2701  unsigned numRegs = 1;
2702  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2703  numRegs = 2;
2704  if (ParamRegs < numRegs)
2705  return;
2706  ParamRegs -= numRegs;
2707  Arg.IsInReg = true;
2708  }
2709  }
2710 }
2711 
2712 const MCExpr *
2714  const MachineBasicBlock *MBB,
2715  unsigned uid,MCContext &Ctx) const{
2716  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2717  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2718  // entries.
2721 }
2722 
2723 /// Returns relocation base for the given PIC jumptable.
2725  SelectionDAG &DAG) const {
2726  if (!Subtarget.is64Bit())
2727  // This doesn't have SDLoc associated with it, but is not really the
2728  // same as a Register.
2729  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2730  getPointerTy(DAG.getDataLayout()));
2731  return Table;
2732 }
2733 
2734 /// This returns the relocation base for the given PIC jumptable,
2735 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2738  MCContext &Ctx) const {
2739  // X86-64 uses RIP relative addressing based on the jump table label.
2740  if (Subtarget.isPICStyleRIPRel())
2741  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2742 
2743  // Otherwise, the reference is relative to the PIC base.
2744  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2745 }
2746 
2747 std::pair<const TargetRegisterClass *, uint8_t>
2749  MVT VT) const {
2750  const TargetRegisterClass *RRC = nullptr;
2751  uint8_t Cost = 1;
2752  switch (VT.SimpleTy) {
2753  default:
2755  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2756  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2757  break;
2758  case MVT::x86mmx:
2759  RRC = &X86::VR64RegClass;
2760  break;
2761  case MVT::f32: case MVT::f64:
2762  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2763  case MVT::v4f32: case MVT::v2f64:
2764  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2765  case MVT::v8f32: case MVT::v4f64:
2766  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2767  case MVT::v16f32: case MVT::v8f64:
2768  RRC = &X86::VR128XRegClass;
2769  break;
2770  }
2771  return std::make_pair(RRC, Cost);
2772 }
2773 
2774 unsigned X86TargetLowering::getAddressSpace() const {
2775  if (Subtarget.is64Bit())
2776  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2777  return 256;
2778 }
2779 
2780 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2781  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2782  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2783 }
2784 
2786  int Offset, unsigned AddressSpace) {
2790 }
2791 
2793  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2794  // tcbhead_t; use it instead of the usual global variable (see
2795  // sysdeps/{i386,x86_64}/nptl/tls.h)
2796  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2797  if (Subtarget.isTargetFuchsia()) {
2798  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2799  return SegmentOffset(IRB, 0x10, getAddressSpace());
2800  } else {
2801  unsigned AddressSpace = getAddressSpace();
2802  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2803  // Specially, some users may customize the base reg and offset.
2804  int Offset = M->getStackProtectorGuardOffset();
2805  // If we don't set -stack-protector-guard-offset value:
2806  // %fs:0x28, unless we're using a Kernel code model, in which case
2807  // it's %gs:0x28. gs:0x14 on i386.
2808  if (Offset == INT_MAX)
2809  Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2810 
2811  StringRef GuardReg = M->getStackProtectorGuardReg();
2812  if (GuardReg == "fs")
2814  else if (GuardReg == "gs")
2816  return SegmentOffset(IRB, Offset, AddressSpace);
2817  }
2818  }
2819  return TargetLowering::getIRStackGuard(IRB);
2820 }
2821 
2823  // MSVC CRT provides functionalities for stack protection.
2824  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2826  // MSVC CRT has a global variable holding security cookie.
2827  M.getOrInsertGlobal("__security_cookie",
2828  Type::getInt8PtrTy(M.getContext()));
2829 
2830  // MSVC CRT has a function to validate security cookie.
2831  FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2832  "__security_check_cookie", Type::getVoidTy(M.getContext()),
2833  Type::getInt8PtrTy(M.getContext()));
2834  if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2835  F->setCallingConv(CallingConv::X86_FastCall);
2836  F->addParamAttr(0, Attribute::AttrKind::InReg);
2837  }
2838  return;
2839  }
2840 
2841  StringRef GuardMode = M.getStackProtectorGuard();
2842 
2843  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2844  if ((GuardMode == "tls" || GuardMode.empty()) &&
2846  return;
2848 }
2849 
2851  // MSVC CRT has a global variable holding security cookie.
2852  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2854  return M.getGlobalVariable("__security_cookie");
2855  }
2857 }
2858 
2860  // MSVC CRT has a function to validate security cookie.
2861  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2863  return M.getFunction("__security_check_cookie");
2864  }
2866 }
2867 
2868 Value *
2870  if (Subtarget.getTargetTriple().isOSContiki())
2871  return getDefaultSafeStackPointerLocation(IRB, false);
2872 
2873  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2874  // definition of TLS_SLOT_SAFESTACK in
2875  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2876  if (Subtarget.isTargetAndroid()) {
2877  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2878  // %gs:0x24 on i386
2879  int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2880  return SegmentOffset(IRB, Offset, getAddressSpace());
2881  }
2882 
2883  // Fuchsia is similar.
2884  if (Subtarget.isTargetFuchsia()) {
2885  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2886  return SegmentOffset(IRB, 0x18, getAddressSpace());
2887  }
2888 
2890 }
2891 
2892 //===----------------------------------------------------------------------===//
2893 // Return Value Calling Convention Implementation
2894 //===----------------------------------------------------------------------===//
2895 
2896 bool X86TargetLowering::CanLowerReturn(
2897  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2898  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2900  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2901  return CCInfo.CheckReturn(Outs, RetCC_X86);
2902 }
2903 
2904 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2905  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2906  return ScratchRegs;
2907 }
2908 
2909 /// Lowers masks values (v*i1) to the local register values
2910 /// \returns DAG node after lowering to register type
2911 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2912  const SDLoc &Dl, SelectionDAG &DAG) {
2913  EVT ValVT = ValArg.getValueType();
2914 
2915  if (ValVT == MVT::v1i1)
2916  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2917  DAG.getIntPtrConstant(0, Dl));
2918 
2919  if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2920  (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2921  // Two stage lowering might be required
2922  // bitcast: v8i1 -> i8 / v16i1 -> i16
2923  // anyextend: i8 -> i32 / i16 -> i32
2924  EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2925  SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2926  if (ValLoc == MVT::i32)
2927  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2928  return ValToCopy;
2929  }
2930 
2931  if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2932  (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2933  // One stage lowering is required
2934  // bitcast: v32i1 -> i32 / v64i1 -> i64
2935  return DAG.getBitcast(ValLoc, ValArg);
2936  }
2937 
2938  return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2939 }
2940 
2941 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2943  const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2944  SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2945  CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2946  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
2947  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2948  assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
2949  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2950  "The value should reside in two registers");
2951 
2952  // Before splitting the value we cast it to i64
2953  Arg = DAG.getBitcast(MVT::i64, Arg);
2954 
2955  // Splitting the value into two i32 types
2956  SDValue Lo, Hi;
2957  Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2958  DAG.getConstant(0, Dl, MVT::i32));
2959  Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2960  DAG.getConstant(1, Dl, MVT::i32));
2961 
2962  // Attach the two i32 types into corresponding registers
2963  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2964  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2965 }
2966 
2967 SDValue
2968 X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2969  bool isVarArg,
2970  const SmallVectorImpl<ISD::OutputArg> &Outs,
2971  const SmallVectorImpl<SDValue> &OutVals,
2972  const SDLoc &dl, SelectionDAG &DAG) const {
2973  MachineFunction &MF = DAG.getMachineFunction();
2975 
2976  // In some cases we need to disable registers from the default CSR list.
2977  // For example, when they are used for argument passing.
2978  bool ShouldDisableCalleeSavedRegister =
2979  CallConv == CallingConv::X86_RegCall ||
2980  MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2981 
2982  if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2983  report_fatal_error("X86 interrupts may not return any value");
2984 
2986  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2987  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2988 
2990  for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2991  ++I, ++OutsIndex) {
2992  CCValAssign &VA = RVLocs[I];
2993  assert(VA.isRegLoc() && "Can only return in registers!");
2994 
2995  // Add the register to the CalleeSaveDisableRegs list.
2996  if (ShouldDisableCalleeSavedRegister)
2997  MF.getRegInfo().