LLVM  14.0.0git
X86ISelLowering.cpp
Go to the documentation of this file.
1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ISelLowering.h"
16 #include "X86.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86IntrinsicsInfo.h"
21 #include "X86MachineFunctionInfo.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DerivedTypes.h"
47 #include "llvm/IR/DiagnosticInfo.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalAlias.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/IRBuilder.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/Intrinsics.h"
54 #include "llvm/IR/PatternMatch.h"
55 #include "llvm/MC/MCAsmInfo.h"
56 #include "llvm/MC/MCContext.h"
57 #include "llvm/MC/MCExpr.h"
58 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/KnownBits.h"
65 #include <algorithm>
66 #include <bitset>
67 #include <cctype>
68 #include <numeric>
69 using namespace llvm;
70 
71 #define DEBUG_TYPE "x86-isel"
72 
73 STATISTIC(NumTailCalls, "Number of tail calls");
74 
76  "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
77  cl::desc(
78  "Sets the preferable loop alignment for experiments (as log2 bytes) "
79  "for innermost loops only. If specified, this option overrides "
80  "alignment set by x86-experimental-pref-loop-alignment."),
81  cl::Hidden);
82 
84  "mul-constant-optimization", cl::init(true),
85  cl::desc("Replace 'mul x, Const' with more effective instructions like "
86  "SHIFT, LEA, etc."),
87  cl::Hidden);
88 
90  "x86-experimental-unordered-atomic-isel", cl::init(false),
91  cl::desc("Use LoadSDNode and StoreSDNode instead of "
92  "AtomicSDNode for unordered atomic loads and "
93  "stores respectively."),
94  cl::Hidden);
95 
96 /// Call this when the user attempts to do something unsupported, like
97 /// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
98 /// report_fatal_error, so calling code should attempt to recover without
99 /// crashing.
100 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
101  const char *Msg) {
103  DAG.getContext()->diagnose(
105 }
106 
108  const X86Subtarget &STI)
109  : TargetLowering(TM), Subtarget(STI) {
110  bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
111  X86ScalarSSEf64 = Subtarget.hasSSE2();
112  X86ScalarSSEf32 = Subtarget.hasSSE1();
113  X86ScalarSSEf16 = Subtarget.hasFP16();
114  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
115 
116  // Set up the TargetLowering object.
117 
118  // X86 is weird. It always uses i8 for shift amounts and setcc results.
120  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
122 
123  // For 64-bit, since we have so many registers, use the ILP scheduler.
124  // For 32-bit, use the register pressure specific scheduling.
125  // For Atom, always use ILP scheduling.
126  if (Subtarget.isAtom())
128  else if (Subtarget.is64Bit())
130  else
132  const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
134 
135  // Bypass expensive divides and use cheaper ones.
136  if (TM.getOptLevel() >= CodeGenOpt::Default) {
137  if (Subtarget.hasSlowDivide32())
138  addBypassSlowDiv(32, 8);
139  if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
140  addBypassSlowDiv(64, 32);
141  }
142 
143  // Setup Windows compiler runtime calls.
144  if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) {
145  static const struct {
146  const RTLIB::Libcall Op;
147  const char * const Name;
148  const CallingConv::ID CC;
149  } LibraryCalls[] = {
150  { RTLIB::SDIV_I64, "_alldiv", CallingConv::X86_StdCall },
151  { RTLIB::UDIV_I64, "_aulldiv", CallingConv::X86_StdCall },
152  { RTLIB::SREM_I64, "_allrem", CallingConv::X86_StdCall },
153  { RTLIB::UREM_I64, "_aullrem", CallingConv::X86_StdCall },
154  { RTLIB::MUL_I64, "_allmul", CallingConv::X86_StdCall },
155  };
156 
157  for (const auto &LC : LibraryCalls) {
158  setLibcallName(LC.Op, LC.Name);
159  setLibcallCallingConv(LC.Op, LC.CC);
160  }
161  }
162 
163  if (Subtarget.getTargetTriple().isOSMSVCRT()) {
164  // MSVCRT doesn't have powi; fall back to pow
165  setLibcallName(RTLIB::POWI_F32, nullptr);
166  setLibcallName(RTLIB::POWI_F64, nullptr);
167  }
168 
169  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
170  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
171  // FIXME: Should we be limiting the atomic size on other configs? Default is
172  // 1024.
173  if (!Subtarget.hasCmpxchg8b())
175 
176  // Set up the register classes.
177  addRegisterClass(MVT::i8, &X86::GR8RegClass);
178  addRegisterClass(MVT::i16, &X86::GR16RegClass);
179  addRegisterClass(MVT::i32, &X86::GR32RegClass);
180  if (Subtarget.is64Bit())
181  addRegisterClass(MVT::i64, &X86::GR64RegClass);
182 
183  for (MVT VT : MVT::integer_valuetypes())
185 
186  // We don't accept any truncstore of integer registers.
193 
195 
196  // SETOEQ and SETUNE require checking two conditions.
197  for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
200  }
201 
202  // Integer absolute.
203  if (Subtarget.hasCMov()) {
206  if (Subtarget.is64Bit())
208  }
209 
210  // Signed saturation subtraction.
214  if (Subtarget.is64Bit())
216 
217  // Funnel shifts.
218  for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
219  // For slow shld targets we only lower for code size.
220  LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
221 
222  setOperationAction(ShiftOp , MVT::i8 , Custom);
223  setOperationAction(ShiftOp , MVT::i16 , Custom);
224  setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction);
225  if (Subtarget.is64Bit())
226  setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction);
227  }
228 
229  if (!Subtarget.useSoftFloat()) {
230  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
231  // operation.
236  // We have an algorithm for SSE2, and we turn this into a 64-bit
237  // FILD or VCVTUSI2SS/SD for other targets.
240  // We have an algorithm for SSE2->double, and we turn this into a
241  // 64-bit FILD followed by conditional FADD for other targets.
244 
245  // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
246  // this operation.
249  // SSE has no i16 to fp conversion, only i32. We promote in the handler
250  // to allow f80 to use i16 and f64 to use i16 with sse1 only
253  // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
256  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
257  // are Legal, f80 is custom lowered.
260 
261  // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
262  // this operation.
264  // FIXME: This doesn't generate invalid exception when it should. PR44019.
270  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
271  // are Legal, f80 is custom lowered.
274 
275  // Handle FP_TO_UINT by promoting the destination to a larger signed
276  // conversion.
278  // FIXME: This doesn't generate invalid exception when it should. PR44019.
281  // FIXME: This doesn't generate invalid exception when it should. PR44019.
287 
292 
293  if (!Subtarget.is64Bit()) {
296  }
297  }
298 
299  if (Subtarget.hasSSE2()) {
300  // Custom lowering for saturating float to int conversions.
301  // We handle promotion to larger result types manually.
302  for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
305  }
306  if (Subtarget.is64Bit()) {
309  }
310  }
311 
312  // Handle address space casts between mixed sized pointers.
315 
316  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
317  if (!X86ScalarSSEf64) {
320  if (Subtarget.is64Bit()) {
322  // Without SSE, i64->f64 goes through memory.
324  }
325  } else if (!Subtarget.is64Bit())
327 
328  // Scalar integer divide and remainder are lowered to use operations that
329  // produce two results, to match the available instructions. This exposes
330  // the two-result form to trivial CSE, which is able to combine x/y and x%y
331  // into a single instruction.
332  //
333  // Scalar integer multiply-high is also lowered to use two-result
334  // operations, to match the available instructions. However, plain multiply
335  // (low) operations are left as Legal, as there are single-result
336  // instructions for this in x86. Using the two-result multiply instructions
337  // when both high and low results are needed must be arranged by dagcombine.
338  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
345  }
346 
349  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128,
353  }
354  if (Subtarget.is64Bit())
359 
364 
365  if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
368  }
369 
370  // Promote the i8 variants and force them on up to i32 which has a shorter
371  // encoding.
374 
375  if (Subtarget.hasBMI()) {
376  // Promote the i16 zero undef variant and force it on up to i32 when tzcnt
377  // is enabled.
379  } else {
384  if (Subtarget.is64Bit()) {
387  }
388  }
389 
390  if (Subtarget.hasLZCNT()) {
391  // When promoting the i8 variants, force them to i32 for a shorter
392  // encoding.
395  } else {
396  for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
397  if (VT == MVT::i64 && !Subtarget.is64Bit())
398  continue;
401  }
402  }
403 
406  // Special handling for half-precision floating point conversions.
407  // If we don't have F16C support, then lower half float conversions
408  // into library calls.
410  Op, MVT::f32,
411  (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) ? Custom : Expand);
412  // There's never any support for operations beyond MVT::f32.
416  }
417 
426 
430  if (Subtarget.is64Bit())
432  if (Subtarget.hasPOPCNT()) {
434  // popcntw is longer to encode than popcntl and also has a false dependency
435  // on the dest that popcntl hasn't had since Cannon Lake.
437  } else {
441  if (Subtarget.is64Bit())
443  else
445  }
446 
448 
449  if (!Subtarget.hasMOVBE())
451 
452  // X86 wants to expand cmov itself.
453  for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
458  }
459  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
460  if (VT == MVT::i64 && !Subtarget.is64Bit())
461  continue;
464  }
465 
466  // Custom action for SELECT MMX and expand action for SELECT_CC MMX
469 
471  // NOTE: EH_SJLJ_SETJMP/_LONGJMP are not recommended, since
472  // LLVM/Clang supports zero-cost DWARF and SEH exception handling.
476  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
477  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
478 
479  // Darwin ABI issue.
480  for (auto VT : { MVT::i32, MVT::i64 }) {
481  if (VT == MVT::i64 && !Subtarget.is64Bit())
482  continue;
489  }
490 
491  // 64-bit shl, sra, srl (iff 32-bit x86)
492  for (auto VT : { MVT::i32, MVT::i64 }) {
493  if (VT == MVT::i64 && !Subtarget.is64Bit())
494  continue;
498  }
499 
500  if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow())
502 
504 
505  // Expand certain atomics
506  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
514  }
515 
516  if (!Subtarget.is64Bit())
518 
519  if (Subtarget.hasCmpxchg16b()) {
521  }
522 
523  // FIXME - use subtarget debug flags
524  if (!Subtarget.isTargetDarwin() && !Subtarget.isTargetELF() &&
525  !Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64() &&
526  TM.Options.ExceptionModel != ExceptionHandling::SjLj) {
528  }
529 
532 
535 
538  if (Subtarget.getTargetTriple().isPS4CPU())
540  else
542 
543  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
546  bool Is64Bit = Subtarget.is64Bit();
549 
552 
554 
555  // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
558 
559  if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
560  // f32 and f64 use SSE.
561  // Set up the FP register classes.
562  addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
563  : &X86::FR32RegClass);
564  addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
565  : &X86::FR64RegClass);
566 
567  // Disable f32->f64 extload as we can only generate this in one instruction
568  // under optsize. So its easier to pattern match (fpext (load)) for that
569  // case instead of needing to emit 2 instructions for extload in the
570  // non-optsize case.
572 
573  for (auto VT : { MVT::f32, MVT::f64 }) {
574  // Use ANDPD to simulate FABS.
576 
577  // Use XORP to simulate FNEG.
579 
580  // Use ANDPD and ORPD to simulate FCOPYSIGN.
582 
583  // These might be better off as horizontal vector ops.
586 
587  // We don't support sin/cos/fmod
591  }
592 
593  // Lower this to MOVMSK plus an AND.
596 
597  } else if (!Subtarget.useSoftFloat() && X86ScalarSSEf32 &&
598  (UseX87 || Is64Bit)) {
599  // Use SSE for f32, x87 for f64.
600  // Set up the FP register classes.
601  addRegisterClass(MVT::f32, &X86::FR32RegClass);
602  if (UseX87)
603  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
604 
605  // Use ANDPS to simulate FABS.
607 
608  // Use XORP to simulate FNEG.
610 
611  if (UseX87)
613 
614  // Use ANDPS and ORPS to simulate FCOPYSIGN.
615  if (UseX87)
618 
619  // We don't support sin/cos/fmod
623 
624  if (UseX87) {
625  // Always expand sin/cos functions even though x87 has an instruction.
629  }
630  } else if (UseX87) {
631  // f32 and f64 in x87.
632  // Set up the FP register classes.
633  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
634  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
635 
636  for (auto VT : { MVT::f32, MVT::f64 }) {
639 
640  // Always expand sin/cos functions even though x87 has an instruction.
644  }
645  }
646 
647  // Expand FP32 immediates into loads from the stack, save special cases.
648  if (isTypeLegal(MVT::f32)) {
649  if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
650  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
651  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
652  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
653  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
654  } else // SSE immediates.
655  addLegalFPImmediate(APFloat(+0.0f)); // xorps
656  }
657  // Expand FP64 immediates into loads from the stack, save special cases.
658  if (isTypeLegal(MVT::f64)) {
659  if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
660  addLegalFPImmediate(APFloat(+0.0)); // FLD0
661  addLegalFPImmediate(APFloat(+1.0)); // FLD1
662  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
663  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
664  } else // SSE immediates.
665  addLegalFPImmediate(APFloat(+0.0)); // xorpd
666  }
667  // Handle constrained floating-point operations of scalar.
681 
682  // We don't support FMA.
685 
686  // f80 always uses X87.
687  if (UseX87) {
688  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
691  {
693  addLegalFPImmediate(TmpFlt); // FLD0
694  TmpFlt.changeSign();
695  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
696 
697  bool ignored;
698  APFloat TmpFlt2(+1.0);
700  &ignored);
701  addLegalFPImmediate(TmpFlt2); // FLD1
702  TmpFlt2.changeSign();
703  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
704  }
705 
706  // Always expand sin/cos functions even though x87 has an instruction.
710 
721 
722  // Handle constrained floating-point operations of scalar.
729  // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
730  // as Custom.
732  }
733 
734  // f128 uses xmm registers, but most operations require libcalls.
735  if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
736  addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
737  : &X86::VR128RegClass);
738 
739  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps
740 
751 
755 
761  // No STRICT_FSINCOS
764 
767  // We need to custom handle any FP_ROUND with an f128 input, but
768  // LegalizeDAG uses the result type to know when to run a custom handler.
769  // So we have to list all legal floating point result types here.
770  if (isTypeLegal(MVT::f32)) {
773  }
774  if (isTypeLegal(MVT::f64)) {
777  }
778  if (isTypeLegal(MVT::f80)) {
781  }
782 
784 
791  }
792 
793  // Always use a library call for pow.
798 
806 
807  // Some FP actions are always expanded for vector types.
808  for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
821  }
822 
823  // First set operation action for all vector types to either promote
824  // (for widening) or expand (for scalarization). Then we will selectively
825  // turn on ones that can be effectively codegen'd.
826  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
864  for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
865  setTruncStoreAction(InnerVT, VT, Expand);
866 
867  setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
868  setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
869 
870  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
871  // types, we have to deal with them whether we ask for Expansion or not.
872  // Setting Expand causes its own optimisation problems though, so leave
873  // them legal.
874  if (VT.getVectorElementType() == MVT::i1)
875  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
876 
877  // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
878  // split/scalarized right now.
879  if (VT.getVectorElementType() == MVT::f16)
880  setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
881  }
882  }
883 
884  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
885  // with -msoft-float, disable use of MMX as well.
886  if (!Subtarget.useSoftFloat() && Subtarget.hasMMX()) {
887  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
888  // No operations on x86mmx supported, everything uses intrinsics.
889  }
890 
891  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) {
892  addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
893  : &X86::VR128RegClass);
894 
903 
906 
912  }
913 
914  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
915  addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
916  : &X86::VR128RegClass);
917 
918  // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
919  // registers cannot be used even for integer operations.
920  addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
921  : &X86::VR128RegClass);
922  addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
923  : &X86::VR128RegClass);
924  addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
925  : &X86::VR128RegClass);
926  addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
927  : &X86::VR128RegClass);
928 
929  for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
935  }
936 
940 
951 
954 
958 
959  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
964  }
965 
976 
981 
982  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
988 
989  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
990  // setcc all the way to isel and prefer SETGT in some isel patterns.
993  }
994 
995  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1001  }
1002 
1003  for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1007 
1008  if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1009  continue;
1010 
1013  }
1014 
1015  // Custom lower v2i64 and v2f64 selects.
1021 
1028 
1029  // Custom legalize these to avoid over promotion or custom promotion.
1030  for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1035  }
1036 
1041 
1044 
1047 
1048  // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
1053 
1058 
1059  // We want to legalize this to an f64 load rather than an i64 load on
1060  // 64-bit targets and two 32-bit loads on a 32-bit target. Similar for
1061  // store.
1068 
1072  if (!Subtarget.hasAVX512())
1074 
1078 
1080 
1087 
1088  // In the customized shift lowering, the legal v4i32/v2i64 cases
1089  // in AVX2 will be recognized.
1090  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1094  if (VT == MVT::v2i64) continue;
1097  }
1098 
1103 
1109  }
1110 
1111  if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) {
1120 
1121  // These might be better off as horizontal vector ops.
1126  }
1127 
1128  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) {
1129  for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
1130  setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1132  setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1134  setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1136  setOperationAction(ISD::FRINT, RoundedTy, Legal);
1142 
1143  setOperationAction(ISD::FROUND, RoundedTy, Custom);
1144  }
1145 
1154 
1158 
1159  // FIXME: Do we need to handle scalar-to-vector here?
1161 
1162  // We directly match byte blends in the backend as they match the VSELECT
1163  // condition form.
1165 
1166  // SSE41 brings specific instructions for doing vector sign extend even in
1167  // cases where we don't have SRA.
1168  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1171  }
1172 
1173  // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1174  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1181  }
1182 
1183  if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
1184  // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
1185  // do the pre and post work in the vector domain.
1188  // We need to mark SINT_TO_FP as Custom even though we want to expand it
1189  // so that DAG combine doesn't try to turn it into uint_to_fp.
1192  }
1193  }
1194 
1195  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE42()) {
1197  }
1198 
1199  if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
1200  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1204  }
1205 
1206  // XOP can efficiently perform BITREVERSE with VPPERM.
1207  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
1209 
1210  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1213  }
1214 
1215  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX()) {
1216  bool HasInt256 = Subtarget.hasInt256();
1217 
1218  addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass
1219  : &X86::VR256RegClass);
1220  addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass
1221  : &X86::VR256RegClass);
1222  addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1223  : &X86::VR256RegClass);
1224  addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass
1225  : &X86::VR256RegClass);
1226  addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1227  : &X86::VR256RegClass);
1228  addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass
1229  : &X86::VR256RegClass);
1230 
1231  for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
1244 
1246 
1250  }
1251 
1252  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1253  // even though v8i16 is a legal type.
1261 
1264 
1277 
1278  if (!Subtarget.hasAVX512())
1280 
1281  // In the customized shift lowering, the legal v8i32/v4i64 cases
1282  // in AVX2 will be recognized.
1283  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1287  if (VT == MVT::v4i64) continue;
1290  }
1291 
1296 
1297  // These types need custom splitting if their input is a 128-bit vector.
1302 
1309 
1310  for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1314  }
1315 
1320 
1321  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1327 
1328  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1329  // setcc all the way to isel and prefer SETGT in some isel patterns.
1332  }
1333 
1334  if (Subtarget.hasAnyFMA()) {
1335  for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1336  MVT::v2f64, MVT::v4f64 }) {
1339  }
1340  }
1341 
1342  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1343  setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1344  setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1345  }
1346 
1351 
1358 
1361 
1367 
1380 
1381  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1382  setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom);
1383  setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1384  setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1385  setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1386  setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1387  }
1388 
1389  for (auto VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64}) {
1392  }
1393 
1394  if (HasInt256) {
1395  // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1396  // when we have a 256bit-wide blend with immediate.
1399 
1400  // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1401  for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1408  }
1409  }
1410 
1411  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1413  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1415  }
1416 
1417  // Extract subvector is special because the value type
1418  // (result) is 128-bit but the source is 256-bit wide.
1419  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
1420  MVT::v4f32, MVT::v2f64 }) {
1422  }
1423 
1424  // Custom lower several nodes for 256-bit types.
1426  MVT::v8f32, MVT::v4f64 }) {
1436  }
1437 
1438  if (HasInt256) {
1440 
1441  // Custom legalize 2x32 to get a little better code.
1444 
1445  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1448  }
1449  }
1450 
1451  // This block controls legalization of the mask vector sizes that are
1452  // available with AVX512. 512-bit vectors are in a separate block controlled
1453  // by useAVX512Regs.
1454  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1455  addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1456  addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1457  addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1458  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1459  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1460 
1464 
1477 
1478  // There is no byte sized k-register load or store without AVX512DQ.
1479  if (!Subtarget.hasDQI()) {
1484 
1489  }
1490 
1491  // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1492  for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1496  }
1497 
1498  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })
1500 
1501  for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1507 
1514  }
1515 
1516  for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
1518  }
1519 
1520  // This block controls legalization for 512-bit operations with 32/64 bit
1521  // elements. 512-bits can be disabled based on prefer-vector-width and
1522  // required-vector-width function attributes.
1523  if (!Subtarget.useSoftFloat() && Subtarget.useAVX512Regs()) {
1524  bool HasBWI = Subtarget.hasBWI();
1525 
1526  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1527  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1528  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1529  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1530  addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531  addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 
1533  for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1539  if (HasBWI)
1541  }
1542 
1543  for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
1549  }
1550 
1551  for (MVT VT : { MVT::v16i1, MVT::v16i8, MVT::v16i16 }) {
1556  }
1565 
1578 
1584  if (HasBWI)
1586 
1587  // With 512-bit vectors and no VLX, we prefer to widen MLOAD/MSTORE
1588  // to 512-bit rather than use the AVX2 instructions so that we can use
1589  // k-masks.
1590  if (!Subtarget.hasVLX()) {
1591  for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1595  }
1596  }
1597 
1611 
1612  if (HasBWI) {
1613  // Extends from v64i1 masks to 512-bit vectors.
1617  }
1618 
1619  for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
1632 
1634  }
1635 
1636  for (auto VT : {MVT::v32i16, MVT::v16i32, MVT::v8i64}) {
1639  }
1640 
1645 
1650 
1657 
1660 
1662 
1663  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 }) {
1670 
1671  // The condition codes aren't legal in SSE/AVX and under AVX512 we use
1672  // setcc all the way to isel and prefer SETGT in some isel patterns.
1675  }
1676  for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
1685  }
1686 
1687  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1688  setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
1689  setOperationAction(ISD::CTPOP, VT, Subtarget.hasBITALG() ? Legal : Custom);
1691  setOperationAction(ISD::SMAX, VT, HasBWI ? Legal : Custom);
1692  setOperationAction(ISD::UMAX, VT, HasBWI ? Legal : Custom);
1693  setOperationAction(ISD::SMIN, VT, HasBWI ? Legal : Custom);
1694  setOperationAction(ISD::UMIN, VT, HasBWI ? Legal : Custom);
1695  setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom);
1696  setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom);
1697  setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom);
1698  setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
1699  }
1700 
1705 
1706  if (Subtarget.hasDQI()) {
1715 
1717  }
1718 
1719  if (Subtarget.hasCDI()) {
1720  // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
1721  for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
1723  }
1724  } // Subtarget.hasCDI()
1725 
1726  if (Subtarget.hasVPOPCNTDQ()) {
1727  for (auto VT : { MVT::v16i32, MVT::v8i64 })
1729  }
1730 
1731  // Extract subvector is special because the value type
1732  // (result) is 256-bit but the source is 512-bit wide.
1733  // 128-bit was made Legal under AVX1.
1734  for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1737 
1738  for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
1739  MVT::v16f32, MVT::v8f64 }) {
1749  }
1750 
1751  for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
1756  }
1757  if (HasBWI) {
1758  for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1761  }
1762  } else {
1765  }
1766 
1767  if (Subtarget.hasVBMI2()) {
1768  for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64,
1773  }
1774 
1779  }
1780  }// useAVX512Regs
1781 
1782  // This block controls legalization for operations that don't have
1783  // pre-AVX512 equivalents. Without VLX we use 512-bit operations for
1784  // narrower widths.
1785  if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
1786  // These operations are handled on non-VLX by artificially widening in
1787  // isel patterns.
1788 
1790  Subtarget.hasVLX() ? Legal : Custom);
1792  Subtarget.hasVLX() ? Legal : Custom);
1794  Subtarget.hasVLX() ? Legal : Custom);
1796  Subtarget.hasVLX() ? Legal : Custom);
1799  Subtarget.hasVLX() ? Legal : Custom);
1801  Subtarget.hasVLX() ? Legal : Custom);
1803  Subtarget.hasVLX() ? Legal : Custom);
1805  Subtarget.hasVLX() ? Legal : Custom);
1806 
1807  if (Subtarget.hasDQI()) {
1808  // Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
1809  // v2f32 UINT_TO_FP is already custom under SSE2.
1812  "Unexpected operation action!");
1813  // v2i64 FP_TO_S/UINT(v2f32) custom conversion.
1818  }
1819 
1820  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1826  }
1827 
1828  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1831  }
1832 
1833  // Custom legalize 2x32 to get a little better code.
1836 
1837  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1840 
1841  if (Subtarget.hasDQI()) {
1842  for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1844  Subtarget.hasVLX() ? Legal : Custom);
1846  Subtarget.hasVLX() ? Legal : Custom);
1848  Subtarget.hasVLX() ? Legal : Custom);
1850  Subtarget.hasVLX() ? Legal : Custom);
1852  Subtarget.hasVLX() ? Legal : Custom);
1854  Subtarget.hasVLX() ? Legal : Custom);
1856  Subtarget.hasVLX() ? Legal : Custom);
1858  Subtarget.hasVLX() ? Legal : Custom);
1860  }
1861  }
1862 
1863  if (Subtarget.hasCDI()) {
1864  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 }) {
1866  }
1867  } // Subtarget.hasCDI()
1868 
1869  if (Subtarget.hasVPOPCNTDQ()) {
1870  for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64 })
1872  }
1873  }
1874 
1875  // This block control legalization of v32i1/v64i1 which are available with
1876  // AVX512BW. 512-bit v32i16 and v64i8 vector legalization is controlled with
1877  // useBWIRegs.
1878  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
1879  addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1880  addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1881 
1882  for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1893  }
1894 
1895  for (auto VT : { MVT::v16i1, MVT::v32i1 })
1897 
1898  // Extends from v32i1 masks to 256-bit vectors.
1902 
1903  for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
1904  setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom);
1905  setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom);
1906  }
1907 
1908  // These operations are handled on non-VLX by artificially widening in
1909  // isel patterns.
1910  // TODO: Custom widen in lowering on non-VLX and drop the isel patterns?
1911 
1912  if (Subtarget.hasBITALG()) {
1913  for (auto VT : { MVT::v16i8, MVT::v32i8, MVT::v8i16, MVT::v16i16 })
1915  }
1916  }
1917 
1918  if (!Subtarget.useSoftFloat() && Subtarget.hasFP16()) {
1919  auto setGroup = [&] (MVT VT) {
1930 
1941 
1944 
1950 
1956  };
1957 
1958  // AVX512_FP16 scalar operations
1959  setGroup(MVT::f16);
1960  addRegisterClass(MVT::f16, &X86::FR16XRegClass);
1973  if (isTypeLegal(MVT::f80)) {
1976  }
1977 
1980 
1981  if (Subtarget.useAVX512Regs()) {
1982  setGroup(MVT::v32f16);
1983  addRegisterClass(MVT::v32f16, &X86::VR512RegClass);
1992 
1999  MVT::v32i16);
2002  MVT::v32i16);
2005  MVT::v32i16);
2008  MVT::v32i16);
2009 
2013 
2016 
2019  }
2020 
2021  if (Subtarget.hasVLX()) {
2022  addRegisterClass(MVT::v8f16, &X86::VR128XRegClass);
2023  addRegisterClass(MVT::v16f16, &X86::VR256XRegClass);
2024  setGroup(MVT::v8f16);
2025  setGroup(MVT::v16f16);
2026 
2037 
2044 
2045  // INSERT_VECTOR_ELT v8f16 extended to VECTOR_SHUFFLE
2048 
2052 
2057 
2058  // Need to custom widen these to prevent scalarization.
2061  }
2062 
2063  // Support fp16 0 immediate
2064  addLegalFPImmediate(APFloat::getZero(APFloat::IEEEhalf()));
2065  }
2066 
2067  if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) {
2073 
2079 
2080  if (Subtarget.hasBWI()) {
2083  }
2084 
2085  if (Subtarget.hasFP16()) {
2086  // vcvttph2[u]dq v4f16 -> v4i32/64, v2f16 -> v2i32/64
2095  // vcvt[u]dq2ph v4i32/64 -> v4f16, v2i32/64 -> v2f16
2104  // vcvtps2phx v4f32 -> v4f16, v2f32 -> v2f16
2109  // vcvtph2psx v4f16 -> v4f32, v2f16 -> v2f32
2114  }
2115 
2119  }
2120 
2121  if (Subtarget.hasAMXTILE()) {
2122  addRegisterClass(MVT::x86amx, &X86::TILERegClass);
2123  }
2124 
2125  // We want to custom lower some of our intrinsics.
2129  if (!Subtarget.is64Bit()) {
2131  }
2132 
2133  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
2134  // handle type legalization for these operations here.
2135  //
2136  // FIXME: We really should do custom legalization for addition and
2137  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
2138  // than generic legalization for 64-bit multiplication-with-overflow, though.
2139  for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
2140  if (VT == MVT::i64 && !Subtarget.is64Bit())
2141  continue;
2142  // Add/Sub/Mul with overflow operations are custom lowered.
2149 
2150  // Support carry in as value rather than glue.
2156  }
2157 
2158  if (!Subtarget.is64Bit()) {
2159  // These libcalls are not available in 32-bit.
2160  setLibcallName(RTLIB::SHL_I128, nullptr);
2161  setLibcallName(RTLIB::SRL_I128, nullptr);
2162  setLibcallName(RTLIB::SRA_I128, nullptr);
2163  setLibcallName(RTLIB::MUL_I128, nullptr);
2164  // The MULO libcall is not part of libgcc, only compiler-rt.
2165  setLibcallName(RTLIB::MULO_I64, nullptr);
2166  }
2167  // The MULO libcall is not part of libgcc, only compiler-rt.
2168  setLibcallName(RTLIB::MULO_I128, nullptr);
2169 
2170  // Combine sin / cos into _sincos_stret if it is available.
2171  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
2172  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
2175  }
2176 
2177  if (Subtarget.isTargetWin64()) {
2190  }
2191 
2192  // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
2193  // is. We should promote the value to 64-bits to solve this.
2194  // This is what the CRT headers do - `fmodf` is an inline header
2195  // function casting to f64 and calling `fmod`.
2196  if (Subtarget.is32Bit() &&
2197  (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()))
2198  for (ISD::NodeType Op :
2210 
2211  // We have target-specific dag combine patterns for the following nodes:
2261 
2263 
2264  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
2266  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
2268  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
2270 
2271  // TODO: These control memcmp expansion in CGP and could be raised higher, but
2272  // that needs to benchmarked and balanced with the potential use of vector
2273  // load/store types (PR33329, PR33914).
2274  MaxLoadsPerMemcmp = 2;
2276 
2277  // Default loop alignment, which can be overridden by -align-loops.
2279 
2280  // An out-of-order CPU can speculatively execute past a predictable branch,
2281  // but a conditional move could be stalled by an expensive earlier operation.
2282  PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
2283  EnableExtLdPromotion = true;
2285 
2287 
2288  // Default to having -disable-strictnode-mutation on
2289  IsStrictFPEnabled = true;
2290 }
2291 
2292 // This has so far only been implemented for 64-bit MachO.
2294  return Subtarget.isTargetMachO() && Subtarget.is64Bit();
2295 }
2296 
2298  // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2299  return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
2300 }
2301 
2303  const SDLoc &DL) const {
2304  EVT PtrTy = getPointerTy(DAG.getDataLayout());
2305  unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
2306  MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2307  return SDValue(Node, 0);
2308 }
2309 
2312  if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2313  !Subtarget.hasBWI())
2314  return TypeSplitVector;
2315 
2316  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
2317  VT.getVectorElementType() != MVT::i1)
2318  return TypeWidenVector;
2319 
2321 }
2322 
2323 static std::pair<MVT, unsigned>
2325  const X86Subtarget &Subtarget) {
2326  // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2327  // convention is one that uses k registers.
2328  if (NumElts == 2)
2329  return {MVT::v2i64, 1};
2330  if (NumElts == 4)
2331  return {MVT::v4i32, 1};
2332  if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
2334  return {MVT::v8i16, 1};
2335  if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
2337  return {MVT::v16i8, 1};
2338  // v32i1 passes in ymm unless we have BWI and the calling convention is
2339  // regcall.
2340  if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
2341  return {MVT::v32i8, 1};
2342  // Split v64i1 vectors if we don't have v64i8 available.
2343  if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
2344  if (Subtarget.useAVX512Regs())
2345  return {MVT::v64i8, 1};
2346  return {MVT::v32i8, 2};
2347  }
2348 
2349  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2350  if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
2351  NumElts > 64)
2352  return {MVT::i8, NumElts};
2353 
2354  return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
2355 }
2356 
2358  CallingConv::ID CC,
2359  EVT VT) const {
2360  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2361  Subtarget.hasAVX512()) {
2362  unsigned NumElts = VT.getVectorNumElements();
2363 
2364  MVT RegisterVT;
2365  unsigned NumRegisters;
2366  std::tie(RegisterVT, NumRegisters) =
2367  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2368  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2369  return RegisterVT;
2370  }
2371 
2372  // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2373  // So its default register type is f16. We override the type to v8f16 here.
2374  if (VT == MVT::v3f16 && Subtarget.hasFP16())
2375  return MVT::v8f16;
2376 
2377  // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
2378  if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
2379  !Subtarget.hasX87())
2380  return MVT::i32;
2381 
2383 }
2384 
2386  CallingConv::ID CC,
2387  EVT VT) const {
2388  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2389  Subtarget.hasAVX512()) {
2390  unsigned NumElts = VT.getVectorNumElements();
2391 
2392  MVT RegisterVT;
2393  unsigned NumRegisters;
2394  std::tie(RegisterVT, NumRegisters) =
2395  handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
2396  if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
2397  return NumRegisters;
2398  }
2399 
2400  // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
2401  // So its default register number is 3. We override the number to 1 here.
2402  if (VT == MVT::v3f16 && Subtarget.hasFP16())
2403  return 1;
2404 
2405  // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
2406  // x87 is disabled.
2407  if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
2408  if (VT == MVT::f64)
2409  return 2;
2410  if (VT == MVT::f80)
2411  return 3;
2412  }
2413 
2415 }
2416 
2418  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
2419  unsigned &NumIntermediates, MVT &RegisterVT) const {
2420  // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
2421  if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
2422  Subtarget.hasAVX512() &&
2424  (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
2425  VT.getVectorNumElements() > 64)) {
2426  RegisterVT = MVT::i8;
2427  IntermediateVT = MVT::i1;
2428  NumIntermediates = VT.getVectorNumElements();
2429  return NumIntermediates;
2430  }
2431 
2432  // Split v64i1 vectors if we don't have v64i8 available.
2433  if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2434  CC != CallingConv::X86_RegCall) {
2435  RegisterVT = MVT::v32i8;
2436  IntermediateVT = MVT::v32i1;
2437  NumIntermediates = 2;
2438  return 2;
2439  }
2440 
2441  return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
2442  NumIntermediates, RegisterVT);
2443 }
2444 
2447  EVT VT) const {
2448  if (!VT.isVector())
2449  return MVT::i8;
2450 
2451  if (Subtarget.hasAVX512()) {
2452  // Figure out what this type will be legalized to.
2453  EVT LegalVT = VT;
2454  while (getTypeAction(Context, LegalVT) != TypeLegal)
2455  LegalVT = getTypeToTransformTo(Context, LegalVT);
2456 
2457  // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
2458  if (LegalVT.getSimpleVT().is512BitVector())
2460 
2461  if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2462  // If we legalized to less than a 512-bit vector, then we will use a vXi1
2463  // compare for vXi32/vXi64 for sure. If we have BWI we will also support
2464  // vXi16/vXi8.
2465  MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2466  if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
2468  }
2469  }
2470 
2472 }
2473 
2474 /// Helper for getByValTypeAlignment to determine
2475 /// the desired ByVal argument alignment.
2476 static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
2477  if (MaxAlign == 16)
2478  return;
2479  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
2480  if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
2481  MaxAlign = Align(16);
2482  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
2483  Align EltAlign;
2484  getMaxByValAlign(ATy->getElementType(), EltAlign);
2485  if (EltAlign > MaxAlign)
2486  MaxAlign = EltAlign;
2487  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
2488  for (auto *EltTy : STy->elements()) {
2489  Align EltAlign;
2490  getMaxByValAlign(EltTy, EltAlign);
2491  if (EltAlign > MaxAlign)
2492  MaxAlign = EltAlign;
2493  if (MaxAlign == 16)
2494  break;
2495  }
2496  }
2497 }
2498 
2499 /// Return the desired alignment for ByVal aggregate
2500 /// function arguments in the caller parameter area. For X86, aggregates
2501 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
2502 /// are at 4-byte boundaries.
2504  const DataLayout &DL) const {
2505  if (Subtarget.is64Bit()) {
2506  // Max of 8 and alignment of type.
2507  Align TyAlign = DL.getABITypeAlign(Ty);
2508  if (TyAlign > 8)
2509  return TyAlign.value();
2510  return 8;
2511  }
2512 
2513  Align Alignment(4);
2514  if (Subtarget.hasSSE1())
2515  getMaxByValAlign(Ty, Alignment);
2516  return Alignment.value();
2517 }
2518 
2519 /// It returns EVT::Other if the type should be determined using generic
2520 /// target-independent logic.
2521 /// For vector ops we check that the overall size isn't larger than our
2522 /// preferred vector width.
2524  const MemOp &Op, const AttributeList &FuncAttributes) const {
2525  if (!FuncAttributes.hasFnAttr(Attribute::NoImplicitFloat)) {
2526  if (Op.size() >= 16 &&
2527  (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
2528  // FIXME: Check if unaligned 64-byte accesses are slow.
2529  if (Op.size() >= 64 && Subtarget.hasAVX512() &&
2530  (Subtarget.getPreferVectorWidth() >= 512)) {
2531  return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
2532  }
2533  // FIXME: Check if unaligned 32-byte accesses are slow.
2534  if (Op.size() >= 32 && Subtarget.hasAVX() &&
2535  (Subtarget.getPreferVectorWidth() >= 256)) {
2536  // Although this isn't a well-supported type for AVX1, we'll let
2537  // legalization and shuffle lowering produce the optimal codegen. If we
2538  // choose an optimal type with a vector element larger than a byte,
2539  // getMemsetStores() may create an intermediate splat (using an integer
2540  // multiply) before we splat as a vector.
2541  return MVT::v32i8;
2542  }
2543  if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
2544  return MVT::v16i8;
2545  // TODO: Can SSE1 handle a byte vector?
2546  // If we have SSE1 registers we should be able to use them.
2547  if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
2548  (Subtarget.getPreferVectorWidth() >= 128))
2549  return MVT::v4f32;
2550  } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
2551  Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
2552  // Do not use f64 to lower memcpy if source is string constant. It's
2553  // better to use i32 to avoid the loads.
2554  // Also, do not use f64 to lower memset unless this is a memset of zeros.
2555  // The gymnastics of splatting a byte value into an XMM register and then
2556  // only using 8-byte stores (because this is a CPU with slow unaligned
2557  // 16-byte accesses) makes that a loser.
2558  return MVT::f64;
2559  }
2560  }
2561  // This is a compromise. If we reach here, unaligned accesses may be slow on
2562  // this target. However, creating smaller, aligned accesses could be even
2563  // slower and would certainly be a lot more code.
2564  if (Subtarget.is64Bit() && Op.size() >= 8)
2565  return MVT::i64;
2566  return MVT::i32;
2567 }
2568 
2570  if (VT == MVT::f32)
2571  return X86ScalarSSEf32;
2572  if (VT == MVT::f64)
2573  return X86ScalarSSEf64;
2574  return true;
2575 }
2576 
2578  EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
2579  bool *Fast) const {
2580  if (Fast) {
2581  switch (VT.getSizeInBits()) {
2582  default:
2583  // 8-byte and under are always assumed to be fast.
2584  *Fast = true;
2585  break;
2586  case 128:
2587  *Fast = !Subtarget.isUnalignedMem16Slow();
2588  break;
2589  case 256:
2590  *Fast = !Subtarget.isUnalignedMem32Slow();
2591  break;
2592  // TODO: What about AVX-512 (512-bit) accesses?
2593  }
2594  }
2595  // NonTemporal vector memory ops must be aligned.
2596  if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
2597  // NT loads can only be vector aligned, so if its less aligned than the
2598  // minimum vector size (which we can split the vector down to), we might as
2599  // well use a regular unaligned vector load.
2600  // We don't have any NT loads pre-SSE41.
2601  if (!!(Flags & MachineMemOperand::MOLoad))
2602  return (Alignment < 16 || !Subtarget.hasSSE41());
2603  return false;
2604  }
2605  // Misaligned accesses of any size are always allowed.
2606  return true;
2607 }
2608 
2609 /// Return the entry encoding for a jump table in the
2610 /// current function. The returned value is a member of the
2611 /// MachineJumpTableInfo::JTEntryKind enum.
2613  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2614  // symbol.
2615  if (isPositionIndependent() && Subtarget.isPICStyleGOT())
2617 
2618  // Otherwise, use the normal jump table encoding heuristics.
2620 }
2621 
2623  return Subtarget.useSoftFloat();
2624 }
2625 
2627  ArgListTy &Args) const {
2628 
2629  // Only relabel X86-32 for C / Stdcall CCs.
2630  if (Subtarget.is64Bit())
2631  return;
2632  if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
2633  return;
2634  unsigned ParamRegs = 0;
2635  if (auto *M = MF->getFunction().getParent())
2636  ParamRegs = M->getNumberRegisterParameters();
2637 
2638  // Mark the first N int arguments as having reg
2639  for (auto &Arg : Args) {
2640  Type *T = Arg.Ty;
2641  if (T->isIntOrPtrTy())
2642  if (MF->getDataLayout().getTypeAllocSize(T) <= 8) {
2643  unsigned numRegs = 1;
2644  if (MF->getDataLayout().getTypeAllocSize(T) > 4)
2645  numRegs = 2;
2646  if (ParamRegs < numRegs)
2647  return;
2648  ParamRegs -= numRegs;
2649  Arg.IsInReg = true;
2650  }
2651  }
2652 }
2653 
2654 const MCExpr *
2656  const MachineBasicBlock *MBB,
2657  unsigned uid,MCContext &Ctx) const{
2658  assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
2659  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2660  // entries.
2663 }
2664 
2665 /// Returns relocation base for the given PIC jumptable.
2667  SelectionDAG &DAG) const {
2668  if (!Subtarget.is64Bit())
2669  // This doesn't have SDLoc associated with it, but is not really the
2670  // same as a Register.
2671  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2672  getPointerTy(DAG.getDataLayout()));
2673  return Table;
2674 }
2675 
2676 /// This returns the relocation base for the given PIC jumptable,
2677 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2680  MCContext &Ctx) const {
2681  // X86-64 uses RIP relative addressing based on the jump table label.
2682  if (Subtarget.isPICStyleRIPRel())
2683  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2684 
2685  // Otherwise, the reference is relative to the PIC base.
2686  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2687 }
2688 
2689 std::pair<const TargetRegisterClass *, uint8_t>
2691  MVT VT) const {
2692  const TargetRegisterClass *RRC = nullptr;
2693  uint8_t Cost = 1;
2694  switch (VT.SimpleTy) {
2695  default:
2697  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2698  RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2699  break;
2700  case MVT::x86mmx:
2701  RRC = &X86::VR64RegClass;
2702  break;
2703  case MVT::f32: case MVT::f64:
2704  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2705  case MVT::v4f32: case MVT::v2f64:
2706  case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
2707  case MVT::v8f32: case MVT::v4f64:
2708  case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
2709  case MVT::v16f32: case MVT::v8f64:
2710  RRC = &X86::VR128XRegClass;
2711  break;
2712  }
2713  return std::make_pair(RRC, Cost);
2714 }
2715 
2716 unsigned X86TargetLowering::getAddressSpace() const {
2717  if (Subtarget.is64Bit())
2718  return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? 256 : 257;
2719  return 256;
2720 }
2721 
2722 static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
2723  return TargetTriple.isOSGlibc() || TargetTriple.isOSFuchsia() ||
2724  (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
2725 }
2726 
2728  int Offset, unsigned AddressSpace) {
2732 }
2733 
2735  // glibc, bionic, and Fuchsia have a special slot for the stack guard in
2736  // tcbhead_t; use it instead of the usual global variable (see
2737  // sysdeps/{i386,x86_64}/nptl/tls.h)
2738  if (hasStackGuardSlotTLS(Subtarget.getTargetTriple())) {
2739  if (Subtarget.isTargetFuchsia()) {
2740  // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
2741  return SegmentOffset(IRB, 0x10, getAddressSpace());
2742  } else {
2743  unsigned AddressSpace = getAddressSpace();
2744  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2745  // Specially, some users may customize the base reg and offset.
2746  int Offset = M->getStackProtectorGuardOffset();
2747  // If we don't set -stack-protector-guard-offset value:
2748  // %fs:0x28, unless we're using a Kernel code model, in which case
2749  // it's %gs:0x28. gs:0x14 on i386.
2750  if (Offset == INT_MAX)
2751  Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
2752 
2753  StringRef GuardReg = M->getStackProtectorGuardReg();
2754  if (GuardReg == "fs")
2756  else if (GuardReg == "gs")
2758  return SegmentOffset(IRB, Offset, AddressSpace);
2759  }
2760  }
2761  return TargetLowering::getIRStackGuard(IRB);
2762 }
2763 
2765  // MSVC CRT provides functionalities for stack protection.
2766  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2768  // MSVC CRT has a global variable holding security cookie.
2769  M.getOrInsertGlobal("__security_cookie",
2770  Type::getInt8PtrTy(M.getContext()));
2771 
2772  // MSVC CRT has a function to validate security cookie.
2773  FunctionCallee SecurityCheckCookie = M.getOrInsertFunction(
2774  "__security_check_cookie", Type::getVoidTy(M.getContext()),
2775  Type::getInt8PtrTy(M.getContext()));
2776  if (Function *F = dyn_cast<Function>(SecurityCheckCookie.getCallee())) {
2777  F->setCallingConv(CallingConv::X86_FastCall);
2778  F->addParamAttr(0, Attribute::AttrKind::InReg);
2779  }
2780  return;
2781  }
2782 
2783  StringRef GuardMode = M.getStackProtectorGuard();
2784 
2785  // glibc, bionic, and Fuchsia have a special slot for the stack guard.
2786  if ((GuardMode == "tls" || GuardMode.empty()) &&
2788  return;
2790 }
2791 
2793  // MSVC CRT has a global variable holding security cookie.
2794  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2796  return M.getGlobalVariable("__security_cookie");
2797  }
2799 }
2800 
2802  // MSVC CRT has a function to validate security cookie.
2803  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
2805  return M.getFunction("__security_check_cookie");
2806  }
2808 }
2809 
2810 Value *
2812  if (Subtarget.getTargetTriple().isOSContiki())
2813  return getDefaultSafeStackPointerLocation(IRB, false);
2814 
2815  // Android provides a fixed TLS slot for the SafeStack pointer. See the
2816  // definition of TLS_SLOT_SAFESTACK in
2817  // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2818  if (Subtarget.isTargetAndroid()) {
2819  // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2820  // %gs:0x24 on i386
2821  int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
2822  return SegmentOffset(IRB, Offset, getAddressSpace());
2823  }
2824 
2825  // Fuchsia is similar.
2826  if (Subtarget.isTargetFuchsia()) {
2827  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
2828  return SegmentOffset(IRB, 0x18, getAddressSpace());
2829  }
2830 
2832 }
2833 
2834 //===----------------------------------------------------------------------===//
2835 // Return Value Calling Convention Implementation
2836 //===----------------------------------------------------------------------===//
2837 
2838 bool X86TargetLowering::CanLowerReturn(
2839  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2840  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2842  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2843  return CCInfo.CheckReturn(Outs, RetCC_X86);
2844 }
2845 
2846 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2847  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2848  return ScratchRegs;
2849 }
2850 
2851 /// Lowers masks values (v*i1) to the local register values
2852 /// \returns DAG node after lowering to register type
2853 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
2854  const SDLoc &Dl, SelectionDAG &DAG) {
2855  EVT ValVT = ValArg.getValueType();
2856 
2857  if (ValVT == MVT::v1i1)
2858  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2859  DAG.getIntPtrConstant(0, Dl));
2860 
2861  if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2862  (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
2863  // Two stage lowering might be required
2864  // bitcast: v8i1 -> i8 / v16i1 -> i16
2865  // anyextend: i8 -> i32 / i16 -> i32
2866  EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2867  SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
2868  if (ValLoc == MVT::i32)
2869  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2870  return ValToCopy;
2871  }
2872 
2873  if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2874  (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2875  // One stage lowering is required
2876  // bitcast: v32i1 -> i32 / v64i1 -> i64
2877  return DAG.getBitcast(ValLoc, ValArg);
2878  }
2879 
2880  return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2881 }
2882 
2883 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2885  const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
2886  SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2887  CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2888  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
2889  assert(Subtarget.is32Bit() && "Expecting 32 bit target");
2890  assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
2891  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2892  "The value should reside in two registers");
2893 
2894  // Before splitting the value we cast it to i64
2895  Arg = DAG.getBitcast(MVT::i64, Arg);
2896 
2897  // Splitting the value into two i32 types
2898  SDValue Lo, Hi;
2900  DAG.getConstant(0, Dl, MVT::i32));
2902  DAG.getConstant(1, Dl, MVT::i32));
2903 
2904  // Attach the two i32 types into corresponding registers
2905  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2906  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2907 }
2908 
2909 SDValue
2910 X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2911  bool isVarArg,
2912  const SmallVectorImpl<ISD::OutputArg> &Outs,
2913  const SmallVectorImpl<SDValue> &OutVals,
2914  const SDLoc &dl, SelectionDAG &DAG) const {
2915  MachineFunction &MF = DAG.getMachineFunction();
2917 
2918  // In some cases we need to disable registers from the default CSR list.
2919  // For example, when they are used for argument passing.
2920  bool ShouldDisableCalleeSavedRegister =
2921  CallConv == CallingConv::X86_RegCall ||
2922  MF.getFunction().hasFnAttribute("no_caller_saved_registers");
2923 
2924  if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2925  report_fatal_error("X86 interrupts may not return any value");
2926 
2928  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2929  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2930 
2932  for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2933  ++I, ++OutsIndex) {
2934  CCValAssign &VA = RVLocs[I];
2935  assert(VA.isRegLoc() && "Can only return in registers!");
2936 
2937  // Add the register to the CalleeSaveDisableRegs list.
2938  if (ShouldDisableCalleeSavedRegister)
2940 
2941  SDValue ValToCopy = OutVals[OutsIndex];
2942  EVT ValVT = ValToCopy.getValueType();
2943 
2944  // Promote values to the appropriate types.
2945  if (VA.getLocInfo() == CCValAssign::SExt)
2946  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2947  else if (VA.getLocInfo() == CCValAssign::ZExt)
2948  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2949  else if (VA.getLocInfo() == CCValAssign::AExt) {
2950  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2951  ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2952  else
2953  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2954  }
2955  else if (VA.getLocInfo() == CCValAssign::BCvt)
2956  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2957 
2959  "Unexpected FP-extend for return value.");
2960 
2961  // Report an error if we have attempted to return a value via an XMM
2962  // register and SSE was disabled.
2963  if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
2964  errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2965  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2966  } else if (!Subtarget.hasSSE2() &&
2967  X86::FR64XRegClass.contains(VA.getLocReg()) &&
2968  ValVT == MVT::f64) {
2969  // When returning a double via an XMM register, report an error if SSE2 is
2970  // not enabled.
2971  errorUnsupported(DAG, dl, "SSE2 register return with SSE2 disabled");
2972  VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2973  }
2974 
2975  // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2976  // the RET instruction and handled by the FP Stackifier.
2977  if (VA.getLocReg() == X86::FP0 ||
2978  VA.getLocReg() == X86::FP1) {
2979  // If this is a copy from an xmm register to ST(0), use an FPExtend to
2980  // change the value to the FP stack register class.
2981  if (isScalarFPTypeInSSEReg(VA.getValVT()))
2982  ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2983  RetVals.push_back(std::make_pair(VA.getLocReg(), ValTo