LLVM  13.0.0git
AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64CallLowering.h"
16 #include "AArch64ISelLowering.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Argument.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstdint>
45 #include <iterator>
46 
47 #define DEBUG_TYPE "aarch64-call-lowering"
48 
49 using namespace llvm;
50 
52  : CallLowering(&TLI) {}
53 
54 namespace {
55 struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
56  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
57  CCAssignFn *AssignFn)
58  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
59 
60  Register getStackAddress(uint64_t Size, int64_t Offset,
61  MachinePointerInfo &MPO,
62  ISD::ArgFlagsTy Flags) override {
63  auto &MFI = MIRBuilder.getMF().getFrameInfo();
64 
65  // Byval is assumed to be writable memory, but other stack passed arguments
66  // are not.
67  const bool IsImmutable = !Flags.isByVal();
68 
69  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
70  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
71  auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
72  StackUsed = std::max(StackUsed, Size + Offset);
73  return AddrReg.getReg(0);
74  }
75 
76  void assignValueToReg(Register ValVReg, Register PhysReg,
77  CCValAssign &VA) override {
78  markPhysRegUsed(PhysReg);
79  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
80  }
81 
82  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
83  MachinePointerInfo &MPO, CCValAssign &VA) override {
84  MachineFunction &MF = MIRBuilder.getMF();
85 
86  // The reported memory location may be wider than the value.
87  const LLT RegTy = MRI.getType(ValVReg);
88  MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
89 
90  auto MMO = MF.getMachineMemOperand(
92  MemSize, inferAlignFromPtrInfo(MF, MPO));
93  const LLT LocVT = LLT{VA.getLocVT()};
94 
95  if (RegTy.getScalarSizeInBits() < LocVT.getScalarSizeInBits()) {
96  auto LocInfo = VA.getLocInfo();
97  if (LocInfo == CCValAssign::LocInfo::ZExt) {
98  // We know the parameter is zero-extended. Perform a load into LocVT,
99  // and use G_ASSERT_ZEXT to communicate that this was zero-extended from
100  // the parameter type. Move down to the parameter type using G_TRUNC.
101  MIRBuilder.buildTrunc(
102  ValVReg, MIRBuilder.buildAssertZExt(
103  LocVT, MIRBuilder.buildLoad(LocVT, Addr, *MMO),
104  RegTy.getScalarSizeInBits()));
105  return;
106  }
107 
108  if (LocInfo == CCValAssign::LocInfo::SExt) {
109  // Same as the ZExt case, but use G_ASSERT_SEXT instead.
110  MIRBuilder.buildTrunc(
111  ValVReg, MIRBuilder.buildAssertSExt(
112  LocVT, MIRBuilder.buildLoad(LocVT, Addr, *MMO),
113  RegTy.getScalarSizeInBits()));
114  return;
115  }
116  }
117 
118  // No extension information, or no extension necessary. Load into the
119  // incoming parameter type directly.
120  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
121  }
122 
123  /// How the physical register gets marked varies between formal
124  /// parameters (it's a basic-block live-in), and a call instruction
125  /// (it's an implicit-def of the BL).
126  virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
127 
128  uint64_t StackUsed;
129 };
130 
131 struct FormalArgHandler : public IncomingArgHandler {
132  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
133  CCAssignFn *AssignFn)
134  : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
135 
136  void markPhysRegUsed(MCRegister PhysReg) override {
137  MIRBuilder.getMRI()->addLiveIn(PhysReg);
138  MIRBuilder.getMBB().addLiveIn(PhysReg);
139  }
140 };
141 
142 struct CallReturnHandler : public IncomingArgHandler {
143  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
144  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
145  : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
146 
147  void markPhysRegUsed(MCRegister PhysReg) override {
148  MIB.addDef(PhysReg, RegState::Implicit);
149  }
150 
152 };
153 
154 /// A special return arg handler for "returned" attribute arg calls.
155 struct ReturnedArgCallReturnHandler : public CallReturnHandler {
156  ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
158  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
159  : CallReturnHandler(MIRBuilder, MRI, MIB, AssignFn) {}
160 
161  void markPhysRegUsed(MCRegister PhysReg) override {}
162 };
163 
164 struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
165  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
166  MachineInstrBuilder MIB, CCAssignFn *AssignFn,
167  CCAssignFn *AssignFnVarArg, bool IsVarArg,
168  bool IsTailCall = false, int FPDiff = 0)
169  : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
170  AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff),
171  StackSize(0), SPReg(0) {
172  MachineFunction &MF = MIRBuilder.getMF();
173  const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
174  bool IsWin =
176  UseVarArgsCCForFixed = IsVarArg && IsWin;
177  }
178 
179  Register getStackAddress(uint64_t Size, int64_t Offset,
180  MachinePointerInfo &MPO,
181  ISD::ArgFlagsTy Flags) override {
182  MachineFunction &MF = MIRBuilder.getMF();
183  LLT p0 = LLT::pointer(0, 64);
184  LLT s64 = LLT::scalar(64);
185 
186  if (IsTailCall) {
187  assert(!Flags.isByVal() && "byval unhandled with tail calls");
188 
189  Offset += FPDiff;
190  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
191  auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
192  MPO = MachinePointerInfo::getFixedStack(MF, FI);
193  return FIReg.getReg(0);
194  }
195 
196  if (!SPReg)
197  SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
198 
199  auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
200 
201  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
202 
204  return AddrReg.getReg(0);
205  }
206 
207  void assignValueToReg(Register ValVReg, Register PhysReg,
208  CCValAssign &VA) override {
209  MIB.addUse(PhysReg, RegState::Implicit);
210  Register ExtReg = extendRegister(ValVReg, VA);
211  MIRBuilder.buildCopy(PhysReg, ExtReg);
212  }
213 
214  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
215  MachinePointerInfo &MPO, CCValAssign &VA) override {
216  MachineFunction &MF = MIRBuilder.getMF();
218  inferAlignFromPtrInfo(MF, MPO));
219  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
220  }
221 
222  void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
223  Register Addr, uint64_t Size,
224  MachinePointerInfo &MPO, CCValAssign &VA) override {
225  unsigned MaxSize = Size * 8;
226  // For varargs, we always want to extend them to 8 bytes, in which case
227  // we disable setting a max.
228  if (!Arg.IsFixed)
229  MaxSize = 0;
230 
231  Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
232  ? extendRegister(Arg.Regs[RegIndex], VA, MaxSize)
233  : Arg.Regs[0];
234 
235  // If we extended we might need to adjust the MMO's Size.
236  const LLT RegTy = MRI.getType(ValVReg);
237  if (RegTy.getSizeInBytes() > Size)
238  Size = RegTy.getSizeInBytes();
239 
240  assignValueToAddress(ValVReg, Addr, Size, MPO, VA);
241  }
242 
243  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
244  CCValAssign::LocInfo LocInfo,
246  ISD::ArgFlagsTy Flags,
247  CCState &State) override {
248  bool Res;
249  if (Info.IsFixed && !UseVarArgsCCForFixed)
250  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
251  else
252  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
253 
254  StackSize = State.getNextStackOffset();
255  return Res;
256  }
257 
259  CCAssignFn *AssignFnVarArg;
260  bool IsTailCall;
261  bool UseVarArgsCCForFixed;
262 
263  /// For tail calls, the byte offset of the call's argument area from the
264  /// callee's. Unused elsewhere.
265  int FPDiff;
266  uint64_t StackSize;
267 
268  // Cache the SP register vreg if we need it more than once in this call site.
269  Register SPReg;
270 };
271 } // namespace
272 
273 static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
274  return CallConv == CallingConv::Fast && TailCallOpt;
275 }
276 
278  const Value *Val,
279  ArrayRef<Register> VRegs,
281  Register SwiftErrorVReg) const {
282  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
283  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
284  "Return value without a vreg");
285 
286  bool Success = true;
287  if (!VRegs.empty()) {
288  MachineFunction &MF = MIRBuilder.getMF();
289  const Function &F = MF.getFunction();
290 
292  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
293  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
294  auto &DL = F.getParent()->getDataLayout();
295  LLVMContext &Ctx = Val->getType()->getContext();
296 
297  SmallVector<EVT, 4> SplitEVTs;
298  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
299  assert(VRegs.size() == SplitEVTs.size() &&
300  "For each split Type there should be exactly one VReg.");
301 
302  SmallVector<ArgInfo, 8> SplitArgs;
303  CallingConv::ID CC = F.getCallingConv();
304 
305  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
306  if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) > 1) {
307  LLVM_DEBUG(dbgs() << "Can't handle extended arg types which need split");
308  return false;
309  }
310 
311  Register CurVReg = VRegs[i];
312  ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
314 
315  // i1 is a special case because SDAG i1 true is naturally zero extended
316  // when widened using ANYEXT. We need to do it explicitly here.
317  if (MRI.getType(CurVReg).getSizeInBits() == 1) {
318  CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
319  } else {
320  // Some types will need extending as specified by the CC.
321  MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
322  if (EVT(NewVT) != SplitEVTs[i]) {
323  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
324  if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
325  Attribute::SExt))
326  ExtendOp = TargetOpcode::G_SEXT;
327  else if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
328  Attribute::ZExt))
329  ExtendOp = TargetOpcode::G_ZEXT;
330 
331  LLT NewLLT(NewVT);
332  LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
333  CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
334  // Instead of an extend, we might have a vector type which needs
335  // padding with more elements, e.g. <2 x half> -> <4 x half>.
336  if (NewVT.isVector()) {
337  if (OldLLT.isVector()) {
338  if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
339  // We don't handle VA types which are not exactly twice the
340  // size, but can easily be done in future.
341  if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
342  LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
343  return false;
344  }
345  auto Undef = MIRBuilder.buildUndef({OldLLT});
346  CurVReg =
347  MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
348  } else {
349  // Just do a vector extend.
350  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
351  .getReg(0);
352  }
353  } else if (NewLLT.getNumElements() == 2) {
354  // We need to pad a <1 x S> type to <2 x S>. Since we don't have
355  // <1 x S> vector types in GISel we use a build_vector instead
356  // of a vector merge/concat.
357  auto Undef = MIRBuilder.buildUndef({OldLLT});
358  CurVReg =
359  MIRBuilder
360  .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
361  .getReg(0);
362  } else {
363  LLVM_DEBUG(dbgs() << "Could not handle ret ty");
364  return false;
365  }
366  } else {
367  // If the split EVT was a <1 x T> vector, and NewVT is T, then we
368  // don't have to do anything since we don't distinguish between the
369  // two.
370  if (NewLLT != MRI.getType(CurVReg)) {
371  // A scalar extend.
372  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
373  .getReg(0);
374  }
375  }
376  }
377  }
378  if (CurVReg != CurArgInfo.Regs[0]) {
379  CurArgInfo.Regs[0] = CurVReg;
380  // Reset the arg flags after modifying CurVReg.
382  }
383  splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
384  }
385 
386  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn,
387  F.isVarArg());
388  Success =
389  handleAssignments(MIRBuilder, SplitArgs, Handler, CC, F.isVarArg());
390  }
391 
392  if (SwiftErrorVReg) {
393  MIB.addUse(AArch64::X21, RegState::Implicit);
394  MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
395  }
396 
397  MIRBuilder.insertInstr(MIB);
398  return Success;
399 }
400 
401 /// Helper function to compute forwarded registers for musttail calls. Computes
402 /// the forwarded registers, sets MBB liveness, and emits COPY instructions that
403 /// can be used to save + restore registers later.
405  CCAssignFn *AssignFn) {
406  MachineBasicBlock &MBB = MIRBuilder.getMBB();
407  MachineFunction &MF = MIRBuilder.getMF();
408  MachineFrameInfo &MFI = MF.getFrameInfo();
409 
410  if (!MFI.hasMustTailInVarArgFunc())
411  return;
412 
414  const Function &F = MF.getFunction();
415  assert(F.isVarArg() && "Expected F to be vararg?");
416 
417  // Compute the set of forwarded registers. The rest are scratch.
419  CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
420  F.getContext());
421  SmallVector<MVT, 2> RegParmTypes;
422  RegParmTypes.push_back(MVT::i64);
423  RegParmTypes.push_back(MVT::f128);
424 
425  // Later on, we can use this vector to restore the registers if necessary.
427  FuncInfo->getForwardedMustTailRegParms();
428  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
429 
430  // Conservatively forward X8, since it might be used for an aggregate
431  // return.
432  if (!CCInfo.isAllocated(AArch64::X8)) {
433  Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
434  Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
435  }
436 
437  // Add the forwards to the MachineBasicBlock and MachineFunction.
438  for (const auto &F : Forwards) {
439  MBB.addLiveIn(F.PReg);
440  MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
441  }
442 }
443 
445  auto &F = MF.getFunction();
446  if (isa<ScalableVectorType>(F.getReturnType()))
447  return true;
448  if (llvm::any_of(F.args(), [](const Argument &A) {
449  return isa<ScalableVectorType>(A.getType());
450  }))
451  return true;
452  const auto &ST = MF.getSubtarget<AArch64Subtarget>();
453  LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON");
454  if (!ST.hasNEON() || !ST.hasFPARMv8())
455  return true;
456  return false;
457 }
458 
460  MachineIRBuilder &MIRBuilder, const Function &F,
461  ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
462  MachineFunction &MF = MIRBuilder.getMF();
463  MachineBasicBlock &MBB = MIRBuilder.getMBB();
465  auto &DL = F.getParent()->getDataLayout();
466 
467  SmallVector<ArgInfo, 8> SplitArgs;
468  unsigned i = 0;
469  for (auto &Arg : F.args()) {
470  if (DL.getTypeStoreSize(Arg.getType()).isZero())
471  continue;
472 
473  ArgInfo OrigArg{VRegs[i], Arg};
475 
476  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
477  ++i;
478  }
479 
480  if (!MBB.empty())
481  MIRBuilder.setInstr(*MBB.begin());
482 
483  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
484  CCAssignFn *AssignFn =
485  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
486 
487  FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
488  if (!handleAssignments(MIRBuilder, SplitArgs, Handler, F.getCallingConv(),
489  F.isVarArg()))
490  return false;
491 
493  uint64_t StackOffset = Handler.StackUsed;
494  if (F.isVarArg()) {
495  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
496  if (!Subtarget.isTargetDarwin()) {
497  // FIXME: we need to reimplement saveVarArgsRegisters from
498  // AArch64ISelLowering.
499  return false;
500  }
501 
502  // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
503  StackOffset = alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8);
504 
505  auto &MFI = MIRBuilder.getMF().getFrameInfo();
506  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
507  }
508 
509  if (doesCalleeRestoreStack(F.getCallingConv(),
511  // We have a non-standard ABI, so why not make full use of the stack that
512  // we're going to pop? It must be aligned to 16 B in any case.
514 
515  // If we're expected to restore the stack (e.g. fastcc), then we'll be
516  // adding a multiple of 16.
518 
519  // Our own callers will guarantee that the space is free by giving an
520  // aligned value to CALLSEQ_START.
521  }
522 
523  // When we tail call, we need to check if the callee's arguments
524  // will fit on the caller's stack. So, whenever we lower formal arguments,
525  // we should keep track of this information, since we might lower a tail call
526  // in this function later.
528 
529  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
530  if (Subtarget.hasCustomCallingConv())
532 
533  handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
534 
535  // Move back to the end of the basic block.
536  MIRBuilder.setMBB(MBB);
537 
538  return true;
539 }
540 
541 /// Return true if the calling convention is one that we can guarantee TCO for.
543  return CC == CallingConv::Fast;
544 }
545 
546 /// Return true if we might ever do TCO for calls with this calling convention.
548  switch (CC) {
549  case CallingConv::C:
551  case CallingConv::Swift:
552  return true;
553  default:
554  return canGuaranteeTCO(CC);
555  }
556 }
557 
558 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
559 /// CC.
560 static std::pair<CCAssignFn *, CCAssignFn *>
562  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
563 }
564 
565 bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
566  CallLoweringInfo &Info, MachineFunction &MF,
567  SmallVectorImpl<ArgInfo> &InArgs) const {
568  const Function &CallerF = MF.getFunction();
569  CallingConv::ID CalleeCC = Info.CallConv;
570  CallingConv::ID CallerCC = CallerF.getCallingConv();
571 
572  // If the calling conventions match, then everything must be the same.
573  if (CalleeCC == CallerCC)
574  return true;
575 
576  // Check if the caller and callee will handle arguments in the same way.
577  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
578  CCAssignFn *CalleeAssignFnFixed;
579  CCAssignFn *CalleeAssignFnVarArg;
580  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
581  getAssignFnsForCC(CalleeCC, TLI);
582 
583  CCAssignFn *CallerAssignFnFixed;
584  CCAssignFn *CallerAssignFnVarArg;
585  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
586  getAssignFnsForCC(CallerCC, TLI);
587 
588  if (!resultsCompatible(Info, MF, InArgs, *CalleeAssignFnFixed,
589  *CalleeAssignFnVarArg, *CallerAssignFnFixed,
590  *CallerAssignFnVarArg))
591  return false;
592 
593  // Make sure that the caller and callee preserve all of the same registers.
594  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
595  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
596  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
598  TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
599  TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
600  }
601 
602  return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
603 }
604 
605 bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
606  CallLoweringInfo &Info, MachineFunction &MF,
607  SmallVectorImpl<ArgInfo> &OutArgs) const {
608  // If there are no outgoing arguments, then we are done.
609  if (OutArgs.empty())
610  return true;
611 
612  const Function &CallerF = MF.getFunction();
613  CallingConv::ID CalleeCC = Info.CallConv;
614  CallingConv::ID CallerCC = CallerF.getCallingConv();
615  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
616 
617  CCAssignFn *AssignFnFixed;
618  CCAssignFn *AssignFnVarArg;
619  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
620 
621  // We have outgoing arguments. Make sure that we can tail call with them.
623  CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
624 
625  if (!analyzeArgInfo(OutInfo, OutArgs, *AssignFnFixed, *AssignFnVarArg)) {
626  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
627  return false;
628  }
629 
630  // Make sure that they can fit on the caller's stack.
631  const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
632  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
633  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
634  return false;
635  }
636 
637  // Verify that the parameters in callee-saved registers match.
638  // TODO: Port this over to CallLowering as general code once swiftself is
639  // supported.
640  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
641  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
643 
644  if (Info.IsVarArg) {
645  // Be conservative and disallow variadic memory operands to match SDAG's
646  // behaviour.
647  // FIXME: If the caller's calling convention is C, then we can
648  // potentially use its argument area. However, for cases like fastcc,
649  // we can't do anything.
650  for (unsigned i = 0; i < OutLocs.size(); ++i) {
651  auto &ArgLoc = OutLocs[i];
652  if (ArgLoc.isRegLoc())
653  continue;
654 
655  LLVM_DEBUG(
656  dbgs()
657  << "... Cannot tail call vararg function with stack arguments\n");
658  return false;
659  }
660  }
661 
662  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
663 }
664 
666  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
667  SmallVectorImpl<ArgInfo> &InArgs,
668  SmallVectorImpl<ArgInfo> &OutArgs) const {
669 
670  // Must pass all target-independent checks in order to tail call optimize.
671  if (!Info.IsTailCall)
672  return false;
673 
674  CallingConv::ID CalleeCC = Info.CallConv;
675  MachineFunction &MF = MIRBuilder.getMF();
676  const Function &CallerF = MF.getFunction();
677 
678  LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
679 
680  if (Info.SwiftErrorVReg) {
681  // TODO: We should handle this.
682  // Note that this is also handled by the check for no outgoing arguments.
683  // Proactively disabling this though, because the swifterror handling in
684  // lowerCall inserts a COPY *after* the location of the call.
685  LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
686  return false;
687  }
688 
689  if (!mayTailCallThisCC(CalleeCC)) {
690  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
691  return false;
692  }
693 
694  // Byval parameters hand the function a pointer directly into the stack area
695  // we want to reuse during a tail call. Working around this *is* possible (see
696  // X86).
697  //
698  // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
699  // it?
700  //
701  // On Windows, "inreg" attributes signify non-aggregate indirect returns.
702  // In this case, it is necessary to save/restore X0 in the callee. Tail
703  // call opt interferes with this. So we disable tail call opt when the
704  // caller has an argument with "inreg" attribute.
705  //
706  // FIXME: Check whether the callee also has an "inreg" argument.
707  //
708  // When the caller has a swifterror argument, we don't want to tail call
709  // because would have to move into the swifterror register before the
710  // tail call.
711  if (any_of(CallerF.args(), [](const Argument &A) {
712  return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
713  })) {
714  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
715  "inreg, or swifterror arguments\n");
716  return false;
717  }
718 
719  // Externally-defined functions with weak linkage should not be
720  // tail-called on AArch64 when the OS does not support dynamic
721  // pre-emption of symbols, as the AAELF spec requires normal calls
722  // to undefined weak functions to be replaced with a NOP or jump to the
723  // next instruction. The behaviour of branch instructions in this
724  // situation (as used for tail calls) is implementation-defined, so we
725  // cannot rely on the linker replacing the tail call with a return.
726  if (Info.Callee.isGlobal()) {
727  const GlobalValue *GV = Info.Callee.getGlobal();
728  const Triple &TT = MF.getTarget().getTargetTriple();
729  if (GV->hasExternalWeakLinkage() &&
730  (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
731  TT.isOSBinFormatMachO())) {
732  LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
733  "with weak linkage for this OS.\n");
734  return false;
735  }
736  }
737 
738  // If we have -tailcallopt, then we're done.
740  return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
741 
742  // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
743  // Try to find cases where we can do that.
744 
745  // I want anyone implementing a new calling convention to think long and hard
746  // about this assert.
747  assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
748  "Unexpected variadic calling convention");
749 
750  // Verify that the incoming and outgoing arguments from the callee are
751  // safe to tail call.
752  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
753  LLVM_DEBUG(
754  dbgs()
755  << "... Caller and callee have incompatible calling conventions.\n");
756  return false;
757  }
758 
759  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
760  return false;
761 
762  LLVM_DEBUG(
763  dbgs() << "... Call is eligible for tail call optimization.\n");
764  return true;
765 }
766 
767 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
768  bool IsTailCall) {
769  if (!IsTailCall)
770  return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
771 
772  if (!IsIndirect)
773  return AArch64::TCRETURNdi;
774 
775  // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
776  // x16 or x17.
778  return AArch64::TCRETURNriBTI;
779 
780  return AArch64::TCRETURNri;
781 }
782 
783 static const uint32_t *
785  AArch64CallLowering::CallLoweringInfo &Info,
787  const uint32_t *Mask;
788  if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
789  // For 'this' returns, use the X0-preserving mask if applicable
790  Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
791  if (!Mask) {
792  OutArgs[0].Flags[0].setReturned(false);
793  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
794  }
795  } else {
796  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
797  }
798  return Mask;
799 }
800 
801 bool AArch64CallLowering::lowerTailCall(
802  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
803  SmallVectorImpl<ArgInfo> &OutArgs) const {
804  MachineFunction &MF = MIRBuilder.getMF();
805  const Function &F = MF.getFunction();
807  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
809 
810  // True when we're tail calling, but without -tailcallopt.
811  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
812 
813  // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
814  // register class. Until we can do that, we should fall back here.
816  LLVM_DEBUG(
817  dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
818  return false;
819  }
820 
821  // Find out which ABI gets to decide where things go.
822  CallingConv::ID CalleeCC = Info.CallConv;
823  CCAssignFn *AssignFnFixed;
824  CCAssignFn *AssignFnVarArg;
825  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
826 
827  MachineInstrBuilder CallSeqStart;
828  if (!IsSibCall)
829  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
830 
831  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
832  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
833  MIB.add(Info.Callee);
834 
835  // Byte offset for the tail call. When we are sibcalling, this will always
836  // be 0.
837  MIB.addImm(0);
838 
839  // Tell the call which registers are clobbered.
840  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
841  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
843  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
844  MIB.addRegMask(Mask);
845 
846  if (TRI->isAnyArgRegReserved(MF))
847  TRI->emitReservedArgRegCallError(MF);
848 
849  // FPDiff is the byte offset of the call's argument area from the callee's.
850  // Stores to callee stack arguments will be placed in FixedStackSlots offset
851  // by this amount for a tail call. In a sibling call it must be 0 because the
852  // caller will deallocate the entire stack and the callee still expects its
853  // arguments to begin at SP+0.
854  int FPDiff = 0;
855 
856  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
857  // by -tailcallopt. For sibcalls, the memory operands for the call are
858  // already available in the caller's incoming argument space.
859  unsigned NumBytes = 0;
860  if (!IsSibCall) {
861  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
862  // before handling assignments, because FPDiff must be known for memory
863  // arguments.
864  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
866  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
867  analyzeArgInfo(OutInfo, OutArgs, *AssignFnFixed, *AssignFnVarArg);
868 
869  // The callee will pop the argument stack as a tail call. Thus, we must
870  // keep it 16-byte aligned.
871  NumBytes = alignTo(OutInfo.getNextStackOffset(), 16);
872 
873  // FPDiff will be negative if this tail call requires more space than we
874  // would automatically have in our incoming argument space. Positive if we
875  // actually shrink the stack.
876  FPDiff = NumReusableBytes - NumBytes;
877 
878  // The stack pointer must be 16-byte aligned at all times it's used for a
879  // memory operation, which in practice means at *all* times and in
880  // particular across call boundaries. Therefore our own arguments started at
881  // a 16-byte aligned SP and the delta applied for the tail call should
882  // satisfy the same constraint.
883  assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
884  }
885 
886  const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
887 
888  // Do the actual argument marshalling.
889  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
890  AssignFnVarArg, Info.IsVarArg, true, FPDiff);
891  if (!handleAssignments(MIRBuilder, OutArgs, Handler, CalleeCC, Info.IsVarArg))
892  return false;
893 
894  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
895 
896  if (Info.IsVarArg && Info.IsMustTailCall) {
897  // Now we know what's being passed to the function. Add uses to the call for
898  // the forwarded registers that we *aren't* passing as parameters. This will
899  // preserve the copies we build earlier.
900  for (const auto &F : Forwards) {
901  Register ForwardedReg = F.PReg;
902  // If the register is already passed, or aliases a register which is
903  // already being passed, then skip it.
904  if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
905  if (!Use.isReg())
906  return false;
907  return TRI->regsOverlap(Use.getReg(), ForwardedReg);
908  }))
909  continue;
910 
911  // We aren't passing it already, so we should add it to the call.
912  MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
913  MIB.addReg(ForwardedReg, RegState::Implicit);
914  }
915  }
916 
917  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
918  // sequence start and end here.
919  if (!IsSibCall) {
920  MIB->getOperand(1).setImm(FPDiff);
921  CallSeqStart.addImm(NumBytes).addImm(0);
922  // End the call sequence *before* emitting the call. Normally, we would
923  // tidy the frame up after the call. However, here, we've laid out the
924  // parameters so that when SP is reset, they will be in the correct
925  // location.
926  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
927  }
928 
929  // Now we can add the actual call instruction to the correct basic block.
930  MIRBuilder.insertInstr(MIB);
931 
932  // If Callee is a reg, since it is used by a target specific instruction,
933  // it must have a register class matching the constraint of that instruction.
934  if (Info.Callee.isReg())
936  *MF.getSubtarget().getRegBankInfo(), *MIB,
937  MIB->getDesc(), Info.Callee, 0);
938 
940  Info.LoweredTailCall = true;
941  return true;
942 }
943 
945  CallLoweringInfo &Info) const {
946  MachineFunction &MF = MIRBuilder.getMF();
947  const Function &F = MF.getFunction();
949  auto &DL = F.getParent()->getDataLayout();
950  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
951 
952  SmallVector<ArgInfo, 8> OutArgs;
953  for (auto &OrigArg : Info.OrigArgs) {
954  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
955  // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
956  if (OrigArg.Ty->isIntegerTy(1))
957  OutArgs.back().Flags[0].setZExt();
958  }
959 
961  if (!Info.OrigRet.Ty->isVoidTy())
962  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
963 
964  // If we can lower as a tail call, do that instead.
965  bool CanTailCallOpt =
966  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
967 
968  // We must emit a tail call if we have musttail.
969  if (Info.IsMustTailCall && !CanTailCallOpt) {
970  // There are types of incoming/outgoing arguments we can't handle yet, so
971  // it doesn't make sense to actually die here like in ISelLowering. Instead,
972  // fall back to SelectionDAG and let it try to handle this.
973  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
974  return false;
975  }
976 
977  if (CanTailCallOpt)
978  return lowerTailCall(MIRBuilder, Info, OutArgs);
979 
980  // Find out which ABI gets to decide where things go.
981  CCAssignFn *AssignFnFixed;
982  CCAssignFn *AssignFnVarArg;
983  std::tie(AssignFnFixed, AssignFnVarArg) =
984  getAssignFnsForCC(Info.CallConv, TLI);
985 
986  MachineInstrBuilder CallSeqStart;
987  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
988 
989  // Create a temporarily-floating call instruction so we can add the implicit
990  // uses of arg registers.
991  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
992 
993  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
994  MIB.add(Info.Callee);
995 
996  // Tell the call which registers are clobbered.
997  const uint32_t *Mask;
998  const auto *TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
999 
1000  // Do the actual argument marshalling.
1001  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
1002  AssignFnVarArg, Info.IsVarArg, false);
1003  if (!handleAssignments(MIRBuilder, OutArgs, Handler, Info.CallConv,
1004  Info.IsVarArg))
1005  return false;
1006 
1007  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1008 
1010  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1011  MIB.addRegMask(Mask);
1012 
1013  if (TRI->isAnyArgRegReserved(MF))
1014  TRI->emitReservedArgRegCallError(MF);
1015 
1016  // Now we can add the actual call instruction to the correct basic block.
1017  MIRBuilder.insertInstr(MIB);
1018 
1019  // If Callee is a reg, since it is used by a target specific
1020  // instruction, it must have a register class matching the
1021  // constraint of that instruction.
1022  if (Info.Callee.isReg())
1024  *MF.getSubtarget().getRegBankInfo(), *MIB,
1025  MIB->getDesc(), Info.Callee, 0);
1026 
1027  // Finally we can copy the returned value back into its virtual-register. In
1028  // symmetry with the arguments, the physical register must be an
1029  // implicit-define of the call instruction.
1030  if (!Info.OrigRet.Ty->isVoidTy()) {
1031  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
1032  CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
1033  bool UsingReturnedArg =
1034  !OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1035  ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB,
1036  RetAssignFn);
1037  if (!handleAssignments(MIRBuilder, InArgs,
1038  UsingReturnedArg ? ReturnedArgHandler : Handler,
1039  Info.CallConv, Info.IsVarArg,
1040  UsingReturnedArg ? OutArgs[0].Regs[0] : Register()))
1041  return false;
1042  }
1043 
1044  if (Info.SwiftErrorVReg) {
1045  MIB.addDef(AArch64::X21, RegState::Implicit);
1046  MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1047  }
1048 
1049  uint64_t CalleePopBytes =
1050  doesCalleeRestoreStack(Info.CallConv,
1052  ? alignTo(Handler.StackSize, 16)
1053  : 0;
1054 
1055  CallSeqStart.addImm(Handler.StackSize).addImm(0);
1056  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1057  .addImm(Handler.StackSize)
1058  .addImm(CalleePopBytes);
1059 
1060  return true;
1061 }
1062 
1064  return Ty.getSizeInBits() == 64;
1065 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
i
i
Definition: README.txt:29
llvm::AArch64CallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: AArch64CallLowering.cpp:277
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:158
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AArch64FunctionInfo::setArgumentStackToRestore
void setArgumentStackToRestore(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:171
LowLevelType.h
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:655
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:211
AArch64MachineFunctionInfo.h
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:807
llvm::AArch64CallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AArch64CallLowering.cpp:944
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:163
llvm::AArch64CallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AArch64CallLowering.cpp:459
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:347
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:7211
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:652
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:316
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:475
llvm::CallLowering::OutgoingValueHandler
Definition: CallLowering.h:244
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:634
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:341
MachineIRBuilder.h
llvm::AArch64FunctionInfo::setVarArgsStackIndex
void setVarArgsStackIndex(int Index)
Definition: AArch64MachineFunctionInfo.h:282
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:446
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::CCState::analyzeMustTailForwardedRegisters
void analyzeMustTailForwardedRegisters(SmallVectorImpl< ForwardedRegister > &Forwards, ArrayRef< MVT > RegParmTypes, CCAssignFn Fn)
Compute the set of registers that need to be preserved and forwarded to any musttail calls.
Definition: CallingConvLower.cpp:245
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:117
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::CallLowering::analyzeArgInfo
bool analyzeArgInfo(CCState &CCState, SmallVectorImpl< ArgInfo > &Args, CCAssignFn &AssignFnFixed, CCAssignFn &AssignFnVarArg) const
Analyze passed or returned values from a call, supplied in ArgInfo, incorporating info about the pass...
Definition: CallLowering.cpp:873
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:426
llvm::AArch64FunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: AArch64MachineFunctionInfo.h:167
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:83
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:332
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::AArch64FunctionInfo::setBytesInStackArgArea
void setBytesInStackArgArea(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:168
llvm::LLT::getSizeInBytes
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:117
llvm::CallLowering::handleAssignments
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke Handler::assignArg on each of the given Args and then use Handler to move them to the assigned...
Definition: CallLowering.cpp:454
Utils.h
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::CallLowering::IncomingValueHandler
Definition: CallLowering.h:230
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AArch64CallLowering.cpp:561
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::MachineFrameInfo::hasMustTailInVarArgFunc
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
Definition: MachineFrameInfo.h:623
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:47
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:95
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
getMaskForArgs
static const uint32_t * getMaskForArgs(SmallVectorImpl< AArch64CallLowering::ArgInfo > &OutArgs, AArch64CallLowering::CallLoweringInfo &Info, const AArch64RegisterInfo &TRI, MachineFunction &MF)
Definition: AArch64CallLowering.cpp:784
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:473
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:388
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1498
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
handleMustTailForwardedRegisters
static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn)
Helper function to compute forwarded registers for musttail calls.
Definition: AArch64CallLowering.cpp:404
AArch64CallLowering.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:228
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:167
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:600
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:4658
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
Analysis.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:96
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:100
ArrayRef.h
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AArch64CallLowering.cpp:767
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:628
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::AArch64FunctionInfo::branchTargetEnforcement
bool branchTargetEnforcement() const
Definition: AArch64MachineFunctionInfo.h:373
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:569
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:124
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:128
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:634
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:198
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:358
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::AArch64FunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: AArch64MachineFunctionInfo.h:345
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AArch64CallLowering.cpp:547
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
AArch64ISelLowering.h
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
Argument.h
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:306
Attributes.h
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
MachineFrameInfo.h
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:584
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:53
Success
#define Success
Definition: AArch64Disassembler.cpp:248
doesCalleeRestoreStack
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
Definition: AArch64CallLowering.cpp:273
Function.h
llvm::CallLowering::ArgInfo::Regs
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:62
llvm::CallLowering::BaseArgInfo::Ty
Type * Ty
Definition: CallLowering.h:49
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:95
llvm::AArch64CallLowering::fallBackToDAGISel
bool fallBackToDAGISel(const MachineFunction &MF) const override
Definition: AArch64CallLowering.cpp:444
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, CCAssignFn &CalleeAssignFnFixed, CCAssignFn &CalleeAssignFnVarArg, CCAssignFn &CallerAssignFnFixed, CCAssignFn &CallerAssignFnVarArg) const
Definition: CallLowering.cpp:942
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:4691
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:196
AArch64Subtarget.h
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:55
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::AArch64CallLowering::isTypeIsValidForThisReturn
bool isTypeIsValidForThisReturn(EVT Ty) const override
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: AArch64CallLowering.cpp:1063
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1490
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:123
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:497
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:588
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:151
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::AArch64CallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AArch64CallLowering.cpp:665
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:388
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AArch64CallLowering.cpp:542
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:479
MachineFunction.h
llvm::AArch64CallLowering::AArch64CallLowering
AArch64CallLowering(const AArch64TargetLowering &TLI)
Definition: AArch64CallLowering.cpp:51
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:890
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
Value.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:390
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
llvm::CCState::isAllocated
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
Definition: CallingConvLower.h:277
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:150