LLVM  14.0.0git
AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64CallLowering.h"
16 #include "AArch64ISelLowering.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Argument.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstdint>
45 #include <iterator>
46 
47 #define DEBUG_TYPE "aarch64-call-lowering"
48 
49 using namespace llvm;
50 
52  : CallLowering(&TLI) {}
53 
54 static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT,
55  MVT &LocVT) {
56  // If ValVT is i1/i8/i16, we should set LocVT to i8/i8/i16. This is a legacy
57  // hack because the DAG calls the assignment function with pre-legalized
58  // register typed values, not the raw type.
59  //
60  // This hack is not applied to return values which are not passed on the
61  // stack.
62  if (OrigVT == MVT::i1 || OrigVT == MVT::i8)
63  ValVT = LocVT = MVT::i8;
64  else if (OrigVT == MVT::i16)
65  ValVT = LocVT = MVT::i16;
66 }
67 
68 // Account for i1/i8/i16 stack passed value hack
70  const MVT ValVT = VA.getValVT();
71  return (ValVT == MVT::i8 || ValVT == MVT::i16) ? LLT(ValVT)
72  : LLT(VA.getLocVT());
73 }
74 
75 namespace {
76 
77 struct AArch64IncomingValueAssigner
79  AArch64IncomingValueAssigner(CCAssignFn *AssignFn_,
80  CCAssignFn *AssignFnVarArg_)
81  : IncomingValueAssigner(AssignFn_, AssignFnVarArg_) {}
82 
83  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
84  CCValAssign::LocInfo LocInfo,
86  CCState &State) override {
87  applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
88  return IncomingValueAssigner::assignArg(ValNo, OrigVT, ValVT, LocVT,
89  LocInfo, Info, Flags, State);
90  }
91 };
92 
93 struct AArch64OutgoingValueAssigner
95  const AArch64Subtarget &Subtarget;
96 
97  /// Track if this is used for a return instead of function argument
98  /// passing. We apply a hack to i1/i8/i16 stack passed values, but do not use
99  /// stack passed returns for them and cannot apply the type adjustment.
100  bool IsReturn;
101 
102  AArch64OutgoingValueAssigner(CCAssignFn *AssignFn_,
103  CCAssignFn *AssignFnVarArg_,
104  const AArch64Subtarget &Subtarget_,
105  bool IsReturn)
106  : OutgoingValueAssigner(AssignFn_, AssignFnVarArg_),
107  Subtarget(Subtarget_), IsReturn(IsReturn) {}
108 
109  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
110  CCValAssign::LocInfo LocInfo,
112  CCState &State) override {
113  bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv());
114  bool UseVarArgsCCForFixed = IsCalleeWin && State.isVarArg();
115 
116  if (!State.isVarArg() && !UseVarArgsCCForFixed && !IsReturn)
117  applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
118 
119  bool Res;
120  if (Info.IsFixed && !UseVarArgsCCForFixed)
121  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
122  else
123  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
124 
126  return Res;
127  }
128 };
129 
130 struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
131  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
132  : IncomingValueHandler(MIRBuilder, MRI) {}
133 
134  Register getStackAddress(uint64_t Size, int64_t Offset,
135  MachinePointerInfo &MPO,
136  ISD::ArgFlagsTy Flags) override {
137  auto &MFI = MIRBuilder.getMF().getFrameInfo();
138 
139  // Byval is assumed to be writable memory, but other stack passed arguments
140  // are not.
141  const bool IsImmutable = !Flags.isByVal();
142 
143  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
144  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
145  auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
146  return AddrReg.getReg(0);
147  }
148 
149  LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
150  ISD::ArgFlagsTy Flags) const override {
151  // For pointers, we just need to fixup the integer types reported in the
152  // CCValAssign.
153  if (Flags.isPointer())
155  return getStackValueStoreTypeHack(VA);
156  }
157 
158  void assignValueToReg(Register ValVReg, Register PhysReg,
159  CCValAssign &VA) override {
160  markPhysRegUsed(PhysReg);
161  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
162  }
163 
164  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
165  MachinePointerInfo &MPO, CCValAssign &VA) override {
166  MachineFunction &MF = MIRBuilder.getMF();
167 
168  LLT ValTy(VA.getValVT());
169  LLT LocTy(VA.getLocVT());
170 
171  // Fixup the types for the DAG compatibility hack.
172  if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
173  std::swap(ValTy, LocTy);
174  else {
175  // The calling code knows if this is a pointer or not, we're only touching
176  // the LocTy for the i8/i16 hack.
177  assert(LocTy.getSizeInBits() == MemTy.getSizeInBits());
178  LocTy = MemTy;
179  }
180 
181  auto MMO = MF.getMachineMemOperand(
183  inferAlignFromPtrInfo(MF, MPO));
184 
185  switch (VA.getLocInfo()) {
186  case CCValAssign::LocInfo::ZExt:
187  MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, ValVReg, Addr, *MMO);
188  return;
189  case CCValAssign::LocInfo::SExt:
190  MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, ValVReg, Addr, *MMO);
191  return;
192  default:
193  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
194  return;
195  }
196  }
197 
198  /// How the physical register gets marked varies between formal
199  /// parameters (it's a basic-block live-in), and a call instruction
200  /// (it's an implicit-def of the BL).
201  virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
202 };
203 
204 struct FormalArgHandler : public IncomingArgHandler {
206  : IncomingArgHandler(MIRBuilder, MRI) {}
207 
208  void markPhysRegUsed(MCRegister PhysReg) override {
209  MIRBuilder.getMRI()->addLiveIn(PhysReg);
210  MIRBuilder.getMBB().addLiveIn(PhysReg);
211  }
212 };
213 
214 struct CallReturnHandler : public IncomingArgHandler {
215  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
217  : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
218 
219  void markPhysRegUsed(MCRegister PhysReg) override {
220  MIB.addDef(PhysReg, RegState::Implicit);
221  }
222 
224 };
225 
226 /// A special return arg handler for "returned" attribute arg calls.
227 struct ReturnedArgCallReturnHandler : public CallReturnHandler {
228  ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
231  : CallReturnHandler(MIRBuilder, MRI, MIB) {}
232 
233  void markPhysRegUsed(MCRegister PhysReg) override {}
234 };
235 
238  MachineInstrBuilder MIB, bool IsTailCall = false,
239  int FPDiff = 0)
240  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall),
241  FPDiff(FPDiff),
242  Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
243 
244  Register getStackAddress(uint64_t Size, int64_t Offset,
245  MachinePointerInfo &MPO,
246  ISD::ArgFlagsTy Flags) override {
247  MachineFunction &MF = MIRBuilder.getMF();
248  LLT p0 = LLT::pointer(0, 64);
249  LLT s64 = LLT::scalar(64);
250 
251  if (IsTailCall) {
252  assert(!Flags.isByVal() && "byval unhandled with tail calls");
253 
254  Offset += FPDiff;
255  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
256  auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
257  MPO = MachinePointerInfo::getFixedStack(MF, FI);
258  return FIReg.getReg(0);
259  }
260 
261  if (!SPReg)
262  SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
263 
264  auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
265 
266  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
267 
269  return AddrReg.getReg(0);
270  }
271 
272  /// We need to fixup the reported store size for certain value types because
273  /// we invert the interpretation of ValVT and LocVT in certain cases. This is
274  /// for compatability with the DAG call lowering implementation, which we're
275  /// currently building on top of.
276  LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
277  ISD::ArgFlagsTy Flags) const override {
278  if (Flags.isPointer())
280  return getStackValueStoreTypeHack(VA);
281  }
282 
283  void assignValueToReg(Register ValVReg, Register PhysReg,
284  CCValAssign &VA) override {
285  MIB.addUse(PhysReg, RegState::Implicit);
286  Register ExtReg = extendRegister(ValVReg, VA);
287  MIRBuilder.buildCopy(PhysReg, ExtReg);
288  }
289 
290  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
291  MachinePointerInfo &MPO, CCValAssign &VA) override {
292  MachineFunction &MF = MIRBuilder.getMF();
293  auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
294  inferAlignFromPtrInfo(MF, MPO));
295  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
296  }
297 
298  void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
299  Register Addr, LLT MemTy, MachinePointerInfo &MPO,
300  CCValAssign &VA) override {
301  unsigned MaxSize = MemTy.getSizeInBytes() * 8;
302  // For varargs, we always want to extend them to 8 bytes, in which case
303  // we disable setting a max.
304  if (!Arg.IsFixed)
305  MaxSize = 0;
306 
307  Register ValVReg = Arg.Regs[RegIndex];
308  if (VA.getLocInfo() != CCValAssign::LocInfo::FPExt) {
309  MVT LocVT = VA.getLocVT();
310  MVT ValVT = VA.getValVT();
311 
312  if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) {
313  std::swap(ValVT, LocVT);
314  MemTy = LLT(VA.getValVT());
315  }
316 
317  ValVReg = extendRegister(ValVReg, VA, MaxSize);
318  } else {
319  // The store does not cover the full allocated stack slot.
320  MemTy = LLT(VA.getValVT());
321  }
322 
323  assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
324  }
325 
327 
328  bool IsTailCall;
329 
330  /// For tail calls, the byte offset of the call's argument area from the
331  /// callee's. Unused elsewhere.
332  int FPDiff;
333 
334  // Cache the SP register vreg if we need it more than once in this call site.
335  Register SPReg;
336 
337  const AArch64Subtarget &Subtarget;
338 };
339 } // namespace
340 
341 static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
342  return (CallConv == CallingConv::Fast && TailCallOpt) ||
343  CallConv == CallingConv::Tail || CallConv == CallingConv::SwiftTail;
344 }
345 
347  const Value *Val,
348  ArrayRef<Register> VRegs,
350  Register SwiftErrorVReg) const {
351  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
352  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
353  "Return value without a vreg");
354 
355  bool Success = true;
356  if (!VRegs.empty()) {
357  MachineFunction &MF = MIRBuilder.getMF();
358  const Function &F = MF.getFunction();
359  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
360 
362  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
363  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
364  auto &DL = F.getParent()->getDataLayout();
365  LLVMContext &Ctx = Val->getType()->getContext();
366 
367  SmallVector<EVT, 4> SplitEVTs;
368  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
369  assert(VRegs.size() == SplitEVTs.size() &&
370  "For each split Type there should be exactly one VReg.");
371 
372  SmallVector<ArgInfo, 8> SplitArgs;
373  CallingConv::ID CC = F.getCallingConv();
374 
375  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
376  Register CurVReg = VRegs[i];
377  ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx), 0};
379 
380  // i1 is a special case because SDAG i1 true is naturally zero extended
381  // when widened using ANYEXT. We need to do it explicitly here.
382  if (MRI.getType(CurVReg).getSizeInBits() == 1) {
383  CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
384  } else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
385  1) {
386  // Some types will need extending as specified by the CC.
387  MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
388  if (EVT(NewVT) != SplitEVTs[i]) {
389  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
390  if (F.getAttributes().hasRetAttr(Attribute::SExt))
391  ExtendOp = TargetOpcode::G_SEXT;
392  else if (F.getAttributes().hasRetAttr(Attribute::ZExt))
393  ExtendOp = TargetOpcode::G_ZEXT;
394 
395  LLT NewLLT(NewVT);
396  LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
397  CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
398  // Instead of an extend, we might have a vector type which needs
399  // padding with more elements, e.g. <2 x half> -> <4 x half>.
400  if (NewVT.isVector()) {
401  if (OldLLT.isVector()) {
402  if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
403  // We don't handle VA types which are not exactly twice the
404  // size, but can easily be done in future.
405  if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
406  LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
407  return false;
408  }
409  auto Undef = MIRBuilder.buildUndef({OldLLT});
410  CurVReg =
411  MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
412  } else {
413  // Just do a vector extend.
414  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
415  .getReg(0);
416  }
417  } else if (NewLLT.getNumElements() == 2) {
418  // We need to pad a <1 x S> type to <2 x S>. Since we don't have
419  // <1 x S> vector types in GISel we use a build_vector instead
420  // of a vector merge/concat.
421  auto Undef = MIRBuilder.buildUndef({OldLLT});
422  CurVReg =
423  MIRBuilder
424  .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
425  .getReg(0);
426  } else {
427  LLVM_DEBUG(dbgs() << "Could not handle ret ty\n");
428  return false;
429  }
430  } else {
431  // If the split EVT was a <1 x T> vector, and NewVT is T, then we
432  // don't have to do anything since we don't distinguish between the
433  // two.
434  if (NewLLT != MRI.getType(CurVReg)) {
435  // A scalar extend.
436  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
437  .getReg(0);
438  }
439  }
440  }
441  }
442  if (CurVReg != CurArgInfo.Regs[0]) {
443  CurArgInfo.Regs[0] = CurVReg;
444  // Reset the arg flags after modifying CurVReg.
446  }
447  splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
448  }
449 
450  AArch64OutgoingValueAssigner Assigner(AssignFn, AssignFn, Subtarget,
451  /*IsReturn*/ true);
452  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
453  Success = determineAndHandleAssignments(Handler, Assigner, SplitArgs,
454  MIRBuilder, CC, F.isVarArg());
455  }
456 
457  if (SwiftErrorVReg) {
458  MIB.addUse(AArch64::X21, RegState::Implicit);
459  MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
460  }
461 
462  MIRBuilder.insertInstr(MIB);
463  return Success;
464 }
465 
466 /// Helper function to compute forwarded registers for musttail calls. Computes
467 /// the forwarded registers, sets MBB liveness, and emits COPY instructions that
468 /// can be used to save + restore registers later.
470  CCAssignFn *AssignFn) {
471  MachineBasicBlock &MBB = MIRBuilder.getMBB();
472  MachineFunction &MF = MIRBuilder.getMF();
473  MachineFrameInfo &MFI = MF.getFrameInfo();
474 
475  if (!MFI.hasMustTailInVarArgFunc())
476  return;
477 
479  const Function &F = MF.getFunction();
480  assert(F.isVarArg() && "Expected F to be vararg?");
481 
482  // Compute the set of forwarded registers. The rest are scratch.
484  CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
485  F.getContext());
486  SmallVector<MVT, 2> RegParmTypes;
487  RegParmTypes.push_back(MVT::i64);
488  RegParmTypes.push_back(MVT::f128);
489 
490  // Later on, we can use this vector to restore the registers if necessary.
492  FuncInfo->getForwardedMustTailRegParms();
493  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
494 
495  // Conservatively forward X8, since it might be used for an aggregate
496  // return.
497  if (!CCInfo.isAllocated(AArch64::X8)) {
498  Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
499  Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
500  }
501 
502  // Add the forwards to the MachineBasicBlock and MachineFunction.
503  for (const auto &F : Forwards) {
504  MBB.addLiveIn(F.PReg);
505  MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
506  }
507 }
508 
510  auto &F = MF.getFunction();
511  if (isa<ScalableVectorType>(F.getReturnType()))
512  return true;
513  if (llvm::any_of(F.args(), [](const Argument &A) {
514  return isa<ScalableVectorType>(A.getType());
515  }))
516  return true;
517  const auto &ST = MF.getSubtarget<AArch64Subtarget>();
518  if (!ST.hasNEON() || !ST.hasFPARMv8()) {
519  LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON\n");
520  return true;
521  }
522  return false;
523 }
524 
526  MachineIRBuilder &MIRBuilder, const Function &F,
527  ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
528  MachineFunction &MF = MIRBuilder.getMF();
529  MachineBasicBlock &MBB = MIRBuilder.getMBB();
531  auto &DL = F.getParent()->getDataLayout();
532 
533  SmallVector<ArgInfo, 8> SplitArgs;
534  unsigned i = 0;
535  for (auto &Arg : F.args()) {
536  if (DL.getTypeStoreSize(Arg.getType()).isZero())
537  continue;
538 
539  ArgInfo OrigArg{VRegs[i], Arg, i};
541 
542  if (Arg.hasAttribute(Attribute::SwiftAsync))
543  MF.getInfo<AArch64FunctionInfo>()->setHasSwiftAsyncContext(true);
544 
545  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
546  ++i;
547  }
548 
549  if (!MBB.empty())
550  MIRBuilder.setInstr(*MBB.begin());
551 
552  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
553  CCAssignFn *AssignFn =
554  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
555 
556  AArch64IncomingValueAssigner Assigner(AssignFn, AssignFn);
557  FormalArgHandler Handler(MIRBuilder, MRI);
558  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
559  F.getCallingConv(), F.isVarArg()))
560  return false;
561 
563  uint64_t StackOffset = Assigner.StackOffset;
564  if (F.isVarArg()) {
565  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
566  if (!Subtarget.isTargetDarwin()) {
567  // FIXME: we need to reimplement saveVarArgsRegisters from
568  // AArch64ISelLowering.
569  return false;
570  }
571 
572  // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
573  StackOffset =
574  alignTo(Assigner.StackOffset, Subtarget.isTargetILP32() ? 4 : 8);
575 
576  auto &MFI = MIRBuilder.getMF().getFrameInfo();
577  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
578  }
579 
580  if (doesCalleeRestoreStack(F.getCallingConv(),
582  // We have a non-standard ABI, so why not make full use of the stack that
583  // we're going to pop? It must be aligned to 16 B in any case.
585 
586  // If we're expected to restore the stack (e.g. fastcc), then we'll be
587  // adding a multiple of 16.
589 
590  // Our own callers will guarantee that the space is free by giving an
591  // aligned value to CALLSEQ_START.
592  }
593 
594  // When we tail call, we need to check if the callee's arguments
595  // will fit on the caller's stack. So, whenever we lower formal arguments,
596  // we should keep track of this information, since we might lower a tail call
597  // in this function later.
599 
600  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
601  if (Subtarget.hasCustomCallingConv())
603 
604  handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
605 
606  // Move back to the end of the basic block.
607  MIRBuilder.setMBB(MBB);
608 
609  return true;
610 }
611 
612 /// Return true if the calling convention is one that we can guarantee TCO for.
613 static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
614  return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
616 }
617 
618 /// Return true if we might ever do TCO for calls with this calling convention.
620  switch (CC) {
621  case CallingConv::C:
623  case CallingConv::Swift:
625  case CallingConv::Tail:
626  case CallingConv::Fast:
627  return true;
628  default:
629  return false;
630  }
631 }
632 
633 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
634 /// CC.
635 static std::pair<CCAssignFn *, CCAssignFn *>
637  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
638 }
639 
640 bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
641  CallLoweringInfo &Info, MachineFunction &MF,
642  SmallVectorImpl<ArgInfo> &InArgs) const {
643  const Function &CallerF = MF.getFunction();
644  CallingConv::ID CalleeCC = Info.CallConv;
645  CallingConv::ID CallerCC = CallerF.getCallingConv();
646 
647  // If the calling conventions match, then everything must be the same.
648  if (CalleeCC == CallerCC)
649  return true;
650 
651  // Check if the caller and callee will handle arguments in the same way.
652  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
653  CCAssignFn *CalleeAssignFnFixed;
654  CCAssignFn *CalleeAssignFnVarArg;
655  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
656  getAssignFnsForCC(CalleeCC, TLI);
657 
658  CCAssignFn *CallerAssignFnFixed;
659  CCAssignFn *CallerAssignFnVarArg;
660  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
661  getAssignFnsForCC(CallerCC, TLI);
662 
663  AArch64IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
664  CalleeAssignFnVarArg);
665  AArch64IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
666  CallerAssignFnVarArg);
667 
668  if (!resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner))
669  return false;
670 
671  // Make sure that the caller and callee preserve all of the same registers.
672  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
673  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
674  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
676  TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
677  TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
678  }
679 
680  return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
681 }
682 
683 bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
684  CallLoweringInfo &Info, MachineFunction &MF,
685  SmallVectorImpl<ArgInfo> &OutArgs) const {
686  // If there are no outgoing arguments, then we are done.
687  if (OutArgs.empty())
688  return true;
689 
690  const Function &CallerF = MF.getFunction();
691  LLVMContext &Ctx = CallerF.getContext();
692  CallingConv::ID CalleeCC = Info.CallConv;
693  CallingConv::ID CallerCC = CallerF.getCallingConv();
694  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
695  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
696 
697  CCAssignFn *AssignFnFixed;
698  CCAssignFn *AssignFnVarArg;
699  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
700 
701  // We have outgoing arguments. Make sure that we can tail call with them.
703  CCState OutInfo(CalleeCC, false, MF, OutLocs, Ctx);
704 
705  AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
706  Subtarget, /*IsReturn*/ false);
707  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo)) {
708  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
709  return false;
710  }
711 
712  // Make sure that they can fit on the caller's stack.
713  const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
714  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
715  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
716  return false;
717  }
718 
719  // Verify that the parameters in callee-saved registers match.
720  // TODO: Port this over to CallLowering as general code once swiftself is
721  // supported.
722  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
723  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
725 
726  if (Info.IsVarArg) {
727  // Be conservative and disallow variadic memory operands to match SDAG's
728  // behaviour.
729  // FIXME: If the caller's calling convention is C, then we can
730  // potentially use its argument area. However, for cases like fastcc,
731  // we can't do anything.
732  for (unsigned i = 0; i < OutLocs.size(); ++i) {
733  auto &ArgLoc = OutLocs[i];
734  if (ArgLoc.isRegLoc())
735  continue;
736 
737  LLVM_DEBUG(
738  dbgs()
739  << "... Cannot tail call vararg function with stack arguments\n");
740  return false;
741  }
742  }
743 
744  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
745 }
746 
748  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
749  SmallVectorImpl<ArgInfo> &InArgs,
750  SmallVectorImpl<ArgInfo> &OutArgs) const {
751 
752  // Must pass all target-independent checks in order to tail call optimize.
753  if (!Info.IsTailCall)
754  return false;
755 
756  CallingConv::ID CalleeCC = Info.CallConv;
757  MachineFunction &MF = MIRBuilder.getMF();
758  const Function &CallerF = MF.getFunction();
759 
760  LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
761 
762  if (Info.SwiftErrorVReg) {
763  // TODO: We should handle this.
764  // Note that this is also handled by the check for no outgoing arguments.
765  // Proactively disabling this though, because the swifterror handling in
766  // lowerCall inserts a COPY *after* the location of the call.
767  LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
768  return false;
769  }
770 
771  if (!mayTailCallThisCC(CalleeCC)) {
772  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
773  return false;
774  }
775 
776  // Byval parameters hand the function a pointer directly into the stack area
777  // we want to reuse during a tail call. Working around this *is* possible (see
778  // X86).
779  //
780  // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
781  // it?
782  //
783  // On Windows, "inreg" attributes signify non-aggregate indirect returns.
784  // In this case, it is necessary to save/restore X0 in the callee. Tail
785  // call opt interferes with this. So we disable tail call opt when the
786  // caller has an argument with "inreg" attribute.
787  //
788  // FIXME: Check whether the callee also has an "inreg" argument.
789  //
790  // When the caller has a swifterror argument, we don't want to tail call
791  // because would have to move into the swifterror register before the
792  // tail call.
793  if (any_of(CallerF.args(), [](const Argument &A) {
794  return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
795  })) {
796  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
797  "inreg, or swifterror arguments\n");
798  return false;
799  }
800 
801  // Externally-defined functions with weak linkage should not be
802  // tail-called on AArch64 when the OS does not support dynamic
803  // pre-emption of symbols, as the AAELF spec requires normal calls
804  // to undefined weak functions to be replaced with a NOP or jump to the
805  // next instruction. The behaviour of branch instructions in this
806  // situation (as used for tail calls) is implementation-defined, so we
807  // cannot rely on the linker replacing the tail call with a return.
808  if (Info.Callee.isGlobal()) {
809  const GlobalValue *GV = Info.Callee.getGlobal();
810  const Triple &TT = MF.getTarget().getTargetTriple();
811  if (GV->hasExternalWeakLinkage() &&
812  (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
813  TT.isOSBinFormatMachO())) {
814  LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
815  "with weak linkage for this OS.\n");
816  return false;
817  }
818  }
819 
820  // If we have -tailcallopt, then we're done.
822  return CalleeCC == CallerF.getCallingConv();
823 
824  // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
825  // Try to find cases where we can do that.
826 
827  // I want anyone implementing a new calling convention to think long and hard
828  // about this assert.
829  assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
830  "Unexpected variadic calling convention");
831 
832  // Verify that the incoming and outgoing arguments from the callee are
833  // safe to tail call.
834  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
835  LLVM_DEBUG(
836  dbgs()
837  << "... Caller and callee have incompatible calling conventions.\n");
838  return false;
839  }
840 
841  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
842  return false;
843 
844  LLVM_DEBUG(
845  dbgs() << "... Call is eligible for tail call optimization.\n");
846  return true;
847 }
848 
849 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
850  bool IsTailCall) {
851  if (!IsTailCall)
852  return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
853 
854  if (!IsIndirect)
855  return AArch64::TCRETURNdi;
856 
857  // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
858  // x16 or x17.
860  return AArch64::TCRETURNriBTI;
861 
862  return AArch64::TCRETURNri;
863 }
864 
865 static const uint32_t *
867  AArch64CallLowering::CallLoweringInfo &Info,
869  const uint32_t *Mask;
870  if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
871  // For 'this' returns, use the X0-preserving mask if applicable
872  Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
873  if (!Mask) {
874  OutArgs[0].Flags[0].setReturned(false);
875  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
876  }
877  } else {
878  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
879  }
880  return Mask;
881 }
882 
883 bool AArch64CallLowering::lowerTailCall(
884  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
885  SmallVectorImpl<ArgInfo> &OutArgs) const {
886  MachineFunction &MF = MIRBuilder.getMF();
887  const Function &F = MF.getFunction();
889  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
891 
892  // True when we're tail calling, but without -tailcallopt.
893  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt &&
894  Info.CallConv != CallingConv::Tail &&
895  Info.CallConv != CallingConv::SwiftTail;
896 
897  // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
898  // register class. Until we can do that, we should fall back here.
900  LLVM_DEBUG(
901  dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
902  return false;
903  }
904 
905  // Find out which ABI gets to decide where things go.
906  CallingConv::ID CalleeCC = Info.CallConv;
907  CCAssignFn *AssignFnFixed;
908  CCAssignFn *AssignFnVarArg;
909  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
910 
911  MachineInstrBuilder CallSeqStart;
912  if (!IsSibCall)
913  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
914 
915  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
916  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
917  MIB.add(Info.Callee);
918 
919  // Byte offset for the tail call. When we are sibcalling, this will always
920  // be 0.
921  MIB.addImm(0);
922 
923  // Tell the call which registers are clobbered.
924  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
925  auto TRI = Subtarget.getRegisterInfo();
926  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
927  if (Subtarget.hasCustomCallingConv())
928  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
929  MIB.addRegMask(Mask);
930 
931  if (TRI->isAnyArgRegReserved(MF))
932  TRI->emitReservedArgRegCallError(MF);
933 
934  // FPDiff is the byte offset of the call's argument area from the callee's.
935  // Stores to callee stack arguments will be placed in FixedStackSlots offset
936  // by this amount for a tail call. In a sibling call it must be 0 because the
937  // caller will deallocate the entire stack and the callee still expects its
938  // arguments to begin at SP+0.
939  int FPDiff = 0;
940 
941  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
942  // by -tailcallopt. For sibcalls, the memory operands for the call are
943  // already available in the caller's incoming argument space.
944  unsigned NumBytes = 0;
945  if (!IsSibCall) {
946  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
947  // before handling assignments, because FPDiff must be known for memory
948  // arguments.
949  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
951  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
952 
953  AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
954  Subtarget, /*IsReturn*/ false);
955  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
956  return false;
957 
958  // The callee will pop the argument stack as a tail call. Thus, we must
959  // keep it 16-byte aligned.
960  NumBytes = alignTo(OutInfo.getNextStackOffset(), 16);
961 
962  // FPDiff will be negative if this tail call requires more space than we
963  // would automatically have in our incoming argument space. Positive if we
964  // actually shrink the stack.
965  FPDiff = NumReusableBytes - NumBytes;
966 
967  // Update the required reserved area if this is the tail call requiring the
968  // most argument stack space.
969  if (FPDiff < 0 && FuncInfo->getTailCallReservedStack() < (unsigned)-FPDiff)
970  FuncInfo->setTailCallReservedStack(-FPDiff);
971 
972  // The stack pointer must be 16-byte aligned at all times it's used for a
973  // memory operation, which in practice means at *all* times and in
974  // particular across call boundaries. Therefore our own arguments started at
975  // a 16-byte aligned SP and the delta applied for the tail call should
976  // satisfy the same constraint.
977  assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
978  }
979 
980  const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
981 
982  AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
983  Subtarget, /*IsReturn*/ false);
984 
985  // Do the actual argument marshalling.
986  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB,
987  /*IsTailCall*/ true, FPDiff);
988  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
989  CalleeCC, Info.IsVarArg))
990  return false;
991 
992  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
993 
994  if (Info.IsVarArg && Info.IsMustTailCall) {
995  // Now we know what's being passed to the function. Add uses to the call for
996  // the forwarded registers that we *aren't* passing as parameters. This will
997  // preserve the copies we build earlier.
998  for (const auto &F : Forwards) {
999  Register ForwardedReg = F.PReg;
1000  // If the register is already passed, or aliases a register which is
1001  // already being passed, then skip it.
1002  if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
1003  if (!Use.isReg())
1004  return false;
1005  return TRI->regsOverlap(Use.getReg(), ForwardedReg);
1006  }))
1007  continue;
1008 
1009  // We aren't passing it already, so we should add it to the call.
1010  MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
1011  MIB.addReg(ForwardedReg, RegState::Implicit);
1012  }
1013  }
1014 
1015  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1016  // sequence start and end here.
1017  if (!IsSibCall) {
1018  MIB->getOperand(1).setImm(FPDiff);
1019  CallSeqStart.addImm(0).addImm(0);
1020  // End the call sequence *before* emitting the call. Normally, we would
1021  // tidy the frame up after the call. However, here, we've laid out the
1022  // parameters so that when SP is reset, they will be in the correct
1023  // location.
1024  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0);
1025  }
1026 
1027  // Now we can add the actual call instruction to the correct basic block.
1028  MIRBuilder.insertInstr(MIB);
1029 
1030  // If Callee is a reg, since it is used by a target specific instruction,
1031  // it must have a register class matching the constraint of that instruction.
1032  if (Info.Callee.isReg())
1034  *MF.getSubtarget().getRegBankInfo(), *MIB,
1035  MIB->getDesc(), Info.Callee, 0);
1036 
1038  Info.LoweredTailCall = true;
1039  return true;
1040 }
1041 
1043  CallLoweringInfo &Info) const {
1044  MachineFunction &MF = MIRBuilder.getMF();
1045  const Function &F = MF.getFunction();
1047  auto &DL = F.getParent()->getDataLayout();
1048  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
1049 
1050  SmallVector<ArgInfo, 8> OutArgs;
1051  for (auto &OrigArg : Info.OrigArgs) {
1052  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1053  // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
1054  if (OrigArg.Ty->isIntegerTy(1))
1055  OutArgs.back().Flags[0].setZExt();
1056  }
1057 
1058  SmallVector<ArgInfo, 8> InArgs;
1059  if (!Info.OrigRet.Ty->isVoidTy())
1060  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1061 
1062  // If we can lower as a tail call, do that instead.
1063  bool CanTailCallOpt =
1064  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1065 
1066  // We must emit a tail call if we have musttail.
1067  if (Info.IsMustTailCall && !CanTailCallOpt) {
1068  // There are types of incoming/outgoing arguments we can't handle yet, so
1069  // it doesn't make sense to actually die here like in ISelLowering. Instead,
1070  // fall back to SelectionDAG and let it try to handle this.
1071  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1072  return false;
1073  }
1074 
1075  if (CanTailCallOpt)
1076  return lowerTailCall(MIRBuilder, Info, OutArgs);
1077 
1078  // Find out which ABI gets to decide where things go.
1079  CCAssignFn *AssignFnFixed;
1080  CCAssignFn *AssignFnVarArg;
1081  std::tie(AssignFnFixed, AssignFnVarArg) =
1082  getAssignFnsForCC(Info.CallConv, TLI);
1083 
1084  MachineInstrBuilder CallSeqStart;
1085  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1086 
1087  // Create a temporarily-floating call instruction so we can add the implicit
1088  // uses of arg registers.
1089  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1090 
1091  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1092  MIB.add(Info.Callee);
1093 
1094  // Tell the call which registers are clobbered.
1095  const uint32_t *Mask;
1096  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1097  const auto *TRI = Subtarget.getRegisterInfo();
1098 
1099  AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1100  Subtarget, /*IsReturn*/ false);
1101  // Do the actual argument marshalling.
1102  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, /*IsReturn*/ false);
1103  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1104  Info.CallConv, Info.IsVarArg))
1105  return false;
1106 
1107  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1108 
1110  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1111  MIB.addRegMask(Mask);
1112 
1113  if (TRI->isAnyArgRegReserved(MF))
1114  TRI->emitReservedArgRegCallError(MF);
1115 
1116  // Now we can add the actual call instruction to the correct basic block.
1117  MIRBuilder.insertInstr(MIB);
1118 
1119  // If Callee is a reg, since it is used by a target specific
1120  // instruction, it must have a register class matching the
1121  // constraint of that instruction.
1122  if (Info.Callee.isReg())
1123  constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),
1124  *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(),
1125  Info.Callee, 0);
1126 
1127  // Finally we can copy the returned value back into its virtual-register. In
1128  // symmetry with the arguments, the physical register must be an
1129  // implicit-define of the call instruction.
1130  if (!Info.OrigRet.Ty->isVoidTy()) {
1131  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
1132  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1133  bool UsingReturnedArg =
1134  !OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1135 
1136  AArch64OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn, Subtarget,
1137  /*IsReturn*/ false);
1138  ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB);
1140  UsingReturnedArg ? ReturnedArgHandler : Handler, Assigner, InArgs,
1141  MIRBuilder, Info.CallConv, Info.IsVarArg,
1142  UsingReturnedArg ? OutArgs[0].Regs[0] : Register()))
1143  return false;
1144  }
1145 
1146  if (Info.SwiftErrorVReg) {
1147  MIB.addDef(AArch64::X21, RegState::Implicit);
1148  MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1149  }
1150 
1151  uint64_t CalleePopBytes =
1152  doesCalleeRestoreStack(Info.CallConv,
1154  ? alignTo(Assigner.StackOffset, 16)
1155  : 0;
1156 
1157  CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
1158  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1159  .addImm(Assigner.StackOffset)
1160  .addImm(CalleePopBytes);
1161 
1162  return true;
1163 }
1164 
1166  return Ty.getSizeInBits() == 64;
1167 }
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:944
i
i
Definition: README.txt:29
llvm::AArch64CallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: AArch64CallLowering.cpp:346
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AArch64FunctionInfo::setArgumentStackToRestore
void setArgumentStackToRestore(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:185
LowLevelType.h
llvm::CallingConv::SwiftTail
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
Definition: CallingConv.h:92
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:213
AArch64MachineFunctionInfo.h
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:772
llvm::AArch64CallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AArch64CallLowering.cpp:1042
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::AArch64CallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AArch64CallLowering.cpp:525
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:61
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:280
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:7557
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:503
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::AArch64Subtarget::getInstrInfo
const AArch64InstrInfo * getInstrInfo() const override
Definition: AArch64Subtarget.h:319
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:326
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:211
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:632
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:333
MachineIRBuilder.h
llvm::AArch64FunctionInfo::setVarArgsStackIndex
void setVarArgsStackIndex(int Index)
Definition: AArch64MachineFunctionInfo.h:308
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
OutgoingArgHandler
Definition: M68kCallLowering.cpp:30
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:446
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::CCState::analyzeMustTailForwardedRegisters
void analyzeMustTailForwardedRegisters(SmallVectorImpl< ForwardedRegister > &Forwards, ArrayRef< MVT > RegParmTypes, CCAssignFn Fn)
Compute the set of registers that need to be preserved and forwarded to any musttail calls.
Definition: CallingConvLower.cpp:245
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
Definition: CallLowering.cpp:966
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:424
llvm::AArch64FunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: AArch64MachineFunctionInfo.h:181
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:324
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::AArch64Subtarget::isTargetILP32
bool isTargetILP32() const
Definition: AArch64Subtarget.h:514
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::AArch64FunctionInfo::setBytesInStackArgArea
void setBytesInStackArgArea(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:182
llvm::CallLowering::ValueHandler::getStackValueStoreType
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
Definition: CallLowering.cpp:1020
applyStackPassedSmallTypeDAGHack
static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT, MVT &LocVT)
Definition: AArch64CallLowering.cpp:54
Utils.h
llvm::FormalArgHandler
Definition: M68kCallLowering.h:65
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:219
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:546
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:262
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:311
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AArch64CallLowering.cpp:636
getStackValueStoreTypeHack
static LLT getStackValueStoreTypeHack(const CCValAssign &VA)
Definition: AArch64CallLowering.cpp:69
llvm::MachineFrameInfo::hasMustTailInVarArgFunc
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
Definition: MachineFrameInfo.h:602
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
getMaskForArgs
static const uint32_t * getMaskForArgs(SmallVectorImpl< AArch64CallLowering::ArgInfo > &OutArgs, AArch64CallLowering::CallLoweringInfo &Info, const AArch64RegisterInfo &TRI, MachineFunction &MF)
Definition: AArch64CallLowering.cpp:866
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:401
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1530
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
handleMustTailForwardedRegisters
static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn)
Helper function to compute forwarded registers for musttail calls.
Definition: AArch64CallLowering.cpp:469
AArch64CallLowering.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:167
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:648
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:5119
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
Analysis.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:123
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:127
ArrayRef.h
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AArch64CallLowering.cpp:849
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:607
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:259
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:120
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:287
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::AArch64FunctionInfo::branchTargetEnforcement
bool branchTargetEnforcement() const
Definition: AArch64MachineFunctionInfo.h:399
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:590
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:128
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:653
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:367
llvm::CCState::isVarArg
bool isVarArg() const
Definition: CallingConvLower.h:260
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:372
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1558
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::AArch64FunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: AArch64MachineFunctionInfo.h:371
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AArch64CallLowering.cpp:619
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:127
AArch64ISelLowering.h
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
Argument.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:320
Attributes.h
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:246
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
CallingConvLower.h
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:227
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
MachineFrameInfo.h
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:582
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:163
Success
#define Success
Definition: AArch64Disassembler.cpp:260
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:522
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:213
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
doesCalleeRestoreStack
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
Definition: AArch64CallLowering.cpp:341
Function.h
llvm::CallLowering::ArgInfo::Regs
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:62
llvm::ISD::ArgFlagsTy::isPointer
bool isPointer() const
Definition: TargetCallingConv.h:141
llvm::CallLowering::BaseArgInfo::Ty
Type * Ty
Definition: CallLowering.h:49
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:101
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:226
llvm::AArch64CallLowering::fallBackToDAGISel
bool fallBackToDAGISel(const MachineFunction &MF) const override
Definition: AArch64CallLowering.cpp:509
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:5154
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
AArch64Subtarget.h
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::AArch64CallLowering::isTypeIsValidForThisReturn
bool isTypeIsValidForThisReturn(EVT Ty) const override
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: AArch64CallLowering.cpp:1165
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AArch64CallLowering.cpp:613
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1522
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:128
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:49
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:526
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:586
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:155
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
MachineOperand.h
llvm::AArch64CallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AArch64CallLowering.cpp:747
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:484
MachineFunction.h
llvm::AArch64CallLowering::AArch64CallLowering
AArch64CallLowering(const AArch64TargetLowering &TLI)
Definition: AArch64CallLowering.cpp:51
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:914
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
Value.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:403
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
llvm::AArch64FunctionInfo::setTailCallReservedStack
void setTailCallReservedStack(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:190
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: M68kCallLowering.h:66
llvm::CCState::isAllocated
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
Definition: CallingConvLower.h:277
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:153