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AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64CallLowering.h"
16 #include "AArch64ISelLowering.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/Analysis.h"
37 #include "llvm/IR/Argument.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstdint>
46 #include <iterator>
47 
48 #define DEBUG_TYPE "aarch64-call-lowering"
49 
50 using namespace llvm;
51 
53  : CallLowering(&TLI) {}
54 
55 static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT,
56  MVT &LocVT) {
57  // If ValVT is i1/i8/i16, we should set LocVT to i8/i8/i16. This is a legacy
58  // hack because the DAG calls the assignment function with pre-legalized
59  // register typed values, not the raw type.
60  //
61  // This hack is not applied to return values which are not passed on the
62  // stack.
63  if (OrigVT == MVT::i1 || OrigVT == MVT::i8)
64  ValVT = LocVT = MVT::i8;
65  else if (OrigVT == MVT::i16)
66  ValVT = LocVT = MVT::i16;
67 }
68 
69 // Account for i1/i8/i16 stack passed value hack
71  const MVT ValVT = VA.getValVT();
72  return (ValVT == MVT::i8 || ValVT == MVT::i16) ? LLT(ValVT)
73  : LLT(VA.getLocVT());
74 }
75 
76 namespace {
77 
78 struct AArch64IncomingValueAssigner
80  AArch64IncomingValueAssigner(CCAssignFn *AssignFn_,
81  CCAssignFn *AssignFnVarArg_)
82  : IncomingValueAssigner(AssignFn_, AssignFnVarArg_) {}
83 
84  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
85  CCValAssign::LocInfo LocInfo,
87  CCState &State) override {
88  applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
89  return IncomingValueAssigner::assignArg(ValNo, OrigVT, ValVT, LocVT,
90  LocInfo, Info, Flags, State);
91  }
92 };
93 
94 struct AArch64OutgoingValueAssigner
96  const AArch64Subtarget &Subtarget;
97 
98  /// Track if this is used for a return instead of function argument
99  /// passing. We apply a hack to i1/i8/i16 stack passed values, but do not use
100  /// stack passed returns for them and cannot apply the type adjustment.
101  bool IsReturn;
102 
103  AArch64OutgoingValueAssigner(CCAssignFn *AssignFn_,
104  CCAssignFn *AssignFnVarArg_,
105  const AArch64Subtarget &Subtarget_,
106  bool IsReturn)
107  : OutgoingValueAssigner(AssignFn_, AssignFnVarArg_),
108  Subtarget(Subtarget_), IsReturn(IsReturn) {}
109 
110  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
111  CCValAssign::LocInfo LocInfo,
113  CCState &State) override {
114  bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv());
115  bool UseVarArgsCCForFixed = IsCalleeWin && State.isVarArg();
116 
117  if (!State.isVarArg() && !UseVarArgsCCForFixed && !IsReturn)
118  applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
119 
120  bool Res;
121  if (Info.IsFixed && !UseVarArgsCCForFixed)
122  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
123  else
124  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
125 
127  return Res;
128  }
129 };
130 
131 struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
132  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
133  : IncomingValueHandler(MIRBuilder, MRI) {}
134 
135  Register getStackAddress(uint64_t Size, int64_t Offset,
136  MachinePointerInfo &MPO,
137  ISD::ArgFlagsTy Flags) override {
138  auto &MFI = MIRBuilder.getMF().getFrameInfo();
139 
140  // Byval is assumed to be writable memory, but other stack passed arguments
141  // are not.
142  const bool IsImmutable = !Flags.isByVal();
143 
144  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
145  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
146  auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
147  return AddrReg.getReg(0);
148  }
149 
150  LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
151  ISD::ArgFlagsTy Flags) const override {
152  // For pointers, we just need to fixup the integer types reported in the
153  // CCValAssign.
154  if (Flags.isPointer())
156  return getStackValueStoreTypeHack(VA);
157  }
158 
159  void assignValueToReg(Register ValVReg, Register PhysReg,
160  CCValAssign VA) override {
161  markPhysRegUsed(PhysReg);
162  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
163  }
164 
165  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
166  MachinePointerInfo &MPO, CCValAssign &VA) override {
167  MachineFunction &MF = MIRBuilder.getMF();
168 
169  LLT ValTy(VA.getValVT());
170  LLT LocTy(VA.getLocVT());
171 
172  // Fixup the types for the DAG compatibility hack.
173  if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
174  std::swap(ValTy, LocTy);
175  else {
176  // The calling code knows if this is a pointer or not, we're only touching
177  // the LocTy for the i8/i16 hack.
178  assert(LocTy.getSizeInBits() == MemTy.getSizeInBits());
179  LocTy = MemTy;
180  }
181 
182  auto MMO = MF.getMachineMemOperand(
184  inferAlignFromPtrInfo(MF, MPO));
185 
186  switch (VA.getLocInfo()) {
187  case CCValAssign::LocInfo::ZExt:
188  MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, ValVReg, Addr, *MMO);
189  return;
190  case CCValAssign::LocInfo::SExt:
191  MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, ValVReg, Addr, *MMO);
192  return;
193  default:
194  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
195  return;
196  }
197  }
198 
199  /// How the physical register gets marked varies between formal
200  /// parameters (it's a basic-block live-in), and a call instruction
201  /// (it's an implicit-def of the BL).
202  virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
203 };
204 
205 struct FormalArgHandler : public IncomingArgHandler {
207  : IncomingArgHandler(MIRBuilder, MRI) {}
208 
209  void markPhysRegUsed(MCRegister PhysReg) override {
210  MIRBuilder.getMRI()->addLiveIn(PhysReg);
211  MIRBuilder.getMBB().addLiveIn(PhysReg);
212  }
213 };
214 
215 struct CallReturnHandler : public IncomingArgHandler {
218  : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
219 
220  void markPhysRegUsed(MCRegister PhysReg) override {
221  MIB.addDef(PhysReg, RegState::Implicit);
222  }
223 
225 };
226 
227 /// A special return arg handler for "returned" attribute arg calls.
228 struct ReturnedArgCallReturnHandler : public CallReturnHandler {
229  ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
232  : CallReturnHandler(MIRBuilder, MRI, MIB) {}
233 
234  void markPhysRegUsed(MCRegister PhysReg) override {}
235 };
236 
237 struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
238  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
239  MachineInstrBuilder MIB, bool IsTailCall = false,
240  int FPDiff = 0)
241  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall),
242  FPDiff(FPDiff),
243  Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
244 
245  Register getStackAddress(uint64_t Size, int64_t Offset,
246  MachinePointerInfo &MPO,
247  ISD::ArgFlagsTy Flags) override {
248  MachineFunction &MF = MIRBuilder.getMF();
249  LLT p0 = LLT::pointer(0, 64);
250  LLT s64 = LLT::scalar(64);
251 
252  if (IsTailCall) {
253  assert(!Flags.isByVal() && "byval unhandled with tail calls");
254 
255  Offset += FPDiff;
256  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
257  auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
258  MPO = MachinePointerInfo::getFixedStack(MF, FI);
259  return FIReg.getReg(0);
260  }
261 
262  if (!SPReg)
263  SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
264 
265  auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
266 
267  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
268 
269  MPO = MachinePointerInfo::getStack(MF, Offset);
270  return AddrReg.getReg(0);
271  }
272 
273  /// We need to fixup the reported store size for certain value types because
274  /// we invert the interpretation of ValVT and LocVT in certain cases. This is
275  /// for compatability with the DAG call lowering implementation, which we're
276  /// currently building on top of.
277  LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
278  ISD::ArgFlagsTy Flags) const override {
279  if (Flags.isPointer())
281  return getStackValueStoreTypeHack(VA);
282  }
283 
284  void assignValueToReg(Register ValVReg, Register PhysReg,
285  CCValAssign VA) override {
286  MIB.addUse(PhysReg, RegState::Implicit);
287  Register ExtReg = extendRegister(ValVReg, VA);
288  MIRBuilder.buildCopy(PhysReg, ExtReg);
289  }
290 
291  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
292  MachinePointerInfo &MPO, CCValAssign &VA) override {
293  MachineFunction &MF = MIRBuilder.getMF();
294  auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
295  inferAlignFromPtrInfo(MF, MPO));
296  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
297  }
298 
299  void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
300  Register Addr, LLT MemTy, MachinePointerInfo &MPO,
301  CCValAssign &VA) override {
302  unsigned MaxSize = MemTy.getSizeInBytes() * 8;
303  // For varargs, we always want to extend them to 8 bytes, in which case
304  // we disable setting a max.
305  if (!Arg.IsFixed)
306  MaxSize = 0;
307 
308  Register ValVReg = Arg.Regs[RegIndex];
309  if (VA.getLocInfo() != CCValAssign::LocInfo::FPExt) {
310  MVT LocVT = VA.getLocVT();
311  MVT ValVT = VA.getValVT();
312 
313  if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) {
314  std::swap(ValVT, LocVT);
315  MemTy = LLT(VA.getValVT());
316  }
317 
318  ValVReg = extendRegister(ValVReg, VA, MaxSize);
319  } else {
320  // The store does not cover the full allocated stack slot.
321  MemTy = LLT(VA.getValVT());
322  }
323 
324  assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
325  }
326 
328 
329  bool IsTailCall;
330 
331  /// For tail calls, the byte offset of the call's argument area from the
332  /// callee's. Unused elsewhere.
333  int FPDiff;
334 
335  // Cache the SP register vreg if we need it more than once in this call site.
336  Register SPReg;
337 
338  const AArch64Subtarget &Subtarget;
339 };
340 } // namespace
341 
342 static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
343  return (CallConv == CallingConv::Fast && TailCallOpt) ||
344  CallConv == CallingConv::Tail || CallConv == CallingConv::SwiftTail;
345 }
346 
348  const Value *Val,
349  ArrayRef<Register> VRegs,
351  Register SwiftErrorVReg) const {
352  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
353  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
354  "Return value without a vreg");
355 
356  bool Success = true;
357  if (!VRegs.empty()) {
358  MachineFunction &MF = MIRBuilder.getMF();
359  const Function &F = MF.getFunction();
360  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
361 
363  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
364  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
365  auto &DL = F.getParent()->getDataLayout();
366  LLVMContext &Ctx = Val->getType()->getContext();
367 
368  SmallVector<EVT, 4> SplitEVTs;
369  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
370  assert(VRegs.size() == SplitEVTs.size() &&
371  "For each split Type there should be exactly one VReg.");
372 
373  SmallVector<ArgInfo, 8> SplitArgs;
374  CallingConv::ID CC = F.getCallingConv();
375 
376  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
377  Register CurVReg = VRegs[i];
378  ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx), 0};
380 
381  // i1 is a special case because SDAG i1 true is naturally zero extended
382  // when widened using ANYEXT. We need to do it explicitly here.
383  if (MRI.getType(CurVReg).getSizeInBits() == 1) {
384  CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
385  } else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
386  1) {
387  // Some types will need extending as specified by the CC.
388  MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
389  if (EVT(NewVT) != SplitEVTs[i]) {
390  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
391  if (F.getAttributes().hasRetAttr(Attribute::SExt))
392  ExtendOp = TargetOpcode::G_SEXT;
393  else if (F.getAttributes().hasRetAttr(Attribute::ZExt))
394  ExtendOp = TargetOpcode::G_ZEXT;
395 
396  LLT NewLLT(NewVT);
397  LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
398  CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
399  // Instead of an extend, we might have a vector type which needs
400  // padding with more elements, e.g. <2 x half> -> <4 x half>.
401  if (NewVT.isVector()) {
402  if (OldLLT.isVector()) {
403  if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
404  // We don't handle VA types which are not exactly twice the
405  // size, but can easily be done in future.
406  if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
407  LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
408  return false;
409  }
410  auto Undef = MIRBuilder.buildUndef({OldLLT});
411  CurVReg =
412  MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
413  } else {
414  // Just do a vector extend.
415  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
416  .getReg(0);
417  }
418  } else if (NewLLT.getNumElements() == 2) {
419  // We need to pad a <1 x S> type to <2 x S>. Since we don't have
420  // <1 x S> vector types in GISel we use a build_vector instead
421  // of a vector merge/concat.
422  auto Undef = MIRBuilder.buildUndef({OldLLT});
423  CurVReg =
424  MIRBuilder
425  .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
426  .getReg(0);
427  } else {
428  LLVM_DEBUG(dbgs() << "Could not handle ret ty\n");
429  return false;
430  }
431  } else {
432  // If the split EVT was a <1 x T> vector, and NewVT is T, then we
433  // don't have to do anything since we don't distinguish between the
434  // two.
435  if (NewLLT != MRI.getType(CurVReg)) {
436  // A scalar extend.
437  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
438  .getReg(0);
439  }
440  }
441  }
442  }
443  if (CurVReg != CurArgInfo.Regs[0]) {
444  CurArgInfo.Regs[0] = CurVReg;
445  // Reset the arg flags after modifying CurVReg.
447  }
448  splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
449  }
450 
451  AArch64OutgoingValueAssigner Assigner(AssignFn, AssignFn, Subtarget,
452  /*IsReturn*/ true);
453  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
454  Success = determineAndHandleAssignments(Handler, Assigner, SplitArgs,
455  MIRBuilder, CC, F.isVarArg());
456  }
457 
458  if (SwiftErrorVReg) {
459  MIB.addUse(AArch64::X21, RegState::Implicit);
460  MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
461  }
462 
463  MIRBuilder.insertInstr(MIB);
464  return Success;
465 }
466 
467 /// Helper function to compute forwarded registers for musttail calls. Computes
468 /// the forwarded registers, sets MBB liveness, and emits COPY instructions that
469 /// can be used to save + restore registers later.
471  CCAssignFn *AssignFn) {
472  MachineBasicBlock &MBB = MIRBuilder.getMBB();
473  MachineFunction &MF = MIRBuilder.getMF();
474  MachineFrameInfo &MFI = MF.getFrameInfo();
475 
476  if (!MFI.hasMustTailInVarArgFunc())
477  return;
478 
480  const Function &F = MF.getFunction();
481  assert(F.isVarArg() && "Expected F to be vararg?");
482 
483  // Compute the set of forwarded registers. The rest are scratch.
485  CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
486  F.getContext());
487  SmallVector<MVT, 2> RegParmTypes;
488  RegParmTypes.push_back(MVT::i64);
489  RegParmTypes.push_back(MVT::f128);
490 
491  // Later on, we can use this vector to restore the registers if necessary.
493  FuncInfo->getForwardedMustTailRegParms();
494  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
495 
496  // Conservatively forward X8, since it might be used for an aggregate
497  // return.
498  if (!CCInfo.isAllocated(AArch64::X8)) {
499  Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
500  Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
501  }
502 
503  // Add the forwards to the MachineBasicBlock and MachineFunction.
504  for (const auto &F : Forwards) {
505  MBB.addLiveIn(F.PReg);
506  MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
507  }
508 }
509 
511  auto &F = MF.getFunction();
512  if (isa<ScalableVectorType>(F.getReturnType()))
513  return true;
514  if (llvm::any_of(F.args(), [](const Argument &A) {
515  return isa<ScalableVectorType>(A.getType());
516  }))
517  return true;
518  const auto &ST = MF.getSubtarget<AArch64Subtarget>();
519  if (!ST.hasNEON() || !ST.hasFPARMv8()) {
520  LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON\n");
521  return true;
522  }
523  return false;
524 }
525 
527  MachineIRBuilder &MIRBuilder, const Function &F,
528  ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
529  MachineFunction &MF = MIRBuilder.getMF();
530  MachineBasicBlock &MBB = MIRBuilder.getMBB();
532  auto &DL = F.getParent()->getDataLayout();
533 
534  SmallVector<ArgInfo, 8> SplitArgs;
536  unsigned i = 0;
537  for (auto &Arg : F.args()) {
538  if (DL.getTypeStoreSize(Arg.getType()).isZero())
539  continue;
540 
541  ArgInfo OrigArg{VRegs[i], Arg, i};
543 
544  // i1 arguments are zero-extended to i8 by the caller. Emit a
545  // hint to reflect this.
546  if (OrigArg.Ty->isIntegerTy(1)) {
547  assert(OrigArg.Regs.size() == 1 &&
548  MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 &&
549  "Unexpected registers used for i1 arg");
550 
551  if (!OrigArg.Flags[0].isZExt()) {
552  // Lower i1 argument as i8, and insert AssertZExt + Trunc later.
553  Register OrigReg = OrigArg.Regs[0];
555  OrigArg.Regs[0] = WideReg;
556  BoolArgs.push_back({OrigReg, WideReg});
557  }
558  }
559 
560  if (Arg.hasAttribute(Attribute::SwiftAsync))
561  MF.getInfo<AArch64FunctionInfo>()->setHasSwiftAsyncContext(true);
562 
563  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
564  ++i;
565  }
566 
567  if (!MBB.empty())
568  MIRBuilder.setInstr(*MBB.begin());
569 
570  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
571  CCAssignFn *AssignFn =
572  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
573 
574  AArch64IncomingValueAssigner Assigner(AssignFn, AssignFn);
575  FormalArgHandler Handler(MIRBuilder, MRI);
576  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
577  F.getCallingConv(), F.isVarArg()))
578  return false;
579 
580  if (!BoolArgs.empty()) {
581  for (auto &KV : BoolArgs) {
582  Register OrigReg = KV.first;
583  Register WideReg = KV.second;
584  LLT WideTy = MRI.getType(WideReg);
585  assert(MRI.getType(OrigReg).getScalarSizeInBits() == 1 &&
586  "Unexpected bit size of a bool arg");
587  MIRBuilder.buildTrunc(
588  OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0));
589  }
590  }
591 
593  uint64_t StackOffset = Assigner.StackOffset;
594  if (F.isVarArg()) {
595  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
596  if (!Subtarget.isTargetDarwin()) {
597  // FIXME: we need to reimplement saveVarArgsRegisters from
598  // AArch64ISelLowering.
599  return false;
600  }
601 
602  // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
603  StackOffset =
604  alignTo(Assigner.StackOffset, Subtarget.isTargetILP32() ? 4 : 8);
605 
606  auto &MFI = MIRBuilder.getMF().getFrameInfo();
607  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
608  }
609 
610  if (doesCalleeRestoreStack(F.getCallingConv(),
612  // We have a non-standard ABI, so why not make full use of the stack that
613  // we're going to pop? It must be aligned to 16 B in any case.
615 
616  // If we're expected to restore the stack (e.g. fastcc), then we'll be
617  // adding a multiple of 16.
619 
620  // Our own callers will guarantee that the space is free by giving an
621  // aligned value to CALLSEQ_START.
622  }
623 
624  // When we tail call, we need to check if the callee's arguments
625  // will fit on the caller's stack. So, whenever we lower formal arguments,
626  // we should keep track of this information, since we might lower a tail call
627  // in this function later.
629 
630  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
631  if (Subtarget.hasCustomCallingConv())
633 
634  handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
635 
636  // Move back to the end of the basic block.
637  MIRBuilder.setMBB(MBB);
638 
639  return true;
640 }
641 
642 /// Return true if the calling convention is one that we can guarantee TCO for.
643 static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
644  return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
646 }
647 
648 /// Return true if we might ever do TCO for calls with this calling convention.
650  switch (CC) {
651  case CallingConv::C:
653  case CallingConv::Swift:
655  case CallingConv::Tail:
656  case CallingConv::Fast:
657  return true;
658  default:
659  return false;
660  }
661 }
662 
663 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
664 /// CC.
665 static std::pair<CCAssignFn *, CCAssignFn *>
667  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
668 }
669 
670 bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
671  CallLoweringInfo &Info, MachineFunction &MF,
672  SmallVectorImpl<ArgInfo> &InArgs) const {
673  const Function &CallerF = MF.getFunction();
674  CallingConv::ID CalleeCC = Info.CallConv;
675  CallingConv::ID CallerCC = CallerF.getCallingConv();
676 
677  // If the calling conventions match, then everything must be the same.
678  if (CalleeCC == CallerCC)
679  return true;
680 
681  // Check if the caller and callee will handle arguments in the same way.
682  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
683  CCAssignFn *CalleeAssignFnFixed;
684  CCAssignFn *CalleeAssignFnVarArg;
685  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
686  getAssignFnsForCC(CalleeCC, TLI);
687 
688  CCAssignFn *CallerAssignFnFixed;
689  CCAssignFn *CallerAssignFnVarArg;
690  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
691  getAssignFnsForCC(CallerCC, TLI);
692 
693  AArch64IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
694  CalleeAssignFnVarArg);
695  AArch64IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
696  CallerAssignFnVarArg);
697 
698  if (!resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner))
699  return false;
700 
701  // Make sure that the caller and callee preserve all of the same registers.
702  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
703  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
704  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
706  TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
707  TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
708  }
709 
710  return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
711 }
712 
713 bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
714  CallLoweringInfo &Info, MachineFunction &MF,
715  SmallVectorImpl<ArgInfo> &OutArgs) const {
716  // If there are no outgoing arguments, then we are done.
717  if (OutArgs.empty())
718  return true;
719 
720  const Function &CallerF = MF.getFunction();
721  LLVMContext &Ctx = CallerF.getContext();
722  CallingConv::ID CalleeCC = Info.CallConv;
723  CallingConv::ID CallerCC = CallerF.getCallingConv();
724  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
725  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
726 
727  CCAssignFn *AssignFnFixed;
728  CCAssignFn *AssignFnVarArg;
729  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
730 
731  // We have outgoing arguments. Make sure that we can tail call with them.
733  CCState OutInfo(CalleeCC, false, MF, OutLocs, Ctx);
734 
735  AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
736  Subtarget, /*IsReturn*/ false);
737  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo)) {
738  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
739  return false;
740  }
741 
742  // Make sure that they can fit on the caller's stack.
743  const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
744  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
745  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
746  return false;
747  }
748 
749  // Verify that the parameters in callee-saved registers match.
750  // TODO: Port this over to CallLowering as general code once swiftself is
751  // supported.
752  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
753  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
755 
756  if (Info.IsVarArg) {
757  // Be conservative and disallow variadic memory operands to match SDAG's
758  // behaviour.
759  // FIXME: If the caller's calling convention is C, then we can
760  // potentially use its argument area. However, for cases like fastcc,
761  // we can't do anything.
762  for (unsigned i = 0; i < OutLocs.size(); ++i) {
763  auto &ArgLoc = OutLocs[i];
764  if (ArgLoc.isRegLoc())
765  continue;
766 
767  LLVM_DEBUG(
768  dbgs()
769  << "... Cannot tail call vararg function with stack arguments\n");
770  return false;
771  }
772  }
773 
774  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
775 }
776 
778  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
779  SmallVectorImpl<ArgInfo> &InArgs,
780  SmallVectorImpl<ArgInfo> &OutArgs) const {
781 
782  // Must pass all target-independent checks in order to tail call optimize.
783  if (!Info.IsTailCall)
784  return false;
785 
786  CallingConv::ID CalleeCC = Info.CallConv;
787  MachineFunction &MF = MIRBuilder.getMF();
788  const Function &CallerF = MF.getFunction();
789 
790  LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
791 
792  if (Info.SwiftErrorVReg) {
793  // TODO: We should handle this.
794  // Note that this is also handled by the check for no outgoing arguments.
795  // Proactively disabling this though, because the swifterror handling in
796  // lowerCall inserts a COPY *after* the location of the call.
797  LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
798  return false;
799  }
800 
801  if (!mayTailCallThisCC(CalleeCC)) {
802  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
803  return false;
804  }
805 
806  // Byval parameters hand the function a pointer directly into the stack area
807  // we want to reuse during a tail call. Working around this *is* possible (see
808  // X86).
809  //
810  // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
811  // it?
812  //
813  // On Windows, "inreg" attributes signify non-aggregate indirect returns.
814  // In this case, it is necessary to save/restore X0 in the callee. Tail
815  // call opt interferes with this. So we disable tail call opt when the
816  // caller has an argument with "inreg" attribute.
817  //
818  // FIXME: Check whether the callee also has an "inreg" argument.
819  //
820  // When the caller has a swifterror argument, we don't want to tail call
821  // because would have to move into the swifterror register before the
822  // tail call.
823  if (any_of(CallerF.args(), [](const Argument &A) {
824  return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
825  })) {
826  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
827  "inreg, or swifterror arguments\n");
828  return false;
829  }
830 
831  // Externally-defined functions with weak linkage should not be
832  // tail-called on AArch64 when the OS does not support dynamic
833  // pre-emption of symbols, as the AAELF spec requires normal calls
834  // to undefined weak functions to be replaced with a NOP or jump to the
835  // next instruction. The behaviour of branch instructions in this
836  // situation (as used for tail calls) is implementation-defined, so we
837  // cannot rely on the linker replacing the tail call with a return.
838  if (Info.Callee.isGlobal()) {
839  const GlobalValue *GV = Info.Callee.getGlobal();
840  const Triple &TT = MF.getTarget().getTargetTriple();
841  if (GV->hasExternalWeakLinkage() &&
842  (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
843  TT.isOSBinFormatMachO())) {
844  LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
845  "with weak linkage for this OS.\n");
846  return false;
847  }
848  }
849 
850  // If we have -tailcallopt, then we're done.
852  return CalleeCC == CallerF.getCallingConv();
853 
854  // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
855  // Try to find cases where we can do that.
856 
857  // I want anyone implementing a new calling convention to think long and hard
858  // about this assert.
859  assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
860  "Unexpected variadic calling convention");
861 
862  // Verify that the incoming and outgoing arguments from the callee are
863  // safe to tail call.
864  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
865  LLVM_DEBUG(
866  dbgs()
867  << "... Caller and callee have incompatible calling conventions.\n");
868  return false;
869  }
870 
871  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
872  return false;
873 
874  LLVM_DEBUG(
875  dbgs() << "... Call is eligible for tail call optimization.\n");
876  return true;
877 }
878 
879 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
880  bool IsTailCall) {
881  if (!IsTailCall)
882  return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
883 
884  if (!IsIndirect)
885  return AArch64::TCRETURNdi;
886 
887  // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
888  // x16 or x17.
890  return AArch64::TCRETURNriBTI;
891 
892  return AArch64::TCRETURNri;
893 }
894 
895 static const uint32_t *
897  AArch64CallLowering::CallLoweringInfo &Info,
899  const uint32_t *Mask;
900  if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
901  // For 'this' returns, use the X0-preserving mask if applicable
902  Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
903  if (!Mask) {
904  OutArgs[0].Flags[0].setReturned(false);
905  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
906  }
907  } else {
908  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
909  }
910  return Mask;
911 }
912 
913 bool AArch64CallLowering::lowerTailCall(
914  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
915  SmallVectorImpl<ArgInfo> &OutArgs) const {
916  MachineFunction &MF = MIRBuilder.getMF();
917  const Function &F = MF.getFunction();
919  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
921 
922  // True when we're tail calling, but without -tailcallopt.
923  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt &&
924  Info.CallConv != CallingConv::Tail &&
925  Info.CallConv != CallingConv::SwiftTail;
926 
927  // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
928  // register class. Until we can do that, we should fall back here.
930  LLVM_DEBUG(
931  dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
932  return false;
933  }
934 
935  // Find out which ABI gets to decide where things go.
936  CallingConv::ID CalleeCC = Info.CallConv;
937  CCAssignFn *AssignFnFixed;
938  CCAssignFn *AssignFnVarArg;
939  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
940 
941  MachineInstrBuilder CallSeqStart;
942  if (!IsSibCall)
943  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
944 
945  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
946  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
947  MIB.add(Info.Callee);
948 
949  // Byte offset for the tail call. When we are sibcalling, this will always
950  // be 0.
951  MIB.addImm(0);
952 
953  // Tell the call which registers are clobbered.
954  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
955  auto TRI = Subtarget.getRegisterInfo();
956  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
957  if (Subtarget.hasCustomCallingConv())
958  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
959  MIB.addRegMask(Mask);
960 
961  if (TRI->isAnyArgRegReserved(MF))
962  TRI->emitReservedArgRegCallError(MF);
963 
964  // FPDiff is the byte offset of the call's argument area from the callee's.
965  // Stores to callee stack arguments will be placed in FixedStackSlots offset
966  // by this amount for a tail call. In a sibling call it must be 0 because the
967  // caller will deallocate the entire stack and the callee still expects its
968  // arguments to begin at SP+0.
969  int FPDiff = 0;
970 
971  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
972  // by -tailcallopt. For sibcalls, the memory operands for the call are
973  // already available in the caller's incoming argument space.
974  unsigned NumBytes = 0;
975  if (!IsSibCall) {
976  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
977  // before handling assignments, because FPDiff must be known for memory
978  // arguments.
979  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
981  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
982 
983  AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
984  Subtarget, /*IsReturn*/ false);
985  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
986  return false;
987 
988  // The callee will pop the argument stack as a tail call. Thus, we must
989  // keep it 16-byte aligned.
990  NumBytes = alignTo(OutInfo.getNextStackOffset(), 16);
991 
992  // FPDiff will be negative if this tail call requires more space than we
993  // would automatically have in our incoming argument space. Positive if we
994  // actually shrink the stack.
995  FPDiff = NumReusableBytes - NumBytes;
996 
997  // Update the required reserved area if this is the tail call requiring the
998  // most argument stack space.
999  if (FPDiff < 0 && FuncInfo->getTailCallReservedStack() < (unsigned)-FPDiff)
1000  FuncInfo->setTailCallReservedStack(-FPDiff);
1001 
1002  // The stack pointer must be 16-byte aligned at all times it's used for a
1003  // memory operation, which in practice means at *all* times and in
1004  // particular across call boundaries. Therefore our own arguments started at
1005  // a 16-byte aligned SP and the delta applied for the tail call should
1006  // satisfy the same constraint.
1007  assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1008  }
1009 
1010  const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
1011 
1012  AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1013  Subtarget, /*IsReturn*/ false);
1014 
1015  // Do the actual argument marshalling.
1016  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB,
1017  /*IsTailCall*/ true, FPDiff);
1018  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1019  CalleeCC, Info.IsVarArg))
1020  return false;
1021 
1022  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1023 
1024  if (Info.IsVarArg && Info.IsMustTailCall) {
1025  // Now we know what's being passed to the function. Add uses to the call for
1026  // the forwarded registers that we *aren't* passing as parameters. This will
1027  // preserve the copies we build earlier.
1028  for (const auto &F : Forwards) {
1029  Register ForwardedReg = F.PReg;
1030  // If the register is already passed, or aliases a register which is
1031  // already being passed, then skip it.
1032  if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
1033  if (!Use.isReg())
1034  return false;
1035  return TRI->regsOverlap(Use.getReg(), ForwardedReg);
1036  }))
1037  continue;
1038 
1039  // We aren't passing it already, so we should add it to the call.
1040  MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
1041  MIB.addReg(ForwardedReg, RegState::Implicit);
1042  }
1043  }
1044 
1045  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1046  // sequence start and end here.
1047  if (!IsSibCall) {
1048  MIB->getOperand(1).setImm(FPDiff);
1049  CallSeqStart.addImm(0).addImm(0);
1050  // End the call sequence *before* emitting the call. Normally, we would
1051  // tidy the frame up after the call. However, here, we've laid out the
1052  // parameters so that when SP is reset, they will be in the correct
1053  // location.
1054  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0);
1055  }
1056 
1057  // Now we can add the actual call instruction to the correct basic block.
1058  MIRBuilder.insertInstr(MIB);
1059 
1060  // If Callee is a reg, since it is used by a target specific instruction,
1061  // it must have a register class matching the constraint of that instruction.
1062  if (MIB->getOperand(0).isReg())
1064  *MF.getSubtarget().getRegBankInfo(), *MIB,
1065  MIB->getDesc(), MIB->getOperand(0), 0);
1066 
1068  Info.LoweredTailCall = true;
1069  return true;
1070 }
1071 
1073  CallLoweringInfo &Info) const {
1074  MachineFunction &MF = MIRBuilder.getMF();
1075  const Function &F = MF.getFunction();
1077  auto &DL = F.getParent()->getDataLayout();
1078  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
1079 
1080  SmallVector<ArgInfo, 8> OutArgs;
1081  for (auto &OrigArg : Info.OrigArgs) {
1082  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1083  // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
1084  if (OrigArg.Ty->isIntegerTy(1)) {
1085  ArgInfo &OutArg = OutArgs.back();
1086  assert(OutArg.Regs.size() == 1 &&
1087  MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 &&
1088  "Unexpected registers used for i1 arg");
1089 
1090  // We cannot use a ZExt ArgInfo flag here, because it will
1091  // zero-extend the argument to i32 instead of just i8.
1092  OutArg.Regs[0] =
1093  MIRBuilder.buildZExt(LLT::scalar(8), OutArg.Regs[0]).getReg(0);
1094  LLVMContext &Ctx = MF.getFunction().getContext();
1095  OutArg.Ty = Type::getInt8Ty(Ctx);
1096  }
1097  }
1098 
1099  SmallVector<ArgInfo, 8> InArgs;
1100  if (!Info.OrigRet.Ty->isVoidTy())
1101  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1102 
1103  // If we can lower as a tail call, do that instead.
1104  bool CanTailCallOpt =
1105  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1106 
1107  // We must emit a tail call if we have musttail.
1108  if (Info.IsMustTailCall && !CanTailCallOpt) {
1109  // There are types of incoming/outgoing arguments we can't handle yet, so
1110  // it doesn't make sense to actually die here like in ISelLowering. Instead,
1111  // fall back to SelectionDAG and let it try to handle this.
1112  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1113  return false;
1114  }
1115 
1116  Info.IsTailCall = CanTailCallOpt;
1117  if (CanTailCallOpt)
1118  return lowerTailCall(MIRBuilder, Info, OutArgs);
1119 
1120  // Find out which ABI gets to decide where things go.
1121  CCAssignFn *AssignFnFixed;
1122  CCAssignFn *AssignFnVarArg;
1123  std::tie(AssignFnFixed, AssignFnVarArg) =
1124  getAssignFnsForCC(Info.CallConv, TLI);
1125 
1126  MachineInstrBuilder CallSeqStart;
1127  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1128 
1129  // Create a temporarily-floating call instruction so we can add the implicit
1130  // uses of arg registers.
1131 
1132  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1133  unsigned Opc = 0;
1134  // Calls with operand bundle "clang.arc.attachedcall" are special. They should
1135  // be expanded to the call, directly followed by a special marker sequence and
1136  // a call to an ObjC library function.
1138  Opc = AArch64::BLR_RVMARKER;
1139  // A call to a returns twice function like setjmp must be followed by a bti
1140  // instruction.
1141  else if (Info.CB &&
1142  Info.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) &&
1143  !Subtarget.noBTIAtReturnTwice() &&
1144  MF.getInfo<AArch64FunctionInfo>()->branchTargetEnforcement())
1145  Opc = AArch64::BLR_BTI;
1146  else
1147  Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1148 
1149  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1150  unsigned CalleeOpNo = 0;
1151 
1152  if (Opc == AArch64::BLR_RVMARKER) {
1153  // Add a target global address for the retainRV/claimRV runtime function
1154  // just before the call target.
1156  MIB.addGlobalAddress(ARCFn);
1157  ++CalleeOpNo;
1158  }
1159 
1160  MIB.add(Info.Callee);
1161 
1162  // Tell the call which registers are clobbered.
1163  const uint32_t *Mask;
1164  const auto *TRI = Subtarget.getRegisterInfo();
1165 
1166  AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1167  Subtarget, /*IsReturn*/ false);
1168  // Do the actual argument marshalling.
1169  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, /*IsReturn*/ false);
1170  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1171  Info.CallConv, Info.IsVarArg))
1172  return false;
1173 
1174  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1175 
1177  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1178  MIB.addRegMask(Mask);
1179 
1180  if (TRI->isAnyArgRegReserved(MF))
1181  TRI->emitReservedArgRegCallError(MF);
1182 
1183  // Now we can add the actual call instruction to the correct basic block.
1184  MIRBuilder.insertInstr(MIB);
1185 
1186  // If Callee is a reg, since it is used by a target specific
1187  // instruction, it must have a register class matching the
1188  // constraint of that instruction.
1189  if (MIB->getOperand(CalleeOpNo).isReg())
1190  constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),
1191  *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(),
1192  MIB->getOperand(CalleeOpNo), CalleeOpNo);
1193 
1194  // Finally we can copy the returned value back into its virtual-register. In
1195  // symmetry with the arguments, the physical register must be an
1196  // implicit-define of the call instruction.
1197  if (!Info.OrigRet.Ty->isVoidTy()) {
1198  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
1199  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1200  bool UsingReturnedArg =
1201  !OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1202 
1203  AArch64OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn, Subtarget,
1204  /*IsReturn*/ false);
1205  ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB);
1207  UsingReturnedArg ? ReturnedArgHandler : Handler, Assigner, InArgs,
1208  MIRBuilder, Info.CallConv, Info.IsVarArg,
1209  UsingReturnedArg ? makeArrayRef(OutArgs[0].Regs) : None))
1210  return false;
1211  }
1212 
1213  if (Info.SwiftErrorVReg) {
1214  MIB.addDef(AArch64::X21, RegState::Implicit);
1215  MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1216  }
1217 
1218  uint64_t CalleePopBytes =
1219  doesCalleeRestoreStack(Info.CallConv,
1221  ? alignTo(Assigner.StackOffset, 16)
1222  : 0;
1223 
1224  CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
1225  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1226  .addImm(Assigner.StackOffset)
1227  .addImm(CalleePopBytes);
1228 
1229  return true;
1230 }
1231 
1233  return Ty.getSizeInBits() == 64;
1234 }
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
i
i
Definition: README.txt:29
llvm::AArch64CallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: AArch64CallLowering.cpp:347
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::AArch64FunctionInfo::setArgumentStackToRestore
void setArgumentStackToRestore(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:193
LowLevelType.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::objcarc::hasAttachedCallOpBundle
bool hasAttachedCallOpBundle(const CallBase *CB)
Definition: ObjCARCUtil.h:29
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:221
AArch64MachineFunctionInfo.h
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:764
llvm::AArch64CallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AArch64CallLowering.cpp:1072
llvm::objcarc::getAttachedARCFunction
Optional< Function * > getAttachedARCFunction(const CallBase *CB)
This function returns operand bundle clang_arc_attachedcall's argument, which is the address of the A...
Definition: ObjCARCUtil.h:43
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:224
llvm::AArch64CallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AArch64CallLowering.cpp:526
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:287
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:8000
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:143
llvm::AArch64Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: AArch64Subtarget.h:242
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MachineBasicBlock.h
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:319
llvm::AArch64Subtarget::getInstrInfo
const AArch64InstrInfo * getInstrInfo() const override
Definition: AArch64Subtarget.h:171
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:330
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:235
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:658
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:38
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:340
MachineIRBuilder.h
llvm::AArch64FunctionInfo::setVarArgsStackIndex
void setVarArgsStackIndex(int Index)
Definition: AArch64MachineFunctionInfo.h:316
llvm::Type::getInt8Ty
static IntegerType * getInt8Ty(LLVMContext &C)
Definition: Type.cpp:237
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:451
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:121
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::CCState::analyzeMustTailForwardedRegisters
void analyzeMustTailForwardedRegisters(SmallVectorImpl< ForwardedRegister > &Forwards, ArrayRef< MVT > RegParmTypes, CCAssignFn Fn)
Compute the set of registers that need to be preserved and forwarded to any musttail calls.
Definition: CallingConvLower.cpp:237
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
Definition: CallLowering.cpp:1004
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:452
llvm::AArch64FunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: AArch64MachineFunctionInfo.h:189
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:331
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::AArch64Subtarget::isTargetILP32
bool isTargetILP32() const
Definition: AArch64Subtarget.h:253
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::AArch64FunctionInfo::setBytesInStackArgArea
void setBytesInStackArgArea(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:190
llvm::CallLowering::ValueHandler::getStackValueStoreType
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
Definition: CallLowering.cpp:1058
applyStackPassedSmallTypeDAGHack
static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT, MVT &LocVT)
Definition: AArch64CallLowering.cpp:55
Utils.h
llvm::FormalArgHandler
Definition: M68kCallLowering.h:66
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:220
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:557
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:315
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AArch64CallLowering.cpp:666
getStackValueStoreTypeHack
static LLT getStackValueStoreTypeHack(const CCValAssign &VA)
Definition: AArch64CallLowering.cpp:70
llvm::MachineFrameInfo::hasMustTailInVarArgFunc
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
Definition: MachineFrameInfo.h:626
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::None
const NoneType None
Definition: None.h:24
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
getMaskForArgs
static const uint32_t * getMaskForArgs(SmallVectorImpl< AArch64CallLowering::ArgInfo > &OutArgs, AArch64CallLowering::CallLoweringInfo &Info, const AArch64RegisterInfo &TRI, MachineFunction &MF)
Definition: AArch64CallLowering.cpp:896
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:492
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:411
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1576
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:406
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
handleMustTailForwardedRegisters
static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn)
Helper function to compute forwarded registers for musttail calls.
Definition: AArch64CallLowering.cpp:470
AArch64CallLowering.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:165
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:696
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:5440
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:38
Analysis.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
ArrayRef.h
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AArch64CallLowering.cpp:879
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:631
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:257
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:294
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::AArch64FunctionInfo::branchTargetEnforcement
bool branchTargetEnforcement() const
Definition: AArch64MachineFunctionInfo.h:407
llvm::AArch64Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: AArch64Subtarget.h:297
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.h:858
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:129
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:374
llvm::CCState::isVarArg
bool isVarArg() const
Definition: CallingConvLower.h:258
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:203
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1612
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:278
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::AArch64FunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: AArch64MachineFunctionInfo.h:379
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AArch64CallLowering.cpp:649
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
AArch64ISelLowering.h
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:376
Argument.h
ObjCARCUtil.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:172
Attributes.h
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:774
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:308
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
CallingConvLower.h
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:228
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
MachineFrameInfo.h
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:610
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:162
Success
#define Success
Definition: AArch64Disassembler.cpp:279
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:214
doesCalleeRestoreStack
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
Definition: AArch64CallLowering.cpp:342
Function.h
llvm::CallLowering::ArgInfo::Regs
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
llvm::ISD::ArgFlagsTy::isPointer
bool isPointer() const
Definition: TargetCallingConv.h:141
llvm::CallLowering::BaseArgInfo::Ty
Type * Ty
Definition: CallLowering.h:50
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:262
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:227
llvm::AArch64CallLowering::fallBackToDAGISel
bool fallBackToDAGISel(const MachineFunction &MF) const override
Definition: AArch64CallLowering.cpp:510
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:5475
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
AArch64Subtarget.h
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
MachineInstrBuilder.h
llvm::CallingConv::SwiftTail
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
Definition: CallingConv.h:92
llvm::AArch64CallLowering::isTypeIsValidForThisReturn
bool isTypeIsValidForThisReturn(EVT Ty) const override
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: AArch64CallLowering.cpp:1232
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AArch64CallLowering.cpp:643
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1568
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:52
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:529
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:614
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:249
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:156
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::AArch64CallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AArch64CallLowering.cpp:777
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::CallReturnHandler
Definition: M68kCallLowering.h:71
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:492
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
MachineFunction.h
llvm::AArch64CallLowering::AArch64CallLowering
AArch64CallLowering(const AArch64TargetLowering &TLI)
Definition: AArch64CallLowering.cpp:52
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:952
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
Value.h
llvm::CallReturnHandler::CallReturnHandler
CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
Definition: M68kCallLowering.h:72
llvm::CallLowering
Definition: CallLowering.h:44
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1019
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:413
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::AArch64FunctionInfo::setTailCallReservedStack
void setTailCallReservedStack(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:198
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: M68kCallLowering.h:67
llvm::CCState::isAllocated
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
Definition: CallingConvLower.h:275
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:532
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:177