LLVM  13.0.0git
AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64CallLowering.h"
16 #include "AArch64ISelLowering.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Argument.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstdint>
45 #include <iterator>
46 
47 #define DEBUG_TYPE "aarch64-call-lowering"
48 
49 using namespace llvm;
50 
52  : CallLowering(&TLI) {}
53 
54 static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT,
55  MVT &LocVT) {
56  // If ValVT is i1/i8/i16, we should set LocVT to i8/i8/i16. This is a legacy
57  // hack because the DAG calls the assignment function with pre-legalized
58  // register typed values, not the raw type.
59  //
60  // This hack is not applied to return values which are not passed on the
61  // stack.
62  if (OrigVT == MVT::i1 || OrigVT == MVT::i8)
63  ValVT = LocVT = MVT::i8;
64  else if (OrigVT == MVT::i16)
65  ValVT = LocVT = MVT::i16;
66 }
67 
68 // Account for i1/i8/i16 stack passed value hack
69 static uint64_t getStackValueStoreSizeHack(const CCValAssign &VA) {
70  const MVT ValVT = VA.getValVT();
71  return (ValVT == MVT::i8 || ValVT == MVT::i16) ? ValVT.getStoreSize()
72  : VA.getLocVT().getStoreSize();
73 }
74 
75 namespace {
76 struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
77  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
78  CCAssignFn *AssignFn)
79  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
80 
81  Register getStackAddress(uint64_t Size, int64_t Offset,
82  MachinePointerInfo &MPO,
83  ISD::ArgFlagsTy Flags) override {
84  auto &MFI = MIRBuilder.getMF().getFrameInfo();
85 
86  // Byval is assumed to be writable memory, but other stack passed arguments
87  // are not.
88  const bool IsImmutable = !Flags.isByVal();
89 
90  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
91  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
92  auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
93  StackUsed = std::max(StackUsed, Size + Offset);
94  return AddrReg.getReg(0);
95  }
96 
97  uint64_t getStackValueStoreSize(const CCValAssign &VA) const override {
98  return getStackValueStoreSizeHack(VA);
99  }
100 
101  void assignValueToReg(Register ValVReg, Register PhysReg,
102  CCValAssign &VA) override {
103  markPhysRegUsed(PhysReg);
104  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
105  }
106 
107  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
108  MachinePointerInfo &MPO, CCValAssign &VA) override {
109  MachineFunction &MF = MIRBuilder.getMF();
110 
111  // The reported memory location may be wider than the value.
112  const LLT RealRegTy = MRI.getType(ValVReg);
113  LLT ValTy(VA.getValVT());
114  LLT LocTy(VA.getLocVT());
115 
116  // Fixup the types for the DAG compatibility hack.
117  if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
118  std::swap(ValTy, LocTy);
119 
120  MemSize = LocTy.getSizeInBytes();
121 
122  auto MMO = MF.getMachineMemOperand(
124  MemSize, inferAlignFromPtrInfo(MF, MPO));
125 
126  if (RealRegTy.getSizeInBits() == ValTy.getSizeInBits()) {
127  // No extension information, or no extension necessary. Load into the
128  // incoming parameter type directly.
129  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
130  } else {
131  auto Tmp = MIRBuilder.buildLoad(LocTy, Addr, *MMO);
132  MIRBuilder.buildTrunc(ValVReg, Tmp);
133  }
134  }
135 
136  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
137  CCValAssign::LocInfo LocInfo,
139  CCState &State) override {
140  applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
141  return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
142  }
143 
144  /// How the physical register gets marked varies between formal
145  /// parameters (it's a basic-block live-in), and a call instruction
146  /// (it's an implicit-def of the BL).
147  virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
148 
149  uint64_t StackUsed;
150 };
151 
152 struct FormalArgHandler : public IncomingArgHandler {
153  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
154  CCAssignFn *AssignFn)
155  : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
156 
157  void markPhysRegUsed(MCRegister PhysReg) override {
158  MIRBuilder.getMRI()->addLiveIn(PhysReg);
159  MIRBuilder.getMBB().addLiveIn(PhysReg);
160  }
161 };
162 
163 struct CallReturnHandler : public IncomingArgHandler {
164  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
165  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
166  : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
167 
168  void markPhysRegUsed(MCRegister PhysReg) override {
169  MIB.addDef(PhysReg, RegState::Implicit);
170  }
171 
173 };
174 
175 /// A special return arg handler for "returned" attribute arg calls.
176 struct ReturnedArgCallReturnHandler : public CallReturnHandler {
177  ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
179  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
180  : CallReturnHandler(MIRBuilder, MRI, MIB, AssignFn) {}
181 
182  void markPhysRegUsed(MCRegister PhysReg) override {}
183 };
184 
185 struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
186  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
187  MachineInstrBuilder MIB, CCAssignFn *AssignFn,
188  CCAssignFn *AssignFnVarArg, bool IsReturn,
189  bool IsTailCall = false, int FPDiff = 0)
190  : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
191  AssignFnVarArg(AssignFnVarArg), IsReturn(IsReturn),
192  IsTailCall(IsTailCall), FPDiff(FPDiff), StackSize(0), SPReg(0),
193  Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
194 
195  Register getStackAddress(uint64_t Size, int64_t Offset,
196  MachinePointerInfo &MPO,
197  ISD::ArgFlagsTy Flags) override {
198  MachineFunction &MF = MIRBuilder.getMF();
199  LLT p0 = LLT::pointer(0, 64);
200  LLT s64 = LLT::scalar(64);
201 
202  if (IsTailCall) {
203  assert(!Flags.isByVal() && "byval unhandled with tail calls");
204 
205  Offset += FPDiff;
206  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
207  auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
208  MPO = MachinePointerInfo::getFixedStack(MF, FI);
209  return FIReg.getReg(0);
210  }
211 
212  if (!SPReg)
213  SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
214 
215  auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
216 
217  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
218 
220  return AddrReg.getReg(0);
221  }
222 
223  /// We need to fixup the reported store size for certain value types because
224  /// we invert the interpretation of ValVT and LocVT in certain cases. This is
225  /// for compatability with the DAG call lowering implementation, which we're
226  /// currently building on top of.
227  uint64_t getStackValueStoreSize(const CCValAssign &VA) const override {
228  return getStackValueStoreSizeHack(VA);
229  }
230 
231  void assignValueToReg(Register ValVReg, Register PhysReg,
232  CCValAssign &VA) override {
233  MIB.addUse(PhysReg, RegState::Implicit);
234  Register ExtReg = extendRegister(ValVReg, VA);
235  MIRBuilder.buildCopy(PhysReg, ExtReg);
236  }
237 
238  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
239  MachinePointerInfo &MPO, CCValAssign &VA) override {
240  MachineFunction &MF = MIRBuilder.getMF();
242  inferAlignFromPtrInfo(MF, MPO));
243  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
244  }
245 
246  void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
247  Register Addr, uint64_t MemSize,
248  MachinePointerInfo &MPO, CCValAssign &VA) override {
249  unsigned MaxSize = MemSize * 8;
250  // For varargs, we always want to extend them to 8 bytes, in which case
251  // we disable setting a max.
252  if (!Arg.IsFixed)
253  MaxSize = 0;
254 
255  Register ValVReg = Arg.Regs[RegIndex];
256  if (VA.getLocInfo() != CCValAssign::LocInfo::FPExt) {
257  MVT LocVT = VA.getLocVT();
258  MVT ValVT = VA.getValVT();
259 
260  if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) {
261  std::swap(ValVT, LocVT);
262  MemSize = VA.getValVT().getStoreSize();
263  }
264 
265  ValVReg = extendRegister(ValVReg, VA, MaxSize);
266  const LLT RegTy = MRI.getType(ValVReg);
267 
268  if (RegTy.getSizeInBits() < LocVT.getSizeInBits())
269  ValVReg = MIRBuilder.buildTrunc(RegTy, ValVReg).getReg(0);
270  } else {
271  // The store does not cover the full allocated stack slot.
272  MemSize = VA.getValVT().getStoreSize();
273  }
274 
275  assignValueToAddress(ValVReg, Addr, MemSize, MPO, VA);
276  }
277 
278  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
279  CCValAssign::LocInfo LocInfo,
281  CCState &State) override {
282  bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv());
283  bool UseVarArgsCCForFixed = IsCalleeWin && State.isVarArg();
284 
285  if (!State.isVarArg() && !UseVarArgsCCForFixed && !IsReturn)
286  applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
287 
288  bool Res;
289  if (Info.IsFixed && !UseVarArgsCCForFixed)
290  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
291  else
292  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
293 
294  StackSize = State.getNextStackOffset();
295  return Res;
296  }
297 
299  CCAssignFn *AssignFnVarArg;
300 
301  /// Track if this is used for a return instead of function argument
302  /// passing. We apply a hack to i1/i8/i16 stack passed values, but do not use
303  /// stack passed returns for them and cannot apply the type adjustment.
304  bool IsReturn;
305  bool IsTailCall;
306 
307  /// For tail calls, the byte offset of the call's argument area from the
308  /// callee's. Unused elsewhere.
309  int FPDiff;
310  uint64_t StackSize;
311 
312  // Cache the SP register vreg if we need it more than once in this call site.
313  Register SPReg;
314 
315  const AArch64Subtarget &Subtarget;
316 };
317 } // namespace
318 
319 static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
320  return CallConv == CallingConv::Fast && TailCallOpt;
321 }
322 
324  const Value *Val,
325  ArrayRef<Register> VRegs,
327  Register SwiftErrorVReg) const {
328  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
329  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
330  "Return value without a vreg");
331 
332  bool Success = true;
333  if (!VRegs.empty()) {
334  MachineFunction &MF = MIRBuilder.getMF();
335  const Function &F = MF.getFunction();
336 
338  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
339  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
340  auto &DL = F.getParent()->getDataLayout();
341  LLVMContext &Ctx = Val->getType()->getContext();
342 
343  SmallVector<EVT, 4> SplitEVTs;
344  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
345  assert(VRegs.size() == SplitEVTs.size() &&
346  "For each split Type there should be exactly one VReg.");
347 
348  SmallVector<ArgInfo, 8> SplitArgs;
349  CallingConv::ID CC = F.getCallingConv();
350 
351  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
352  if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) > 1) {
353  LLVM_DEBUG(dbgs() << "Can't handle extended arg types which need split");
354  return false;
355  }
356 
357  Register CurVReg = VRegs[i];
358  ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
360 
361  // i1 is a special case because SDAG i1 true is naturally zero extended
362  // when widened using ANYEXT. We need to do it explicitly here.
363  if (MRI.getType(CurVReg).getSizeInBits() == 1) {
364  CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
365  } else {
366  // Some types will need extending as specified by the CC.
367  MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
368  if (EVT(NewVT) != SplitEVTs[i]) {
369  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
370  if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
371  Attribute::SExt))
372  ExtendOp = TargetOpcode::G_SEXT;
373  else if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
374  Attribute::ZExt))
375  ExtendOp = TargetOpcode::G_ZEXT;
376 
377  LLT NewLLT(NewVT);
378  LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
379  CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
380  // Instead of an extend, we might have a vector type which needs
381  // padding with more elements, e.g. <2 x half> -> <4 x half>.
382  if (NewVT.isVector()) {
383  if (OldLLT.isVector()) {
384  if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
385  // We don't handle VA types which are not exactly twice the
386  // size, but can easily be done in future.
387  if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
388  LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
389  return false;
390  }
391  auto Undef = MIRBuilder.buildUndef({OldLLT});
392  CurVReg =
393  MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
394  } else {
395  // Just do a vector extend.
396  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
397  .getReg(0);
398  }
399  } else if (NewLLT.getNumElements() == 2) {
400  // We need to pad a <1 x S> type to <2 x S>. Since we don't have
401  // <1 x S> vector types in GISel we use a build_vector instead
402  // of a vector merge/concat.
403  auto Undef = MIRBuilder.buildUndef({OldLLT});
404  CurVReg =
405  MIRBuilder
406  .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
407  .getReg(0);
408  } else {
409  LLVM_DEBUG(dbgs() << "Could not handle ret ty\n");
410  return false;
411  }
412  } else {
413  // If the split EVT was a <1 x T> vector, and NewVT is T, then we
414  // don't have to do anything since we don't distinguish between the
415  // two.
416  if (NewLLT != MRI.getType(CurVReg)) {
417  // A scalar extend.
418  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
419  .getReg(0);
420  }
421  }
422  }
423  }
424  if (CurVReg != CurArgInfo.Regs[0]) {
425  CurArgInfo.Regs[0] = CurVReg;
426  // Reset the arg flags after modifying CurVReg.
428  }
429  splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
430  }
431 
432  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn,
433  /*IsReturn*/ true);
434  Success =
435  handleAssignments(MIRBuilder, SplitArgs, Handler, CC, F.isVarArg());
436  }
437 
438  if (SwiftErrorVReg) {
439  MIB.addUse(AArch64::X21, RegState::Implicit);
440  MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
441  }
442 
443  MIRBuilder.insertInstr(MIB);
444  return Success;
445 }
446 
447 /// Helper function to compute forwarded registers for musttail calls. Computes
448 /// the forwarded registers, sets MBB liveness, and emits COPY instructions that
449 /// can be used to save + restore registers later.
451  CCAssignFn *AssignFn) {
452  MachineBasicBlock &MBB = MIRBuilder.getMBB();
453  MachineFunction &MF = MIRBuilder.getMF();
454  MachineFrameInfo &MFI = MF.getFrameInfo();
455 
456  if (!MFI.hasMustTailInVarArgFunc())
457  return;
458 
460  const Function &F = MF.getFunction();
461  assert(F.isVarArg() && "Expected F to be vararg?");
462 
463  // Compute the set of forwarded registers. The rest are scratch.
465  CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
466  F.getContext());
467  SmallVector<MVT, 2> RegParmTypes;
468  RegParmTypes.push_back(MVT::i64);
469  RegParmTypes.push_back(MVT::f128);
470 
471  // Later on, we can use this vector to restore the registers if necessary.
473  FuncInfo->getForwardedMustTailRegParms();
474  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
475 
476  // Conservatively forward X8, since it might be used for an aggregate
477  // return.
478  if (!CCInfo.isAllocated(AArch64::X8)) {
479  Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
480  Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
481  }
482 
483  // Add the forwards to the MachineBasicBlock and MachineFunction.
484  for (const auto &F : Forwards) {
485  MBB.addLiveIn(F.PReg);
486  MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
487  }
488 }
489 
491  auto &F = MF.getFunction();
492  if (isa<ScalableVectorType>(F.getReturnType()))
493  return true;
494  if (llvm::any_of(F.args(), [](const Argument &A) {
495  return isa<ScalableVectorType>(A.getType());
496  }))
497  return true;
498  const auto &ST = MF.getSubtarget<AArch64Subtarget>();
499  if (!ST.hasNEON() || !ST.hasFPARMv8()) {
500  LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON\n");
501  return true;
502  }
503  return false;
504 }
505 
507  MachineIRBuilder &MIRBuilder, const Function &F,
508  ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
509  MachineFunction &MF = MIRBuilder.getMF();
510  MachineBasicBlock &MBB = MIRBuilder.getMBB();
512  auto &DL = F.getParent()->getDataLayout();
513 
514  SmallVector<ArgInfo, 8> SplitArgs;
515  unsigned i = 0;
516  for (auto &Arg : F.args()) {
517  if (DL.getTypeStoreSize(Arg.getType()).isZero())
518  continue;
519 
520  ArgInfo OrigArg{VRegs[i], Arg};
522 
523  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
524  ++i;
525  }
526 
527  if (!MBB.empty())
528  MIRBuilder.setInstr(*MBB.begin());
529 
530  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
531  CCAssignFn *AssignFn =
532  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
533 
534  FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
535  if (!handleAssignments(MIRBuilder, SplitArgs, Handler, F.getCallingConv(),
536  F.isVarArg()))
537  return false;
538 
540  uint64_t StackOffset = Handler.StackUsed;
541  if (F.isVarArg()) {
542  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
543  if (!Subtarget.isTargetDarwin()) {
544  // FIXME: we need to reimplement saveVarArgsRegisters from
545  // AArch64ISelLowering.
546  return false;
547  }
548 
549  // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
550  StackOffset = alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8);
551 
552  auto &MFI = MIRBuilder.getMF().getFrameInfo();
553  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
554  }
555 
556  if (doesCalleeRestoreStack(F.getCallingConv(),
558  // We have a non-standard ABI, so why not make full use of the stack that
559  // we're going to pop? It must be aligned to 16 B in any case.
561 
562  // If we're expected to restore the stack (e.g. fastcc), then we'll be
563  // adding a multiple of 16.
565 
566  // Our own callers will guarantee that the space is free by giving an
567  // aligned value to CALLSEQ_START.
568  }
569 
570  // When we tail call, we need to check if the callee's arguments
571  // will fit on the caller's stack. So, whenever we lower formal arguments,
572  // we should keep track of this information, since we might lower a tail call
573  // in this function later.
575 
576  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
577  if (Subtarget.hasCustomCallingConv())
579 
580  handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
581 
582  // Move back to the end of the basic block.
583  MIRBuilder.setMBB(MBB);
584 
585  return true;
586 }
587 
588 /// Return true if the calling convention is one that we can guarantee TCO for.
590  return CC == CallingConv::Fast;
591 }
592 
593 /// Return true if we might ever do TCO for calls with this calling convention.
595  switch (CC) {
596  case CallingConv::C:
598  case CallingConv::Swift:
599  return true;
600  default:
601  return canGuaranteeTCO(CC);
602  }
603 }
604 
605 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
606 /// CC.
607 static std::pair<CCAssignFn *, CCAssignFn *>
609  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
610 }
611 
612 bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
613  CallLoweringInfo &Info, MachineFunction &MF,
614  SmallVectorImpl<ArgInfo> &InArgs) const {
615  const Function &CallerF = MF.getFunction();
616  CallingConv::ID CalleeCC = Info.CallConv;
617  CallingConv::ID CallerCC = CallerF.getCallingConv();
618 
619  // If the calling conventions match, then everything must be the same.
620  if (CalleeCC == CallerCC)
621  return true;
622 
623  // Check if the caller and callee will handle arguments in the same way.
624  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
625  CCAssignFn *CalleeAssignFnFixed;
626  CCAssignFn *CalleeAssignFnVarArg;
627  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
628  getAssignFnsForCC(CalleeCC, TLI);
629 
630  CCAssignFn *CallerAssignFnFixed;
631  CCAssignFn *CallerAssignFnVarArg;
632  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
633  getAssignFnsForCC(CallerCC, TLI);
634 
635  if (!resultsCompatible(Info, MF, InArgs, *CalleeAssignFnFixed,
636  *CalleeAssignFnVarArg, *CallerAssignFnFixed,
637  *CallerAssignFnVarArg))
638  return false;
639 
640  // Make sure that the caller and callee preserve all of the same registers.
641  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
642  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
643  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
645  TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
646  TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
647  }
648 
649  return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
650 }
651 
652 bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
653  CallLoweringInfo &Info, MachineFunction &MF,
654  SmallVectorImpl<ArgInfo> &OutArgs) const {
655  // If there are no outgoing arguments, then we are done.
656  if (OutArgs.empty())
657  return true;
658 
659  const Function &CallerF = MF.getFunction();
660  CallingConv::ID CalleeCC = Info.CallConv;
661  CallingConv::ID CallerCC = CallerF.getCallingConv();
662  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
663 
664  CCAssignFn *AssignFnFixed;
665  CCAssignFn *AssignFnVarArg;
666  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
667 
668  // We have outgoing arguments. Make sure that we can tail call with them.
670  CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
671 
672  if (!analyzeArgInfo(OutInfo, OutArgs, *AssignFnFixed, *AssignFnVarArg)) {
673  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
674  return false;
675  }
676 
677  // Make sure that they can fit on the caller's stack.
678  const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
679  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
680  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
681  return false;
682  }
683 
684  // Verify that the parameters in callee-saved registers match.
685  // TODO: Port this over to CallLowering as general code once swiftself is
686  // supported.
687  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
688  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
690 
691  if (Info.IsVarArg) {
692  // Be conservative and disallow variadic memory operands to match SDAG's
693  // behaviour.
694  // FIXME: If the caller's calling convention is C, then we can
695  // potentially use its argument area. However, for cases like fastcc,
696  // we can't do anything.
697  for (unsigned i = 0; i < OutLocs.size(); ++i) {
698  auto &ArgLoc = OutLocs[i];
699  if (ArgLoc.isRegLoc())
700  continue;
701 
702  LLVM_DEBUG(
703  dbgs()
704  << "... Cannot tail call vararg function with stack arguments\n");
705  return false;
706  }
707  }
708 
709  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
710 }
711 
713  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
714  SmallVectorImpl<ArgInfo> &InArgs,
715  SmallVectorImpl<ArgInfo> &OutArgs) const {
716 
717  // Must pass all target-independent checks in order to tail call optimize.
718  if (!Info.IsTailCall)
719  return false;
720 
721  CallingConv::ID CalleeCC = Info.CallConv;
722  MachineFunction &MF = MIRBuilder.getMF();
723  const Function &CallerF = MF.getFunction();
724 
725  LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
726 
727  if (Info.SwiftErrorVReg) {
728  // TODO: We should handle this.
729  // Note that this is also handled by the check for no outgoing arguments.
730  // Proactively disabling this though, because the swifterror handling in
731  // lowerCall inserts a COPY *after* the location of the call.
732  LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
733  return false;
734  }
735 
736  if (!mayTailCallThisCC(CalleeCC)) {
737  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
738  return false;
739  }
740 
741  // Byval parameters hand the function a pointer directly into the stack area
742  // we want to reuse during a tail call. Working around this *is* possible (see
743  // X86).
744  //
745  // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
746  // it?
747  //
748  // On Windows, "inreg" attributes signify non-aggregate indirect returns.
749  // In this case, it is necessary to save/restore X0 in the callee. Tail
750  // call opt interferes with this. So we disable tail call opt when the
751  // caller has an argument with "inreg" attribute.
752  //
753  // FIXME: Check whether the callee also has an "inreg" argument.
754  //
755  // When the caller has a swifterror argument, we don't want to tail call
756  // because would have to move into the swifterror register before the
757  // tail call.
758  if (any_of(CallerF.args(), [](const Argument &A) {
759  return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
760  })) {
761  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
762  "inreg, or swifterror arguments\n");
763  return false;
764  }
765 
766  // Externally-defined functions with weak linkage should not be
767  // tail-called on AArch64 when the OS does not support dynamic
768  // pre-emption of symbols, as the AAELF spec requires normal calls
769  // to undefined weak functions to be replaced with a NOP or jump to the
770  // next instruction. The behaviour of branch instructions in this
771  // situation (as used for tail calls) is implementation-defined, so we
772  // cannot rely on the linker replacing the tail call with a return.
773  if (Info.Callee.isGlobal()) {
774  const GlobalValue *GV = Info.Callee.getGlobal();
775  const Triple &TT = MF.getTarget().getTargetTriple();
776  if (GV->hasExternalWeakLinkage() &&
777  (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
778  TT.isOSBinFormatMachO())) {
779  LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
780  "with weak linkage for this OS.\n");
781  return false;
782  }
783  }
784 
785  // If we have -tailcallopt, then we're done.
787  return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
788 
789  // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
790  // Try to find cases where we can do that.
791 
792  // I want anyone implementing a new calling convention to think long and hard
793  // about this assert.
794  assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
795  "Unexpected variadic calling convention");
796 
797  // Verify that the incoming and outgoing arguments from the callee are
798  // safe to tail call.
799  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
800  LLVM_DEBUG(
801  dbgs()
802  << "... Caller and callee have incompatible calling conventions.\n");
803  return false;
804  }
805 
806  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
807  return false;
808 
809  LLVM_DEBUG(
810  dbgs() << "... Call is eligible for tail call optimization.\n");
811  return true;
812 }
813 
814 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
815  bool IsTailCall) {
816  if (!IsTailCall)
817  return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
818 
819  if (!IsIndirect)
820  return AArch64::TCRETURNdi;
821 
822  // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
823  // x16 or x17.
825  return AArch64::TCRETURNriBTI;
826 
827  return AArch64::TCRETURNri;
828 }
829 
830 static const uint32_t *
832  AArch64CallLowering::CallLoweringInfo &Info,
834  const uint32_t *Mask;
835  if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
836  // For 'this' returns, use the X0-preserving mask if applicable
837  Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
838  if (!Mask) {
839  OutArgs[0].Flags[0].setReturned(false);
840  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
841  }
842  } else {
843  Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
844  }
845  return Mask;
846 }
847 
848 bool AArch64CallLowering::lowerTailCall(
849  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
850  SmallVectorImpl<ArgInfo> &OutArgs) const {
851  MachineFunction &MF = MIRBuilder.getMF();
852  const Function &F = MF.getFunction();
854  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
856 
857  // True when we're tail calling, but without -tailcallopt.
858  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
859 
860  // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
861  // register class. Until we can do that, we should fall back here.
863  LLVM_DEBUG(
864  dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
865  return false;
866  }
867 
868  // Find out which ABI gets to decide where things go.
869  CallingConv::ID CalleeCC = Info.CallConv;
870  CCAssignFn *AssignFnFixed;
871  CCAssignFn *AssignFnVarArg;
872  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
873 
874  MachineInstrBuilder CallSeqStart;
875  if (!IsSibCall)
876  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
877 
878  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
879  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
880  MIB.add(Info.Callee);
881 
882  // Byte offset for the tail call. When we are sibcalling, this will always
883  // be 0.
884  MIB.addImm(0);
885 
886  // Tell the call which registers are clobbered.
887  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
888  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
890  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
891  MIB.addRegMask(Mask);
892 
893  if (TRI->isAnyArgRegReserved(MF))
894  TRI->emitReservedArgRegCallError(MF);
895 
896  // FPDiff is the byte offset of the call's argument area from the callee's.
897  // Stores to callee stack arguments will be placed in FixedStackSlots offset
898  // by this amount for a tail call. In a sibling call it must be 0 because the
899  // caller will deallocate the entire stack and the callee still expects its
900  // arguments to begin at SP+0.
901  int FPDiff = 0;
902 
903  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
904  // by -tailcallopt. For sibcalls, the memory operands for the call are
905  // already available in the caller's incoming argument space.
906  unsigned NumBytes = 0;
907  if (!IsSibCall) {
908  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
909  // before handling assignments, because FPDiff must be known for memory
910  // arguments.
911  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
913  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
914  analyzeArgInfo(OutInfo, OutArgs, *AssignFnFixed, *AssignFnVarArg);
915 
916  // The callee will pop the argument stack as a tail call. Thus, we must
917  // keep it 16-byte aligned.
918  NumBytes = alignTo(OutInfo.getNextStackOffset(), 16);
919 
920  // FPDiff will be negative if this tail call requires more space than we
921  // would automatically have in our incoming argument space. Positive if we
922  // actually shrink the stack.
923  FPDiff = NumReusableBytes - NumBytes;
924 
925  // The stack pointer must be 16-byte aligned at all times it's used for a
926  // memory operation, which in practice means at *all* times and in
927  // particular across call boundaries. Therefore our own arguments started at
928  // a 16-byte aligned SP and the delta applied for the tail call should
929  // satisfy the same constraint.
930  assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
931  }
932 
933  const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
934 
935  // Do the actual argument marshalling.
936  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
937  AssignFnVarArg, /*IsReturn*/ false,
938  /*IsTailCall*/ true, FPDiff);
939  if (!handleAssignments(MIRBuilder, OutArgs, Handler, CalleeCC, Info.IsVarArg))
940  return false;
941 
942  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
943 
944  if (Info.IsVarArg && Info.IsMustTailCall) {
945  // Now we know what's being passed to the function. Add uses to the call for
946  // the forwarded registers that we *aren't* passing as parameters. This will
947  // preserve the copies we build earlier.
948  for (const auto &F : Forwards) {
949  Register ForwardedReg = F.PReg;
950  // If the register is already passed, or aliases a register which is
951  // already being passed, then skip it.
952  if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
953  if (!Use.isReg())
954  return false;
955  return TRI->regsOverlap(Use.getReg(), ForwardedReg);
956  }))
957  continue;
958 
959  // We aren't passing it already, so we should add it to the call.
960  MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
961  MIB.addReg(ForwardedReg, RegState::Implicit);
962  }
963  }
964 
965  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
966  // sequence start and end here.
967  if (!IsSibCall) {
968  MIB->getOperand(1).setImm(FPDiff);
969  CallSeqStart.addImm(NumBytes).addImm(0);
970  // End the call sequence *before* emitting the call. Normally, we would
971  // tidy the frame up after the call. However, here, we've laid out the
972  // parameters so that when SP is reset, they will be in the correct
973  // location.
974  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
975  }
976 
977  // Now we can add the actual call instruction to the correct basic block.
978  MIRBuilder.insertInstr(MIB);
979 
980  // If Callee is a reg, since it is used by a target specific instruction,
981  // it must have a register class matching the constraint of that instruction.
982  if (Info.Callee.isReg())
984  *MF.getSubtarget().getRegBankInfo(), *MIB,
985  MIB->getDesc(), Info.Callee, 0);
986 
988  Info.LoweredTailCall = true;
989  return true;
990 }
991 
993  CallLoweringInfo &Info) const {
994  MachineFunction &MF = MIRBuilder.getMF();
995  const Function &F = MF.getFunction();
997  auto &DL = F.getParent()->getDataLayout();
998  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
999 
1000  SmallVector<ArgInfo, 8> OutArgs;
1001  for (auto &OrigArg : Info.OrigArgs) {
1002  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1003  // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
1004  if (OrigArg.Ty->isIntegerTy(1))
1005  OutArgs.back().Flags[0].setZExt();
1006  }
1007 
1008  SmallVector<ArgInfo, 8> InArgs;
1009  if (!Info.OrigRet.Ty->isVoidTy())
1010  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1011 
1012  // If we can lower as a tail call, do that instead.
1013  bool CanTailCallOpt =
1014  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1015 
1016  // We must emit a tail call if we have musttail.
1017  if (Info.IsMustTailCall && !CanTailCallOpt) {
1018  // There are types of incoming/outgoing arguments we can't handle yet, so
1019  // it doesn't make sense to actually die here like in ISelLowering. Instead,
1020  // fall back to SelectionDAG and let it try to handle this.
1021  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1022  return false;
1023  }
1024 
1025  if (CanTailCallOpt)
1026  return lowerTailCall(MIRBuilder, Info, OutArgs);
1027 
1028  // Find out which ABI gets to decide where things go.
1029  CCAssignFn *AssignFnFixed;
1030  CCAssignFn *AssignFnVarArg;
1031  std::tie(AssignFnFixed, AssignFnVarArg) =
1032  getAssignFnsForCC(Info.CallConv, TLI);
1033 
1034  MachineInstrBuilder CallSeqStart;
1035  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1036 
1037  // Create a temporarily-floating call instruction so we can add the implicit
1038  // uses of arg registers.
1039  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1040 
1041  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1042  MIB.add(Info.Callee);
1043 
1044  // Tell the call which registers are clobbered.
1045  const uint32_t *Mask;
1046  const auto *TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
1047 
1048  // Do the actual argument marshalling.
1049  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
1050  AssignFnVarArg, /*IsReturn*/ false);
1051  if (!handleAssignments(MIRBuilder, OutArgs, Handler, Info.CallConv,
1052  Info.IsVarArg))
1053  return false;
1054 
1055  Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1056 
1058  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1059  MIB.addRegMask(Mask);
1060 
1061  if (TRI->isAnyArgRegReserved(MF))
1062  TRI->emitReservedArgRegCallError(MF);
1063 
1064  // Now we can add the actual call instruction to the correct basic block.
1065  MIRBuilder.insertInstr(MIB);
1066 
1067  // If Callee is a reg, since it is used by a target specific
1068  // instruction, it must have a register class matching the
1069  // constraint of that instruction.
1070  if (Info.Callee.isReg())
1072  *MF.getSubtarget().getRegBankInfo(), *MIB,
1073  MIB->getDesc(), Info.Callee, 0);
1074 
1075  // Finally we can copy the returned value back into its virtual-register. In
1076  // symmetry with the arguments, the physical register must be an
1077  // implicit-define of the call instruction.
1078  if (!Info.OrigRet.Ty->isVoidTy()) {
1079  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
1080  CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
1081  bool UsingReturnedArg =
1082  !OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1083  ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB,
1084  RetAssignFn);
1085  if (!handleAssignments(MIRBuilder, InArgs,
1086  UsingReturnedArg ? ReturnedArgHandler : Handler,
1087  Info.CallConv, Info.IsVarArg,
1088  UsingReturnedArg ? OutArgs[0].Regs[0] : Register()))
1089  return false;
1090  }
1091 
1092  if (Info.SwiftErrorVReg) {
1093  MIB.addDef(AArch64::X21, RegState::Implicit);
1094  MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1095  }
1096 
1097  uint64_t CalleePopBytes =
1098  doesCalleeRestoreStack(Info.CallConv,
1100  ? alignTo(Handler.StackSize, 16)
1101  : 0;
1102 
1103  CallSeqStart.addImm(Handler.StackSize).addImm(0);
1104  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1105  .addImm(Handler.StackSize)
1106  .addImm(CalleePopBytes);
1107 
1108  return true;
1109 }
1110 
1112  return Ty.getSizeInBits() == 64;
1113 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
i
i
Definition: README.txt:29
llvm::AArch64CallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: AArch64CallLowering.cpp:323
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AArch64FunctionInfo::setArgumentStackToRestore
void setArgumentStackToRestore(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:171
LowLevelType.h
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1022
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
Definition: AllocatorList.h:23
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:207
AArch64MachineFunctionInfo.h
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:817
llvm::AArch64CallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AArch64CallLowering.cpp:992
llvm::AArch64CallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AArch64CallLowering.cpp:506
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:61
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:349
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:7436
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:316
llvm::CallLowering::OutgoingValueHandler
Definition: CallLowering.h:255
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:634
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:341
MachineIRBuilder.h
llvm::AArch64FunctionInfo::setVarArgsStackIndex
void setVarArgsStackIndex(int Index)
Definition: AArch64MachineFunctionInfo.h:282
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:446
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::CCState::analyzeMustTailForwardedRegisters
void analyzeMustTailForwardedRegisters(SmallVectorImpl< ForwardedRegister > &Forwards, ArrayRef< MVT > RegParmTypes, CCAssignFn Fn)
Compute the set of registers that need to be preserved and forwarded to any musttail calls.
Definition: CallingConvLower.cpp:245
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:568
llvm::CallLowering::analyzeArgInfo
bool analyzeArgInfo(CCState &CCState, SmallVectorImpl< ArgInfo > &Args, CCAssignFn &AssignFnFixed, CCAssignFn &AssignFnVarArg) const
Analyze passed or returned values from a call, supplied in ArgInfo, incorporating info about the pass...
Definition: CallLowering.cpp:880
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:426
llvm::AArch64FunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: AArch64MachineFunctionInfo.h:167
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:83
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:332
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:656
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::AArch64FunctionInfo::setBytesInStackArgArea
void setBytesInStackArgArea(unsigned bytes)
Definition: AArch64MachineFunctionInfo.h:168
llvm::CallLowering::handleAssignments
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke Handler::assignArg on each of the given Args and then use Handler to move them to the assigned...
Definition: CallLowering.cpp:491
applyStackPassedSmallTypeDAGHack
static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT, MVT &LocVT)
Definition: AArch64CallLowering.cpp:54
Utils.h
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::CallLowering::IncomingValueHandler
Definition: CallLowering.h:241
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AArch64CallLowering.cpp:608
llvm::MachineFrameInfo::hasMustTailInVarArgFunc
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
Definition: MachineFrameInfo.h:623
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
getMaskForArgs
static const uint32_t * getMaskForArgs(SmallVectorImpl< AArch64CallLowering::ArgInfo > &OutArgs, AArch64CallLowering::CallLoweringInfo &Info, const AArch64RegisterInfo &TRI, MachineFunction &MF)
Definition: AArch64CallLowering.cpp:831
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:490
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:558
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:388
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1499
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
handleMustTailForwardedRegisters
static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn)
Helper function to compute forwarded registers for musttail calls.
Definition: AArch64CallLowering.cpp:450
AArch64CallLowering.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:167
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:608
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:4678
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
Analysis.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:96
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:100
ArrayRef.h
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AArch64CallLowering.cpp:814
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:628
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:259
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:821
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:574
llvm::AArch64FunctionInfo::branchTargetEnforcement
bool branchTargetEnforcement() const
Definition: AArch64MachineFunctionInfo.h:373
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:128
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:634
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::CCState::isVarArg
bool isVarArg() const
Definition: CallingConvLower.h:260
llvm::AArch64Subtarget::hasCustomCallingConv
bool hasCustomCallingConv() const
Definition: AArch64Subtarget.h:357
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1489
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::AArch64FunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: AArch64MachineFunctionInfo.h:345
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AArch64CallLowering.cpp:594
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
AArch64ISelLowering.h
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
Argument.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:305
Attributes.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:554
MachineFrameInfo.h
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:584
getStackValueStoreSizeHack
static uint64_t getStackValueStoreSizeHack(const CCValAssign &VA)
Definition: AArch64CallLowering.cpp:69
Success
#define Success
Definition: AArch64Disassembler.cpp:248
doesCalleeRestoreStack
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
Definition: AArch64CallLowering.cpp:319
Function.h
llvm::CallLowering::ArgInfo::Regs
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:62
llvm::CallLowering::BaseArgInfo::Ty
Type * Ty
Definition: CallLowering.h:49
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:95
llvm::AArch64CallLowering::fallBackToDAGISel
bool fallBackToDAGISel(const MachineFunction &MF) const override
Definition: AArch64CallLowering.cpp:490
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, CCAssignFn &CalleeAssignFnFixed, CCAssignFn &CalleeAssignFnVarArg, CCAssignFn &CallerAssignFnFixed, CCAssignFn &CallerAssignFnVarArg) const
Definition: CallLowering.cpp:949
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:4711
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:196
AArch64Subtarget.h
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:55
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::AArch64CallLowering::isTypeIsValidForThisReturn
bool isTypeIsValidForThisReturn(EVT Ty) const override
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: AArch64CallLowering.cpp:1111
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1491
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:123
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:501
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:588
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:151
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::AArch64CallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AArch64CallLowering.cpp:712
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AArch64CallLowering.cpp:589
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:480
MachineFunction.h
llvm::AArch64CallLowering::AArch64CallLowering
AArch64CallLowering(const AArch64TargetLowering &TLI)
Definition: AArch64CallLowering.cpp:51
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:897
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
Value.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:390
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:491
llvm::CCState::isAllocated
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
Definition: CallingConvLower.h:277
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:150