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AArch64ISelLowering.h
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1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 
17 #include "AArch64.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Instruction.h"
24 
25 namespace llvm {
26 
27 namespace AArch64ISD {
28 
29 // For predicated nodes where the result is a vector, the operation is
30 // controlled by a governing predicate and the inactive lanes are explicitly
31 // defined with a value, please stick the following naming convention:
32 //
33 // _MERGE_OP<n> The result value is a vector with inactive lanes equal
34 // to source operand OP<n>.
35 //
36 // _MERGE_ZERO The result value is a vector with inactive lanes
37 // actively zeroed.
38 //
39 // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
40 // to the last source operand which only purpose is being
41 // a passthru value.
42 //
43 // For other cases where no explicit action is needed to set the inactive lanes,
44 // or when the result is not a vector and it is needed or helpful to
45 // distinguish a node from similar unpredicated nodes, use:
46 //
47 // _PRED
48 //
49 enum NodeType : unsigned {
51  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
52  CALL, // Function call.
53 
54  // Pseudo for a OBJC call that gets emitted together with a special `mov
55  // x29, x29` marker instruction.
57 
58  // Produces the full sequence of instructions for getting the thread pointer
59  // offset of a variable into X0, using the TLSDesc model.
61  ADRP, // Page address of a TargetGlobalAddress operand.
62  ADR, // ADR
63  ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
64  LOADgot, // Load from automatically generated descriptor (e.g. Global
65  // Offset Table, TLS record).
66  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
67  BRCOND, // Conditional branch instruction; "b.cond".
69  CSINV, // Conditional select invert.
70  CSNEG, // Conditional select negate.
71  CSINC, // Conditional select increment.
72 
73  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
74  // ELF.
76  ADC,
77  SBC, // adc, sbc instructions
78 
79  // Predicated instructions where inactive lanes produce undefined results.
103 
104  // Predicated instructions with the result of inactive lanes provided by the
105  // last operand.
127 
129 
130  // Arithmetic instructions which write flags.
136 
137  // Conditional compares. Operands: left,right,falsecc,cc,flags
141 
142  // Floating point comparison
144 
145  // Scalar extract
147 
148  // Scalar-to-vector duplication
154 
155  // Vector immedate moves
163 
164  // Vector immediate ops
167 
168  // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
169  // element must be identical.
171 
172  // Vector arithmetic negation
174 
175  // Vector shuffles
186 
187  // Vector shift by scalar
191 
192  // Vector shift by scalar (again)
198 
199  // Vector shift by constant and insert
202 
203  // Vector comparisons
212 
213  // Vector zero comparisons
224 
225  // Vector across-lanes addition
226  // Only the lower result lane is defined.
229 
230  // Vector halving addition
233 
234  // Vector rounding halving addition
237 
238  // Absolute difference
241 
242  // udot/sdot instructions
245 
246  // Vector across-lanes min/max
247  // Only the lower result lane is defined.
252 
262 
263  // Vector bitwise insertion
265 
266  // Compare-and-branch
271 
272  // Tail calls
274 
275  // Custom prefetch handling
277 
278  // {s|u}int to FP within a FP register.
281 
282  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
283  /// world w.r.t vectors; which causes additional REV instructions to be
284  /// generated to compensate for the byte-swapping. But sometimes we do
285  /// need to re-interpret the data in SIMD vector registers in big-endian
286  /// mode without emitting such REV instructions.
288 
289  MRS, // MRS, also sets the flags via a glue.
290 
293 
294  // Reciprocal estimates and steps.
299 
304 
310 
311  // Floating-point reductions.
318 
322 
329 
330  // Cast between vectors of the same element type but differ in length.
332 
341 
342  // Structured loads.
346 
347  // Unsigned gather loads.
355 
356  // Signed gather loads
364 
365  // Unsigned gather loads.
373 
374  // Signed gather loads.
382 
383  // Non-temporal gather loads
387 
388  // Contiguous masked store.
390 
391  // Scatter store
399 
400  // Non-temporal scatter store
403 
404  // Strict (exception-raising) floating point comparison
407 
408  // NEON Load/Store with post-increment base updates
432 
437 
441 };
442 
443 } // end namespace AArch64ISD
444 
445 namespace {
446 
447 // Any instruction that defines a 32-bit result zeros out the high half of the
448 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
449 // be copying from a truncate. But any other 32-bit operation will zero-extend
450 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
451 // 32 bits, they're probably just qualifying a CopyFromReg.
452 // FIXME: X86 also checks for CMOV here. Do we need something similar?
453 static inline bool isDef32(const SDNode &N) {
454  unsigned Opc = N.getOpcode();
455  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
456  Opc != ISD::CopyFromReg && Opc != ISD::AssertSext &&
457  Opc != ISD::AssertZext;
458 }
459 
460 } // end anonymous namespace
461 
462 namespace AArch64 {
463 /// Possible values of current rounding mode, which is specified in bits
464 /// 23:22 of FPCR.
465 enum Rounding {
466  RN = 0, // Round to Nearest
467  RP = 1, // Round towards Plus infinity
468  RM = 2, // Round towards Minus infinity
469  RZ = 3, // Round towards Zero
470  rmMask = 3 // Bit mask selecting rounding mode
471 };
472 
473 // Bit position of rounding mode bits in FPCR.
474 const unsigned RoundingBitsPos = 22;
475 } // namespace AArch64
476 
477 class AArch64Subtarget;
479 
481 public:
482  explicit AArch64TargetLowering(const TargetMachine &TM,
483  const AArch64Subtarget &STI);
484 
485  /// Selects the correct CCAssignFn for a given CallingConvention value.
486  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
487 
488  /// Selects the correct CCAssignFn for a given CallingConvention value.
490 
491  /// Determine which of the bits specified in Mask are known to be either zero
492  /// or one and return them in the KnownZero/KnownOne bitsets.
494  const APInt &DemandedElts,
495  const SelectionDAG &DAG,
496  unsigned Depth = 0) const override;
497 
498  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
499  // Returning i64 unconditionally here (i.e. even for ILP32) means that the
500  // *DAG* representation of pointers will always be 64-bits. They will be
501  // truncated and extended when transferred to memory, but the 64-bit DAG
502  // allows us to use AArch64's addressing modes much more easily.
503  return MVT::getIntegerVT(64);
504  }
505 
507  const APInt &DemandedElts,
508  TargetLoweringOpt &TLO) const override;
509 
510  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
511 
512  /// Returns true if the target allows unaligned memory accesses of the
513  /// specified type.
515  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
517  bool *Fast = nullptr) const override;
518  /// LLT variant.
519  bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
520  Align Alignment,
522  bool *Fast = nullptr) const override;
523 
524  /// Provide custom lowering hooks for some operations.
525  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
526 
527  const char *getTargetNodeName(unsigned Opcode) const override;
528 
529  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
530 
531  /// This method returns a target specific FastISel object, or null if the
532  /// target does not support "fast" ISel.
534  const TargetLibraryInfo *libInfo) const override;
535 
536  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
537 
538  bool isFPImmLegal(const APFloat &Imm, EVT VT,
539  bool ForCodeSize) const override;
540 
541  /// Return true if the given shuffle mask can be codegen'd directly, or if it
542  /// should be stack expanded.
543  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
544 
545  /// Return the ISD::SETCC ValueType.
547  EVT VT) const override;
548 
550 
552  MachineBasicBlock *BB) const;
553 
555  MachineBasicBlock *BB) const;
556 
559  MachineBasicBlock *MBB) const override;
560 
561  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
562  MachineFunction &MF,
563  unsigned Intrinsic) const override;
564 
566  EVT NewVT) const override;
567 
568  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
569  bool isTruncateFree(EVT VT1, EVT VT2) const override;
570 
571  bool isProfitableToHoist(Instruction *I) const override;
572 
573  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
574  bool isZExtFree(EVT VT1, EVT VT2) const override;
575  bool isZExtFree(SDValue Val, EVT VT2) const override;
576 
578  SmallVectorImpl<Use *> &Ops) const override;
579 
580  bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
581 
582  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
583 
586  ArrayRef<unsigned> Indices,
587  unsigned Factor) const override;
589  unsigned Factor) const override;
590 
591  bool isLegalAddImmediate(int64_t) const override;
592  bool isLegalICmpImmediate(int64_t) const override;
593 
594  bool shouldConsiderGEPOffsetSplit() const override;
595 
597  const AttributeList &FuncAttributes) const override;
598 
600  const AttributeList &FuncAttributes) const override;
601 
602  /// Return true if the addressing mode represented by AM is legal for this
603  /// target, for a load/store of the specified type.
604  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
605  unsigned AS,
606  Instruction *I = nullptr) const override;
607 
608  /// Return the cost of the scaling factor used in the addressing
609  /// mode represented by AM for this target, for a load/store
610  /// of the specified type.
611  /// If the AM is supported, the return value must be >= 0.
612  /// If the AM is not supported, it returns a negative value.
614  Type *Ty, unsigned AS) const override;
615 
616  /// Return true if an FMA operation is faster than a pair of fmul and fadd
617  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
618  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
620  EVT VT) const override;
621  bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
622 
624  CodeGenOpt::Level OptLevel) const override;
625 
626  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
627 
628  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
630  CombineLevel Level) const override;
631 
632  /// Returns true if it is beneficial to convert a load of a constant
633  /// to just the constant itself.
635  Type *Ty) const override;
636 
637  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
638  /// with this index.
639  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
640  unsigned Index) const override;
641 
642  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
643  bool MathUsed) const override {
644  // Using overflow ops for overflow checks only should beneficial on
645  // AArch64.
646  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
647  }
648 
650  AtomicOrdering Ord) const override;
652  Value *Addr, AtomicOrdering Ord) const override;
653 
655 
657  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
658  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
660  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
661 
664 
665  bool useLoadStackGuardNode() const override;
667  getPreferredVectorAction(MVT VT) const override;
668 
669  /// If the target has a standard location for the stack protector cookie,
670  /// returns the address of that location. Otherwise, returns nullptr.
671  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
672 
673  void insertSSPDeclarations(Module &M) const override;
674  Value *getSDagStackGuard(const Module &M) const override;
675  Function *getSSPStackGuardCheck(const Module &M) const override;
676 
677  /// If the target has a standard location for the unsafe stack pointer,
678  /// returns the address of that location. Otherwise, returns nullptr.
679  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
680 
681  /// If a physical register, this returns the register that receives the
682  /// exception address on entry to an EH pad.
683  Register
684  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
685  // FIXME: This is a guess. Has this been defined yet?
686  return AArch64::X0;
687  }
688 
689  /// If a physical register, this returns the register that receives the
690  /// exception typeid on entry to a landing pad.
691  Register
692  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
693  // FIXME: This is a guess. Has this been defined yet?
694  return AArch64::X1;
695  }
696 
697  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
698 
699  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
700  const SelectionDAG &DAG) const override {
701  // Do not merge to float value size (128 bytes) if no implicit
702  // float attribute is set.
703 
704  bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
705  Attribute::NoImplicitFloat);
706 
707  if (NoFloat)
708  return (MemVT.getSizeInBits() <= 64);
709  return true;
710  }
711 
712  bool isCheapToSpeculateCttz() const override {
713  return true;
714  }
715 
716  bool isCheapToSpeculateCtlz() const override {
717  return true;
718  }
719 
720  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
721 
722  bool hasAndNotCompare(SDValue V) const override {
723  // We can use bics for any scalar.
724  return V.getValueType().isScalarInteger();
725  }
726 
727  bool hasAndNot(SDValue Y) const override {
728  EVT VT = Y.getValueType();
729 
730  if (!VT.isVector())
731  return hasAndNotCompare(Y);
732 
733  return VT.getSizeInBits() >= 64; // vector 'bic'
734  }
735 
738  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
739  SelectionDAG &DAG) const override;
740 
741  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
742 
744  unsigned KeptBits) const override {
745  // For vectors, we don't have a preference..
746  if (XVT.isVector())
747  return false;
748 
749  auto VTIsOk = [](EVT VT) -> bool {
750  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
751  VT == MVT::i64;
752  };
753 
754  // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
755  // XVT will be larger than KeptBitsVT.
756  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
757  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
758  }
759 
760  bool preferIncOfAddToSubOfNot(EVT VT) const override;
761 
762  bool hasBitPreservingFPLogic(EVT VT) const override {
763  // FIXME: Is this always true? It should be true for vectors at least.
764  return VT == MVT::f32 || VT == MVT::f64;
765  }
766 
767  bool supportSplitCSR(MachineFunction *MF) const override {
769  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
770  }
771  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
773  MachineBasicBlock *Entry,
774  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
775 
776  bool supportSwiftError() const override {
777  return true;
778  }
779 
780  /// Enable aggressive FMA fusion on targets that want it.
781  bool enableAggressiveFMAFusion(EVT VT) const override;
782 
783  /// Returns the size of the platform's va_list object.
784  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
785 
786  /// Returns true if \p VecTy is a legal interleaved access type. This
787  /// function checks the vector element type and the overall width of the
788  /// vector.
790  const DataLayout &DL) const;
791 
792  /// Returns the number of interleaved accesses that will be generated when
793  /// lowering accesses of the given type.
794  unsigned getNumInterleavedAccesses(VectorType *VecTy,
795  const DataLayout &DL) const;
796 
798  const Instruction &I) const override;
799 
801  CallingConv::ID CallConv,
802  bool isVarArg) const override;
803  /// Used for exception handling on Win64.
804  bool needsFixedCatchObjects() const override;
805 
806  bool fallBackToDAGISel(const Instruction &Inst) const override;
807 
808  /// SVE code generation for fixed length vectors does not custom lower
809  /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
810  /// merge. However, merging them creates a BUILD_VECTOR that is just as
811  /// illegal as the original, thus leading to an infinite legalisation loop.
812  /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
813  /// vector types this override can be removed.
814  bool mergeStoresAfterLegalization(EVT VT) const override;
815 
816  // If the platform/function should have a redzone, return the size in bytes.
817  unsigned getRedZoneSize(const Function &F) const {
818  if (F.hasFnAttribute(Attribute::NoRedZone))
819  return 0;
820  return 128;
821  }
822 
823 private:
824  /// Keep a pointer to the AArch64Subtarget around so that we can
825  /// make the right decision when generating code for different targets.
826  const AArch64Subtarget *Subtarget;
827 
828  bool isExtFreeImpl(const Instruction *Ext) const override;
829 
830  void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
831  void addTypeForFixedLengthSVE(MVT VT);
832  void addDRTypeForNEON(MVT VT);
833  void addQRTypeForNEON(MVT VT);
834 
835  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
836  bool isVarArg,
838  const SDLoc &DL, SelectionDAG &DAG,
839  SmallVectorImpl<SDValue> &InVals) const override;
840 
841  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
842  SmallVectorImpl<SDValue> &InVals) const override;
843 
844  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
845  CallingConv::ID CallConv, bool isVarArg,
847  const SDLoc &DL, SelectionDAG &DAG,
848  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
849  SDValue ThisVal) const;
850 
851  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
852  SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
853 
854  SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
855  SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
856 
857  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
858 
859  bool isEligibleForTailCallOptimization(
860  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
862  const SmallVectorImpl<SDValue> &OutVals,
863  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
864 
865  /// Finds the incoming stack arguments which overlap the given fixed stack
866  /// object and incorporates their load into the current chain. This prevents
867  /// an upcoming store from clobbering the stack argument before it's used.
868  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
869  MachineFrameInfo &MFI, int ClobberedFI) const;
870 
871  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
872 
873  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
874  SDValue &Chain) const;
875 
876  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
877  bool isVarArg,
879  LLVMContext &Context) const override;
880 
881  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
883  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
884  SelectionDAG &DAG) const override;
885 
886  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
887  unsigned Flag) const;
888  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
889  unsigned Flag) const;
890  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
891  unsigned Flag) const;
892  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
893  unsigned Flag) const;
894  template <class NodeTy>
895  SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
896  template <class NodeTy>
897  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
898  template <class NodeTy>
899  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
900  template <class NodeTy>
901  SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
902  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
903  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
904  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
905  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
906  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
907  SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
908  const SDLoc &DL, SelectionDAG &DAG) const;
909  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
910  SelectionDAG &DAG) const;
911  SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
912  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
913  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
914  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
915  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
916  SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
917  SDValue TVal, SDValue FVal, const SDLoc &dl,
918  SelectionDAG &DAG) const;
919  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
920  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
921  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
922  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
923  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
924  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
925  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
926  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
927  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
928  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
929  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
930  SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
931  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
932  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
933  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
934  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
935  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
936  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
937  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
938  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
939  SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
940  SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
941  SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
942  bool OverrideNEON = false) const;
943  SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
944  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
945  SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
946  SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
947  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
948  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
949  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
950  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
951  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
952  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
953  SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
954  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
955  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
956  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
957  SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
958  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
959  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
960  SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
961  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
962  SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
963  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
964  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
965  SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
966  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
967  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
968  SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
969  SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
970  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
971  SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
972  SDValue &Size,
973  SelectionDAG &DAG) const;
974  SDValue LowerSVEStructLoad(unsigned Intrinsic, ArrayRef<SDValue> LoadOps,
975  EVT VT, SelectionDAG &DAG, const SDLoc &DL) const;
976 
977  SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
978  SelectionDAG &DAG) const;
979  SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
980  SelectionDAG &DAG) const;
981  SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
982  SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
983  SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
984  SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
985  SelectionDAG &DAG) const;
986  SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
987  SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
988  SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
989  SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
990  SelectionDAG &DAG) const;
991  SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
992  SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
993 
994  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
995  SmallVectorImpl<SDNode *> &Created) const override;
996  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
997  int &ExtraSteps, bool &UseOneConst,
998  bool Reciprocal) const override;
999  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1000  int &ExtraSteps) const override;
1001  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1002  const DenormalMode &Mode) const override;
1003  SDValue getSqrtResultForDenormInput(SDValue Operand,
1004  SelectionDAG &DAG) const override;
1005  unsigned combineRepeatedFPDivisors() const override;
1006 
1007  ConstraintType getConstraintType(StringRef Constraint) const override;
1008  Register getRegisterByName(const char* RegName, LLT VT,
1009  const MachineFunction &MF) const override;
1010 
1011  /// Examine constraint string and operand type and determine a weight value.
1012  /// The operand object must already have been set up with the operand type.
1014  getSingleConstraintMatchWeight(AsmOperandInfo &info,
1015  const char *constraint) const override;
1016 
1017  std::pair<unsigned, const TargetRegisterClass *>
1018  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1019  StringRef Constraint, MVT VT) const override;
1020 
1021  const char *LowerXConstraint(EVT ConstraintVT) const override;
1022 
1023  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1024  std::vector<SDValue> &Ops,
1025  SelectionDAG &DAG) const override;
1026 
1027  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1028  if (ConstraintCode == "Q")
1029  return InlineAsm::Constraint_Q;
1030  // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1031  // followed by llvm_unreachable so we'll leave them unimplemented in
1032  // the backend for now.
1033  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1034  }
1035 
1036  bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1037  bool shouldRemoveExtendFromGSIndex(EVT VT) const override;
1038  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1039  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1040  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1041  bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
1042  ISD::MemIndexedMode &AM, bool &IsInc,
1043  SelectionDAG &DAG) const;
1044  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1045  ISD::MemIndexedMode &AM,
1046  SelectionDAG &DAG) const override;
1047  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1048  SDValue &Offset, ISD::MemIndexedMode &AM,
1049  SelectionDAG &DAG) const override;
1050 
1051  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1052  SelectionDAG &DAG) const override;
1053  void ReplaceExtractSubVectorResults(SDNode *N,
1054  SmallVectorImpl<SDValue> &Results,
1055  SelectionDAG &DAG) const;
1056 
1057  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1058 
1059  void finalizeLowering(MachineFunction &MF) const override;
1060 
1061  bool shouldLocalize(const MachineInstr &MI,
1062  const TargetTransformInfo *TTI) const override;
1063 
1064  // Normally SVE is only used for byte size vectors that do not fit within a
1065  // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
1066  // used for 64bit and 128bit vectors as well.
1067  bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
1068 
1069  // With the exception of data-predicate transitions, no instructions are
1070  // required to cast between legal scalable vector types. However:
1071  // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1072  // is not universally useable.
1073  // 2. Most unpacked integer types are not legal and thus integer extends
1074  // cannot be used to convert between unpacked and packed types.
1075  // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1076  // to transition between unpacked and packed types of the same element type,
1077  // with BITCAST used otherwise.
1078  SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1079 };
1080 
1081 namespace AArch64 {
1082 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1083  const TargetLibraryInfo *libInfo);
1084 } // end namespace AArch64
1085 
1086 } // end namespace llvm
1087 
1088 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AArch64ISD::LD1x2post
@ LD1x2post
Definition: AArch64ISelLowering.h:415
llvm::AArch64ISD::EORV_PRED
@ EORV_PRED
Definition: AArch64ISelLowering.h:260
llvm::AArch64ISD::NodeType
NodeType
Definition: AArch64ISelLowering.h:49
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::AArch64ISD::LD2DUPpost
@ LD2DUPpost
Definition: AArch64ISelLowering.h:422
llvm::AArch64ISD::SVE_LD4_MERGE_ZERO
@ SVE_LD4_MERGE_ZERO
Definition: AArch64ISelLowering.h:345
llvm::AArch64ISD::UMULL
@ UMULL
Definition: AArch64ISelLowering.h:292
llvm::AArch64ISD::LOADgot
@ LOADgot
Definition: AArch64ISelLowering.h:64
llvm::AArch64ISD::LD3post
@ LD3post
Definition: AArch64ISelLowering.h:410
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1536
llvm::AArch64ISD::UUNPKHI
@ UUNPKHI
Definition: AArch64ISelLowering.h:302
llvm::AArch64ISD::VLSHR
@ VLSHR
Definition: AArch64ISelLowering.h:189
llvm::AArch64ISD::SSTNT1_INDEX_PRED
@ SSTNT1_INDEX_PRED
Definition: AArch64ISelLowering.h:402
llvm::AArch64ISD::ST1x4post
@ ST1x4post
Definition: AArch64ISelLowering.h:420
llvm::AArch64ISD::UMINV
@ UMINV
Definition: AArch64ISelLowering.h:249
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1290
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::AArch64TargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: AArch64ISelLowering.cpp:16943
llvm::AArch64ISD::CLASTA_N
@ CLASTA_N
Definition: AArch64ISelLowering.h:305
llvm
Definition: AllocatorList.h:23
llvm::AArch64TargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: AArch64ISelLowering.cpp:16703
llvm::AArch64TargetLowering::generateFMAsInMachineCombiner
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOpt::Level OptLevel) const override
Definition: AArch64ISelLowering.cpp:11789
AArch64.h
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:144
llvm::AArch64TargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: AArch64ISelLowering.cpp:16950
llvm::AArch64TargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: AArch64ISelLowering.h:642
llvm::AArch64ISD::FMINV_PRED
@ FMINV_PRED
Definition: AArch64ISelLowering.h:316
llvm::AArch64ISD::SITOF
@ SITOF
Definition: AArch64ISelLowering.h:279
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::AArch64TargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: AArch64ISelLowering.cpp:1621
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4103
llvm::AArch64ISD::FCMGEz
@ FCMGEz
Definition: AArch64ISelLowering.h:220
llvm::AArch64TargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition: AArch64ISelLowering.cpp:1789
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::AArch64ISD::SMAX_PRED
@ SMAX_PRED
Definition: AArch64ISelLowering.h:95
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:59
llvm::AArch64ISD::CCMN
@ CCMN
Definition: AArch64ISelLowering.h:139
llvm::AArch64ISD::DUP_MERGE_PASSTHRU
@ DUP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:327
llvm::AArch64TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: AArch64ISelLowering.cpp:11678
llvm::AArch64ISD::FCMLEz
@ FCMLEz
Definition: AArch64ISelLowering.h:222
llvm::AArch64ISD::CTPOP_MERGE_PASSTHRU
@ CTPOP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:326
llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO
@ GLDFF1S_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:379
llvm::AArch64ISD::PREFETCH
@ PREFETCH
Definition: AArch64ISelLowering.h:276
llvm::Function
Definition: Function.h:61
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:249
llvm::AArch64TargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: AArch64ISelLowering.h:767
llvm::AArch64ISD::UMAX_PRED
@ UMAX_PRED
Definition: AArch64ISelLowering.h:101
llvm::AArch64TargetLowering::needsFixedCatchObjects
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Definition: AArch64ISelLowering.cpp:17088
llvm::AArch64ISD::TC_RETURN
@ TC_RETURN
Definition: AArch64ISelLowering.h:273
llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU
@ CTLZ_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:325
llvm::AArch64ISD::LD3LANEpost
@ LD3LANEpost
Definition: AArch64ISelLowering.h:427
llvm::AArch64ISD::SST1_UXTW_SCALED_PRED
@ SST1_UXTW_SCALED_PRED
Definition: AArch64ISelLowering.h:396
llvm::AArch64ISD::SBCS
@ SBCS
Definition: AArch64ISelLowering.h:134
llvm::AArch64ISD::TBNZ
@ TBNZ
Definition: AArch64ISelLowering.h:270
llvm::AArch64ISD::FMAXNMV_PRED
@ FMAXNMV_PRED
Definition: AArch64ISelLowering.h:315
llvm::AArch64ISD::SADDV
@ SADDV
Definition: AArch64ISelLowering.h:227
llvm::AArch64ISD::LD1x3post
@ LD1x3post
Definition: AArch64ISelLowering.h:416
llvm::AArch64ISD::UZP1
@ UZP1
Definition: AArch64ISelLowering.h:178
llvm::AArch64ISD::ZIP1
@ ZIP1
Definition: AArch64ISelLowering.h:176
llvm::AArch64ISD::MULHU_PRED
@ MULHU_PRED
Definition: AArch64ISelLowering.h:92
llvm::AArch64TargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Definition: AArch64ISelLowering.cpp:11806
llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO
@ GLDFF1S_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:376
llvm::AArch64ISD::CMHS
@ CMHS
Definition: AArch64ISelLowering.h:208
llvm::AArch64ISD::STNP
@ STNP
Definition: AArch64ISelLowering.h:440
llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO
@ GLD1_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:353
llvm::AArch64TargetLowering::getSafeStackPointerLocation
Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
Definition: AArch64ISelLowering.cpp:16957
llvm::AArch64ISD::ST3LANEpost
@ ST3LANEpost
Definition: AArch64ISelLowering.h:430
llvm::AArch64ISD::UMIN_PRED
@ UMIN_PRED
Definition: AArch64ISelLowering.h:102
llvm::IRBuilder<>
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU
@ FCEIL_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:107
llvm::AArch64ISD::LD2post
@ LD2post
Definition: AArch64ISelLowering.h:409
llvm::AArch64ISD::MULHS_PRED
@ MULHS_PRED
Definition: AArch64ISelLowering.h:91
llvm::AArch64ISD::FRECPX_MERGE_PASSTHRU
@ FRECPX_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:111
llvm::AArch64ISD::STG
@ STG
Definition: AArch64ISelLowering.h:433
llvm::AArch64ISD::CMGE
@ CMGE
Definition: AArch64ISelLowering.h:205
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::AArch64ISD::FCMGTz
@ FCMGTz
Definition: AArch64ISelLowering.h:221
llvm::AArch64ISD::SMAXV_PRED
@ SMAXV_PRED
Definition: AArch64ISelLowering.h:255
llvm::AArch64ISD::CMLTz
@ CMLTz
Definition: AArch64ISelLowering.h:218
llvm::AArch64TargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: AArch64ISelLowering.cpp:11795
llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: AArch64ISelLowering.cpp:1738
llvm::AArch64ISD::FMAX_PRED
@ FMAX_PRED
Definition: AArch64ISelLowering.h:86
llvm::MemOp
Definition: TargetLowering.h:109
llvm::AArch64ISD::DUP
@ DUP
Definition: AArch64ISelLowering.h:149
llvm::AArch64TargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: AArch64ISelLowering.h:582
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::AArch64ISD::FCVTZS_MERGE_PASSTHRU
@ FCVTZS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:122
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::AArch64ISD::LDFF1_MERGE_ZERO
@ LDFF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:337
llvm::AArch64ISD::ST1x2post
@ ST1x2post
Definition: AArch64ISelLowering.h:418
llvm::AArch64TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: AArch64ISelLowering.cpp:10954
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::AArch64ISD::MOVIshift
@ MOVIshift
Definition: AArch64ISelLowering.h:157
llvm::AArch64ISD::LDP
@ LDP
Definition: AArch64ISelLowering.h:438
llvm::AttributeList
Definition: Attributes.h:385
llvm::AArch64TargetLowering::ReconstructShuffle
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
Definition: AArch64ISelLowering.cpp:8178
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::AArch64ISD::GLDNT1_MERGE_ZERO
@ GLDNT1_MERGE_ZERO
Definition: AArch64ISelLowering.h:384
llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO
@ GLDFF1_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:368
llvm::AArch64TargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
Definition: AArch64ISelLowering.cpp:10922
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:355
llvm::AArch64ISD::CALL_RVMARKER
@ CALL_RVMARKER
Definition: AArch64ISelLowering.h:56
llvm::AArch64ISD::CBZ
@ CBZ
Definition: AArch64ISelLowering.h:267
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU
@ FFLOOR_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:108
llvm::AArch64ISD::ADC
@ ADC
Definition: AArch64ISelLowering.h:76
llvm::AArch64TargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: AArch64ISelLowering.cpp:11737
llvm::AArch64TargetLowering::EmitLoweredCatchRet
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2141
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::AArch64ISD::SMINV_PRED
@ SMINV_PRED
Definition: AArch64ISelLowering.h:257
llvm::AArch64ISD::MOVImsl
@ MOVImsl
Definition: AArch64ISelLowering.h:159
llvm::AArch64ISD::GLDFF1_MERGE_ZERO
@ GLDFF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:366
llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO
@ GLDFF1S_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:377
llvm::AArch64ISD::FCMGT
@ FCMGT
Definition: AArch64ISelLowering.h:211
llvm::AArch64ISD::TRN2
@ TRN2
Definition: AArch64ISelLowering.h:181
llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO
@ GLDFF1_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:372
llvm::AArch64ISD::CCMP
@ CCMP
Definition: AArch64ISelLowering.h:138
llvm::AArch64ISD::FMINNMV_PRED
@ FMINNMV_PRED
Definition: AArch64ISelLowering.h:317
llvm::AArch64ISD::URSHR_I
@ URSHR_I
Definition: AArch64ISelLowering.h:197
llvm::AArch64ISD::FRECPS
@ FRECPS
Definition: AArch64ISelLowering.h:296
llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO
@ GLD1S_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:363
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2106
llvm::AArch64ISD::REV32
@ REV32
Definition: AArch64ISelLowering.h:183
llvm::AArch64ISD::TLSDESC_CALLSEQ
@ TLSDESC_CALLSEQ
Definition: AArch64ISelLowering.h:60
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AArch64ISD::LD1x4post
@ LD1x4post
Definition: AArch64ISelLowering.h:417
llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO
@ GLD1S_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:361
llvm::AArch64ISD::SHL_PRED
@ SHL_PRED
Definition: AArch64ISelLowering.h:94
llvm::AArch64ISD::FCMP
@ FCMP
Definition: AArch64ISelLowering.h:143
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AArch64ISD::SUNPKLO
@ SUNPKLO
Definition: AArch64ISelLowering.h:301
llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU
@ SIGN_EXTEND_INREG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:123
llvm::AArch64ISD::LD4LANEpost
@ LD4LANEpost
Definition: AArch64ISelLowering.h:428
llvm::AArch64ISD::LD3DUPpost
@ LD3DUPpost
Definition: AArch64ISelLowering.h:423
llvm::AArch64ISD::ADDlow
@ ADDlow
Definition: AArch64ISelLowering.h:63
llvm::AArch64ISD::STRICT_FCMP
@ STRICT_FCMP
Definition: AArch64ISelLowering.h:405
llvm::AArch64ISD::GLD1_MERGE_ZERO
@ GLD1_MERGE_ZERO
Definition: AArch64ISelLowering.h:348
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AArch64ISD::MVNIshift
@ MVNIshift
Definition: AArch64ISelLowering.h:161
llvm::AArch64ISD::SST1_UXTW_PRED
@ SST1_UXTW_PRED
Definition: AArch64ISelLowering.h:394
llvm::AArch64ISD::FCMLTz
@ FCMLTz
Definition: AArch64ISelLowering.h:223
Instruction.h
llvm::AArch64ISD::CMEQz
@ CMEQz
Definition: AArch64ISelLowering.h:214
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1321
TargetLowering.h
llvm::AArch64ISD::NEG
@ NEG
Definition: AArch64ISelLowering.h:173
llvm::AArch64ISD::FMUL_PRED
@ FMUL_PRED
Definition: AArch64ISelLowering.h:88
llvm::AArch64ISD::FRINT_MERGE_PASSTHRU
@ FRINT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:112
llvm::AArch64ISD::CSEL
@ CSEL
Definition: AArch64ISelLowering.h:68
llvm::AArch64TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: AArch64ISelLowering.cpp:15973
llvm::AArch64ISD::MVNImsl
@ MVNImsl
Definition: AArch64ISelLowering.h:162
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1113
llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: AArch64ISelLowering.cpp:11758
llvm::AArch64ISD::ST4LANEpost
@ ST4LANEpost
Definition: AArch64ISelLowering.h:431
llvm::AArch64ISD::TRN1
@ TRN1
Definition: AArch64ISelLowering.h:180
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::AArch64ISD::SST1_SCALED_PRED
@ SST1_SCALED_PRED
Definition: AArch64ISelLowering.h:393
llvm::AArch64ISD::CMGEz
@ CMGEz
Definition: AArch64ISelLowering.h:215
llvm::AArch64ISD::SMAXV
@ SMAXV
Definition: AArch64ISelLowering.h:250
llvm::AArch64ISD::SRL_PRED
@ SRL_PRED
Definition: AArch64ISelLowering.h:98
llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: AArch64ISelLowering.cpp:16785
llvm::AArch64TargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
Definition: AArch64ISelLowering.cpp:11436
llvm::AArch64ISD::GLDNT1S_MERGE_ZERO
@ GLDNT1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:386
llvm::AArch64ISD::LD1_MERGE_ZERO
@ LD1_MERGE_ZERO
Definition: AArch64ISelLowering.h:333
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:66
llvm::AArch64ISD::MRS
@ MRS
Definition: AArch64ISelLowering.h:289
llvm::AArch64::RP
@ RP
Definition: AArch64ISelLowering.h:467
llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO
@ GLD1S_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:358
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::AArch64ISD::ORRi
@ ORRi
Definition: AArch64ISelLowering.h:166
llvm::AArch64ISD::VSRI
@ VSRI
Definition: AArch64ISelLowering.h:201
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::AArch64ISD::LASTB
@ LASTB
Definition: AArch64ISelLowering.h:308
llvm::AArch64TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: AArch64ISelLowering.h:776
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1795
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::AArch64ISD::SRA_PRED
@ SRA_PRED
Definition: AArch64ISelLowering.h:97
llvm::AArch64ISD::UDIV_PRED
@ UDIV_PRED
Definition: AArch64ISelLowering.h:100
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AArch64TargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: AArch64ISelLowering.cpp:11264
SI
@ SI
Definition: SIInstrInfo.cpp:7411
llvm::AArch64ISD::MUL_PRED
@ MUL_PRED
Definition: AArch64ISelLowering.h:90
llvm::AArch64ISD::CMLEz
@ CMLEz
Definition: AArch64ISelLowering.h:217
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:725
llvm::AArch64ISD::FRSQRTE
@ FRSQRTE
Definition: AArch64ISelLowering.h:297
llvm::AArch64ISD::ADD_PRED
@ ADD_PRED
Definition: AArch64ISelLowering.h:80
llvm::AArch64ISD::MOVIedit
@ MOVIedit
Definition: AArch64ISelLowering.h:158
llvm::AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU
@ SINT_TO_FP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:120
llvm::AArch64TargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: AArch64ISelLowering.cpp:11846
llvm::AArch64TargetLowering::getTargetMMOFlags
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: AArch64ISelLowering.cpp:11270
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::AArch64ISD::ST1_PRED
@ ST1_PRED
Definition: AArch64ISelLowering.h:389
llvm::AArch64ISD::STZ2G
@ STZ2G
Definition: AArch64ISelLowering.h:436
llvm::AArch64TargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: AArch64ISelLowering.cpp:11742
llvm::AArch64ISD::UMINV_PRED
@ UMINV_PRED
Definition: AArch64ISelLowering.h:258
llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO
@ GLD1S_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:359
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:25
llvm::AArch64ISD::DUPLANE16
@ DUPLANE16
Definition: AArch64ISelLowering.h:151
llvm::AArch64ISD::SST1_PRED
@ SST1_PRED
Definition: AArch64ISelLowering.h:392
llvm::AArch64ISD::ZIP2
@ ZIP2
Definition: AArch64ISelLowering.h:177
llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO
@ GLDFF1S_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:378
llvm::AArch64ISD::FCMEQ
@ FCMEQ
Definition: AArch64ISelLowering.h:209
llvm::AArch64ISD::VSLI
@ VSLI
Definition: AArch64ISelLowering.h:200
llvm::AArch64ISD::FABS_MERGE_PASSTHRU
@ FABS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:106
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AArch64ISD::FP_ROUND_MERGE_PASSTHRU
@ FP_ROUND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:117
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::AArch64TargetLowering::hasPairedLoad
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
Definition: AArch64ISelLowering.cpp:11250
llvm::AArch64ISD::VSHL
@ VSHL
Definition: AArch64ISelLowering.h:188
llvm::AArch64ISD::SETCC_MERGE_ZERO
@ SETCC_MERGE_ZERO
Definition: AArch64ISelLowering.h:128
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AArch64ISD::UUNPKLO
@ UUNPKLO
Definition: AArch64ISelLowering.h:303
llvm::AArch64ISD::SBC
@ SBC
Definition: AArch64ISelLowering.h:77
llvm::AArch64TargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: AArch64ISelLowering.cpp:16800
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:201
llvm::AArch64ISD::SADDV_PRED
@ SADDV_PRED
Definition: AArch64ISelLowering.h:253
llvm::AArch64ISD::SHADD
@ SHADD
Definition: AArch64ISelLowering.h:231
llvm::AArch64ISD::UITOF
@ UITOF
Definition: AArch64ISelLowering.h:280
llvm::AArch64TargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: AArch64ISelLowering.cpp:16745
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::AArch64TargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: AArch64ISelLowering.cpp:11598
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AArch64TargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
Definition: AArch64ISelLowering.cpp:11307
llvm::AArch64ISD::UQSHL_I
@ UQSHL_I
Definition: AArch64ISelLowering.h:194
llvm::AArch64ISD::PTEST
@ PTEST
Definition: AArch64ISelLowering.h:320
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::AArch64ISD::FCVTZU_MERGE_PASSTHRU
@ FCVTZU_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:121
llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO
@ GLD1_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:354
llvm::APFloat
Definition: APFloat.h:701
llvm::AArch64TargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: AArch64ISelLowering.h:762
llvm::AArch64TargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: AArch64ISelLowering.cpp:17053
llvm::AArch64ISD::CMHI
@ CMHI
Definition: AArch64ISelLowering.h:207
llvm::AArch64ISD::ST3post
@ ST3post
Definition: AArch64ISelLowering.h:413
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MipsISD::Ext
@ Ext
Definition: MipsISelLowering.h:156
llvm::AArch64TargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: AArch64ISelLowering.cpp:16738
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::AArch64ISD::SDOT
@ SDOT
Definition: AArch64ISelLowering.h:244
llvm::AArch64TargetLowering::AArch64TargetLowering
AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)
Definition: AArch64ISelLowering.cpp:234
llvm::AArch64ISD::SST1_SXTW_SCALED_PRED
@ SST1_SXTW_SCALED_PRED
Definition: AArch64ISelLowering.h:397
llvm::AArch64ISD::FRECPE
@ FRECPE
Definition: AArch64ISelLowering.h:295
llvm::AArch64ISD::SABD
@ SABD
Definition: AArch64ISelLowering.h:240
llvm::AArch64ISD::INDEX_VECTOR
@ INDEX_VECTOR
Definition: AArch64ISelLowering.h:328
llvm::AArch64ISD::SQSHL_I
@ SQSHL_I
Definition: AArch64ISelLowering.h:193
llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU
@ ZERO_EXTEND_INREG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:124
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::AArch64ISD::SDIV_PRED
@ SDIV_PRED
Definition: AArch64ISelLowering.h:93
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::AArch64ISD::FMINNM_PRED
@ FMINNM_PRED
Definition: AArch64ISelLowering.h:85
llvm::AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: AArch64ISelLowering.cpp:16972
llvm::AArch64TargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: AArch64ISelLowering.cpp:16845
llvm::AArch64ISD::UHADD
@ UHADD
Definition: AArch64ISelLowering.h:232
llvm::AArch64::rmMask
@ rmMask
Definition: AArch64ISelLowering.h:470
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1241
llvm::AArch64::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: AArch64FastISel.cpp:5097
llvm::AArch64ISD::LD1RQ_MERGE_ZERO
@ LD1RQ_MERGE_ZERO
Definition: AArch64ISelLowering.h:339
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::AArch64TargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: AArch64ISelLowering.cpp:16998
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:60
llvm::AArch64ISD::SST1_IMM_PRED
@ SST1_IMM_PRED
Definition: AArch64ISelLowering.h:398
llvm::AArch64TargetLowering::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
Definition: AArch64ISelLowering.cpp:10972
llvm::AArch64TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
Definition: AArch64ISelLowering.cpp:1517
llvm::AArch64ISD::VASHR
@ VASHR
Definition: AArch64ISelLowering.h:190
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::AArch64TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: AArch64ISelLowering.cpp:4374
llvm::AArch64ISD::EXT
@ EXT
Definition: AArch64ISelLowering.h:185
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:4678
llvm::AArch64ISD::CSINV
@ CSINV
Definition: AArch64ISelLowering.h:69
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:2765
llvm::AArch64ISD::FADDV_PRED
@ FADDV_PRED
Definition: AArch64ISelLowering.h:313
llvm::AArch64ISD::CMGT
@ CMGT
Definition: AArch64ISelLowering.h:206
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:67
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:130
llvm::AArch64ISD::FADDA_PRED
@ FADDA_PRED
Definition: AArch64ISelLowering.h:312
llvm::AArch64ISD::BICi
@ BICi
Definition: AArch64ISelLowering.h:165
llvm::AArch64ISD::LD1RO_MERGE_ZERO
@ LD1RO_MERGE_ZERO
Definition: AArch64ISelLowering.h:340
llvm::AArch64TargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: AArch64ISelLowering.h:716
llvm::AArch64ISD::SMULL
@ SMULL
Definition: AArch64ISelLowering.h:291
llvm::AArch64TargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: AArch64ISelLowering.cpp:10229
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
llvm::AArch64ISD::FCMGE
@ FCMGE
Definition: AArch64ISelLowering.h:210
llvm::AArch64TargetLowering::getOptimalMemOpLLT
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
Definition: AArch64ISelLowering.cpp:11629
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::AArch64ISD::SQSHLU_I
@ SQSHLU_I
Definition: AArch64ISelLowering.h:195
llvm::AArch64TargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: AArch64ISelLowering.h:722
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::AArch64ISD::EXTR
@ EXTR
Definition: AArch64ISelLowering.h:146
llvm::AArch64TargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: AArch64ISelLowering.cpp:17012
llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO
@ GLDFF1_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:371
llvm::AArch64ISD::LDFF1S_MERGE_ZERO
@ LDFF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:338
llvm::AArch64ISD::SRSHR_I
@ SRSHR_I
Definition: AArch64ISelLowering.h:196
llvm::AArch64ISD::SMIN_PRED
@ SMIN_PRED
Definition: AArch64ISelLowering.h:96
llvm::AArch64ISD::FNEG_MERGE_PASSTHRU
@ FNEG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:110
llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO
@ GLD1_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:351
llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO
@ GLDFF1S_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:381
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::AArch64TargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
Definition: AArch64ISelLowering.cpp:11277
llvm::AArch64TargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AArch64ISelLowering.cpp:7611
llvm::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfo.h:162
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::AArch64TargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: AArch64ISelLowering.cpp:7618
llvm::AArch64::RN
@ RN
Definition: AArch64ISelLowering.h:466
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU
@ FSQRT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:115
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO
@ GLDFF1_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:369
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::AArch64ISD::BSP
@ BSP
Definition: AArch64ISelLowering.h:170
llvm::AArch64ISD::ADCS
@ ADCS
Definition: AArch64ISelLowering.h:133
llvm::AArch64ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: AArch64ISelLowering.h:50
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::AArch64ISD::LDNF1_MERGE_ZERO
@ LDNF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:335
llvm::AArch64TargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Definition: AArch64ISelLowering.cpp:4624
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:649
llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO
@ GLD1_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:352
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AArch64ISD::LD1LANEpost
@ LD1LANEpost
Definition: AArch64ISelLowering.h:425
llvm::AArch64TargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Definition: AArch64ISelLowering.cpp:17070
llvm::AArch64ISD::CLASTB_N
@ CLASTB_N
Definition: AArch64ISelLowering.h:306
llvm::AArch64TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: AArch64ISelLowering.h:699
llvm::AArch64ISD::ANDV_PRED
@ ANDV_PRED
Definition: AArch64ISelLowering.h:261
llvm::AArch64ISD::BITREVERSE_MERGE_PASSTHRU
@ BITREVERSE_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:323
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:468
llvm::AArch64ISD::LDNF1S_MERGE_ZERO
@ LDNF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:336
llvm::AArch64ISD::STRICT_FCMPE
@ STRICT_FCMPE
Definition: AArch64ISelLowering.h:406
llvm::ArrayRef< int >
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:149
llvm::AArch64ISD::LD4post
@ LD4post
Definition: AArch64ISelLowering.h:411
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1816
llvm::AArch64ISD::CMEQ
@ CMEQ
Definition: AArch64ISelLowering.h:204
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::AArch64TargetLowering::fallBackToDAGISel
bool fallBackToDAGISel(const Instruction &Inst) const override
Definition: AArch64ISelLowering.cpp:17115
llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO
@ GLDFF1_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:370
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AArch64ISD::DUPLANE8
@ DUPLANE8
Definition: AArch64ISelLowering.h:150
llvm::AArch64TargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: AArch64ISelLowering.h:684
llvm::AArch64TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: AArch64ISelLowering.cpp:1733
uint32_t
llvm::AArch64ISD::MOVI
@ MOVI
Definition: AArch64ISelLowering.h:156
llvm::AArch64ISD::ADDS
@ ADDS
Definition: AArch64ISelLowering.h:131
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:62
llvm::AArch64ISD::REV64
@ REV64
Definition: AArch64ISelLowering.h:184
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64ISD::CMGTz
@ CMGTz
Definition: AArch64ISelLowering.h:216
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::AArch64ISD::SSTNT1_PRED
@ SSTNT1_PRED
Definition: AArch64ISelLowering.h:401
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::AArch64ISD::LD1DUPpost
@ LD1DUPpost
Definition: AArch64ISelLowering.h:421
llvm::AArch64ISD::FMA_PRED
@ FMA_PRED
Definition: AArch64ISelLowering.h:83
llvm::AArch64TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AArch64ISelLowering.cpp:1794
llvm::AArch64ISD::UABD
@ UABD
Definition: AArch64ISelLowering.h:239
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64ISD::SVE_LD2_MERGE_ZERO
@ SVE_LD2_MERGE_ZERO
Definition: AArch64ISelLowering.h:343
llvm::AArch64ISD::CBNZ
@ CBNZ
Definition: AArch64ISelLowering.h:268
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::AArch64ISD::ORV_PRED
@ ORV_PRED
Definition: AArch64ISelLowering.h:259
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
llvm::AArch64ISD::UZP2
@ UZP2
Definition: AArch64ISelLowering.h:179
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64TargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: AArch64ISelLowering.cpp:11823
llvm::AArch64ISD::PTRUE
@ PTRUE
Definition: AArch64ISelLowering.h:321
llvm::AArch64ISD::ANDS
@ ANDS
Definition: AArch64ISelLowering.h:135
llvm::AArch64ISD::FMAXV_PRED
@ FMAXV_PRED
Definition: AArch64ISelLowering.h:314
llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU
@ FROUNDEVEN_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:114
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO
@ GLD1S_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:362
llvm::AArch64ISD::FMAXNM_PRED
@ FMAXNM_PRED
Definition: AArch64ISelLowering.h:84
llvm::AArch64TargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: AArch64ISelLowering.cpp:11661
llvm::AArch64ISD::THREAD_POINTER
@ THREAD_POINTER
Definition: AArch64ISelLowering.h:75
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1692
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
llvm::AArch64::RZ
@ RZ
Definition: AArch64ISelLowering.h:469
llvm::AArch64ISD::FRSQRTS
@ FRSQRTS
Definition: AArch64ISelLowering.h:298
llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition: AArch64ISelLowering.h:743
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:247
uint16_t
CallingConvLower.h
llvm::AArch64TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
Definition: AArch64ISelLowering.cpp:10999
llvm::AArch64ISD::CSNEG
@ CSNEG
Definition: AArch64ISelLowering.h:70
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::AArch64ISD::STZG
@ STZG
Definition: AArch64ISelLowering.h:434
llvm::AArch64ISD::UDOT
@ UDOT
Definition: AArch64ISelLowering.h:243
llvm::AArch64TargetLowering::getVaListSizeInBits
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
Definition: AArch64ISelLowering.cpp:17075
llvm::AArch64ISD::FMOV
@ FMOV
Definition: AArch64ISelLowering.h:160
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4112
llvm::AArch64ISD::UADDV_PRED
@ UADDV_PRED
Definition: AArch64ISelLowering.h:254
llvm::AArch64TargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: AArch64ISelLowering.cpp:16716
llvm::AArch64TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AArch64ISelLowering.cpp:2149
llvm::AArch64ISD::NEG_MERGE_PASSTHRU
@ NEG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:126
llvm::AArch64ISD::SRHADD
@ SRHADD
Definition: AArch64ISelLowering.h:235
llvm::AArch64ISD::CSINC
@ CSINC
Definition: AArch64ISelLowering.h:71
llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO
@ GLDFF1S_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:380
llvm::AArch64ISD::TBL
@ TBL
Definition: AArch64ISelLowering.h:309
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::AArch64TargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: AArch64ISelLowering.cpp:17006
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:203
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:207
llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO
@ GLD1S_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:360
llvm::AArch64ISD::SUB_PRED
@ SUB_PRED
Definition: AArch64ISelLowering.h:99
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::AArch64TargetLowering::EmitF128CSEL
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2082
llvm::AArch64ISD::SVE_LD3_MERGE_ZERO
@ SVE_LD3_MERGE_ZERO
Definition: AArch64ISelLowering.h:344
llvm::AArch64ISD::FP_EXTEND_MERGE_PASSTHRU
@ FP_EXTEND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:118
llvm::AArch64ISD::GLDFF1S_MERGE_ZERO
@ GLDFF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:375
llvm::AArch64ISD::ADRP
@ ADRP
Definition: AArch64ISelLowering.h:61
llvm::AArch64ISD::FCMEQz
@ FCMEQz
Definition: AArch64ISelLowering.h:219
llvm::AArch64ISD::DUPLANE64
@ DUPLANE64
Definition: AArch64ISelLowering.h:153
llvm::AArch64ISD::ST2G
@ ST2G
Definition: AArch64ISelLowering.h:435
llvm::AArch64ISD::SST1_SXTW_PRED
@ SST1_SXTW_PRED
Definition: AArch64ISelLowering.h:395
llvm::AArch64ISD::FSUB_PRED
@ FSUB_PRED
Definition: AArch64ISelLowering.h:89
llvm::AArch64TargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: AArch64ISelLowering.h:712
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:4711
llvm::AArch64TargetLowering::getRedZoneSize
unsigned getRedZoneSize(const Function &F) const
Definition: AArch64ISelLowering.h:817
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:1986
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::AArch64ISD::REINTERPRET_CAST
@ REINTERPRET_CAST
Definition: AArch64ISelLowering.h:331
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU
@ FTRUNC_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:116
llvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: AArch64ISelLowering.cpp:16986
llvm::AArch64ISD::REV16
@ REV16
Definition: AArch64ISelLowering.h:182
llvm::AArch64::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: AArch64ISelLowering.h:474
llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO
@ GLD1_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:350
llvm::AArch64ISD::UADDV
@ UADDV
Definition: AArch64ISelLowering.h:228
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1247
llvm::AArch64ISD::UMAXV_PRED
@ UMAXV_PRED
Definition: AArch64ISelLowering.h:256
N
#define N
llvm::AArch64ISD::ABS_MERGE_PASSTHRU
@ ABS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:125
llvm::AArch64ISD::URHADD
@ URHADD
Definition: AArch64ISelLowering.h:236
llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO
@ GLD1_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:349
llvm::AArch64ISD::ST2LANEpost
@ ST2LANEpost
Definition: AArch64ISelLowering.h:429
llvm::AArch64ISD::UMAXV
@ UMAXV
Definition: AArch64ISelLowering.h:251
llvm::AArch64TargetLowering::getIRStackGuard
Value * getIRStackGuard(IRBuilder<> &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
Definition: AArch64ISelLowering.cpp:16908
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4204
llvm::AArch64ISD::GLD1S_MERGE_ZERO
@ GLD1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:357
llvm::AArch64ISD::TBZ
@ TBZ
Definition: AArch64ISelLowering.h:269
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::AArch64ISD::FCCMP
@ FCCMP
Definition: AArch64ISelLowering.h:140
llvm::AArch64TargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: AArch64ISelLowering.cpp:10790
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
RegName
#define RegName(no)
llvm::AArch64TargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: AArch64ISelLowering.cpp:11160
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:482
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override
Definition: AArch64ISelLowering.cpp:16839
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU
@ BSWAP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:324
llvm::AArch64TargetLowering::shouldExpandAtomicStoreInIR
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
Definition: AArch64ISelLowering.cpp:16729
llvm::AArch64ISD::INSR
@ INSR
Definition: AArch64ISelLowering.h:319
llvm::AArch64ISD::LD2LANEpost
@ LD2LANEpost
Definition: AArch64ISelLowering.h:426
llvm::AArch64ISD::LASTA
@ LASTA
Definition: AArch64ISelLowering.h:307
llvm::AArch64TargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: AArch64ISelLowering.cpp:17065
llvm::AArch64ISD::ST4post
@ ST4post
Definition: AArch64ISelLowering.h:414
llvm::AArch64ISD::ST1x3post
@ ST1x3post
Definition: AArch64ISelLowering.h:419
llvm::AArch64ISD::WrapperLarge
@ WrapperLarge
Definition: AArch64ISelLowering.h:51
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AArch64ISelLowering.cpp:11684
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:480
llvm::AArch64TargetLowering::getPointerTy
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: AArch64ISelLowering.h:498
llvm::AArch64ISD::LD4DUPpost
@ LD4DUPpost
Definition: AArch64ISelLowering.h:424
MachineFunction.h
llvm::AArch64ISD::BIT
@ BIT
Definition: AArch64ISelLowering.h:264
llvm::AArch64ISD::BRCOND
@ BRCOND
Definition: AArch64ISelLowering.h:67
llvm::AArch64ISD::SUNPKHI
@ SUNPKHI
Definition: AArch64ISelLowering.h:300
llvm::AArch64TargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: AArch64ISelLowering.cpp:16923
llvm::AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU
@ UINT_TO_FP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:119
llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU
@ FNEARBYINT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:109
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO
@ GLDFF1_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:367
llvm::AArch64TargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: AArch64ISelLowering.cpp:1666
llvm::AArch64ISD::SMINV
@ SMINV
Definition: AArch64ISelLowering.h:248
llvm::AArch64TargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: AArch64ISelLowering.h:727
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:52
llvm::AArch64ISD::FADD_PRED
@ FADD_PRED
Definition: AArch64ISelLowering.h:81
llvm::AArch64ISD::ST2post
@ ST2post
Definition: AArch64ISelLowering.h:412
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
llvm::AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Definition: AArch64ISelLowering.cpp:16881
llvm::AArch64TargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: AArch64ISelLowering.h:692
llvm::AArch64ISD::LD1S_MERGE_ZERO
@ LD1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:334
llvm::AArch64ISD::STP
@ STP
Definition: AArch64ISelLowering.h:439
llvm::AArch64ISD::FMIN_PRED
@ FMIN_PRED
Definition: AArch64ISelLowering.h:87
llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO
@ GLDNT1_INDEX_MERGE_ZERO
Definition: AArch64ISelLowering.h:385
llvm::AArch64ISD::DUPLANE32
@ DUPLANE32
Definition: AArch64ISelLowering.h:152
llvm::AArch64ISD::FDIV_PRED
@ FDIV_PRED
Definition: AArch64ISelLowering.h:82
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1108
llvm::AArch64ISD::FROUND_MERGE_PASSTHRU
@ FROUND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:113
llvm::AArch64::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
Definition: AArch64ISelLowering.h:465
llvm::AArch64ISD::NVCAST
@ NVCAST
Natural vector cast.
Definition: AArch64ISelLowering.h:287
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::AArch64ISD::SUBS
@ SUBS
Definition: AArch64ISelLowering.h:132