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AArch64ISelLowering.h
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1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 
17 #include "AArch64.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Instruction.h"
25 
26 namespace llvm {
27 
28 namespace AArch64ISD {
29 
30 // For predicated nodes where the result is a vector, the operation is
31 // controlled by a governing predicate and the inactive lanes are explicitly
32 // defined with a value, please stick the following naming convention:
33 //
34 // _MERGE_OP<n> The result value is a vector with inactive lanes equal
35 // to source operand OP<n>.
36 //
37 // _MERGE_ZERO The result value is a vector with inactive lanes
38 // actively zeroed.
39 //
40 // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
41 // to the last source operand which only purpose is being
42 // a passthru value.
43 //
44 // For other cases where no explicit action is needed to set the inactive lanes,
45 // or when the result is not a vector and it is needed or helpful to
46 // distinguish a node from similar unpredicated nodes, use:
47 //
48 // _PRED
49 //
50 enum NodeType : unsigned {
52  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
53  CALL, // Function call.
54 
55  // Pseudo for a OBJC call that gets emitted together with a special `mov
56  // x29, x29` marker instruction.
58 
59  CALL_BTI, // Function call followed by a BTI instruction.
60 
61  // Essentially like a normal COPY that works on GPRs, but cannot be
62  // rematerialised by passes like the simple register coalescer. It's
63  // required for SME when lowering calls because we cannot allow frame
64  // index calculations using addvl to slip in between the smstart/smstop
65  // and the bl instruction. The scalable vector length may change across
66  // the smstart/smstop boundary.
71 
72  // Produces the full sequence of instructions for getting the thread pointer
73  // offset of a variable into X0, using the TLSDesc model.
75  ADRP, // Page address of a TargetGlobalAddress operand.
76  ADR, // ADR
77  ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
78  LOADgot, // Load from automatically generated descriptor (e.g. Global
79  // Offset Table, TLS record).
80  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
81  BRCOND, // Conditional branch instruction; "b.cond".
83  CSINV, // Conditional select invert.
84  CSNEG, // Conditional select negate.
85  CSINC, // Conditional select increment.
86 
87  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
88  // ELF.
90  ADC,
91  SBC, // adc, sbc instructions
92 
93  // Predicated instructions where inactive lanes produce undefined results.
117 
118  // Unpredicated vector instructions
120 
122 
123  // Predicated instructions with the result of inactive lanes provided by the
124  // last operand.
146 
148 
149  // Arithmetic instructions which write flags.
155 
156  // Conditional compares. Operands: left,right,falsecc,cc,flags
160 
161  // Floating point comparison
163 
164  // Scalar extract
166 
167  // Scalar-to-vector duplication
174 
175  // Vector immedate moves
183 
184  // Vector immediate ops
187 
188  // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
189  // element must be identical.
191 
192  // Vector shuffles
204 
205  // Vector shift by scalar
209 
210  // Vector shift by scalar (again)
216 
217  // Vector shift by constant and insert
220 
221  // Vector comparisons
230 
231  // Vector zero comparisons
242 
243  // Vector across-lanes addition
244  // Only the lower result lane is defined.
247 
248  // Add Pairwise of two vectors
250  // Add Long Pairwise
253 
254  // udot/sdot instructions
257 
258  // Vector across-lanes min/max
259  // Only the lower result lane is defined.
264 
274 
275  // Vector bitwise insertion
277 
278  // Compare-and-branch
283 
284  // Tail calls
286 
287  // Custom prefetch handling
289 
290  // {s|u}int to FP within a FP register.
293 
294  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
295  /// world w.r.t vectors; which causes additional REV instructions to be
296  /// generated to compensate for the byte-swapping. But sometimes we do
297  /// need to re-interpret the data in SIMD vector registers in big-endian
298  /// mode without emitting such REV instructions.
300 
301  MRS, // MRS, also sets the flags via a glue.
302 
305 
307 
308  // Reciprocal estimates and steps.
313 
318 
324 
325  // Floating-point reductions.
332 
337 
346 
347  // Cast between vectors of the same element type but differ in length.
349 
350  // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
353 
362 
363  // Structured loads.
367 
368  // Unsigned gather loads.
376 
377  // Signed gather loads
385 
386  // Unsigned gather loads.
394 
395  // Signed gather loads.
403 
404  // Non-temporal gather loads
408 
409  // Contiguous masked store.
411 
412  // Scatter store
420 
421  // Non-temporal scatter store
424 
425  // SME
428 
429  // Asserts that a function argument (i32) is zero-extended to i8 by
430  // the caller
432 
433  // Strict (exception-raising) floating point comparison
436 
437  // NEON Load/Store with post-increment base updates
461 
466 
471 
472  // Memory Operations
477 };
478 
479 } // end namespace AArch64ISD
480 
481 namespace AArch64 {
482 /// Possible values of current rounding mode, which is specified in bits
483 /// 23:22 of FPCR.
484 enum Rounding {
485  RN = 0, // Round to Nearest
486  RP = 1, // Round towards Plus infinity
487  RM = 2, // Round towards Minus infinity
488  RZ = 3, // Round towards Zero
489  rmMask = 3 // Bit mask selecting rounding mode
490 };
491 
492 // Bit position of rounding mode bits in FPCR.
493 const unsigned RoundingBitsPos = 22;
494 } // namespace AArch64
495 
496 class AArch64Subtarget;
497 
499 public:
500  explicit AArch64TargetLowering(const TargetMachine &TM,
501  const AArch64Subtarget &STI);
502 
503  /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
504  /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
506  SDValue N1) const override;
507 
508  /// Selects the correct CCAssignFn for a given CallingConvention value.
509  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
510 
511  /// Selects the correct CCAssignFn for a given CallingConvention value.
513 
514  /// Determine which of the bits specified in Mask are known to be either zero
515  /// or one and return them in the KnownZero/KnownOne bitsets.
517  const APInt &DemandedElts,
518  const SelectionDAG &DAG,
519  unsigned Depth = 0) const override;
520 
521  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
522  // Returning i64 unconditionally here (i.e. even for ILP32) means that the
523  // *DAG* representation of pointers will always be 64-bits. They will be
524  // truncated and extended when transferred to memory, but the 64-bit DAG
525  // allows us to use AArch64's addressing modes much more easily.
526  return MVT::getIntegerVT(64);
527  }
528 
530  const APInt &DemandedElts,
531  TargetLoweringOpt &TLO) const override;
532 
533  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
534 
535  /// Returns true if the target allows unaligned memory accesses of the
536  /// specified type.
538  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
540  unsigned *Fast = nullptr) const override;
541  /// LLT variant.
542  bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
543  Align Alignment,
545  unsigned *Fast = nullptr) const override;
546 
547  /// Provide custom lowering hooks for some operations.
548  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
549 
550  const char *getTargetNodeName(unsigned Opcode) const override;
551 
552  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
553 
554  /// This method returns a target specific FastISel object, or null if the
555  /// target does not support "fast" ISel.
557  const TargetLibraryInfo *libInfo) const override;
558 
559  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
560 
561  bool isFPImmLegal(const APFloat &Imm, EVT VT,
562  bool ForCodeSize) const override;
563 
564  /// Return true if the given shuffle mask can be codegen'd directly, or if it
565  /// should be stack expanded.
566  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
567 
568  /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
569  /// shuffle mask can be codegen'd directly.
570  bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
571 
572  /// Return the ISD::SETCC ValueType.
574  EVT VT) const override;
575 
577 
579  MachineBasicBlock *BB) const;
580 
582  MachineBasicBlock *BB) const;
583 
584  MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
585  MachineInstr &MI,
586  MachineBasicBlock *BB) const;
588  MachineBasicBlock *EmitMopa(unsigned Opc, unsigned BaseReg, MachineInstr &MI,
589  MachineBasicBlock *BB) const;
590  MachineBasicBlock *EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg,
591  MachineInstr &MI,
592  MachineBasicBlock *BB) const;
594  MachineBasicBlock *EmitAddVectorToTile(unsigned Opc, unsigned BaseReg,
595  MachineInstr &MI,
596  MachineBasicBlock *BB) const;
597 
600  MachineBasicBlock *MBB) const override;
601 
602  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
603  MachineFunction &MF,
604  unsigned Intrinsic) const override;
605 
607  EVT NewVT) const override;
608 
609  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
610  bool isTruncateFree(EVT VT1, EVT VT2) const override;
611 
612  bool isProfitableToHoist(Instruction *I) const override;
613 
614  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
615  bool isZExtFree(EVT VT1, EVT VT2) const override;
616  bool isZExtFree(SDValue Val, EVT VT2) const override;
617 
619  SmallVectorImpl<Use *> &Ops) const override;
620 
622  Loop *L) const override;
623 
624  bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
625 
626  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
627 
630  ArrayRef<unsigned> Indices,
631  unsigned Factor) const override;
633  unsigned Factor) const override;
634 
635  bool isLegalAddImmediate(int64_t) const override;
636  bool isLegalICmpImmediate(int64_t) const override;
637 
639  SDValue ConstNode) const override;
640 
641  bool shouldConsiderGEPOffsetSplit() const override;
642 
644  const AttributeList &FuncAttributes) const override;
645 
647  const AttributeList &FuncAttributes) const override;
648 
649  /// Return true if the addressing mode represented by AM is legal for this
650  /// target, for a load/store of the specified type.
651  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
652  unsigned AS,
653  Instruction *I = nullptr) const override;
654 
655  /// Return true if an FMA operation is faster than a pair of fmul and fadd
656  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
657  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
659  EVT VT) const override;
660  bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
661 
663  CodeGenOpt::Level OptLevel) const override;
664 
665  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
666 
667  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
669  CombineLevel Level) const override;
670 
671  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
672  bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
673 
674  /// Return true if it is profitable to fold a pair of shifts into a mask.
676  CombineLevel Level) const override;
677 
678  /// Returns true if it is beneficial to convert a load of a constant
679  /// to just the constant itself.
681  Type *Ty) const override;
682 
683  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
684  /// with this index.
685  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
686  unsigned Index) const override;
687 
688  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
689  bool MathUsed) const override {
690  // Using overflow ops for overflow checks only should beneficial on
691  // AArch64.
692  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
693  }
694 
696  AtomicOrdering Ord) const override;
698  AtomicOrdering Ord) const override;
699 
701 
702  bool isOpSuitableForLDPSTP(const Instruction *I) const;
703  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
704 
706  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
708  shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
710  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
711 
714 
715  bool useLoadStackGuardNode() const override;
717  getPreferredVectorAction(MVT VT) const override;
718 
719  /// If the target has a standard location for the stack protector cookie,
720  /// returns the address of that location. Otherwise, returns nullptr.
721  Value *getIRStackGuard(IRBuilderBase &IRB) const override;
722 
723  void insertSSPDeclarations(Module &M) const override;
724  Value *getSDagStackGuard(const Module &M) const override;
725  Function *getSSPStackGuardCheck(const Module &M) const override;
726 
727  /// If the target has a standard location for the unsafe stack pointer,
728  /// returns the address of that location. Otherwise, returns nullptr.
729  Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
730 
731  /// If a physical register, this returns the register that receives the
732  /// exception address on entry to an EH pad.
733  Register
734  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
735  // FIXME: This is a guess. Has this been defined yet?
736  return AArch64::X0;
737  }
738 
739  /// If a physical register, this returns the register that receives the
740  /// exception typeid on entry to a landing pad.
741  Register
742  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
743  // FIXME: This is a guess. Has this been defined yet?
744  return AArch64::X1;
745  }
746 
747  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
748 
749  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
750  const MachineFunction &MF) const override {
751  // Do not merge to float value size (128 bytes) if no implicit
752  // float attribute is set.
753 
754  bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
755 
756  if (NoFloat)
757  return (MemVT.getSizeInBits() <= 64);
758  return true;
759  }
760 
761  bool isCheapToSpeculateCttz(Type *) const override {
762  return true;
763  }
764 
765  bool isCheapToSpeculateCtlz(Type *) const override {
766  return true;
767  }
768 
769  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
770 
771  bool hasAndNotCompare(SDValue V) const override {
772  // We can use bics for any scalar.
773  return V.getValueType().isScalarInteger();
774  }
775 
776  bool hasAndNot(SDValue Y) const override {
777  EVT VT = Y.getValueType();
778 
779  if (!VT.isVector())
780  return hasAndNotCompare(Y);
781 
782  TypeSize TS = VT.getSizeInBits();
783  // TODO: We should be able to use bic/bif too for SVE.
784  return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
785  }
786 
789  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
790  SelectionDAG &DAG) const override;
791 
792  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
793 
795  unsigned KeptBits) const override {
796  // For vectors, we don't have a preference..
797  if (XVT.isVector())
798  return false;
799 
800  auto VTIsOk = [](EVT VT) -> bool {
801  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
802  VT == MVT::i64;
803  };
804 
805  // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
806  // XVT will be larger than KeptBitsVT.
807  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
808  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
809  }
810 
811  bool preferIncOfAddToSubOfNot(EVT VT) const override;
812 
813  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
814 
815  bool isComplexDeinterleavingSupported() const override;
817  ComplexDeinterleavingOperation Operation, Type *Ty) const override;
818 
821  ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
822  Value *Accumulator = nullptr) const override;
823 
824  bool hasBitPreservingFPLogic(EVT VT) const override {
825  // FIXME: Is this always true? It should be true for vectors at least.
826  return VT == MVT::f32 || VT == MVT::f64;
827  }
828 
829  bool supportSplitCSR(MachineFunction *MF) const override {
831  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
832  }
833  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
835  MachineBasicBlock *Entry,
836  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
837 
838  bool supportSwiftError() const override {
839  return true;
840  }
841 
842  bool supportKCFIBundles() const override { return true; }
843 
844  /// Enable aggressive FMA fusion on targets that want it.
845  bool enableAggressiveFMAFusion(EVT VT) const override;
846 
847  /// Returns the size of the platform's va_list object.
848  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
849 
850  /// Returns true if \p VecTy is a legal interleaved access type. This
851  /// function checks the vector element type and the overall width of the
852  /// vector.
854  bool &UseScalable) const;
855 
856  /// Returns the number of interleaved accesses that will be generated when
857  /// lowering accesses of the given type.
858  unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
859  bool UseScalable) const;
860 
862  const Instruction &I) const override;
863 
865  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
866  const DataLayout &DL) const override;
867 
868  /// Used for exception handling on Win64.
869  bool needsFixedCatchObjects() const override;
870 
871  bool fallBackToDAGISel(const Instruction &Inst) const override;
872 
873  /// SVE code generation for fixed length vectors does not custom lower
874  /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
875  /// merge. However, merging them creates a BUILD_VECTOR that is just as
876  /// illegal as the original, thus leading to an infinite legalisation loop.
877  /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
878  /// vector types this override can be removed.
879  bool mergeStoresAfterLegalization(EVT VT) const override;
880 
881  // If the platform/function should have a redzone, return the size in bytes.
882  unsigned getRedZoneSize(const Function &F) const {
883  if (F.hasFnAttribute(Attribute::NoRedZone))
884  return 0;
885  return 128;
886  }
887 
888  bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
890 
892  bool AllowUnknown = false) const override;
893 
894  bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
895 
896  /// If a change in streaming mode is required on entry to/return from a
897  /// function call it emits and returns the corresponding SMSTART or SMSTOP node.
898  /// \p Entry tells whether this is before/after the Call, which is necessary
899  /// because PSTATE.SM is only queried once.
900  SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable,
901  SDValue Chain, SDValue InFlag,
902  SDValue PStateSM, bool Entry) const;
903 
904  // Normally SVE is only used for byte size vectors that do not fit within a
905  // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
906  // used for 64bit and 128bit vectors as well.
907  bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
908 
909 private:
910  /// Keep a pointer to the AArch64Subtarget around so that we can
911  /// make the right decision when generating code for different targets.
912  const AArch64Subtarget *Subtarget;
913 
914  bool isExtFreeImpl(const Instruction *Ext) const override;
915 
916  void addTypeForNEON(MVT VT);
917  void addTypeForStreamingSVE(MVT VT);
918  void addTypeForFixedLengthSVE(MVT VT);
919  void addDRTypeForNEON(MVT VT);
920  void addQRTypeForNEON(MVT VT);
921 
922  unsigned allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL,
923  SelectionDAG &DAG) const;
924 
925  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
926  bool isVarArg,
928  const SDLoc &DL, SelectionDAG &DAG,
929  SmallVectorImpl<SDValue> &InVals) const override;
930 
931  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
932  SmallVectorImpl<SDValue> &InVals) const override;
933 
934  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
935  CallingConv::ID CallConv, bool isVarArg,
936  const SmallVectorImpl<CCValAssign> &RVLocs,
937  const SDLoc &DL, SelectionDAG &DAG,
938  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
939  SDValue ThisVal) const;
940 
941  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
942  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
943  SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
944  SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
945 
946  SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
947  SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
948 
949  SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
950 
951  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
952  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
953 
954  bool
955  isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
956 
957  /// Finds the incoming stack arguments which overlap the given fixed stack
958  /// object and incorporates their load into the current chain. This prevents
959  /// an upcoming store from clobbering the stack argument before it's used.
960  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
961  MachineFrameInfo &MFI, int ClobberedFI) const;
962 
963  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
964 
965  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
966  SDValue &Chain) const;
967 
968  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
969  bool isVarArg,
971  LLVMContext &Context) const override;
972 
973  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
975  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
976  SelectionDAG &DAG) const override;
977 
978  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
979  unsigned Flag) const;
980  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
981  unsigned Flag) const;
982  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
983  unsigned Flag) const;
984  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
985  unsigned Flag) const;
986  template <class NodeTy>
987  SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
988  template <class NodeTy>
989  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
990  template <class NodeTy>
991  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
992  template <class NodeTy>
993  SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
994  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
995  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
996  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
997  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
998  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
999  SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
1000  const SDLoc &DL, SelectionDAG &DAG) const;
1001  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
1002  SelectionDAG &DAG) const;
1003  SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1004  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1005  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1006  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
1007  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1008  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1009  SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
1010  SDValue TVal, SDValue FVal, const SDLoc &dl,
1011  SelectionDAG &DAG) const;
1012  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1013  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
1014  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1015  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1016  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
1017  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
1018  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
1019  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1020  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1021  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1022  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1023  SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
1024  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1025  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1026  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1027  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1028  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1029  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1030  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1031  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1032  SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1033  SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
1034  SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
1035  unsigned NewOp) const;
1036  SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
1037  SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
1038  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1039  SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1040  SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1041  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1042  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
1043  SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
1044  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
1045  SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const;
1046  SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
1047  SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
1048  SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
1049  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
1050  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1051  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1052  SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1053  SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1054  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1055  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1056  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1057  SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1058  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
1059  SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1060  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
1061  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
1062  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1063  SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
1064  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1065  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
1066  SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
1067  SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
1068  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1069  SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
1070  SDValue &Size,
1071  SelectionDAG &DAG) const;
1072 
1073  SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
1074  SelectionDAG &DAG) const;
1075  SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
1076  SelectionDAG &DAG) const;
1077  SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1078  SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1079  SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1080  SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1081  SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
1082  SelectionDAG &DAG) const;
1083  SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
1084  SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
1085  SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
1086  SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1087  SelectionDAG &DAG) const;
1088  SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
1089  SelectionDAG &DAG) const;
1090  SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
1091  SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
1092  SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
1093  SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
1094  SelectionDAG &DAG) const;
1095  SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
1096  SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
1097  SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
1098  SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
1099  SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
1100  SelectionDAG &DAG) const;
1101 
1102  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1103  SmallVectorImpl<SDNode *> &Created) const override;
1104  SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1105  SmallVectorImpl<SDNode *> &Created) const override;
1106  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1107  int &ExtraSteps, bool &UseOneConst,
1108  bool Reciprocal) const override;
1109  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1110  int &ExtraSteps) const override;
1111  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1112  const DenormalMode &Mode) const override;
1113  SDValue getSqrtResultForDenormInput(SDValue Operand,
1114  SelectionDAG &DAG) const override;
1115  unsigned combineRepeatedFPDivisors() const override;
1116 
1117  ConstraintType getConstraintType(StringRef Constraint) const override;
1118  Register getRegisterByName(const char* RegName, LLT VT,
1119  const MachineFunction &MF) const override;
1120 
1121  /// Examine constraint string and operand type and determine a weight value.
1122  /// The operand object must already have been set up with the operand type.
1124  getSingleConstraintMatchWeight(AsmOperandInfo &info,
1125  const char *constraint) const override;
1126 
1127  std::pair<unsigned, const TargetRegisterClass *>
1128  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1129  StringRef Constraint, MVT VT) const override;
1130 
1131  const char *LowerXConstraint(EVT ConstraintVT) const override;
1132 
1133  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1134  std::vector<SDValue> &Ops,
1135  SelectionDAG &DAG) const override;
1136 
1137  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1138  if (ConstraintCode == "Q")
1139  return InlineAsm::Constraint_Q;
1140  // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1141  // followed by llvm_unreachable so we'll leave them unimplemented in
1142  // the backend for now.
1143  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1144  }
1145 
1146  bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1147  bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
1148  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1149  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1150  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1151  bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
1152  ISD::MemIndexedMode &AM, bool &IsInc,
1153  SelectionDAG &DAG) const;
1154  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1155  ISD::MemIndexedMode &AM,
1156  SelectionDAG &DAG) const override;
1157  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1158  SDValue &Offset, ISD::MemIndexedMode &AM,
1159  SelectionDAG &DAG) const override;
1160 
1161  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1162  SelectionDAG &DAG) const override;
1163  void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1164  SelectionDAG &DAG) const;
1165  void ReplaceExtractSubVectorResults(SDNode *N,
1166  SmallVectorImpl<SDValue> &Results,
1167  SelectionDAG &DAG) const;
1168 
1169  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1170 
1171  void finalizeLowering(MachineFunction &MF) const override;
1172 
1173  bool shouldLocalize(const MachineInstr &MI,
1174  const TargetTransformInfo *TTI) const override;
1175 
1176  bool SimplifyDemandedBitsForTargetNode(SDValue Op,
1177  const APInt &OriginalDemandedBits,
1178  const APInt &OriginalDemandedElts,
1179  KnownBits &Known,
1180  TargetLoweringOpt &TLO,
1181  unsigned Depth) const override;
1182 
1183  bool isTargetCanonicalConstantNode(SDValue Op) const override;
1184 
1185  // With the exception of data-predicate transitions, no instructions are
1186  // required to cast between legal scalable vector types. However:
1187  // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1188  // is not universally useable.
1189  // 2. Most unpacked integer types are not legal and thus integer extends
1190  // cannot be used to convert between unpacked and packed types.
1191  // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1192  // to transition between unpacked and packed types of the same element type,
1193  // with BITCAST used otherwise.
1194  // This function does not handle predicate bitcasts.
1195  SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1196 
1197  // Returns the runtime value for PSTATE.SM. When the function is streaming-
1198  // compatible, this generates a call to __arm_sme_state.
1199  SDValue getPStateSM(SelectionDAG &DAG, SDValue Chain, SMEAttrs Attrs,
1200  SDLoc DL, EVT VT) const;
1201 
1202  bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
1203  LLT Ty2) const override;
1204 };
1205 
1206 namespace AArch64 {
1207 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1208  const TargetLibraryInfo *libInfo);
1209 } // end namespace AArch64
1210 
1211 } // end namespace llvm
1212 
1213 #endif
llvm::AArch64ISD::LD1x2post
@ LD1x2post
Definition: AArch64ISelLowering.h:444
llvm::AArch64ISD::MOPS_MEMSET_TAGGING
@ MOPS_MEMSET_TAGGING
Definition: AArch64ISelLowering.h:474
llvm::AArch64ISD::EORV_PRED
@ EORV_PRED
Definition: AArch64ISelLowering.h:272
llvm::AArch64ISD::NodeType
NodeType
Definition: AArch64ISelLowering.h:50
llvm::AArch64ISD::LD2DUPpost
@ LD2DUPpost
Definition: AArch64ISelLowering.h:451
llvm::AArch64ISD::SVE_LD4_MERGE_ZERO
@ SVE_LD4_MERGE_ZERO
Definition: AArch64ISelLowering.h:366
llvm::AArch64ISD::UMULL
@ UMULL
Definition: AArch64ISelLowering.h:304
llvm::AArch64ISD::LOADgot
@ LOADgot
Definition: AArch64ISelLowering.h:78
llvm::AArch64ISD::LD3post
@ LD3post
Definition: AArch64ISelLowering.h:439
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm::AArch64ISD::UUNPKHI
@ UUNPKHI
Definition: AArch64ISelLowering.h:316
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::AArch64ISD::VLSHR
@ VLSHR
Definition: AArch64ISelLowering.h:207
llvm::AArch64ISD::SSTNT1_INDEX_PRED
@ SSTNT1_INDEX_PRED
Definition: AArch64ISelLowering.h:423
llvm::AArch64ISD::ST1x4post
@ ST1x4post
Definition: AArch64ISelLowering.h:449
llvm::AArch64ISD::UMINV
@ UMINV
Definition: AArch64ISelLowering.h:261
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1373
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::AArch64TargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: AArch64ISelLowering.cpp:21997
llvm::AArch64ISD::CLASTA_N
@ CLASTA_N
Definition: AArch64ISelLowering.h:319
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64TargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: AArch64ISelLowering.cpp:21707
llvm::AArch64TargetLowering::generateFMAsInMachineCombiner
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOpt::Level OptLevel) const override
Definition: AArch64ISelLowering.cpp:14584
llvm::AArch64ISD::ADDP
@ ADDP
Definition: AArch64ISelLowering.h:249
AArch64.h
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::AArch64TargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: AArch64ISelLowering.cpp:22004
llvm::AArch64TargetLowering::EmitMopa
MachineBasicBlock * EmitMopa(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2582
llvm::AArch64TargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: AArch64ISelLowering.h:688
llvm::AArch64ISD::FMINV_PRED
@ FMINV_PRED
Definition: AArch64ISelLowering.h:330
llvm::AArch64ISD::SITOF
@ SITOF
Definition: AArch64ISelLowering.h:291
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AArch64TargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: AArch64ISelLowering.cpp:1957
llvm::AArch64TargetLowering::EmitInsertVectorToTile
MachineBasicBlock * EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2599
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4569
llvm::AArch64ISD::FCMGEz
@ FCMGEz
Definition: AArch64ISelLowering.h:238
llvm::AArch64TargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition: AArch64ISelLowering.cpp:2168
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::AArch64ISD::SMAX_PRED
@ SMAX_PRED
Definition: AArch64ISelLowering.h:110
llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT
bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const
Definition: AArch64ISelLowering.cpp:5933
llvm::AArch64TargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: AArch64ISelLowering.h:765
llvm::AArch64ISD::CCMN
@ CCMN
Definition: AArch64ISelLowering.h:158
llvm::AArch64ISD::DUP_MERGE_PASSTHRU
@ DUP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:344
llvm::AArch64TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: AArch64ISelLowering.cpp:14485
llvm::AArch64TargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: AArch64ISelLowering.cpp:21848
llvm::AArch64ISD::SMSTOP
@ SMSTOP
Definition: AArch64ISelLowering.h:69
llvm::AArch64ISD::FCMLEz
@ FCMLEz
Definition: AArch64ISelLowering.h:240
llvm::AArch64ISD::CTPOP_MERGE_PASSTHRU
@ CTPOP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:343
llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO
@ GLDFF1S_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:400
llvm::AArch64ISD::PREFETCH
@ PREFETCH
Definition: AArch64ISelLowering.h:288
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::AArch64TargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: AArch64ISelLowering.h:829
llvm::AArch64ISD::UMAX_PRED
@ UMAX_PRED
Definition: AArch64ISelLowering.h:115
llvm::AArch64TargetLowering::needsFixedCatchObjects
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Definition: AArch64ISelLowering.cpp:22170
llvm::AArch64ISD::TC_RETURN
@ TC_RETURN
Definition: AArch64ISelLowering.h:285
llvm::AArch64TargetLowering::EmitTileLoad
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2548
llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU
@ CTLZ_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:342
llvm::AArch64ISD::LD3LANEpost
@ LD3LANEpost
Definition: AArch64ISelLowering.h:456
llvm::AArch64ISD::SST1_UXTW_SCALED_PRED
@ SST1_UXTW_SCALED_PRED
Definition: AArch64ISelLowering.h:417
llvm::AArch64TargetLowering::EmitAddVectorToTile
MachineBasicBlock * EmitAddVectorToTile(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2634
llvm::AArch64ISD::SBCS
@ SBCS
Definition: AArch64ISelLowering.h:153
llvm::AArch64ISD::TBNZ
@ TBNZ
Definition: AArch64ISelLowering.h:282
llvm::AArch64ISD::FMAXNMV_PRED
@ FMAXNMV_PRED
Definition: AArch64ISelLowering.h:329
llvm::AArch64ISD::SADDV
@ SADDV
Definition: AArch64ISelLowering.h:245
llvm::AArch64ISD::ASSERT_ZEXT_BOOL
@ ASSERT_ZEXT_BOOL
Definition: AArch64ISelLowering.h:431
llvm::AArch64ISD::LD1x3post
@ LD1x3post
Definition: AArch64ISelLowering.h:445
llvm::AArch64ISD::UZP1
@ UZP1
Definition: AArch64ISelLowering.h:195
llvm::AArch64ISD::ZIP1
@ ZIP1
Definition: AArch64ISelLowering.h:193
llvm::AArch64ISD::MULHU_PRED
@ MULHU_PRED
Definition: AArch64ISelLowering.h:107
llvm::AArch64TargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Definition: AArch64ISelLowering.cpp:14602
llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO
@ GLDFF1S_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:397
llvm::AArch64ISD::CMHS
@ CMHS
Definition: AArch64ISelLowering.h:226
llvm::AArch64ISD::STNP
@ STNP
Definition: AArch64ISelLowering.h:470
llvm::AArch64ISD::BIC
@ BIC
Definition: AArch64ISelLowering.h:119
llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO
@ GLD1_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:374
llvm::AArch64ISD::ST3LANEpost
@ ST3LANEpost
Definition: AArch64ISelLowering.h:459
llvm::AArch64ISD::UMIN_PRED
@ UMIN_PRED
Definition: AArch64ISelLowering.h:116
llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU
@ FCEIL_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:126
llvm::AArch64ISD::LD2post
@ LD2post
Definition: AArch64ISelLowering.h:438
llvm::AArch64ISD::MULHS_PRED
@ MULHS_PRED
Definition: AArch64ISelLowering.h:106
llvm::AArch64ISD::FRECPX_MERGE_PASSTHRU
@ FRECPX_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:130
llvm::AArch64ISD::STG
@ STG
Definition: AArch64ISelLowering.h:462
llvm::AArch64ISD::CMGE
@ CMGE
Definition: AArch64ISelLowering.h:223
llvm::AArch64TargetLowering::getAsmOperandValueType
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
Definition: AArch64ISelLowering.cpp:9918
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::AArch64ISD::FCMGTz
@ FCMGTz
Definition: AArch64ISelLowering.h:239
llvm::AArch64ISD::SMAXV_PRED
@ SMAXV_PRED
Definition: AArch64ISelLowering.h:267
llvm::AArch64ISD::CMLTz
@ CMLTz
Definition: AArch64ISelLowering.h:236
llvm::AArch64TargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: AArch64ISelLowering.cpp:14591
llvm::AArch64ISD::FMAX_PRED
@ FMAX_PRED
Definition: AArch64ISelLowering.h:99
llvm::MemOp
Definition: TargetLowering.h:111
llvm::AArch64ISD::DUP
@ DUP
Definition: AArch64ISelLowering.h:168
llvm::AArch64TargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: AArch64ISelLowering.h:626
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::AArch64ISD::FCVTZS_MERGE_PASSTHRU
@ FCVTZS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:141
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::AArch64ISD::LDFF1_MERGE_ZERO
@ LDFF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:358
llvm::AArch64ISD::ST1x2post
@ ST1x2post
Definition: AArch64ISelLowering.h:447
llvm::AArch64TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: AArch64ISelLowering.cpp:13404
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AArch64ISD::MOVIshift
@ MOVIshift
Definition: AArch64ISelLowering.h:177
llvm::AArch64ISD::LDP
@ LDP
Definition: AArch64ISelLowering.h:467
llvm::AttributeList
Definition: Attributes.h:432
llvm::AArch64TargetLowering::isComplexDeinterleavingSupported
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
Definition: AArch64ISelLowering.cpp:23376
llvm::AArch64TargetLowering::isOpSuitableForLDPSTP
bool isOpSuitableForLDPSTP(const Instruction *I) const
Definition: AArch64ISelLowering.cpp:21732
llvm::AArch64TargetLowering::ReconstructShuffle
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
Definition: AArch64ISelLowering.cpp:10115
llvm::AArch64ISD::MOPS_MEMSET
@ MOPS_MEMSET
Definition: AArch64ISelLowering.h:473
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:53
llvm::AArch64ISD::GLDNT1_MERGE_ZERO
@ GLDNT1_MERGE_ZERO
Definition: AArch64ISelLowering.h:405
llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO
@ GLDFF1_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:389
llvm::AArch64TargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
Definition: AArch64ISelLowering.cpp:13369
llvm::AArch64ISD::CALL_RVMARKER
@ CALL_RVMARKER
Definition: AArch64ISelLowering.h:57
llvm::AArch64ISD::CBZ
@ CBZ
Definition: AArch64ISelLowering.h:279
llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU
@ FFLOOR_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:127
llvm::AArch64ISD::ADC
@ ADC
Definition: AArch64ISelLowering.h:90
llvm::AArch64TargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: AArch64ISelLowering.cpp:14548
llvm::AArch64TargetLowering::EmitLoweredCatchRet
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2539
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::AArch64TargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
Definition: AArch64ISelLowering.cpp:13966
llvm::AArch64ISD::SMINV_PRED
@ SMINV_PRED
Definition: AArch64ISelLowering.h:269
llvm::AArch64ISD::MOVImsl
@ MOVImsl
Definition: AArch64ISelLowering.h:179
llvm::AArch64ISD::GLDFF1_MERGE_ZERO
@ GLDFF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:387
llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO
@ GLDFF1S_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:398
llvm::AArch64ISD::FCMGT
@ FCMGT
Definition: AArch64ISelLowering.h:229
llvm::AArch64ISD::TRN2
@ TRN2
Definition: AArch64ISelLowering.h:198
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO
@ GLDFF1_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:393
llvm::AArch64ISD::CCMP
@ CCMP
Definition: AArch64ISelLowering.h:157
llvm::AArch64ISD::FMINNMV_PRED
@ FMINNMV_PRED
Definition: AArch64ISelLowering.h:331
llvm::AArch64ISD::URSHR_I
@ URSHR_I
Definition: AArch64ISelLowering.h:215
llvm::AArch64ISD::FRECPS
@ FRECPS
Definition: AArch64ISelLowering.h:310
llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO
@ GLD1S_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:384
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2195
llvm::AArch64ISD::REV32
@ REV32
Definition: AArch64ISelLowering.h:200
llvm::AArch64ISD::TLSDESC_CALLSEQ
@ TLSDESC_CALLSEQ
Definition: AArch64ISelLowering.h:74
SelectionDAG.h
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::AArch64ISD::RDSVL
@ RDSVL
Definition: AArch64ISelLowering.h:426
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AArch64ISD::LD1x4post
@ LD1x4post
Definition: AArch64ISelLowering.h:446
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::AArch64TargetLowering::isAllActivePredicate
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
Definition: AArch64ISelLowering.cpp:23292
llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO
@ GLD1S_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:382
llvm::AArch64ISD::SHL_PRED
@ SHL_PRED
Definition: AArch64ISelLowering.h:109
llvm::AArch64ISD::FCMP
@ FCMP
Definition: AArch64ISelLowering.h:162
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64ISD::SUNPKLO
@ SUNPKLO
Definition: AArch64ISelLowering.h:315
llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU
@ SIGN_EXTEND_INREG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:142
llvm::ComplexDeinterleavingOperation
ComplexDeinterleavingOperation
Definition: ComplexDeinterleavingPass.h:36
llvm::AArch64ISD::LD4LANEpost
@ LD4LANEpost
Definition: AArch64ISelLowering.h:457
llvm::AArch64ISD::LD3DUPpost
@ LD3DUPpost
Definition: AArch64ISelLowering.h:452
llvm::AArch64ISD::ADDlow
@ ADDlow
Definition: AArch64ISelLowering.h:77
llvm::AArch64ISD::STRICT_FCMP
@ STRICT_FCMP
Definition: AArch64ISelLowering.h:434
llvm::AArch64ISD::GLD1_MERGE_ZERO
@ GLD1_MERGE_ZERO
Definition: AArch64ISelLowering.h:369
llvm::AArch64ISD::RESTORE_ZA
@ RESTORE_ZA
Definition: AArch64ISelLowering.h:70
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AArch64ISD::MVNIshift
@ MVNIshift
Definition: AArch64ISelLowering.h:181
llvm::AArch64ISD::REVD_MERGE_PASSTHRU
@ REVD_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:427
llvm::AArch64ISD::SST1_UXTW_PRED
@ SST1_UXTW_PRED
Definition: AArch64ISelLowering.h:415
llvm::AArch64ISD::FCMLTz
@ FCMLTz
Definition: AArch64ISelLowering.h:241
Instruction.h
llvm::AArch64ISD::CMEQz
@ CMEQz
Definition: AArch64ISelLowering.h:232
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1404
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::AArch64TargetLowering::optimizeExtendOrTruncateConversion
bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L) const override
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
Definition: AArch64ISelLowering.cpp:13864
llvm::AArch64ISD::FMUL_PRED
@ FMUL_PRED
Definition: AArch64ISelLowering.h:103
llvm::AArch64ISD::REVW_MERGE_PASSTHRU
@ REVW_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:341
llvm::AArch64ISD::FRINT_MERGE_PASSTHRU
@ FRINT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:131
llvm::AArch64ISD::CSEL
@ CSEL
Definition: AArch64ISelLowering.h:82
llvm::AArch64TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: AArch64ISelLowering.cpp:20889
llvm::AArch64ISD::MVNImsl
@ MVNImsl
Definition: AArch64ISelLowering.h:182
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1141
llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: AArch64ISelLowering.cpp:14553
llvm::AArch64ISD::ST4LANEpost
@ ST4LANEpost
Definition: AArch64ISelLowering.h:460
llvm::AArch64ISD::TRN1
@ TRN1
Definition: AArch64ISelLowering.h:197
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::AArch64ISD::SST1_SCALED_PRED
@ SST1_SCALED_PRED
Definition: AArch64ISelLowering.h:414
llvm::AArch64ISD::CMGEz
@ CMGEz
Definition: AArch64ISelLowering.h:233
llvm::AArch64ISD::SMAXV
@ SMAXV
Definition: AArch64ISelLowering.h:262
llvm::AArch64ISD::SRL_PRED
@ SRL_PRED
Definition: AArch64ISelLowering.h:113
llvm::AArch64ISD::MOPS_MEMMOVE
@ MOPS_MEMMOVE
Definition: AArch64ISelLowering.h:476
llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: AArch64ISelLowering.cpp:21826
llvm::AArch64TargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
Definition: AArch64ISelLowering.cpp:14213
llvm::AArch64ISD::GLDNT1S_MERGE_ZERO
@ GLDNT1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:407
llvm::AArch64ISD::LD1_MERGE_ZERO
@ LD1_MERGE_ZERO
Definition: AArch64ISelLowering.h:354
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:80
llvm::AArch64ISD::MRS
@ MRS
Definition: AArch64ISelLowering.h:301
llvm::AArch64::RP
@ RP
Definition: AArch64ISelLowering.h:486
Operation
PowerPC Reduce CR logical Operation
Definition: PPCReduceCRLogicals.cpp:735
llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO
@ GLD1S_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:379
llvm::AArch64ISD::LDNP
@ LDNP
Definition: AArch64ISelLowering.h:468
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::AArch64ISD::ORRi
@ ORRi
Definition: AArch64ISelLowering.h:186
llvm::AArch64ISD::VSRI
@ VSRI
Definition: AArch64ISelLowering.h:219
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::AArch64ISD::LASTB
@ LASTB
Definition: AArch64ISelLowering.h:322
llvm::AArch64TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: AArch64ISelLowering.h:838
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1862
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3506
llvm::AArch64ISD::SADDLP
@ SADDLP
Definition: AArch64ISelLowering.h:251
llvm::AArch64ISD::SRA_PRED
@ SRA_PRED
Definition: AArch64ISelLowering.h:112
llvm::AArch64ISD::UDIV_PRED
@ UDIV_PRED
Definition: AArch64ISelLowering.h:114
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::AArch64ISD::MUL_PRED
@ MUL_PRED
Definition: AArch64ISelLowering.h:105
llvm::AArch64ISD::CMLEz
@ CMLEz
Definition: AArch64ISelLowering.h:235
llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
Definition: AArch64ISelLowering.cpp:23380
llvm::AArch64ISD::OBSCURE_COPY
@ OBSCURE_COPY
Definition: AArch64ISelLowering.h:67
llvm::AArch64ISD::FRSQRTE
@ FRSQRTE
Definition: AArch64ISelLowering.h:311
llvm::dwarf::Index
Index
Definition: Dwarf.h:490
llvm::AArch64TargetLowering::getIRStackGuard
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
Definition: AArch64ISelLowering.cpp:21962
llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: AArch64ISelLowering.cpp:2117
llvm::AArch64TargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: AArch64ISelLowering.cpp:14459
llvm::AArch64ISD::MOVIedit
@ MOVIedit
Definition: AArch64ISelLowering.h:178
llvm::AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU
@ SINT_TO_FP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:139
llvm::AArch64TargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: AArch64ISelLowering.cpp:14701
llvm::AArch64TargetLowering::getTargetMMOFlags
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: AArch64ISelLowering.cpp:13959
llvm::AArch64ISD::SRAD_MERGE_OP1
@ SRAD_MERGE_OP1
Definition: AArch64ISelLowering.h:121
llvm::Instruction
Definition: Instruction.h:42
llvm::AArch64ISD::UADDLP
@ UADDLP
Definition: AArch64ISelLowering.h:252
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::AArch64ISD::ST1_PRED
@ ST1_PRED
Definition: AArch64ISelLowering.h:410
llvm::AArch64ISD::STZ2G
@ STZ2G
Definition: AArch64ISelLowering.h:465
llvm::AArch64ISD::UMINV_PRED
@ UMINV_PRED
Definition: AArch64ISelLowering.h:270
llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO
@ GLD1S_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:380
llvm::AArch64ISD::DUPLANE16
@ DUPLANE16
Definition: AArch64ISelLowering.h:170
llvm::AArch64ISD::SST1_PRED
@ SST1_PRED
Definition: AArch64ISelLowering.h:413
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
llvm::AArch64ISD::ZIP2
@ ZIP2
Definition: AArch64ISelLowering.h:194
llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO
@ GLDFF1S_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:399
llvm::AArch64ISD::FCMEQ
@ FCMEQ
Definition: AArch64ISelLowering.h:227
llvm::AArch64ISD::VSLI
@ VSLI
Definition: AArch64ISelLowering.h:218
llvm::AArch64ISD::FABS_MERGE_PASSTHRU
@ FABS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:125
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AArch64ISD::FP_ROUND_MERGE_PASSTHRU
@ FP_ROUND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:136
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::AArch64TargetLowering::hasPairedLoad
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
Definition: AArch64ISelLowering.cpp:13937
llvm::AArch64ISD::VSHL
@ VSHL
Definition: AArch64ISelLowering.h:206
llvm::AArch64ISD::SETCC_MERGE_ZERO
@ SETCC_MERGE_ZERO
Definition: AArch64ISelLowering.h:147
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AArch64ISD::UUNPKLO
@ UUNPKLO
Definition: AArch64ISelLowering.h:317
llvm::AArch64ISD::SBC
@ SBC
Definition: AArch64ISelLowering.h:91
llvm::AArch64ISD::SMSTART
@ SMSTART
Definition: AArch64ISelLowering.h:68
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::AArch64ISD::SADDV_PRED
@ SADDV_PRED
Definition: AArch64ISelLowering.h:265
llvm::AArch64ISD::UITOF
@ UITOF
Definition: AArch64ISelLowering.h:292
llvm::AArch64TargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: AArch64ISelLowering.cpp:21786
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::AArch64TargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: AArch64ISelLowering.cpp:14380
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AArch64TargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
Definition: AArch64ISelLowering.cpp:14040
llvm::AArch64ISD::UQSHL_I
@ UQSHL_I
Definition: AArch64ISelLowering.h:212
llvm::AArch64TargetLowering::EmitFill
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2566
llvm::AArch64ISD::PTEST
@ PTEST
Definition: AArch64ISelLowering.h:334
llvm::ComplexDeinterleavingRotation
ComplexDeinterleavingRotation
Definition: ComplexDeinterleavingPass.h:44
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::AArch64TargetLowering::getPromotedVTForPredicate
EVT getPromotedVTForPredicate(EVT VT) const
Definition: AArch64ISelLowering.cpp:23297
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::AArch64ISD::FCVTZU_MERGE_PASSTHRU
@ FCVTZU_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:140
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO
@ GLD1_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:375
llvm::APFloat
Definition: APFloat.h:716
llvm::AArch64ISD::SPLICE
@ SPLICE
Definition: AArch64ISelLowering.h:203
llvm::AArch64TargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: AArch64ISelLowering.h:824
llvm::AArch64TargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: AArch64ISelLowering.cpp:22108
llvm::AArch64ISD::CMHI
@ CMHI
Definition: AArch64ISelLowering.h:225
llvm::AArch64ISD::ST3post
@ ST3post
Definition: AArch64ISelLowering.h:442
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:298
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MipsISD::Ext
@ Ext
Definition: MipsISelLowering.h:159
llvm::AArch64TargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: AArch64ISelLowering.cpp:21767
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::AArch64ISD::SDOT
@ SDOT
Definition: AArch64ISelLowering.h:256
llvm::AArch64TargetLowering::AArch64TargetLowering
AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)
Definition: AArch64ISelLowering.cpp:294
llvm::AArch64ISD::SST1_SXTW_SCALED_PRED
@ SST1_SXTW_SCALED_PRED
Definition: AArch64ISelLowering.h:418
llvm::AArch64ISD::FRECPE
@ FRECPE
Definition: AArch64ISelLowering.h:309
llvm::AArch64ISD::INDEX_VECTOR
@ INDEX_VECTOR
Definition: AArch64ISelLowering.h:345
llvm::AArch64ISD::SQSHL_I
@ SQSHL_I
Definition: AArch64ISelLowering.h:211
llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU
@ ZERO_EXTEND_INREG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:143
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AArch64ISD::SDIV_PRED
@ SDIV_PRED
Definition: AArch64ISelLowering.h:108
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AArch64ISD::FMINNM_PRED
@ FMINNM_PRED
Definition: AArch64ISelLowering.h:102
AArch64SMEAttributes.h
llvm::AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: AArch64ISelLowering.cpp:22027
llvm::AArch64::rmMask
@ rmMask
Definition: AArch64ISelLowering.h:489
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1313
llvm::AArch64::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: AArch64FastISel.cpp:5141
llvm::AArch64ISD::LD1RQ_MERGE_ZERO
@ LD1RQ_MERGE_ZERO
Definition: AArch64ISelLowering.h:360
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::AArch64TargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: AArch64ISelLowering.cpp:22053
llvm::AArch64ISD::SST1_IMM_PRED
@ SST1_IMM_PRED
Definition: AArch64ISelLowering.h:419
llvm::AArch64ISD::DUPLANE128
@ DUPLANE128
Definition: AArch64ISelLowering.h:173
llvm::AArch64TargetLowering::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
Definition: AArch64ISelLowering.cpp:13422
llvm::AArch64TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
Definition: AArch64ISelLowering.cpp:1834
llvm::AArch64ISD::VASHR
@ VASHR
Definition: AArch64ISelLowering.h:208
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::AArch64TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: AArch64ISelLowering.cpp:5651
llvm::AArch64ISD::EXT
@ EXT
Definition: AArch64ISelLowering.h:202
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:6014
llvm::AArch64ISD::CSINV
@ CSINV
Definition: AArch64ISelLowering.h:83
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:3090
llvm::AArch64TargetLowering::shouldExpandAtomicStoreInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition: AArch64ISelLowering.cpp:21756
llvm::AArch64ISD::FADDV_PRED
@ FADDV_PRED
Definition: AArch64ISelLowering.h:327
llvm::AArch64ISD::CMGT
@ CMGT
Definition: AArch64ISelLowering.h:224
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:69
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:124
llvm::AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
Definition: AArch64ISelLowering.cpp:21888
llvm::AArch64TargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: AArch64ISelLowering.cpp:21747
llvm::AArch64ISD::FADDA_PRED
@ FADDA_PRED
Definition: AArch64ISelLowering.h:326
llvm::AArch64TargetLowering::isVectorClearMaskLegal
bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override
Similar to isShuffleMaskLegal.
Definition: AArch64ISelLowering.cpp:12692
llvm::AArch64ISD::BICi
@ BICi
Definition: AArch64ISelLowering.h:185
llvm::AArch64ISD::LD1RO_MERGE_ZERO
@ LD1RO_MERGE_ZERO
Definition: AArch64ISelLowering.h:361
llvm::AArch64ISD::PMULL
@ PMULL
Definition: AArch64ISelLowering.h:306
llvm::AArch64ISD::SMULL
@ SMULL
Definition: AArch64ISelLowering.h:303
llvm::AArch64TargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: AArch64ISelLowering.cpp:12662
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::AArch64ISD::ABDS_PRED
@ ABDS_PRED
Definition: AArch64ISelLowering.h:94
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::AArch64ISD::FCMGE
@ FCMGE
Definition: AArch64ISelLowering.h:228
llvm::AArch64TargetLowering::getOptimalMemOpLLT
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
Definition: AArch64ISelLowering.cpp:14410
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::AArch64ISD::SQSHLU_I
@ SQSHLU_I
Definition: AArch64ISelLowering.h:213
llvm::AArch64TargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: AArch64ISelLowering.h:771
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::AArch64ISD::EXTR
@ EXTR
Definition: AArch64ISelLowering.h:165
llvm::AArch64TargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: AArch64ISelLowering.cpp:22067
llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO
@ GLDFF1_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:392
llvm::AArch64ISD::LDFF1S_MERGE_ZERO
@ LDFF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:359
llvm::AArch64ISD::SRSHR_I
@ SRSHR_I
Definition: AArch64ISelLowering.h:214
llvm::AArch64ISD::SMIN_PRED
@ SMIN_PRED
Definition: AArch64ISelLowering.h:111
llvm::AArch64ISD::FNEG_MERGE_PASSTHRU
@ FNEG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:129
llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO
@ GLD1_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:372
llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO
@ GLDFF1S_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:402
llvm::AArch64TargetLowering::isReassocProfitable
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
Definition: AArch64ISelLowering.cpp:5997
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::AArch64TargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AArch64ISelLowering.cpp:9539
llvm::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfo.h:168
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
llvm::AArch64TargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: AArch64ISelLowering.cpp:9546
llvm::AArch64::RN
@ RN
Definition: AArch64ISelLowering.h:485
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU
@ FSQRT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:134
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO
@ GLDFF1_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:390
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::AArch64ISD::BSP
@ BSP
Definition: AArch64ISelLowering.h:190
llvm::AArch64ISD::ADCS
@ ADCS
Definition: AArch64ISelLowering.h:152
llvm::AArch64ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: AArch64ISelLowering.h:51
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::AArch64ISD::LDNF1_MERGE_ZERO
@ LDNF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:356
llvm::AArch64TargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Definition: AArch64ISelLowering.cpp:5929
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO
@ GLD1_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:373
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AArch64ISD::LD1LANEpost
@ LD1LANEpost
Definition: AArch64ISelLowering.h:454
llvm::AArch64TargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Definition: AArch64ISelLowering.cpp:22134
llvm::AArch64ISD::CLASTB_N
@ CLASTB_N
Definition: AArch64ISelLowering.h:320
llvm::AArch64ISD::ANDV_PRED
@ ANDV_PRED
Definition: AArch64ISelLowering.h:273
llvm::AArch64ISD::REVH_MERGE_PASSTHRU
@ REVH_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:340
llvm::AArch64TargetLowering::isDesirableToCommuteXorWithShift
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Definition: AArch64ISelLowering.cpp:14632
llvm::AArch64ISD::BITREVERSE_MERGE_PASSTHRU
@ BITREVERSE_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:338
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::AArch64ISD::LDNF1S_MERGE_ZERO
@ LDNF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:357
llvm::AArch64ISD::STRICT_FCMPE
@ STRICT_FCMPE
Definition: AArch64ISelLowering.h:435
llvm::ArrayRef< int >
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::AArch64ISD::LD4post
@ LD4post
Definition: AArch64ISelLowering.h:440
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1883
llvm::AArch64ISD::CMEQ
@ CMEQ
Definition: AArch64ISelLowering.h:222
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::AArch64TargetLowering::fallBackToDAGISel
bool fallBackToDAGISel(const Instruction &Inst) const override
Definition: AArch64ISelLowering.cpp:22227
llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO
@ GLDFF1_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:391
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::AArch64ISD::DUPLANE8
@ DUPLANE8
Definition: AArch64ISelLowering.h:169
llvm::AArch64TargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: AArch64ISelLowering.h:734
llvm::LinearPolySize::getFixedValue
ScalarTy getFixedValue() const
Definition: TypeSize.h:312
llvm::AArch64TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: AArch64ISelLowering.cpp:2112
uint32_t
llvm::AArch64ISD::MOVI
@ MOVI
Definition: AArch64ISelLowering.h:176
llvm::AArch64ISD::ADDS
@ ADDS
Definition: AArch64ISelLowering.h:150
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:76
llvm::AArch64TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: AArch64ISelLowering.h:749
llvm::AArch64ISD::REV64
@ REV64
Definition: AArch64ISelLowering.h:201
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64ISD::CMGTz
@ CMGTz
Definition: AArch64ISelLowering.h:234
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::AArch64ISD::SSTNT1_PRED
@ SSTNT1_PRED
Definition: AArch64ISelLowering.h:422
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::AArch64ISD::LD1DUPpost
@ LD1DUPpost
Definition: AArch64ISelLowering.h:450
llvm::AArch64ISD::FMA_PRED
@ FMA_PRED
Definition: AArch64ISelLowering.h:98
llvm::AArch64ISD::LS64_EXTRACT
@ LS64_EXTRACT
Definition: AArch64ISelLowering.h:352
llvm::AArch64TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AArch64ISelLowering.cpp:2173
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64ISD::SVE_LD2_MERGE_ZERO
@ SVE_LD2_MERGE_ZERO
Definition: AArch64ISelLowering.h:364
llvm::AArch64ISD::ABDU_PRED
@ ABDU_PRED
Definition: AArch64ISelLowering.h:95
llvm::AArch64ISD::CBNZ
@ CBNZ
Definition: AArch64ISelLowering.h:280
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::AArch64TargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: AArch64ISelLowering.cpp:21894
llvm::AArch64ISD::ORV_PRED
@ ORV_PRED
Definition: AArch64ISelLowering.h:271
llvm::AArch64TargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: AArch64ISelLowering.cpp:14656
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
llvm::AArch64ISD::UZP2
@ UZP2
Definition: AArch64ISelLowering.h:196
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64TargetLowering::createComplexDeinterleavingIR
Value * createComplexDeinterleavingIR(Instruction *I, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
Definition: AArch64ISelLowering.cpp:23397
llvm::AArch64TargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: AArch64ISelLowering.cpp:14678
llvm::AArch64ISD::PTRUE
@ PTRUE
Definition: AArch64ISelLowering.h:336
llvm::AArch64ISD::ANDS
@ ANDS
Definition: AArch64ISelLowering.h:154
llvm::AArch64ISD::FMAXV_PRED
@ FMAXV_PRED
Definition: AArch64ISelLowering.h:328
llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU
@ FROUNDEVEN_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:133
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64TargetLowering::changeStreamingMode
SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InFlag, SDValue PStateSM, bool Entry) const
If a change in streaming mode is required on entry to/return from a function call it emits and return...
Definition: AArch64ISelLowering.cpp:6914
llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO
@ GLD1S_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:383
llvm::AArch64ISD::FMAXNM_PRED
@ FMAXNM_PRED
Definition: AArch64ISelLowering.h:100
llvm::AArch64TargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: AArch64ISelLowering.cpp:14441
llvm::AArch64ISD::THREAD_POINTER
@ THREAD_POINTER
Definition: AArch64ISelLowering.h:89
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::AArch64::RZ
@ RZ
Definition: AArch64ISelLowering.h:488
llvm::AArch64ISD::FRSQRTS
@ FRSQRTS
Definition: AArch64ISelLowering.h:312
llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition: AArch64ISelLowering.h:794
llvm::AArch64TargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: AArch64ISelLowering.cpp:13950
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
uint16_t
CallingConvLower.h
llvm::AArch64TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
Definition: AArch64ISelLowering.cpp:13448
llvm::AArch64ISD::CSNEG
@ CSNEG
Definition: AArch64ISelLowering.h:84
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::AArch64ISD::STZG
@ STZG
Definition: AArch64ISelLowering.h:463
llvm::AArch64ISD::UDOT
@ UDOT
Definition: AArch64ISelLowering.h:255
llvm::AArch64ISD::CALL_BTI
@ CALL_BTI
Definition: AArch64ISelLowering.h:59
llvm::AArch64TargetLowering::getVaListSizeInBits
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
Definition: AArch64ISelLowering.cpp:22139
llvm::AArch64ISD::FMOV
@ FMOV
Definition: AArch64ISelLowering.h:180
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4579
llvm::AArch64TargetLowering::supportKCFIBundles
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
Definition: AArch64ISelLowering.h:842
llvm::AArch64ISD::UADDV_PRED
@ UADDV_PRED
Definition: AArch64ISelLowering.h:266
llvm::AArch64TargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: AArch64ISelLowering.cpp:21720
llvm::TypeSize
Definition: TypeSize.h:435
llvm::AArch64TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AArch64ISelLowering.cpp:2650
llvm::AArch64ISD::NEG_MERGE_PASSTHRU
@ NEG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:145
llvm::AArch64ISD::CSINC
@ CSINC
Definition: AArch64ISelLowering.h:85
llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO
@ GLDFF1S_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:401
llvm::AArch64ISD::TBL
@ TBL
Definition: AArch64ISelLowering.h:323
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::AArch64TargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: AArch64ISelLowering.cpp:22061
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:226
llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO
@ GLD1S_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:381
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::AArch64TargetLowering::EmitF128CSEL
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2480
llvm::AArch64ISD::SVE_LD3_MERGE_ZERO
@ SVE_LD3_MERGE_ZERO
Definition: AArch64ISelLowering.h:365
llvm::AArch64ISD::FP_EXTEND_MERGE_PASSTHRU
@ FP_EXTEND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:137
llvm::AArch64ISD::GLDFF1S_MERGE_ZERO
@ GLDFF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:396
llvm::AArch64TargetLowering::getSafeStackPointerLocation
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
Definition: AArch64ISelLowering.cpp:22012
llvm::AArch64ISD::ADRP
@ ADRP
Definition: AArch64ISelLowering.h:75
llvm::AArch64ISD::FCMEQz
@ FCMEQz
Definition: AArch64ISelLowering.h:237
llvm::AArch64ISD::DUPLANE64
@ DUPLANE64
Definition: AArch64ISelLowering.h:172
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AArch64ISD::ST2G
@ ST2G
Definition: AArch64ISelLowering.h:464
llvm::AArch64ISD::SST1_SXTW_PRED
@ SST1_SXTW_PRED
Definition: AArch64ISelLowering.h:416
llvm::AArch64ISD::FSUB_PRED
@ FSUB_PRED
Definition: AArch64ISelLowering.h:104
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:6059
llvm::AArch64TargetLowering::getRedZoneSize
unsigned getRedZoneSize(const Function &F) const
Definition: AArch64ISelLowering.h:882
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2006
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
Definition: AArch64ISelLowering.cpp:1612
llvm::AArch64ISD::REINTERPRET_CAST
@ REINTERPRET_CAST
Definition: AArch64ISelLowering.h:348
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU
@ FTRUNC_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:135
llvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: AArch64ISelLowering.cpp:22041
llvm::AArch64ISD::REV16
@ REV16
Definition: AArch64ISelLowering.h:199
llvm::AArch64ISD::LS64_BUILD
@ LS64_BUILD
Definition: AArch64ISelLowering.h:351
llvm::AArch64::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: AArch64ISelLowering.h:493
llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO
@ GLD1_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:371
llvm::AArch64ISD::UADDV
@ UADDV
Definition: AArch64ISelLowering.h:246
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1319
llvm::AArch64TargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: AArch64ISelLowering.cpp:22125
llvm::AArch64TargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: AArch64ISelLowering.h:761
llvm::AArch64ISD::UMAXV_PRED
@ UMAXV_PRED
Definition: AArch64ISelLowering.h:268
N
#define N
llvm::AArch64ISD::ABS_MERGE_PASSTHRU
@ ABS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:144
llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO
@ GLD1_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:370
llvm::AArch64ISD::ST2LANEpost
@ ST2LANEpost
Definition: AArch64ISelLowering.h:458
llvm::AArch64ISD::UMAXV
@ UMAXV
Definition: AArch64ISelLowering.h:263
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4671
llvm::AArch64ISD::GLD1S_MERGE_ZERO
@ GLD1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:378
llvm::AArch64ISD::TBZ
@ TBZ
Definition: AArch64ISelLowering.h:281
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::AArch64ISD::FCCMP
@ FCCMP
Definition: AArch64ISelLowering.h:159
llvm::AArch64TargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: AArch64ISelLowering.cpp:13227
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
llvm::AArch64TargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: AArch64ISelLowering.cpp:13630
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:515
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU
@ BSWAP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:339
llvm::AArch64ISD::INSR
@ INSR
Definition: AArch64ISelLowering.h:333
llvm::AArch64ISD::LD2LANEpost
@ LD2LANEpost
Definition: AArch64ISelLowering.h:455
llvm::AArch64ISD::LASTA
@ LASTA
Definition: AArch64ISelLowering.h:321
llvm::AArch64TargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: AArch64ISelLowering.cpp:22120
llvm::AArch64ISD::ST4post
@ ST4post
Definition: AArch64ISelLowering.h:443
llvm::AArch64ISD::ST1x3post
@ ST1x3post
Definition: AArch64ISelLowering.h:448
llvm::AArch64ISD::WrapperLarge
@ WrapperLarge
Definition: AArch64ISelLowering.h:52
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AArch64ISelLowering.cpp:14491
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:498
llvm::AArch64TargetLowering::getPointerTy
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: AArch64ISelLowering.h:521
llvm::AArch64ISD::MOPS_MEMCOPY
@ MOPS_MEMCOPY
Definition: AArch64ISelLowering.h:475
llvm::AArch64ISD::LD4DUPpost
@ LD4DUPpost
Definition: AArch64ISelLowering.h:453
MachineFunction.h
llvm::AArch64ISD::PTEST_ANY
@ PTEST_ANY
Definition: AArch64ISelLowering.h:335
llvm::AArch64ISD::BIT
@ BIT
Definition: AArch64ISelLowering.h:276
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:263
llvm::AArch64ISD::BRCOND
@ BRCOND
Definition: AArch64ISelLowering.h:81
llvm::AArch64ISD::SUNPKHI
@ SUNPKHI
Definition: AArch64ISelLowering.h:314
llvm::AArch64TargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: AArch64ISelLowering.cpp:21977
llvm::AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU
@ UINT_TO_FP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:138
llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU
@ FNEARBYINT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:128
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO
@ GLDFF1_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:388
llvm::AArch64TargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: AArch64ISelLowering.cpp:2002
llvm::AArch64ISD::SMINV
@ SMINV
Definition: AArch64ISelLowering.h:260
llvm::AArch64TargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: AArch64ISelLowering.h:776
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::AArch64TargetLowering::EmitZero
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2617
llvm::AArch64ISD::FADD_PRED
@ FADD_PRED
Definition: AArch64ISelLowering.h:96
llvm::AArch64ISD::ST2post
@ ST2post
Definition: AArch64ISelLowering.h:441
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:510
llvm::AArch64TargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: AArch64ISelLowering.h:742
llvm::AArch64ISD::LD1S_MERGE_ZERO
@ LD1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:355
llvm::AArch64ISD::STP
@ STP
Definition: AArch64ISelLowering.h:469
llvm::AArch64ISD::FMIN_PRED
@ FMIN_PRED
Definition: AArch64ISelLowering.h:101
llvm::AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Definition: AArch64ISelLowering.cpp:21933
llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO
@ GLDNT1_INDEX_MERGE_ZERO
Definition: AArch64ISelLowering.h:406
llvm::AArch64ISD::DUPLANE32
@ DUPLANE32
Definition: AArch64ISelLowering.h:171
llvm::AArch64ISD::FDIV_PRED
@ FDIV_PRED
Definition: AArch64ISelLowering.h:97
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1240
llvm::AArch64ISD::FROUND_MERGE_PASSTHRU
@ FROUND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:132
llvm::AArch64::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
Definition: AArch64ISelLowering.h:484
llvm::AArch64ISD::NVCAST
@ NVCAST
Natural vector cast.
Definition: AArch64ISelLowering.h:299
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::AArch64ISD::SUBS
@ SUBS
Definition: AArch64ISelLowering.h:151