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AArch64ISelLowering.h
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1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AArch64 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16
17#include "AArch64.h"
23#include "llvm/IR/CallingConv.h"
24#include "llvm/IR/Instruction.h"
25
26namespace llvm {
27
28namespace AArch64ISD {
29
30// For predicated nodes where the result is a vector, the operation is
31// controlled by a governing predicate and the inactive lanes are explicitly
32// defined with a value, please stick the following naming convention:
33//
34// _MERGE_OP<n> The result value is a vector with inactive lanes equal
35// to source operand OP<n>.
36//
37// _MERGE_ZERO The result value is a vector with inactive lanes
38// actively zeroed.
39//
40// _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
41// to the last source operand which only purpose is being
42// a passthru value.
43//
44// For other cases where no explicit action is needed to set the inactive lanes,
45// or when the result is not a vector and it is needed or helpful to
46// distinguish a node from similar unpredicated nodes, use:
47//
48// _PRED
49//
50enum NodeType : unsigned {
52 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
53 CALL, // Function call.
54
55 // Pseudo for a OBJC call that gets emitted together with a special `mov
56 // x29, x29` marker instruction.
58
59 CALL_BTI, // Function call followed by a BTI instruction.
60
61 // Essentially like a normal COPY that works on GPRs, but cannot be
62 // rematerialised by passes like the simple register coalescer. It's
63 // required for SME when lowering calls because we cannot allow frame
64 // index calculations using addvl to slip in between the smstart/smstop
65 // and the bl instruction. The scalable vector length may change across
66 // the smstart/smstop boundary.
71
72 // Produces the full sequence of instructions for getting the thread pointer
73 // offset of a variable into X0, using the TLSDesc model.
75 ADRP, // Page address of a TargetGlobalAddress operand.
76 ADR, // ADR
77 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
78 LOADgot, // Load from automatically generated descriptor (e.g. Global
79 // Offset Table, TLS record).
80 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
81 BRCOND, // Conditional branch instruction; "b.cond".
83 CSINV, // Conditional select invert.
84 CSNEG, // Conditional select negate.
85 CSINC, // Conditional select increment.
86
87 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
88 // ELF.
91 SBC, // adc, sbc instructions
92
93 // Predicated instructions where inactive lanes produce undefined results.
121
122 // Unpredicated vector instructions
124
126
127 // Predicated instructions with the result of inactive lanes provided by the
128 // last operand.
150
152
153 // Arithmetic instructions which write flags.
159
160 // Conditional compares. Operands: left,right,falsecc,cc,flags
164
165 // Floating point comparison
167
168 // Scalar extract
170
171 // Scalar-to-vector duplication
178
179 // Vector immedate moves
187
188 // Vector immediate ops
191
192 // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
193 // element must be identical.
195
196 // Vector shuffles
208
209 // Vector shift by scalar
213
214 // Vector shift by scalar (again)
220
221 // Vector shift by constant and insert
224
225 // Vector comparisons
234
235 // Vector zero comparisons
246
247 // Vector across-lanes addition
248 // Only the lower result lane is defined.
251
252 // Add Pairwise of two vectors
254 // Add Long Pairwise
257
258 // udot/sdot instructions
261
262 // Vector across-lanes min/max
263 // Only the lower result lane is defined.
268
278
279 // Vector bitwise insertion
281
282 // Compare-and-branch
287
288 // Tail calls
290
291 // Custom prefetch handling
293
294 // {s|u}int to FP within a FP register.
297
298 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
299 /// world w.r.t vectors; which causes additional REV instructions to be
300 /// generated to compensate for the byte-swapping. But sometimes we do
301 /// need to re-interpret the data in SIMD vector registers in big-endian
302 /// mode without emitting such REV instructions.
304
305 MRS, // MRS, also sets the flags via a glue.
306
309
311
312 // Reciprocal estimates and steps.
317
322
328
329 // Floating-point reductions.
336
341
350
351 // Cast between vectors of the same element type but differ in length.
353
354 // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
357
366
367 // Structured loads.
371
372 // Unsigned gather loads.
380
381 // Signed gather loads
389
390 // Unsigned gather loads.
398
399 // Signed gather loads.
407
408 // Non-temporal gather loads
412
413 // Contiguous masked store.
415
416 // Scatter store
424
425 // Non-temporal scatter store
428
429 // SME
432
433 // Asserts that a function argument (i32) is zero-extended to i8 by
434 // the caller
436
437 // 128-bit system register accesses
438 // lo64, hi64, chain = MRRS(chain, sysregname)
440 // chain = MSRR(chain, sysregname, lo64, hi64)
442
443 // Strict (exception-raising) floating point comparison
446
447 // NEON Load/Store with post-increment base updates
471
476
483
484 // Memory Operations
489};
490
491} // end namespace AArch64ISD
492
493namespace AArch64 {
494/// Possible values of current rounding mode, which is specified in bits
495/// 23:22 of FPCR.
497 RN = 0, // Round to Nearest
498 RP = 1, // Round towards Plus infinity
499 RM = 2, // Round towards Minus infinity
500 RZ = 3, // Round towards Zero
501 rmMask = 3 // Bit mask selecting rounding mode
503
504// Bit position of rounding mode bits in FPCR.
505const unsigned RoundingBitsPos = 22;
506
507// Registers used to pass function arguments.
510
511} // namespace AArch64
512
513class AArch64Subtarget;
514
516public:
517 explicit AArch64TargetLowering(const TargetMachine &TM,
518 const AArch64Subtarget &STI);
519
520 /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
521 /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
523 SDValue N1) const override;
524
525 /// Selects the correct CCAssignFn for a given CallingConvention value.
526 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
527
528 /// Selects the correct CCAssignFn for a given CallingConvention value.
530
531 /// Determine which of the bits specified in Mask are known to be either zero
532 /// or one and return them in the KnownZero/KnownOne bitsets.
533 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
534 const APInt &DemandedElts,
535 const SelectionDAG &DAG,
536 unsigned Depth = 0) const override;
537
538 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
539 // Returning i64 unconditionally here (i.e. even for ILP32) means that the
540 // *DAG* representation of pointers will always be 64-bits. They will be
541 // truncated and extended when transferred to memory, but the 64-bit DAG
542 // allows us to use AArch64's addressing modes much more easily.
543 return MVT::getIntegerVT(64);
544 }
545
547 const APInt &DemandedElts,
548 TargetLoweringOpt &TLO) const override;
549
550 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
551
552 /// Returns true if the target allows unaligned memory accesses of the
553 /// specified type.
555 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
557 unsigned *Fast = nullptr) const override;
558 /// LLT variant.
559 bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
560 Align Alignment,
562 unsigned *Fast = nullptr) const override;
563
564 /// Provide custom lowering hooks for some operations.
565 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
566
567 const char *getTargetNodeName(unsigned Opcode) const override;
568
569 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
570
571 /// This method returns a target specific FastISel object, or null if the
572 /// target does not support "fast" ISel.
574 const TargetLibraryInfo *libInfo) const override;
575
576 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
577
578 bool isFPImmLegal(const APFloat &Imm, EVT VT,
579 bool ForCodeSize) const override;
580
581 /// Return true if the given shuffle mask can be codegen'd directly, or if it
582 /// should be stack expanded.
583 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
584
585 /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero'
586 /// shuffle mask can be codegen'd directly.
587 bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
588
589 /// Return the ISD::SETCC ValueType.
591 EVT VT) const override;
592
594
596 MachineBasicBlock *BB) const;
597
599 MachineBasicBlock *BB) const;
600
601 MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
603 MachineBasicBlock *BB) const;
605 MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
607 bool HasTile) const;
609
612 MachineBasicBlock *MBB) const override;
613
614 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
615 MachineFunction &MF,
616 unsigned Intrinsic) const override;
617
619 EVT NewVT) const override;
620
621 bool shouldRemoveRedundantExtend(SDValue Op) const override;
622
623 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
624 bool isTruncateFree(EVT VT1, EVT VT2) const override;
625
626 bool isProfitableToHoist(Instruction *I) const override;
627
628 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
629 bool isZExtFree(EVT VT1, EVT VT2) const override;
630 bool isZExtFree(SDValue Val, EVT VT2) const override;
631
633 SmallVectorImpl<Use *> &Ops) const override;
634
636 Loop *L) const override;
637
638 bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
639
640 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
641
644 ArrayRef<unsigned> Indices,
645 unsigned Factor) const override;
647 unsigned Factor) const override;
648
649 bool isLegalAddImmediate(int64_t) const override;
650 bool isLegalICmpImmediate(int64_t) const override;
651
653 SDValue ConstNode) const override;
654
655 bool shouldConsiderGEPOffsetSplit() const override;
656
657 EVT getOptimalMemOpType(const MemOp &Op,
658 const AttributeList &FuncAttributes) const override;
659
660 LLT getOptimalMemOpLLT(const MemOp &Op,
661 const AttributeList &FuncAttributes) const override;
662
663 /// Return true if the addressing mode represented by AM is legal for this
664 /// target, for a load/store of the specified type.
665 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
666 unsigned AS,
667 Instruction *I = nullptr) const override;
668
669 /// Return true if an FMA operation is faster than a pair of fmul and fadd
670 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
671 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
673 EVT VT) const override;
674 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
675
677 CodeGenOpt::Level OptLevel) const override;
678
679 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
681
682 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
684 CombineLevel Level) const override;
685
686 /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
687 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
688
689 /// Return true if it is profitable to fold a pair of shifts into a mask.
691 CombineLevel Level) const override;
692
693 /// Returns true if it is beneficial to convert a load of a constant
694 /// to just the constant itself.
696 Type *Ty) const override;
697
698 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
699 /// with this index.
700 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
701 unsigned Index) const override;
702
703 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
704 bool MathUsed) const override {
705 // Using overflow ops for overflow checks only should beneficial on
706 // AArch64.
707 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
708 }
709
710 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
711 AtomicOrdering Ord) const override;
713 AtomicOrdering Ord) const override;
714
715 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
716
717 bool isOpSuitableForLDPSTP(const Instruction *I) const;
718 bool isOpSuitableForLSE128(const Instruction *I) const;
719 bool isOpSuitableForRCPC3(const Instruction *I) const;
720 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
721 bool
723
725 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
727 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
729 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
730
733
734 bool useLoadStackGuardNode() const override;
736 getPreferredVectorAction(MVT VT) const override;
737
738 /// If the target has a standard location for the stack protector cookie,
739 /// returns the address of that location. Otherwise, returns nullptr.
740 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
741
742 void insertSSPDeclarations(Module &M) const override;
743 Value *getSDagStackGuard(const Module &M) const override;
744 Function *getSSPStackGuardCheck(const Module &M) const override;
745
746 /// If the target has a standard location for the unsafe stack pointer,
747 /// returns the address of that location. Otherwise, returns nullptr.
748 Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
749
750 /// If a physical register, this returns the register that receives the
751 /// exception address on entry to an EH pad.
753 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
754 // FIXME: This is a guess. Has this been defined yet?
755 return AArch64::X0;
756 }
757
758 /// If a physical register, this returns the register that receives the
759 /// exception typeid on entry to a landing pad.
761 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
762 // FIXME: This is a guess. Has this been defined yet?
763 return AArch64::X1;
764 }
765
766 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
767
768 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
769 const MachineFunction &MF) const override {
770 // Do not merge to float value size (128 bytes) if no implicit
771 // float attribute is set.
772
773 bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
774
775 if (NoFloat)
776 return (MemVT.getSizeInBits() <= 64);
777 return true;
778 }
779
780 bool isCheapToSpeculateCttz(Type *) const override {
781 return true;
782 }
783
784 bool isCheapToSpeculateCtlz(Type *) const override {
785 return true;
786 }
787
788 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
789
790 bool hasAndNotCompare(SDValue V) const override {
791 // We can use bics for any scalar.
792 return V.getValueType().isScalarInteger();
793 }
794
795 bool hasAndNot(SDValue Y) const override {
796 EVT VT = Y.getValueType();
797
798 if (!VT.isVector())
799 return hasAndNotCompare(Y);
800
801 TypeSize TS = VT.getSizeInBits();
802 // TODO: We should be able to use bic/bif too for SVE.
803 return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
804 }
805
808 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
809 SelectionDAG &DAG) const override;
810
813 unsigned ExpansionFactor) const override;
814
816 unsigned KeptBits) const override {
817 // For vectors, we don't have a preference..
818 if (XVT.isVector())
819 return false;
820
821 auto VTIsOk = [](EVT VT) -> bool {
822 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
823 VT == MVT::i64;
824 };
825
826 // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
827 // XVT will be larger than KeptBitsVT.
828 MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
829 return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
830 }
831
832 bool preferIncOfAddToSubOfNot(EVT VT) const override;
833
834 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
835
836 bool isComplexDeinterleavingSupported() const override;
838 ComplexDeinterleavingOperation Operation, Type *Ty) const override;
839
842 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
843 Value *Accumulator = nullptr) const override;
844
845 bool supportSplitCSR(MachineFunction *MF) const override {
847 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
848 }
849 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
851 MachineBasicBlock *Entry,
852 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
853
854 bool supportSwiftError() const override {
855 return true;
856 }
857
858 bool supportKCFIBundles() const override { return true; }
859
860 /// Enable aggressive FMA fusion on targets that want it.
861 bool enableAggressiveFMAFusion(EVT VT) const override;
862
863 /// Returns the size of the platform's va_list object.
864 unsigned getVaListSizeInBits(const DataLayout &DL) const override;
865
866 /// Returns true if \p VecTy is a legal interleaved access type. This
867 /// function checks the vector element type and the overall width of the
868 /// vector.
870 bool &UseScalable) const;
871
872 /// Returns the number of interleaved accesses that will be generated when
873 /// lowering accesses of the given type.
874 unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
875 bool UseScalable) const;
876
878 const Instruction &I) const override;
879
881 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
882 const DataLayout &DL) const override;
883
884 /// Used for exception handling on Win64.
885 bool needsFixedCatchObjects() const override;
886
887 bool fallBackToDAGISel(const Instruction &Inst) const override;
888
889 /// SVE code generation for fixed length vectors does not custom lower
890 /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
891 /// merge. However, merging them creates a BUILD_VECTOR that is just as
892 /// illegal as the original, thus leading to an infinite legalisation loop.
893 /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
894 /// vector types this override can be removed.
895 bool mergeStoresAfterLegalization(EVT VT) const override;
896
897 // If the platform/function should have a redzone, return the size in bytes.
898 unsigned getRedZoneSize(const Function &F) const {
899 if (F.hasFnAttribute(Attribute::NoRedZone))
900 return 0;
901 return 128;
902 }
903
904 bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
906
908 bool AllowUnknown = false) const override;
909
910 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
911
912 /// If a change in streaming mode is required on entry to/return from a
913 /// function call it emits and returns the corresponding SMSTART or SMSTOP node.
914 /// \p Entry tells whether this is before/after the Call, which is necessary
915 /// because PSTATE.SM is only queried once.
917 SDValue Chain, SDValue InFlag,
918 SDValue PStateSM, bool Entry) const;
919
920 bool isVScaleKnownToBeAPowerOfTwo() const override { return true; }
921
922 // Normally SVE is only used for byte size vectors that do not fit within a
923 // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
924 // used for 64bit and 128bit vectors as well.
925 bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
926
927private:
928 /// Keep a pointer to the AArch64Subtarget around so that we can
929 /// make the right decision when generating code for different targets.
930 const AArch64Subtarget *Subtarget;
931
932 bool isExtFreeImpl(const Instruction *Ext) const override;
933
934 void addTypeForNEON(MVT VT);
935 void addTypeForFixedLengthSVE(MVT VT, bool StreamingSVE);
936 void addDRTypeForNEON(MVT VT);
937 void addQRTypeForNEON(MVT VT);
938
939 unsigned allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL,
940 SelectionDAG &DAG) const;
941
942 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
943 bool isVarArg,
945 const SDLoc &DL, SelectionDAG &DAG,
946 SmallVectorImpl<SDValue> &InVals) const override;
947
948 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
949 SmallVectorImpl<SDValue> &InVals) const override;
950
951 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
952 CallingConv::ID CallConv, bool isVarArg,
953 const SmallVectorImpl<CCValAssign> &RVLocs,
954 const SDLoc &DL, SelectionDAG &DAG,
955 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
956 SDValue ThisVal) const;
957
958 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
959 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
960 SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
961 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
962
963 SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
964 SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
965
966 SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
967
968 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
969 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
970 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
971
972 bool
973 isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
974
975 /// Finds the incoming stack arguments which overlap the given fixed stack
976 /// object and incorporates their load into the current chain. This prevents
977 /// an upcoming store from clobbering the stack argument before it's used.
978 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
979 MachineFrameInfo &MFI, int ClobberedFI) const;
980
981 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
982
983 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
984 SDValue &Chain) const;
985
986 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
987 bool isVarArg,
989 LLVMContext &Context) const override;
990
991 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
993 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
994 SelectionDAG &DAG) const override;
995
996 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
997 unsigned Flag) const;
998 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
999 unsigned Flag) const;
1000 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
1001 unsigned Flag) const;
1002 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
1003 unsigned Flag) const;
1004 template <class NodeTy>
1005 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1006 template <class NodeTy>
1007 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1008 template <class NodeTy>
1009 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1010 template <class NodeTy>
1011 SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
1012 SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
1018 const SDLoc &DL, SelectionDAG &DAG) const;
1019 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
1020 SelectionDAG &DAG) const;
1021 SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1023 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1024 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1026 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1027 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
1028 SDValue TVal, SDValue FVal, const SDLoc &dl,
1029 SelectionDAG &DAG) const;
1030 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1031 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
1032 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1033 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1034 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
1035 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
1036 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
1037 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1038 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1039 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1040 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1041 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
1042 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1043 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1044 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
1045 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1046 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1047 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1048 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1049 SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
1050 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1051 SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1052 SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
1053 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
1054 unsigned NewOp) const;
1055 SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
1056 SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
1057 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1058 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
1059 SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1060 SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
1061 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1062 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1063 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
1064 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
1065 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
1066 SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const;
1067 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
1068 SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
1069 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
1070 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
1071 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1072 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1073 SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1074 SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1075 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1076 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1077 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1078 SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1079 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
1080 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1081 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
1082 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
1083 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1084 SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
1085 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1086 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
1087 SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
1088 SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
1089 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1090 SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
1091 SDValue &Size,
1092 SelectionDAG &DAG) const;
1093 SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const;
1094
1095 SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
1096 SelectionDAG &DAG) const;
1097 SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
1098 SelectionDAG &DAG) const;
1099 SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1100 SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1101 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1102 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1103 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
1104 SelectionDAG &DAG) const;
1105 SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
1106 SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
1107 SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
1108 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1109 SelectionDAG &DAG) const;
1110 SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
1111 SelectionDAG &DAG) const;
1112 SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
1113 SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
1114 SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
1115 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
1116 SelectionDAG &DAG) const;
1117 SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
1118 SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
1119 SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
1120 SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
1121 SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
1122 SelectionDAG &DAG) const;
1123
1124 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1125 SmallVectorImpl<SDNode *> &Created) const override;
1126 SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1127 SmallVectorImpl<SDNode *> &Created) const override;
1128 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1129 int &ExtraSteps, bool &UseOneConst,
1130 bool Reciprocal) const override;
1131 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1132 int &ExtraSteps) const override;
1133 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1134 const DenormalMode &Mode) const override;
1135 SDValue getSqrtResultForDenormInput(SDValue Operand,
1136 SelectionDAG &DAG) const override;
1137 unsigned combineRepeatedFPDivisors() const override;
1138
1139 ConstraintType getConstraintType(StringRef Constraint) const override;
1140 Register getRegisterByName(const char* RegName, LLT VT,
1141 const MachineFunction &MF) const override;
1142
1143 /// Examine constraint string and operand type and determine a weight value.
1144 /// The operand object must already have been set up with the operand type.
1146 getSingleConstraintMatchWeight(AsmOperandInfo &info,
1147 const char *constraint) const override;
1148
1149 std::pair<unsigned, const TargetRegisterClass *>
1150 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1151 StringRef Constraint, MVT VT) const override;
1152
1153 const char *LowerXConstraint(EVT ConstraintVT) const override;
1154
1155 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1156 std::vector<SDValue> &Ops,
1157 SelectionDAG &DAG) const override;
1158
1159 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1160 if (ConstraintCode == "Q")
1162 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1163 // followed by llvm_unreachable so we'll leave them unimplemented in
1164 // the backend for now.
1165 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1166 }
1167
1168 bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1169 bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
1170 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1171 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1172 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1173 bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1174 SDValue &Offset, SelectionDAG &DAG) const;
1175 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1177 SelectionDAG &DAG) const override;
1178 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1179 SDValue &Offset, ISD::MemIndexedMode &AM,
1180 SelectionDAG &DAG) const override;
1181
1182 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1183 SelectionDAG &DAG) const override;
1184 void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1185 SelectionDAG &DAG) const;
1186 void ReplaceExtractSubVectorResults(SDNode *N,
1187 SmallVectorImpl<SDValue> &Results,
1188 SelectionDAG &DAG) const;
1189
1190 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1191
1192 void finalizeLowering(MachineFunction &MF) const override;
1193
1194 bool shouldLocalize(const MachineInstr &MI,
1195 const TargetTransformInfo *TTI) const override;
1196
1197 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
1198 const APInt &OriginalDemandedBits,
1199 const APInt &OriginalDemandedElts,
1200 KnownBits &Known,
1201 TargetLoweringOpt &TLO,
1202 unsigned Depth) const override;
1203
1204 bool isTargetCanonicalConstantNode(SDValue Op) const override;
1205
1206 // With the exception of data-predicate transitions, no instructions are
1207 // required to cast between legal scalable vector types. However:
1208 // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1209 // is not universally useable.
1210 // 2. Most unpacked integer types are not legal and thus integer extends
1211 // cannot be used to convert between unpacked and packed types.
1212 // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1213 // to transition between unpacked and packed types of the same element type,
1214 // with BITCAST used otherwise.
1215 // This function does not handle predicate bitcasts.
1216 SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1217
1218 // Returns the runtime value for PSTATE.SM. When the function is streaming-
1219 // compatible, this generates a call to __arm_sme_state.
1220 SDValue getPStateSM(SelectionDAG &DAG, SDValue Chain, SMEAttrs Attrs,
1221 SDLoc DL, EVT VT) const;
1222
1223 bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
1224 LLT Ty2) const override;
1225};
1226
1227namespace AArch64 {
1228FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1229 const TargetLibraryInfo *libInfo);
1230} // end namespace AArch64
1231
1232} // end namespace llvm
1233
1234#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const char LLVMTargetMachineRef TM
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
This file describes how to lower LLVM code to machine code.
@ Flags
Definition: TextStubV5.cpp:93
Value * RHS
Value * LHS
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
bool shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering f...
bool optimizeExtendOrTruncateConversion(Instruction *I, Loop *L) const override
Try to optimize extending or truncating conversion instructions (like zext, trunc,...
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOpt::Level OptLevel) const override
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveRedundantExtend(SDValue Op) const override
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant,...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
MachineBasicBlock * EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB, bool HasTile) const
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
bool isOpSuitableForLSE128(const Instruction *I) const
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
bool fallBackToDAGISel(const Instruction &Inst) const override
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InFlag, SDValue PStateSM, bool Entry) const
If a change in streaming mode is required on entry to/return from a function call it emits and return...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
bool isOpSuitableForRCPC3(const Instruction *I) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
unsigned getRedZoneSize(const Function &F) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isOpSuitableForLDPSTP(const Instruction *I) const
Value * createComplexDeinterleavingIR(Instruction *I, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool shouldConsiderGEPOffsetSplit() const override
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const override
Similar to isShuffleMaskLegal.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
ArrayRef< MCPhysReg > getRoundingControlRegisters() const override
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) const
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:237
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:644
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
Machine Value Type.
static MVT getIntegerVT(unsigned BitWidth)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Provides information about what library functions are available for the current target.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:182
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:166
@ NVCAST
Natural vector cast.
const ArrayRef< MCPhysReg > getFPRArgRegs()
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
const ArrayRef< MCPhysReg > getGPRArgRegs()
const unsigned RoundingBitsPos
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1324
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1336
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1396
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1330
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1447
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1427
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
AddressSpace
Definition: NVPTXBaseInfo.h:21
AtomicOrdering
Atomic ordering for LLVM's memory model.
TargetTransformInfo TTI
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
@ Enable
Enable colors.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Represent subnormal handling kind for floating point instruction inputs and outputs.
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160