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AArch64ISelLowering.h
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1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 
17 #include "AArch64.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Instruction.h"
24 
25 namespace llvm {
26 
27 namespace AArch64ISD {
28 
29 // For predicated nodes where the result is a vector, the operation is
30 // controlled by a governing predicate and the inactive lanes are explicitly
31 // defined with a value, please stick the following naming convention:
32 //
33 // _MERGE_OP<n> The result value is a vector with inactive lanes equal
34 // to source operand OP<n>.
35 //
36 // _MERGE_ZERO The result value is a vector with inactive lanes
37 // actively zeroed.
38 //
39 // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
40 // to the last source operand which only purpose is being
41 // a passthru value.
42 //
43 // For other cases where no explicit action is needed to set the inactive lanes,
44 // or when the result is not a vector and it is needed or helpful to
45 // distinguish a node from similar unpredicated nodes, use:
46 //
47 // _PRED
48 //
49 enum NodeType : unsigned {
51  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
52  CALL, // Function call.
53 
54  // Pseudo for a OBJC call that gets emitted together with a special `mov
55  // x29, x29` marker instruction.
57 
58  CALL_BTI, // Function call followed by a BTI instruction.
59 
60  // Produces the full sequence of instructions for getting the thread pointer
61  // offset of a variable into X0, using the TLSDesc model.
63  ADRP, // Page address of a TargetGlobalAddress operand.
64  ADR, // ADR
65  ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
66  LOADgot, // Load from automatically generated descriptor (e.g. Global
67  // Offset Table, TLS record).
68  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
69  BRCOND, // Conditional branch instruction; "b.cond".
71  CSINV, // Conditional select invert.
72  CSNEG, // Conditional select negate.
73  CSINC, // Conditional select increment.
74 
75  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
76  // ELF.
78  ADC,
79  SBC, // adc, sbc instructions
80 
81  // Predicated instructions where inactive lanes produce undefined results.
105 
106  // Unpredicated vector instructions
108 
110 
111  // Predicated instructions with the result of inactive lanes provided by the
112  // last operand.
134 
136 
137  // Arithmetic instructions which write flags.
143 
144  // Conditional compares. Operands: left,right,falsecc,cc,flags
148 
149  // Floating point comparison
151 
152  // Scalar extract
154 
155  // Scalar-to-vector duplication
161 
162  // Vector immedate moves
170 
171  // Vector immediate ops
174 
175  // Vector bitwise select: similar to ISD::VSELECT but not all bits within an
176  // element must be identical.
178 
179  // Vector shuffles
191 
192  // Vector shift by scalar
196 
197  // Vector shift by scalar (again)
203 
204  // Vector shift by constant and insert
207 
208  // Vector comparisons
217 
218  // Vector zero comparisons
229 
230  // Vector across-lanes addition
231  // Only the lower result lane is defined.
234 
235  // Add Pairwise of two vectors
237  // Add Long Pairwise
240 
241  // udot/sdot instructions
244 
245  // Vector across-lanes min/max
246  // Only the lower result lane is defined.
251 
261 
262  // Vector bitwise insertion
264 
265  // Compare-and-branch
270 
271  // Tail calls
273 
274  // Custom prefetch handling
276 
277  // {s|u}int to FP within a FP register.
280 
281  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
282  /// world w.r.t vectors; which causes additional REV instructions to be
283  /// generated to compensate for the byte-swapping. But sometimes we do
284  /// need to re-interpret the data in SIMD vector registers in big-endian
285  /// mode without emitting such REV instructions.
287 
288  MRS, // MRS, also sets the flags via a glue.
289 
292 
293  // Reciprocal estimates and steps.
298 
303 
309 
310  // Floating-point reductions.
317 
321 
330 
331  // Cast between vectors of the same element type but differ in length.
333 
334  // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa
337 
346 
347  // Structured loads.
351 
352  // Unsigned gather loads.
360 
361  // Signed gather loads
369 
370  // Unsigned gather loads.
378 
379  // Signed gather loads.
387 
388  // Non-temporal gather loads
392 
393  // Contiguous masked store.
395 
396  // Scatter store
404 
405  // Non-temporal scatter store
408 
409  // SME
412 
413  // Asserts that a function argument (i32) is zero-extended to i8 by
414  // the caller
416 
417  // Strict (exception-raising) floating point comparison
420 
421  // NEON Load/Store with post-increment base updates
445 
450 
454 
455  // Memory Operations
460 };
461 
462 } // end namespace AArch64ISD
463 
464 namespace AArch64 {
465 /// Possible values of current rounding mode, which is specified in bits
466 /// 23:22 of FPCR.
467 enum Rounding {
468  RN = 0, // Round to Nearest
469  RP = 1, // Round towards Plus infinity
470  RM = 2, // Round towards Minus infinity
471  RZ = 3, // Round towards Zero
472  rmMask = 3 // Bit mask selecting rounding mode
473 };
474 
475 // Bit position of rounding mode bits in FPCR.
476 const unsigned RoundingBitsPos = 22;
477 } // namespace AArch64
478 
479 class AArch64Subtarget;
480 
482 public:
483  explicit AArch64TargetLowering(const TargetMachine &TM,
484  const AArch64Subtarget &STI);
485 
486  /// Control the following reassociation of operands: (op (op x, c1), y) -> (op
487  /// (op x, y), c1) where N0 is (op x, c1) and N1 is y.
489  SDValue N1) const override;
490 
491  /// Selects the correct CCAssignFn for a given CallingConvention value.
492  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
493 
494  /// Selects the correct CCAssignFn for a given CallingConvention value.
496 
497  /// Determine which of the bits specified in Mask are known to be either zero
498  /// or one and return them in the KnownZero/KnownOne bitsets.
500  const APInt &DemandedElts,
501  const SelectionDAG &DAG,
502  unsigned Depth = 0) const override;
503 
504  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override {
505  // Returning i64 unconditionally here (i.e. even for ILP32) means that the
506  // *DAG* representation of pointers will always be 64-bits. They will be
507  // truncated and extended when transferred to memory, but the 64-bit DAG
508  // allows us to use AArch64's addressing modes much more easily.
509  return MVT::getIntegerVT(64);
510  }
511 
513  const APInt &DemandedElts,
514  TargetLoweringOpt &TLO) const override;
515 
516  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
517 
518  /// Returns true if the target allows unaligned memory accesses of the
519  /// specified type.
521  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
523  bool *Fast = nullptr) const override;
524  /// LLT variant.
525  bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace,
526  Align Alignment,
528  bool *Fast = nullptr) const override;
529 
530  /// Provide custom lowering hooks for some operations.
531  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
532 
533  const char *getTargetNodeName(unsigned Opcode) const override;
534 
535  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
536 
537  /// This method returns a target specific FastISel object, or null if the
538  /// target does not support "fast" ISel.
540  const TargetLibraryInfo *libInfo) const override;
541 
542  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
543 
544  bool isFPImmLegal(const APFloat &Imm, EVT VT,
545  bool ForCodeSize) const override;
546 
547  /// Return true if the given shuffle mask can be codegen'd directly, or if it
548  /// should be stack expanded.
549  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
550 
551  /// Return the ISD::SETCC ValueType.
553  EVT VT) const override;
554 
556 
558  MachineBasicBlock *BB) const;
559 
561  MachineBasicBlock *BB) const;
562 
563  MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
564  MachineInstr &MI,
565  MachineBasicBlock *BB) const;
567  MachineBasicBlock *EmitMopa(unsigned Opc, unsigned BaseReg, MachineInstr &MI,
568  MachineBasicBlock *BB) const;
569  MachineBasicBlock *EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg,
570  MachineInstr &MI,
571  MachineBasicBlock *BB) const;
573 
576  MachineBasicBlock *MBB) const override;
577 
578  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
579  MachineFunction &MF,
580  unsigned Intrinsic) const override;
581 
583  EVT NewVT) const override;
584 
585  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
586  bool isTruncateFree(EVT VT1, EVT VT2) const override;
587 
588  bool isProfitableToHoist(Instruction *I) const override;
589 
590  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
591  bool isZExtFree(EVT VT1, EVT VT2) const override;
592  bool isZExtFree(SDValue Val, EVT VT2) const override;
593 
595  SmallVectorImpl<Use *> &Ops) const override;
596 
597  bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override;
598 
599  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
600 
603  ArrayRef<unsigned> Indices,
604  unsigned Factor) const override;
606  unsigned Factor) const override;
607 
608  bool isLegalAddImmediate(int64_t) const override;
609  bool isLegalICmpImmediate(int64_t) const override;
610 
612  SDValue ConstNode) const override;
613 
614  bool shouldConsiderGEPOffsetSplit() const override;
615 
617  const AttributeList &FuncAttributes) const override;
618 
620  const AttributeList &FuncAttributes) const override;
621 
622  /// Return true if the addressing mode represented by AM is legal for this
623  /// target, for a load/store of the specified type.
624  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
625  unsigned AS,
626  Instruction *I = nullptr) const override;
627 
628  /// Return the cost of the scaling factor used in the addressing
629  /// mode represented by AM for this target, for a load/store
630  /// of the specified type.
631  /// If the AM is supported, the return value must be >= 0.
632  /// If the AM is not supported, it returns a negative value.
634  Type *Ty, unsigned AS) const override;
635 
636  /// Return true if an FMA operation is faster than a pair of fmul and fadd
637  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
638  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
640  EVT VT) const override;
641  bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
642 
644  CodeGenOpt::Level OptLevel) const override;
645 
646  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
647 
648  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
650  CombineLevel Level) const override;
651 
652  /// Return true if it is profitable to fold a pair of shifts into a mask.
654  CombineLevel Level) const override;
655 
656  /// Returns true if it is beneficial to convert a load of a constant
657  /// to just the constant itself.
659  Type *Ty) const override;
660 
661  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
662  /// with this index.
663  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
664  unsigned Index) const override;
665 
666  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
667  bool MathUsed) const override {
668  // Using overflow ops for overflow checks only should beneficial on
669  // AArch64.
670  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
671  }
672 
674  AtomicOrdering Ord) const override;
676  AtomicOrdering Ord) const override;
677 
679 
680  bool isOpSuitableForLDPSTP(const Instruction *I) const;
681  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
682 
684  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
686  shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
688  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
689 
692 
693  bool useLoadStackGuardNode() const override;
695  getPreferredVectorAction(MVT VT) const override;
696 
697  /// If the target has a standard location for the stack protector cookie,
698  /// returns the address of that location. Otherwise, returns nullptr.
699  Value *getIRStackGuard(IRBuilderBase &IRB) const override;
700 
701  void insertSSPDeclarations(Module &M) const override;
702  Value *getSDagStackGuard(const Module &M) const override;
703  Function *getSSPStackGuardCheck(const Module &M) const override;
704 
705  /// If the target has a standard location for the unsafe stack pointer,
706  /// returns the address of that location. Otherwise, returns nullptr.
707  Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
708 
709  /// If a physical register, this returns the register that receives the
710  /// exception address on entry to an EH pad.
711  Register
712  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
713  // FIXME: This is a guess. Has this been defined yet?
714  return AArch64::X0;
715  }
716 
717  /// If a physical register, this returns the register that receives the
718  /// exception typeid on entry to a landing pad.
719  Register
720  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
721  // FIXME: This is a guess. Has this been defined yet?
722  return AArch64::X1;
723  }
724 
725  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
726 
727  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
728  const MachineFunction &MF) const override {
729  // Do not merge to float value size (128 bytes) if no implicit
730  // float attribute is set.
731 
732  bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
733 
734  if (NoFloat)
735  return (MemVT.getSizeInBits() <= 64);
736  return true;
737  }
738 
739  bool isCheapToSpeculateCttz() const override {
740  return true;
741  }
742 
743  bool isCheapToSpeculateCtlz() const override {
744  return true;
745  }
746 
747  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
748 
749  bool hasAndNotCompare(SDValue V) const override {
750  // We can use bics for any scalar.
751  return V.getValueType().isScalarInteger();
752  }
753 
754  bool hasAndNot(SDValue Y) const override {
755  EVT VT = Y.getValueType();
756 
757  if (!VT.isVector())
758  return hasAndNotCompare(Y);
759 
760  TypeSize TS = VT.getSizeInBits();
761  // TODO: We should be able to use bic/bif too for SVE.
762  return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
763  }
764 
767  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
768  SelectionDAG &DAG) const override;
769 
770  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
771 
773  unsigned KeptBits) const override {
774  // For vectors, we don't have a preference..
775  if (XVT.isVector())
776  return false;
777 
778  auto VTIsOk = [](EVT VT) -> bool {
779  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
780  VT == MVT::i64;
781  };
782 
783  // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
784  // XVT will be larger than KeptBitsVT.
785  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
786  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
787  }
788 
789  bool preferIncOfAddToSubOfNot(EVT VT) const override;
790 
791  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
792 
793  bool hasBitPreservingFPLogic(EVT VT) const override {
794  // FIXME: Is this always true? It should be true for vectors at least.
795  return VT == MVT::f32 || VT == MVT::f64;
796  }
797 
798  bool supportSplitCSR(MachineFunction *MF) const override {
800  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
801  }
802  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
804  MachineBasicBlock *Entry,
805  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
806 
807  bool supportSwiftError() const override {
808  return true;
809  }
810 
811  /// Enable aggressive FMA fusion on targets that want it.
812  bool enableAggressiveFMAFusion(EVT VT) const override;
813 
814  /// Returns the size of the platform's va_list object.
815  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
816 
817  /// Returns true if \p VecTy is a legal interleaved access type. This
818  /// function checks the vector element type and the overall width of the
819  /// vector.
821  bool &UseScalable) const;
822 
823  /// Returns the number of interleaved accesses that will be generated when
824  /// lowering accesses of the given type.
825  unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL,
826  bool UseScalable) const;
827 
829  const Instruction &I) const override;
830 
832  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
833  const DataLayout &DL) const override;
834 
835  /// Used for exception handling on Win64.
836  bool needsFixedCatchObjects() const override;
837 
838  bool fallBackToDAGISel(const Instruction &Inst) const override;
839 
840  /// SVE code generation for fixed length vectors does not custom lower
841  /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
842  /// merge. However, merging them creates a BUILD_VECTOR that is just as
843  /// illegal as the original, thus leading to an infinite legalisation loop.
844  /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
845  /// vector types this override can be removed.
846  bool mergeStoresAfterLegalization(EVT VT) const override;
847 
848  // If the platform/function should have a redzone, return the size in bytes.
849  unsigned getRedZoneSize(const Function &F) const {
850  if (F.hasFnAttribute(Attribute::NoRedZone))
851  return 0;
852  return 128;
853  }
854 
855  bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
857 
859  bool AllowUnknown = false) const override;
860 
861  bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
862 
863 private:
864  /// Keep a pointer to the AArch64Subtarget around so that we can
865  /// make the right decision when generating code for different targets.
866  const AArch64Subtarget *Subtarget;
867 
868  bool isExtFreeImpl(const Instruction *Ext) const override;
869 
870  void addTypeForNEON(MVT VT);
871  void addTypeForFixedLengthSVE(MVT VT);
872  void addDRTypeForNEON(MVT VT);
873  void addQRTypeForNEON(MVT VT);
874 
875  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
876  bool isVarArg,
878  const SDLoc &DL, SelectionDAG &DAG,
879  SmallVectorImpl<SDValue> &InVals) const override;
880 
881  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
882  SmallVectorImpl<SDValue> &InVals) const override;
883 
884  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
885  CallingConv::ID CallConv, bool isVarArg,
887  const SDLoc &DL, SelectionDAG &DAG,
888  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
889  SDValue ThisVal) const;
890 
891  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
892  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
893  SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
894  SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
895 
896  SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
897  SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
898 
899  SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
900 
901  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
902  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
903 
904  bool
905  isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const;
906 
907  /// Finds the incoming stack arguments which overlap the given fixed stack
908  /// object and incorporates their load into the current chain. This prevents
909  /// an upcoming store from clobbering the stack argument before it's used.
910  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
911  MachineFrameInfo &MFI, int ClobberedFI) const;
912 
913  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
914 
915  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
916  SDValue &Chain) const;
917 
918  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
919  bool isVarArg,
921  LLVMContext &Context) const override;
922 
923  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
925  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
926  SelectionDAG &DAG) const override;
927 
928  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
929  unsigned Flag) const;
930  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
931  unsigned Flag) const;
932  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
933  unsigned Flag) const;
934  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
935  unsigned Flag) const;
936  template <class NodeTy>
937  SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
938  template <class NodeTy>
939  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
940  template <class NodeTy>
941  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
942  template <class NodeTy>
943  SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
944  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
945  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
946  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
947  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
948  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
949  SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase,
950  const SDLoc &DL, SelectionDAG &DAG) const;
951  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
952  SelectionDAG &DAG) const;
953  SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
954  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
955  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
956  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
957  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
958  SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
959  SDValue TVal, SDValue FVal, const SDLoc &dl,
960  SelectionDAG &DAG) const;
961  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
962  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
963  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
964  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
965  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
966  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
967  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
968  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
969  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
970  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
971  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
972  SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
973  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
974  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
975  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
976  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
977  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
978  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
979  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
980  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
981  SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
982  SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
983  SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
984  unsigned NewOp) const;
985  SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
986  SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
987  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
988  SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
989  SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
990  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
991  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
992  SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
993  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
994  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
995  SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
996  SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
997  SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
998  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
999  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1000  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
1001  SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1002  SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1003  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1004  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
1005  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1006  SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1007  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
1008  SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1009  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
1010  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
1011  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1012  SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;
1013  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1014  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
1015  SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
1016  SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
1017  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1018  SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
1019  SDValue &Size,
1020  SelectionDAG &DAG) const;
1021  SDValue LowerSVEStructLoad(unsigned Intrinsic, ArrayRef<SDValue> LoadOps,
1022  EVT VT, SelectionDAG &DAG, const SDLoc &DL) const;
1023 
1024  SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
1025  SelectionDAG &DAG) const;
1026  SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
1027  SelectionDAG &DAG) const;
1028  SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1029  SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
1030  SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1031  SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1032  SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
1033  SelectionDAG &DAG) const;
1034  SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const;
1035  SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
1036  SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
1037  SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1038  SelectionDAG &DAG) const;
1039  SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
1040  SelectionDAG &DAG) const;
1041  SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
1042  SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const;
1043  SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const;
1044  SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
1045  SelectionDAG &DAG) const;
1046  SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const;
1047  SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const;
1048  SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const;
1049  SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
1050  SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op,
1051  SelectionDAG &DAG) const;
1052 
1053  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1054  SmallVectorImpl<SDNode *> &Created) const override;
1055  SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1056  SmallVectorImpl<SDNode *> &Created) const override;
1057  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1058  int &ExtraSteps, bool &UseOneConst,
1059  bool Reciprocal) const override;
1060  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1061  int &ExtraSteps) const override;
1062  SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
1063  const DenormalMode &Mode) const override;
1064  SDValue getSqrtResultForDenormInput(SDValue Operand,
1065  SelectionDAG &DAG) const override;
1066  unsigned combineRepeatedFPDivisors() const override;
1067 
1068  ConstraintType getConstraintType(StringRef Constraint) const override;
1069  Register getRegisterByName(const char* RegName, LLT VT,
1070  const MachineFunction &MF) const override;
1071 
1072  /// Examine constraint string and operand type and determine a weight value.
1073  /// The operand object must already have been set up with the operand type.
1075  getSingleConstraintMatchWeight(AsmOperandInfo &info,
1076  const char *constraint) const override;
1077 
1078  std::pair<unsigned, const TargetRegisterClass *>
1079  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1080  StringRef Constraint, MVT VT) const override;
1081 
1082  const char *LowerXConstraint(EVT ConstraintVT) const override;
1083 
1084  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1085  std::vector<SDValue> &Ops,
1086  SelectionDAG &DAG) const override;
1087 
1088  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1089  if (ConstraintCode == "Q")
1090  return InlineAsm::Constraint_Q;
1091  // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
1092  // followed by llvm_unreachable so we'll leave them unimplemented in
1093  // the backend for now.
1094  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1095  }
1096 
1097  bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
1098  bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
1099  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
1100  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1101  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1102  bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
1103  ISD::MemIndexedMode &AM, bool &IsInc,
1104  SelectionDAG &DAG) const;
1105  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
1106  ISD::MemIndexedMode &AM,
1107  SelectionDAG &DAG) const override;
1108  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
1109  SDValue &Offset, ISD::MemIndexedMode &AM,
1110  SelectionDAG &DAG) const override;
1111 
1112  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1113  SelectionDAG &DAG) const override;
1114  void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1115  SelectionDAG &DAG) const;
1116  void ReplaceExtractSubVectorResults(SDNode *N,
1117  SmallVectorImpl<SDValue> &Results,
1118  SelectionDAG &DAG) const;
1119 
1120  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
1121 
1122  void finalizeLowering(MachineFunction &MF) const override;
1123 
1124  bool shouldLocalize(const MachineInstr &MI,
1125  const TargetTransformInfo *TTI) const override;
1126 
1127  bool SimplifyDemandedBitsForTargetNode(SDValue Op,
1128  const APInt &OriginalDemandedBits,
1129  const APInt &OriginalDemandedElts,
1130  KnownBits &Known,
1131  TargetLoweringOpt &TLO,
1132  unsigned Depth) const override;
1133 
1134  bool isTargetCanonicalConstantNode(SDValue Op) const override;
1135 
1136  // Normally SVE is only used for byte size vectors that do not fit within a
1137  // NEON vector. This changes when OverrideNEON is true, allowing SVE to be
1138  // used for 64bit and 128bit vectors as well.
1139  bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const;
1140 
1141  // With the exception of data-predicate transitions, no instructions are
1142  // required to cast between legal scalable vector types. However:
1143  // 1. Packed and unpacked types have different bit lengths, meaning BITCAST
1144  // is not universally useable.
1145  // 2. Most unpacked integer types are not legal and thus integer extends
1146  // cannot be used to convert between unpacked and packed types.
1147  // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
1148  // to transition between unpacked and packed types of the same element type,
1149  // with BITCAST used otherwise.
1150  SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
1151 
1152  bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
1153  LLT Ty2) const override;
1154 };
1155 
1156 namespace AArch64 {
1157 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1158  const TargetLibraryInfo *libInfo);
1159 } // end namespace AArch64
1160 
1161 } // end namespace llvm
1162 
1163 #endif
llvm::AArch64ISD::LD1x2post
@ LD1x2post
Definition: AArch64ISelLowering.h:428
llvm::AArch64ISD::MOPS_MEMSET_TAGGING
@ MOPS_MEMSET_TAGGING
Definition: AArch64ISelLowering.h:457
llvm::AArch64ISD::EORV_PRED
@ EORV_PRED
Definition: AArch64ISelLowering.h:259
llvm::AArch64ISD::NodeType
NodeType
Definition: AArch64ISelLowering.h:49
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::AArch64ISD::LD2DUPpost
@ LD2DUPpost
Definition: AArch64ISelLowering.h:435
llvm::AArch64ISD::SVE_LD4_MERGE_ZERO
@ SVE_LD4_MERGE_ZERO
Definition: AArch64ISelLowering.h:350
llvm::AArch64ISD::UMULL
@ UMULL
Definition: AArch64ISelLowering.h:291
llvm::AArch64ISD::LOADgot
@ LOADgot
Definition: AArch64ISelLowering.h:66
llvm::AArch64ISD::LD3post
@ LD3post
Definition: AArch64ISelLowering.h:423
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::AArch64ISD::UUNPKHI
@ UUNPKHI
Definition: AArch64ISelLowering.h:301
llvm::AArch64ISD::VLSHR
@ VLSHR
Definition: AArch64ISelLowering.h:194
llvm::AArch64ISD::SSTNT1_INDEX_PRED
@ SSTNT1_INDEX_PRED
Definition: AArch64ISelLowering.h:407
llvm::AArch64ISD::ST1x4post
@ ST1x4post
Definition: AArch64ISelLowering.h:433
llvm::AArch64ISD::UMINV
@ UMINV
Definition: AArch64ISelLowering.h:248
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1360
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::AArch64TargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: AArch64ISelLowering.cpp:20256
llvm::AArch64ISD::CLASTA_N
@ CLASTA_N
Definition: AArch64ISelLowering.h:304
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AArch64TargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: AArch64ISelLowering.cpp:19966
llvm::AArch64TargetLowering::generateFMAsInMachineCombiner
bool generateFMAsInMachineCombiner(EVT VT, CodeGenOpt::Level OptLevel) const override
Definition: AArch64ISelLowering.cpp:13497
llvm::AArch64ISD::ADDP
@ ADDP
Definition: AArch64ISelLowering.h:236
AArch64.h
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::AArch64TargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: AArch64ISelLowering.cpp:20263
llvm::AArch64TargetLowering::EmitMopa
MachineBasicBlock * EmitMopa(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2378
llvm::AArch64TargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: AArch64ISelLowering.h:666
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:259
llvm::AArch64ISD::FMINV_PRED
@ FMINV_PRED
Definition: AArch64ISelLowering.h:315
llvm::AArch64ISD::SITOF
@ SITOF
Definition: AArch64ISelLowering.h:278
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AArch64TargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: AArch64ISelLowering.cpp:1767
llvm::AArch64TargetLowering::EmitInsertVectorToTile
MachineBasicBlock * EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2395
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4419
llvm::AArch64ISD::FCMGEz
@ FCMGEz
Definition: AArch64ISelLowering.h:225
llvm::AArch64TargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Definition: AArch64ISelLowering.cpp:1972
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::AArch64ISD::SMAX_PRED
@ SMAX_PRED
Definition: AArch64ISelLowering.h:98
llvm::AArch64ISD::CCMN
@ CCMN
Definition: AArch64ISelLowering.h:146
llvm::AArch64ISD::DUP_MERGE_PASSTHRU
@ DUP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:328
llvm::AArch64TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: AArch64ISelLowering.cpp:13382
llvm::AArch64TargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: AArch64ISelLowering.cpp:20107
llvm::AArch64ISD::FCMLEz
@ FCMLEz
Definition: AArch64ISelLowering.h:227
llvm::AArch64ISD::CTPOP_MERGE_PASSTHRU
@ CTPOP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:327
llvm::AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO
@ GLDFF1S_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:384
llvm::AArch64ISD::PREFETCH
@ PREFETCH
Definition: AArch64ISelLowering.h:275
llvm::Function
Definition: Function.h:60
llvm::AArch64TargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: AArch64ISelLowering.h:798
llvm::AArch64ISD::UMAX_PRED
@ UMAX_PRED
Definition: AArch64ISelLowering.h:103
llvm::AArch64TargetLowering::needsFixedCatchObjects
bool needsFixedCatchObjects() const override
Used for exception handling on Win64.
Definition: AArch64ISelLowering.cpp:20429
llvm::AArch64ISD::TC_RETURN
@ TC_RETURN
Definition: AArch64ISelLowering.h:272
llvm::AArch64TargetLowering::EmitTileLoad
MachineBasicBlock * EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2344
llvm::AArch64ISD::CTLZ_MERGE_PASSTHRU
@ CTLZ_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:326
llvm::AArch64ISD::LD3LANEpost
@ LD3LANEpost
Definition: AArch64ISelLowering.h:440
llvm::AArch64ISD::SST1_UXTW_SCALED_PRED
@ SST1_UXTW_SCALED_PRED
Definition: AArch64ISelLowering.h:401
llvm::AArch64ISD::SBCS
@ SBCS
Definition: AArch64ISelLowering.h:141
llvm::AArch64ISD::TBNZ
@ TBNZ
Definition: AArch64ISelLowering.h:269
llvm::AArch64ISD::FMAXNMV_PRED
@ FMAXNMV_PRED
Definition: AArch64ISelLowering.h:314
llvm::AArch64ISD::SADDV
@ SADDV
Definition: AArch64ISelLowering.h:232
llvm::AArch64ISD::ASSERT_ZEXT_BOOL
@ ASSERT_ZEXT_BOOL
Definition: AArch64ISelLowering.h:415
llvm::AArch64ISD::LD1x3post
@ LD1x3post
Definition: AArch64ISelLowering.h:429
llvm::AArch64ISD::UZP1
@ UZP1
Definition: AArch64ISelLowering.h:182
llvm::AArch64ISD::ZIP1
@ ZIP1
Definition: AArch64ISelLowering.h:180
llvm::AArch64ISD::MULHU_PRED
@ MULHU_PRED
Definition: AArch64ISelLowering.h:95
llvm::AArch64TargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
Definition: AArch64ISelLowering.cpp:13515
llvm::AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO
@ GLDFF1S_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:381
llvm::AArch64ISD::CMHS
@ CMHS
Definition: AArch64ISelLowering.h:213
llvm::AArch64ISD::STNP
@ STNP
Definition: AArch64ISelLowering.h:453
llvm::AArch64ISD::BIC
@ BIC
Definition: AArch64ISelLowering.h:107
llvm::AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO
@ GLD1_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:358
llvm::AArch64ISD::ST3LANEpost
@ ST3LANEpost
Definition: AArch64ISelLowering.h:443
llvm::AArch64ISD::UMIN_PRED
@ UMIN_PRED
Definition: AArch64ISelLowering.h:104
llvm::AArch64ISD::FCEIL_MERGE_PASSTHRU
@ FCEIL_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:114
llvm::AArch64ISD::LD2post
@ LD2post
Definition: AArch64ISelLowering.h:422
llvm::AArch64ISD::MULHS_PRED
@ MULHS_PRED
Definition: AArch64ISelLowering.h:94
llvm::AArch64ISD::FRECPX_MERGE_PASSTHRU
@ FRECPX_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:118
llvm::AArch64ISD::STG
@ STG
Definition: AArch64ISelLowering.h:446
llvm::AArch64ISD::CMGE
@ CMGE
Definition: AArch64ISelLowering.h:210
llvm::AArch64TargetLowering::getAsmOperandValueType
EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const override
Definition: AArch64ISelLowering.cpp:9056
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::AArch64ISD::FCMGTz
@ FCMGTz
Definition: AArch64ISelLowering.h:226
llvm::AArch64ISD::SMAXV_PRED
@ SMAXV_PRED
Definition: AArch64ISelLowering.h:254
llvm::AArch64ISD::CMLTz
@ CMLTz
Definition: AArch64ISelLowering.h:223
llvm::AArch64TargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: AArch64ISelLowering.cpp:13504
llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: AArch64ISelLowering.cpp:1921
llvm::AArch64ISD::FMAX_PRED
@ FMAX_PRED
Definition: AArch64ISelLowering.h:87
llvm::MemOp
Definition: TargetLowering.h:111
llvm::AArch64ISD::DUP
@ DUP
Definition: AArch64ISelLowering.h:156
llvm::AArch64TargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: AArch64ISelLowering.h:599
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::AArch64ISD::FCVTZS_MERGE_PASSTHRU
@ FCVTZS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:129
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::AArch64ISD::LDFF1_MERGE_ZERO
@ LDFF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:342
llvm::AArch64ISD::ST1x2post
@ ST1x2post
Definition: AArch64ISelLowering.h:431
llvm::AArch64TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: AArch64ISelLowering.cpp:12435
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AArch64ISD::MOVIshift
@ MOVIshift
Definition: AArch64ISelLowering.h:164
llvm::AArch64ISD::LDP
@ LDP
Definition: AArch64ISelLowering.h:451
llvm::AttributeList
Definition: Attributes.h:425
llvm::AArch64TargetLowering::isOpSuitableForLDPSTP
bool isOpSuitableForLDPSTP(const Instruction *I) const
Definition: AArch64ISelLowering.cpp:19991
llvm::AArch64TargetLowering::ReconstructShuffle
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
Definition: AArch64ISelLowering.cpp:9253
llvm::AArch64ISD::MOPS_MEMSET
@ MOPS_MEMSET
Definition: AArch64ISelLowering.h:456
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::AArch64ISD::GLDNT1_MERGE_ZERO
@ GLDNT1_MERGE_ZERO
Definition: AArch64ISelLowering.h:389
llvm::AArch64ISD::GLDFF1_UXTW_MERGE_ZERO
@ GLDFF1_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:373
llvm::AArch64TargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
Definition: AArch64ISelLowering.cpp:12400
llvm::AArch64ISD::CALL_RVMARKER
@ CALL_RVMARKER
Definition: AArch64ISelLowering.h:56
llvm::AArch64ISD::CBZ
@ CBZ
Definition: AArch64ISelLowering.h:266
llvm::AArch64ISD::FFLOOR_MERGE_PASSTHRU
@ FFLOOR_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:115
llvm::AArch64ISD::ADC
@ ADC
Definition: AArch64ISelLowering.h:78
llvm::AArch64TargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: AArch64ISelLowering.cpp:13445
llvm::AArch64TargetLowering::EmitLoweredCatchRet
MachineBasicBlock * EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2335
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::AArch64TargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) const
Returns true if VecTy is a legal interleaved access type.
Definition: AArch64ISelLowering.cpp:12825
llvm::AArch64ISD::SMINV_PRED
@ SMINV_PRED
Definition: AArch64ISelLowering.h:256
llvm::AArch64ISD::MOVImsl
@ MOVImsl
Definition: AArch64ISelLowering.h:166
llvm::AArch64ISD::GLDFF1_MERGE_ZERO
@ GLDFF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:371
llvm::AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO
@ GLDFF1S_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:382
llvm::AArch64ISD::FCMGT
@ FCMGT
Definition: AArch64ISelLowering.h:216
llvm::AArch64ISD::TRN2
@ TRN2
Definition: AArch64ISelLowering.h:185
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::AArch64ISD::GLDFF1_IMM_MERGE_ZERO
@ GLDFF1_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:377
llvm::AArch64ISD::CCMP
@ CCMP
Definition: AArch64ISelLowering.h:145
llvm::AArch64ISD::FMINNMV_PRED
@ FMINNMV_PRED
Definition: AArch64ISelLowering.h:316
llvm::AArch64ISD::URSHR_I
@ URSHR_I
Definition: AArch64ISelLowering.h:202
llvm::AArch64ISD::FRECPS
@ FRECPS
Definition: AArch64ISelLowering.h:295
llvm::AArch64ISD::GLD1S_IMM_MERGE_ZERO
@ GLD1S_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:368
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2165
llvm::AArch64ISD::REV32
@ REV32
Definition: AArch64ISelLowering.h:187
llvm::AArch64ISD::TLSDESC_CALLSEQ
@ TLSDESC_CALLSEQ
Definition: AArch64ISelLowering.h:62
SelectionDAG.h
llvm::AArch64ISD::RDSVL
@ RDSVL
Definition: AArch64ISelLowering.h:410
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AArch64ISD::LD1x4post
@ LD1x4post
Definition: AArch64ISelLowering.h:430
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::AArch64TargetLowering::isAllActivePredicate
bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const
Definition: AArch64ISelLowering.cpp:21495
llvm::AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO
@ GLD1S_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:366
llvm::AArch64ISD::SHL_PRED
@ SHL_PRED
Definition: AArch64ISelLowering.h:97
llvm::AArch64ISD::FCMP
@ FCMP
Definition: AArch64ISelLowering.h:150
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64ISD::SUNPKLO
@ SUNPKLO
Definition: AArch64ISelLowering.h:300
llvm::AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU
@ SIGN_EXTEND_INREG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:130
llvm::AArch64ISD::LD4LANEpost
@ LD4LANEpost
Definition: AArch64ISelLowering.h:441
llvm::AArch64ISD::LD3DUPpost
@ LD3DUPpost
Definition: AArch64ISelLowering.h:436
llvm::AArch64ISD::ADDlow
@ ADDlow
Definition: AArch64ISelLowering.h:65
llvm::AArch64ISD::STRICT_FCMP
@ STRICT_FCMP
Definition: AArch64ISelLowering.h:418
llvm::AArch64ISD::GLD1_MERGE_ZERO
@ GLD1_MERGE_ZERO
Definition: AArch64ISelLowering.h:353
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AArch64ISD::MVNIshift
@ MVNIshift
Definition: AArch64ISelLowering.h:168
llvm::AArch64ISD::REVD_MERGE_PASSTHRU
@ REVD_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:411
llvm::AArch64ISD::SST1_UXTW_PRED
@ SST1_UXTW_PRED
Definition: AArch64ISelLowering.h:399
llvm::AArch64ISD::FCMLTz
@ FCMLTz
Definition: AArch64ISelLowering.h:228
Instruction.h
llvm::AArch64ISD::CMEQz
@ CMEQz
Definition: AArch64ISelLowering.h:219
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1391
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::AArch64ISD::FMUL_PRED
@ FMUL_PRED
Definition: AArch64ISelLowering.h:91
llvm::AArch64ISD::REVW_MERGE_PASSTHRU
@ REVW_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:325
llvm::AArch64ISD::FRINT_MERGE_PASSTHRU
@ FRINT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:119
llvm::AArch64ISD::CSEL
@ CSEL
Definition: AArch64ISelLowering.h:70
llvm::AArch64TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: AArch64ISelLowering.cpp:19098
llvm::AArch64ISD::MVNImsl
@ MVNImsl
Definition: AArch64ISelLowering.h:169
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1125
llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: AArch64ISelLowering.cpp:13466
llvm::AArch64ISD::ST4LANEpost
@ ST4LANEpost
Definition: AArch64ISelLowering.h:444
llvm::AArch64ISD::TRN1
@ TRN1
Definition: AArch64ISelLowering.h:184
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::AArch64ISD::SST1_SCALED_PRED
@ SST1_SCALED_PRED
Definition: AArch64ISelLowering.h:398
llvm::AArch64ISD::CMGEz
@ CMGEz
Definition: AArch64ISelLowering.h:220
llvm::AArch64ISD::SMAXV
@ SMAXV
Definition: AArch64ISelLowering.h:249
llvm::AArch64ISD::SRL_PRED
@ SRL_PRED
Definition: AArch64ISelLowering.h:101
llvm::AArch64ISD::MOPS_MEMMOVE
@ MOPS_MEMMOVE
Definition: AArch64ISelLowering.h:459
llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: AArch64ISelLowering.cpp:20085
llvm::AArch64TargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
Definition: AArch64ISelLowering.cpp:13067
llvm::AArch64ISD::GLDNT1S_MERGE_ZERO
@ GLDNT1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:391
llvm::AArch64ISD::LD1_MERGE_ZERO
@ LD1_MERGE_ZERO
Definition: AArch64ISelLowering.h:338
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:68
llvm::AArch64ISD::MRS
@ MRS
Definition: AArch64ISelLowering.h:288
llvm::AArch64::RP
@ RP
Definition: AArch64ISelLowering.h:469
llvm::AArch64ISD::GLD1S_SCALED_MERGE_ZERO
@ GLD1S_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:363
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::AArch64ISD::ORRi
@ ORRi
Definition: AArch64ISelLowering.h:173
llvm::AArch64ISD::VSRI
@ VSRI
Definition: AArch64ISelLowering.h:206
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::AArch64ISD::LASTB
@ LASTB
Definition: AArch64ISelLowering.h:307
llvm::AArch64TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: AArch64ISelLowering.h:807
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
llvm::AArch64ISD::SADDLP
@ SADDLP
Definition: AArch64ISelLowering.h:238
llvm::AArch64ISD::SRA_PRED
@ SRA_PRED
Definition: AArch64ISelLowering.h:100
llvm::AArch64ISD::UDIV_PRED
@ UDIV_PRED
Definition: AArch64ISelLowering.h:102
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AArch64ISD::MUL_PRED
@ MUL_PRED
Definition: AArch64ISelLowering.h:93
llvm::AArch64ISD::CMLEz
@ CMLEz
Definition: AArch64ISelLowering.h:222
llvm::AArch64ISD::FRSQRTE
@ FRSQRTE
Definition: AArch64ISelLowering.h:296
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::AArch64TargetLowering::getIRStackGuard
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
Definition: AArch64ISelLowering.cpp:20221
llvm::AArch64TargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: AArch64ISelLowering.cpp:13356
llvm::AArch64ISD::MOVIedit
@ MOVIedit
Definition: AArch64ISelLowering.h:165
llvm::AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU
@ SINT_TO_FP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:127
llvm::AArch64TargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: AArch64ISelLowering.cpp:13577
llvm::AArch64TargetLowering::getTargetMMOFlags
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: AArch64ISelLowering.cpp:12818
llvm::AArch64ISD::SRAD_MERGE_OP1
@ SRAD_MERGE_OP1
Definition: AArch64ISelLowering.h:109
llvm::Instruction
Definition: Instruction.h:42
llvm::AArch64ISD::UADDLP
@ UADDLP
Definition: AArch64ISelLowering.h:239
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::AArch64ISD::ST1_PRED
@ ST1_PRED
Definition: AArch64ISelLowering.h:394
llvm::AArch64ISD::STZ2G
@ STZ2G
Definition: AArch64ISelLowering.h:449
llvm::AArch64TargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: AArch64ISelLowering.cpp:13450
llvm::AArch64ISD::UMINV_PRED
@ UMINV_PRED
Definition: AArch64ISelLowering.h:257
llvm::AArch64ISD::GLD1S_UXTW_MERGE_ZERO
@ GLD1S_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:364
llvm::AArch64ISD::DUPLANE16
@ DUPLANE16
Definition: AArch64ISelLowering.h:158
llvm::AArch64ISD::SST1_PRED
@ SST1_PRED
Definition: AArch64ISelLowering.h:397
llvm::AArch64ISD::ZIP2
@ ZIP2
Definition: AArch64ISelLowering.h:181
llvm::AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO
@ GLDFF1S_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:383
llvm::AArch64ISD::FCMEQ
@ FCMEQ
Definition: AArch64ISelLowering.h:214
llvm::AArch64ISD::VSLI
@ VSLI
Definition: AArch64ISelLowering.h:205
llvm::AArch64ISD::FABS_MERGE_PASSTHRU
@ FABS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:113
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AArch64ISD::FP_ROUND_MERGE_PASSTHRU
@ FP_ROUND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:124
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::AArch64TargetLowering::hasPairedLoad
bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
Definition: AArch64ISelLowering.cpp:12798
llvm::AArch64ISD::VSHL
@ VSHL
Definition: AArch64ISelLowering.h:193
llvm::AArch64ISD::SETCC_MERGE_ZERO
@ SETCC_MERGE_ZERO
Definition: AArch64ISelLowering.h:135
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AArch64ISD::UUNPKLO
@ UUNPKLO
Definition: AArch64ISelLowering.h:302
llvm::AArch64ISD::SBC
@ SBC
Definition: AArch64ISelLowering.h:79
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::AArch64ISD::SADDV_PRED
@ SADDV_PRED
Definition: AArch64ISelLowering.h:252
llvm::AArch64ISD::UITOF
@ UITOF
Definition: AArch64ISelLowering.h:279
llvm::AArch64TargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: AArch64ISelLowering.cpp:20045
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::AArch64TargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: AArch64ISelLowering.cpp:13277
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AArch64TargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
Definition: AArch64ISelLowering.cpp:12894
llvm::AArch64ISD::UQSHL_I
@ UQSHL_I
Definition: AArch64ISelLowering.h:199
llvm::AArch64TargetLowering::EmitFill
MachineBasicBlock * EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2362
llvm::AArch64ISD::PTEST
@ PTEST
Definition: AArch64ISelLowering.h:319
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::AArch64TargetLowering::getPromotedVTForPredicate
EVT getPromotedVTForPredicate(EVT VT) const
Definition: AArch64ISelLowering.cpp:21500
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::AArch64ISD::FCVTZU_MERGE_PASSTHRU
@ FCVTZU_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:128
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::AArch64ISD::GLD1_IMM_MERGE_ZERO
@ GLD1_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:359
llvm::APFloat
Definition: APFloat.h:701
llvm::AArch64ISD::SPLICE
@ SPLICE
Definition: AArch64ISelLowering.h:190
llvm::AArch64TargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: AArch64ISelLowering.h:793
llvm::AArch64TargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: AArch64ISelLowering.cpp:20367
llvm::AArch64ISD::CMHI
@ CMHI
Definition: AArch64ISelLowering.h:212
llvm::AArch64ISD::ST3post
@ ST3post
Definition: AArch64ISelLowering.h:426
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:297
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MipsISD::Ext
@ Ext
Definition: MipsISelLowering.h:159
llvm::AArch64TargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: AArch64ISelLowering.cpp:20026
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::AArch64ISD::SDOT
@ SDOT
Definition: AArch64ISelLowering.h:243
llvm::AArch64TargetLowering::AArch64TargetLowering
AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)
Definition: AArch64ISelLowering.cpp:240
llvm::AArch64ISD::SST1_SXTW_SCALED_PRED
@ SST1_SXTW_SCALED_PRED
Definition: AArch64ISelLowering.h:402
llvm::AArch64ISD::FRECPE
@ FRECPE
Definition: AArch64ISelLowering.h:294
llvm::AArch64ISD::INDEX_VECTOR
@ INDEX_VECTOR
Definition: AArch64ISelLowering.h:329
llvm::AArch64ISD::SQSHL_I
@ SQSHL_I
Definition: AArch64ISelLowering.h:198
llvm::AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU
@ ZERO_EXTEND_INREG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:131
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AArch64ISD::SDIV_PRED
@ SDIV_PRED
Definition: AArch64ISelLowering.h:96
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AArch64ISD::FMINNM_PRED
@ FMINNM_PRED
Definition: AArch64ISelLowering.h:90
llvm::AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: AArch64ISelLowering.cpp:20286
llvm::AArch64::rmMask
@ rmMask
Definition: AArch64ISelLowering.h:472
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1300
llvm::AArch64::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: AArch64FastISel.cpp:5110
llvm::AArch64ISD::LD1RQ_MERGE_ZERO
@ LD1RQ_MERGE_ZERO
Definition: AArch64ISelLowering.h:344
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::AArch64TargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: AArch64ISelLowering.cpp:20312
llvm::AArch64ISD::SST1_IMM_PRED
@ SST1_IMM_PRED
Definition: AArch64ISelLowering.h:403
llvm::AArch64TargetLowering::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
Definition: AArch64ISelLowering.cpp:12453
llvm::AArch64TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
Definition: AArch64ISelLowering.cpp:1663
llvm::AArch64ISD::VASHR
@ VASHR
Definition: AArch64ISelLowering.h:195
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::AArch64TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: AArch64ISelLowering.cpp:5273
llvm::AArch64ISD::EXT
@ EXT
Definition: AArch64ISelLowering.h:189
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::AArch64TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:5632
llvm::AArch64ISD::CSINV
@ CSINV
Definition: AArch64ISelLowering.h:71
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:3022
llvm::AArch64TargetLowering::shouldExpandAtomicStoreInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition: AArch64ISelLowering.cpp:20015
llvm::AArch64ISD::FADDV_PRED
@ FADDV_PRED
Definition: AArch64ISelLowering.h:312
llvm::AArch64ISD::CMGT
@ CMGT
Definition: AArch64ISelLowering.h:211
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:69
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
Definition: AArch64ISelLowering.cpp:20147
llvm::AArch64TargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: AArch64ISelLowering.cpp:20006
llvm::AArch64ISD::FADDA_PRED
@ FADDA_PRED
Definition: AArch64ISelLowering.h:311
llvm::AArch64ISD::BICi
@ BICi
Definition: AArch64ISelLowering.h:172
llvm::AArch64ISD::LD1RO_MERGE_ZERO
@ LD1RO_MERGE_ZERO
Definition: AArch64ISelLowering.h:345
llvm::AArch64TargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: AArch64ISelLowering.h:743
llvm::AArch64ISD::SMULL
@ SMULL
Definition: AArch64ISelLowering.h:290
llvm::AArch64TargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: AArch64ISelLowering.cpp:11712
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::AArch64ISD::ABDS_PRED
@ ABDS_PRED
Definition: AArch64ISelLowering.h:82
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::AArch64ISD::FCMGE
@ FCMGE
Definition: AArch64ISelLowering.h:215
llvm::AArch64TargetLowering::getOptimalMemOpLLT
LLT getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const override
LLT returning variant.
Definition: AArch64ISelLowering.cpp:13307
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::AArch64ISD::SQSHLU_I
@ SQSHLU_I
Definition: AArch64ISelLowering.h:200
llvm::AArch64TargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue V) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: AArch64ISelLowering.h:749
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::AArch64ISD::EXTR
@ EXTR
Definition: AArch64ISelLowering.h:153
llvm::AArch64TargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: AArch64ISelLowering.cpp:20326
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO
@ GLDFF1_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:376
llvm::AArch64ISD::LDFF1S_MERGE_ZERO
@ LDFF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:343
llvm::AArch64ISD::SRSHR_I
@ SRSHR_I
Definition: AArch64ISelLowering.h:201
llvm::AArch64ISD::SMIN_PRED
@ SMIN_PRED
Definition: AArch64ISelLowering.h:99
llvm::AArch64ISD::FNEG_MERGE_PASSTHRU
@ FNEG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:117
llvm::AArch64ISD::GLD1_SXTW_MERGE_ZERO
@ GLD1_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:356
llvm::AArch64ISD::GLDFF1S_IMM_MERGE_ZERO
@ GLDFF1S_IMM_MERGE_ZERO
Definition: AArch64ISelLowering.h:386
llvm::AArch64TargetLowering::isReassocProfitable
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...
Definition: AArch64ISelLowering.cpp:5615
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1411
llvm::AArch64TargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AArch64ISelLowering.cpp:8677
llvm::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfo.h:163
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::AArch64TargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: AArch64ISelLowering.cpp:8684
llvm::AArch64::RN
@ RN
Definition: AArch64ISelLowering.h:468
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::AArch64ISD::FSQRT_MERGE_PASSTHRU
@ FSQRT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:122
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::AArch64ISD::GLDFF1_SXTW_MERGE_ZERO
@ GLDFF1_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:374
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::AArch64ISD::BSP
@ BSP
Definition: AArch64ISelLowering.h:177
llvm::AArch64ISD::ADCS
@ ADCS
Definition: AArch64ISelLowering.h:140
llvm::AArch64ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: AArch64ISelLowering.h:50
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::AArch64ISD::LDNF1_MERGE_ZERO
@ LDNF1_MERGE_ZERO
Definition: AArch64ISelLowering.h:340
llvm::AArch64TargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT VT) const override
SVE code generation for fixed length vectors does not custom lower BUILD_VECTOR.
Definition: AArch64ISelLowering.cpp:5547
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO
@ GLD1_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:357
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AArch64ISD::LD1LANEpost
@ LD1LANEpost
Definition: AArch64ISelLowering.h:438
llvm::AArch64TargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Enable aggressive FMA fusion on targets that want it.
Definition: AArch64ISelLowering.cpp:20393
llvm::AArch64ISD::CLASTB_N
@ CLASTB_N
Definition: AArch64ISelLowering.h:305
llvm::AArch64ISD::ANDV_PRED
@ ANDV_PRED
Definition: AArch64ISelLowering.h:260
llvm::AArch64ISD::REVH_MERGE_PASSTHRU
@ REVH_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:324
llvm::AArch64ISD::BITREVERSE_MERGE_PASSTHRU
@ BITREVERSE_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:322
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:470
llvm::AArch64ISD::LDNF1S_MERGE_ZERO
@ LDNF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:341
llvm::AArch64ISD::STRICT_FCMPE
@ STRICT_FCMPE
Definition: AArch64ISelLowering.h:419
llvm::ArrayRef< int >
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::AArch64ISD::LD4post
@ LD4post
Definition: AArch64ISelLowering.h:424
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::AArch64ISD::CMEQ
@ CMEQ
Definition: AArch64ISelLowering.h:209
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::AArch64TargetLowering::fallBackToDAGISel
bool fallBackToDAGISel(const Instruction &Inst) const override
Definition: AArch64ISelLowering.cpp:20456
llvm::AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO
@ GLDFF1_UXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:375
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AArch64ISD::DUPLANE8
@ DUPLANE8
Definition: AArch64ISelLowering.h:157
llvm::AArch64TargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: AArch64ISelLowering.h:712
llvm::LinearPolySize::getFixedValue
ScalarTy getFixedValue() const
Definition: TypeSize.h:312
llvm::AArch64TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: AArch64ISelLowering.cpp:1916
uint32_t
llvm::AArch64ISD::MOVI
@ MOVI
Definition: AArch64ISelLowering.h:163
llvm::AArch64ISD::ADDS
@ ADDS
Definition: AArch64ISelLowering.h:138
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:64
llvm::AArch64TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: AArch64ISelLowering.h:727
llvm::AArch64ISD::REV64
@ REV64
Definition: AArch64ISelLowering.h:188
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64ISD::CMGTz
@ CMGTz
Definition: AArch64ISelLowering.h:221
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::AArch64ISD::SSTNT1_PRED
@ SSTNT1_PRED
Definition: AArch64ISelLowering.h:406
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1294
llvm::AArch64ISD::LD1DUPpost
@ LD1DUPpost
Definition: AArch64ISelLowering.h:434
llvm::AArch64ISD::FMA_PRED
@ FMA_PRED
Definition: AArch64ISelLowering.h:86
llvm::AArch64ISD::LS64_EXTRACT
@ LS64_EXTRACT
Definition: AArch64ISelLowering.h:336
llvm::AArch64TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AArch64ISelLowering.cpp:1977
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64ISD::SVE_LD2_MERGE_ZERO
@ SVE_LD2_MERGE_ZERO
Definition: AArch64ISelLowering.h:348
llvm::AArch64ISD::ABDU_PRED
@ ABDU_PRED
Definition: AArch64ISelLowering.h:83
llvm::AArch64ISD::CBNZ
@ CBNZ
Definition: AArch64ISelLowering.h:267
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::AArch64TargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: AArch64ISelLowering.cpp:20153
llvm::AArch64ISD::ORV_PRED
@ ORV_PRED
Definition: AArch64ISelLowering.h:258
llvm::AArch64TargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: AArch64ISelLowering.cpp:13532
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:714
llvm::AArch64ISD::UZP2
@ UZP2
Definition: AArch64ISelLowering.h:183
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64TargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: AArch64ISelLowering.cpp:13554
llvm::AArch64ISD::PTRUE
@ PTRUE
Definition: AArch64ISelLowering.h:320
llvm::AArch64ISD::ANDS
@ ANDS
Definition: AArch64ISelLowering.h:142
llvm::AArch64ISD::FMAXV_PRED
@ FMAXV_PRED
Definition: AArch64ISelLowering.h:313
llvm::AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU
@ FROUNDEVEN_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:121
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO
@ GLD1S_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:367
llvm::AArch64ISD::FMAXNM_PRED
@ FMAXNM_PRED
Definition: AArch64ISelLowering.h:88
llvm::AArch64TargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: AArch64ISelLowering.cpp:13338
llvm::AArch64ISD::THREAD_POINTER
@ THREAD_POINTER
Definition: AArch64ISelLowering.h:77
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::AArch64::RZ
@ RZ
Definition: AArch64ISelLowering.h:471
llvm::AArch64ISD::FRSQRTS
@ FRSQRTS
Definition: AArch64ISelLowering.h:297
llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
Definition: AArch64ISelLowering.h:772
llvm::AArch64TargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: AArch64ISelLowering.cpp:12811
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
uint16_t
CallingConvLower.h
llvm::AArch64TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
Definition: AArch64ISelLowering.cpp:12479
llvm::AArch64ISD::CSNEG
@ CSNEG
Definition: AArch64ISelLowering.h:72
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AArch64ISD::STZG
@ STZG
Definition: AArch64ISelLowering.h:447
llvm::AArch64ISD::UDOT
@ UDOT
Definition: AArch64ISelLowering.h:242
llvm::AArch64ISD::CALL_BTI
@ CALL_BTI
Definition: AArch64ISelLowering.h:58
llvm::AArch64TargetLowering::getVaListSizeInBits
unsigned getVaListSizeInBits(const DataLayout &DL) const override
Returns the size of the platform's va_list object.
Definition: AArch64ISelLowering.cpp:20398
llvm::AArch64ISD::FMOV
@ FMOV
Definition: AArch64ISelLowering.h:167
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4429
llvm::AArch64ISD::UADDV_PRED
@ UADDV_PRED
Definition: AArch64ISelLowering.h:253
llvm::AArch64TargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: AArch64ISelLowering.cpp:19979
llvm::TypeSize
Definition: TypeSize.h:435
llvm::AArch64TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AArch64ISelLowering.cpp:2429
llvm::AArch64ISD::NEG_MERGE_PASSTHRU
@ NEG_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:133
llvm::AArch64ISD::CSINC
@ CSINC
Definition: AArch64ISelLowering.h:73
llvm::AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO
@ GLDFF1S_SXTW_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:385
llvm::AArch64ISD::TBL
@ TBL
Definition: AArch64ISelLowering.h:308
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::AArch64TargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: AArch64ISelLowering.cpp:20320
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:222
llvm::AArch64ISD::GLD1S_SXTW_MERGE_ZERO
@ GLD1S_SXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:365
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::AArch64TargetLowering::EmitF128CSEL
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2276
llvm::AArch64ISD::SVE_LD3_MERGE_ZERO
@ SVE_LD3_MERGE_ZERO
Definition: AArch64ISelLowering.h:349
llvm::AArch64ISD::FP_EXTEND_MERGE_PASSTHRU
@ FP_EXTEND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:125
llvm::AArch64ISD::GLDFF1S_MERGE_ZERO
@ GLDFF1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:380
llvm::AArch64TargetLowering::getSafeStackPointerLocation
Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
Definition: AArch64ISelLowering.cpp:20271
llvm::AArch64ISD::ADRP
@ ADRP
Definition: AArch64ISelLowering.h:63
llvm::AArch64ISD::FCMEQz
@ FCMEQz
Definition: AArch64ISelLowering.h:224
llvm::AArch64ISD::DUPLANE64
@ DUPLANE64
Definition: AArch64ISelLowering.h:160
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AArch64ISD::ST2G
@ ST2G
Definition: AArch64ISelLowering.h:448
llvm::AArch64ISD::SST1_SXTW_PRED
@ SST1_SXTW_PRED
Definition: AArch64ISelLowering.h:400
llvm::AArch64ISD::FSUB_PRED
@ FSUB_PRED
Definition: AArch64ISelLowering.h:92
llvm::AArch64TargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: AArch64ISelLowering.h:739
llvm::AArch64TargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AArch64ISelLowering.cpp:5667
llvm::AArch64TargetLowering::getRedZoneSize
unsigned getRedZoneSize(const Function &F) const
Definition: AArch64ISelLowering.h:849
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:1995
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::AArch64TargetLowering::shouldExpandGetActiveLaneMask
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
Definition: AArch64ISelLowering.cpp:1501
llvm::AArch64ISD::REINTERPRET_CAST
@ REINTERPRET_CAST
Definition: AArch64ISelLowering.h:332
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::AArch64ISD::FTRUNC_MERGE_PASSTHRU
@ FTRUNC_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:123
llvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: AArch64ISelLowering.cpp:20300
llvm::AArch64ISD::REV16
@ REV16
Definition: AArch64ISelLowering.h:186
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::AArch64ISD::LS64_BUILD
@ LS64_BUILD
Definition: AArch64ISelLowering.h:335
llvm::AArch64::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: AArch64ISelLowering.h:476
llvm::AArch64ISD::GLD1_UXTW_MERGE_ZERO
@ GLD1_UXTW_MERGE_ZERO
Definition: AArch64ISelLowering.h:355
llvm::AArch64ISD::UADDV
@ UADDV
Definition: AArch64ISelLowering.h:233
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1306
llvm::AArch64TargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: AArch64ISelLowering.cpp:20384
llvm::AArch64ISD::UMAXV_PRED
@ UMAXV_PRED
Definition: AArch64ISelLowering.h:255
N
#define N
llvm::AArch64ISD::ABS_MERGE_PASSTHRU
@ ABS_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:132
llvm::AArch64ISD::GLD1_SCALED_MERGE_ZERO
@ GLD1_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:354
llvm::AArch64ISD::ST2LANEpost
@ ST2LANEpost
Definition: AArch64ISelLowering.h:442
llvm::AArch64ISD::UMAXV
@ UMAXV
Definition: AArch64ISelLowering.h:250
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4521
llvm::AArch64ISD::GLD1S_MERGE_ZERO
@ GLD1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:362
llvm::AArch64ISD::TBZ
@ TBZ
Definition: AArch64ISelLowering.h:268
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::AArch64ISD::FCCMP
@ FCCMP
Definition: AArch64ISelLowering.h:147
llvm::AArch64TargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: AArch64ISelLowering.cpp:12258
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
llvm::AArch64TargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: AArch64ISelLowering.cpp:12646
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:513
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1461
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AArch64ISD::BSWAP_MERGE_PASSTHRU
@ BSWAP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:323
llvm::AArch64ISD::INSR
@ INSR
Definition: AArch64ISelLowering.h:318
llvm::AArch64ISD::LD2LANEpost
@ LD2LANEpost
Definition: AArch64ISelLowering.h:439
llvm::AArch64ISD::LASTA
@ LASTA
Definition: AArch64ISelLowering.h:306
llvm::AArch64TargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: AArch64ISelLowering.cpp:20379
llvm::AArch64ISD::ST4post
@ ST4post
Definition: AArch64ISelLowering.h:427
llvm::AArch64ISD::ST1x3post
@ ST1x3post
Definition: AArch64ISelLowering.h:432
llvm::AArch64ISD::WrapperLarge
@ WrapperLarge
Definition: AArch64ISelLowering.h:51
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AArch64ISelLowering.cpp:13388
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:481
llvm::AArch64TargetLowering::getPointerTy
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: AArch64ISelLowering.h:504
llvm::AArch64ISD::MOPS_MEMCOPY
@ MOPS_MEMCOPY
Definition: AArch64ISelLowering.h:458
llvm::AArch64ISD::LD4DUPpost
@ LD4DUPpost
Definition: AArch64ISelLowering.h:437
MachineFunction.h
llvm::AArch64ISD::BIT
@ BIT
Definition: AArch64ISelLowering.h:263
llvm::AArch64ISD::BRCOND
@ BRCOND
Definition: AArch64ISelLowering.h:69
llvm::AArch64ISD::SUNPKHI
@ SUNPKHI
Definition: AArch64ISelLowering.h:299
llvm::AArch64TargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: AArch64ISelLowering.cpp:20236
llvm::AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU
@ UINT_TO_FP_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:126
llvm::AArch64ISD::FNEARBYINT_MERGE_PASSTHRU
@ FNEARBYINT_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:116
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::AArch64ISD::GLDFF1_SCALED_MERGE_ZERO
@ GLDFF1_SCALED_MERGE_ZERO
Definition: AArch64ISelLowering.h:372
llvm::AArch64TargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: AArch64ISelLowering.cpp:1812
llvm::AArch64ISD::SMINV
@ SMINV
Definition: AArch64ISelLowering.h:247
llvm::AArch64TargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: AArch64ISelLowering.h:754
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::AArch64TargetLowering::EmitZero
MachineBasicBlock * EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: AArch64ISelLowering.cpp:2413
llvm::AArch64ISD::FADD_PRED
@ FADD_PRED
Definition: AArch64ISelLowering.h:84
llvm::AArch64ISD::ST2post
@ ST2post
Definition: AArch64ISelLowering.h:425
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:509
llvm::AArch64TargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: AArch64ISelLowering.h:720
llvm::AArch64ISD::LD1S_MERGE_ZERO
@ LD1S_MERGE_ZERO
Definition: AArch64ISelLowering.h:339
llvm::AArch64ISD::STP
@ STP
Definition: AArch64ISelLowering.h:452
llvm::AArch64ISD::FMIN_PRED
@ FMIN_PRED
Definition: AArch64ISelLowering.h:89
llvm::AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Definition: AArch64ISelLowering.cpp:20192
llvm::AArch64ISD::GLDNT1_INDEX_MERGE_ZERO
@ GLDNT1_INDEX_MERGE_ZERO
Definition: AArch64ISelLowering.h:390
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::AArch64ISD::DUPLANE32
@ DUPLANE32
Definition: AArch64ISelLowering.h:159
llvm::AArch64ISD::FDIV_PRED
@ FDIV_PRED
Definition: AArch64ISelLowering.h:85
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1193
llvm::AArch64ISD::FROUND_MERGE_PASSTHRU
@ FROUND_MERGE_PASSTHRU
Definition: AArch64ISelLowering.h:120
llvm::AArch64::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPCR.
Definition: AArch64ISelLowering.h:467
llvm::AArch64ISD::NVCAST
@ NVCAST
Natural vector cast.
Definition: AArch64ISelLowering.h:286
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::AArch64ISD::SUBS
@ SUBS
Definition: AArch64ISelLowering.h:139