25 ExportClustering() =
default;
29static bool isExport(
const SUnit &SU) {
35 unsigned Imm =
TII->getNamedOperand(*
MI, AMDGPU::OpName::tgt)->getImm();
41 if (!PosCount || PosCount == Chain.
size())
50 unsigned OtherIdx = PosCount;
51 for (
SUnit *SU : Copy) {
52 if (isPositionExport(
TII, SU))
55 Chain[OtherIdx++] = SU;
71 if (!isExport(*PredSU) && !Pred.
isWeak())
87 if (Pred.
isBarrier() && isExport(*PredSU)) {
94 for (
const SDep &ExportPred : PredSU->
Preds) {
96 if (ExportPred.
isBarrier() && !isExport(*ExportPredSU))
104 for (
SDep Pred : ToAdd)
117 unsigned PosCount = 0;
123 if (isPositionExport(
TII, &SU))
126 removeExportDependencies(DAG, SU);
129 for (
SDep Succ : Succs)
130 removeExportDependencies(DAG, *Succ.getSUnit());
134 if (Chain.
size() > 1) {
135 sortChain(
TII, Chain, PosCount);
136 buildCluster(Chain, DAG);
145 return std::make_unique<ExportClustering>();
Provides AMDGPU specific target descriptions.
ReachingDefAnalysis InstSet & ToRemove
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
Interface definition for SIInstrInfo.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & front() const
front - Get the first element.
size_t size() const
size - Get the array size.
Representation of each machine instruction.
bool isWeak() const
Tests if this a weak dependence.
@ Cluster
Weak DAG edge linking a chain of clustered instrs.
@ Barrier
An unknown scheduling barrier.
@ Artificial
Arbitrary strong DAG edge (no real dependence).
bool isBarrier() const
Tests if this is an Order dependence that is marked as a barrier.
static bool isEXP(const MachineInstr &MI)
Scheduling unit. This is a node in the scheduling DAG.
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
SmallVector< SDep, 4 > Succs
All sunit successors.
SmallVector< SDep, 4 > Preds
All sunit predecessors.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
A ScheduleDAG for scheduling lists of MachineInstr.
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Mutate the DAG as a postpass after normal DAG building.
virtual void apply(ScheduleDAGInstrs *DAG)=0
const TargetInstrInfo * TII
Target instruction information.
std::vector< SUnit > SUnits
The scheduling units.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This is an optimization pass for GlobalISel generic memory operations.
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()