LLVM 19.0.0git
AMDGPUMacroFusion.cpp
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1//===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file contains the AMDGPU implementation of the DAG scheduling
10/// mutation to pair instructions back to back.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPUMacroFusion.h"
16#include "SIInstrInfo.h"
18
19using namespace llvm;
20
21namespace {
22
23/// Check if the instr pair, FirstMI and SecondMI, should be fused
24/// together. Given SecondMI, when FirstMI is unspecified, then check if
25/// SecondMI may be part of a fused pair at all.
26static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
27 const TargetSubtargetInfo &TSI,
28 const MachineInstr *FirstMI,
29 const MachineInstr &SecondMI) {
30 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_);
31
32 switch (SecondMI.getOpcode()) {
33 case AMDGPU::V_ADDC_U32_e64:
34 case AMDGPU::V_SUBB_U32_e64:
35 case AMDGPU::V_SUBBREV_U32_e64:
36 case AMDGPU::V_CNDMASK_B32_e64: {
37 // Try to cluster defs of condition registers to their uses. This improves
38 // the chance VCC will be available which will allow shrinking to VOP2
39 // encodings.
40 if (!FirstMI)
41 return true;
42
43 const MachineBasicBlock &MBB = *FirstMI->getParent();
45 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
47 AMDGPU::OpName::src2);
48 return FirstMI->definesRegister(Src2->getReg(), TRI);
49 }
50 default:
51 return false;
52 }
53
54 return false;
55}
56
57} // end namespace
58
59
60namespace llvm {
61
62std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation() {
64}
65
66} // end namespace llvm
unsigned const MachineRegisterInfo * MRI
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
MachineBasicBlock & MBB
Provides AMDGPU specific target descriptions.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
Interface definition for SIInstrInfo.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:326
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ArrayRef< MacroFusionPredTy > Predicates, bool BranchOnly=false)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.