24#define DEBUG_TYPE "gi-combiner"
120 const GTrunc *Trunc = cast<GTrunc>(&Root);
121 const GExtOp *Ext = cast<GExtOp>(&ExtMI);
131 if (SrcTy == DstTy) {
145 B.buildInstr(Ext->getOpcode(), {Dst}, {Src});
165bool CombinerHelper::isCastFree(
unsigned Opcode,
LLT ToTy,
LLT FromTy)
const {
171 case TargetOpcode::G_ANYEXT:
172 case TargetOpcode::G_ZEXT:
174 case TargetOpcode::G_TRUNC:
201 if (!isCastFree(Cast->
getOpcode(), DstTy, SrcTy))
205 auto True =
B.buildInstr(Cast->
getOpcode(), {DstTy}, {TrueReg});
206 auto False =
B.buildInstr(Cast->
getOpcode(), {DstTy}, {FalseReg});
207 B.buildSelect(Dst,
Cond, True, False);
217 const GExtOp *Second = cast<GExtOp>(&SecondMI);
230 if (Second->
getOpcode() == TargetOpcode::G_ZEXT) {
239 B.buildInstr(Second->
getOpcode(), {Dst}, {Src});
246 if (
First->getOpcode() == TargetOpcode::G_ANYEXT &&
248 if (Second->
getOpcode() == TargetOpcode::G_ZEXT) {
261 if (Second->
getOpcode() == TargetOpcode::G_ANYEXT &&
263 if (
First->getOpcode() == TargetOpcode::G_ZEXT) {
297 {TargetOpcode::G_BUILD_VECTOR, {DstTy, ElemTy}}) ||
299 !isCastFree(Cast->
getOpcode(), ElemTy, InputElemTy))
305 for (
unsigned I = 0;
I < Elements; ++
I) {
311 B.buildBuildVector(Dst, Casts);
amdgpu AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This contains common combine transformations that may be used in a combine pass,or by the target else...
Interface for Targets to specify which operations they can successfully select and how the others sho...
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MachineIRBuilder class.
const SmallVectorImpl< MachineOperand > & Cond
bool matchSextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo)
Combine sext of trunc.
const DataLayout & getDataLayout() const
const TargetLowering & getTargetLowering() const
LLVMContext & getContext() const
bool matchExtOfExt(const MachineInstr &FirstMI, const MachineInstr &SecondMI, BuildFnTy &MatchInfo)
bool matchCastOfSelect(const MachineInstr &Cast, const MachineInstr &SelectMI, BuildFnTy &MatchInfo)
MachineRegisterInfo & MRI
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
bool matchNonNegZext(const MachineOperand &MO, BuildFnTy &MatchInfo)
Combine zext nneg to sext.
bool matchZextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo)
Combine zext of trunc.
bool matchTruncateOfExt(const MachineInstr &Root, const MachineInstr &ExtMI, BuildFnTy &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
bool matchCastOfBuildVector(const MachineInstr &CastMI, const MachineInstr &BVMI, BuildFnTy &MatchInfo)
A parsed version of the target data layout string in and methods for querying it.
Represents a G_BUILD_VECTOR.
Register getSrcReg() const
Represents an integer-like extending operation.
Represents an integer-like extending or truncating operation.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
constexpr unsigned getScalarSizeInBits() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr LLT getScalarType() const
This is an important class for using LLVM in a threaded context.
Helper class to build MachineInstr.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Wrapper class representing virtual and physical registers.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This is an optimization pass for GlobalISel generic memory operations.
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
std::function< void(MachineIRBuilder &)> BuildFnTy
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.