LLVM  13.0.0git
Disassembler.cpp
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1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "Disassembler.h"
10 #include "llvm-c/Disassembler.h"
11 #include "llvm/ADT/ArrayRef.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/Triple.h"
14 #include "llvm/MC/MCAsmInfo.h"
15 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstPrinter.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSchedule.h"
32 #include <cassert>
33 #include <cstddef>
34 #include <cstring>
35 
36 using namespace llvm;
37 
38 // LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
39 // disassembly is supported by passing a block of information in the DisInfo
40 // parameter and specifying the TagType and callback functions as described in
41 // the header llvm-c/Disassembler.h . The pointer to the block and the
42 // functions can all be passed as NULL. If successful, this returns a
43 // disassembler context. If not, it returns NULL.
44 //
46 LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
47  const char *Features, void *DisInfo, int TagType,
48  LLVMOpInfoCallback GetOpInfo,
49  LLVMSymbolLookupCallback SymbolLookUp) {
50  // Get the target.
51  std::string Error;
52  const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
53  if (!TheTarget)
54  return nullptr;
55 
56  std::unique_ptr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT));
57  if (!MRI)
58  return nullptr;
59 
60  MCTargetOptions MCOptions;
61  // Get the assembler info needed to setup the MCContext.
62  std::unique_ptr<const MCAsmInfo> MAI(
63  TheTarget->createMCAsmInfo(*MRI, TT, MCOptions));
64  if (!MAI)
65  return nullptr;
66 
67  std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
68  if (!MII)
69  return nullptr;
70 
71  std::unique_ptr<const MCSubtargetInfo> STI(
72  TheTarget->createMCSubtargetInfo(TT, CPU, Features));
73  if (!STI)
74  return nullptr;
75 
76  // Set up the MCContext for creating symbols and MCExpr's.
77  std::unique_ptr<MCContext> Ctx(new MCContext(MAI.get(), MRI.get(), nullptr));
78  if (!Ctx)
79  return nullptr;
80 
81  // Set up disassembler.
82  std::unique_ptr<MCDisassembler> DisAsm(
83  TheTarget->createMCDisassembler(*STI, *Ctx));
84  if (!DisAsm)
85  return nullptr;
86 
87  std::unique_ptr<MCRelocationInfo> RelInfo(
88  TheTarget->createMCRelocationInfo(TT, *Ctx));
89  if (!RelInfo)
90  return nullptr;
91 
92  std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
93  TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx.get(), std::move(RelInfo)));
94  DisAsm->setSymbolizer(std::move(Symbolizer));
95 
96  // Set up the instruction printer.
97  int AsmPrinterVariant = MAI->getAssemblerDialect();
98  std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
99  Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI));
100  if (!IP)
101  return nullptr;
102 
104  TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget, std::move(MAI),
105  std::move(MRI), std::move(STI), std::move(MII), std::move(Ctx),
106  std::move(DisAsm), std::move(IP));
107  if (!DC)
108  return nullptr;
109 
110  DC->setCPU(CPU);
111  return DC;
112 }
113 
115 LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType,
116  LLVMOpInfoCallback GetOpInfo,
117  LLVMSymbolLookupCallback SymbolLookUp) {
118  return LLVMCreateDisasmCPUFeatures(TT, CPU, "", DisInfo, TagType, GetOpInfo,
119  SymbolLookUp);
120 }
121 
122 LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo,
123  int TagType, LLVMOpInfoCallback GetOpInfo,
124  LLVMSymbolLookupCallback SymbolLookUp) {
125  return LLVMCreateDisasmCPUFeatures(TT, "", "", DisInfo, TagType, GetOpInfo,
126  SymbolLookUp);
127 }
128 
129 //
130 // LLVMDisasmDispose() disposes of the disassembler specified by the context.
131 //
133  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
134  delete DC;
135 }
136 
137 /// Emits the comments that are stored in \p DC comment stream.
138 /// Each comment in the comment stream must end with a newline.
140  formatted_raw_ostream &FormattedOS) {
141  // Flush the stream before taking its content.
142  StringRef Comments = DC->CommentsToEmit.str();
143  // Get the default information for printing a comment.
144  const MCAsmInfo *MAI = DC->getAsmInfo();
145  StringRef CommentBegin = MAI->getCommentString();
146  unsigned CommentColumn = MAI->getCommentColumn();
147  bool IsFirst = true;
148  while (!Comments.empty()) {
149  if (!IsFirst)
150  FormattedOS << '\n';
151  // Emit a line of comments.
152  FormattedOS.PadToColumn(CommentColumn);
153  size_t Position = Comments.find('\n');
154  FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
155  // Move after the newline character.
156  Comments = Comments.substr(Position+1);
157  IsFirst = false;
158  }
159  FormattedOS.flush();
160 
161  // Tell the comment stream that the vector changed underneath it.
162  DC->CommentsToEmit.clear();
163 }
164 
165 /// Gets latency information for \p Inst from the itinerary
166 /// scheduling model, based on \p DC information.
167 /// \return The maximum expected latency over all the operands or -1
168 /// if no information is available.
169 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
170  const int NoInformationAvailable = -1;
171 
172  // Check if we have a CPU to get the itinerary information.
173  if (DC->getCPU().empty())
174  return NoInformationAvailable;
175 
176  // Get itinerary information.
177  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
178  InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
179  // Get the scheduling class of the requested instruction.
180  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
181  unsigned SCClass = Desc.getSchedClass();
182 
183  int Latency = 0;
184  for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
185  ++OpIdx)
186  Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
187 
188  return Latency;
189 }
190 
191 /// Gets latency information for \p Inst, based on \p DC information.
192 /// \return The maximum expected latency over all the definitions or -1
193 /// if no information is available.
194 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
195  // Try to compute scheduling information.
196  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
197  const MCSchedModel SCModel = STI->getSchedModel();
198  const int NoInformationAvailable = -1;
199 
200  // Check if we have a scheduling model for instructions.
201  if (!SCModel.hasInstrSchedModel())
202  // Try to fall back to the itinerary model if the scheduling model doesn't
203  // have a scheduling table. Note the default does not have a table.
204  return getItineraryLatency(DC, Inst);
205 
206  // Get the scheduling class of the requested instruction.
207  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
208  unsigned SCClass = Desc.getSchedClass();
209  const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
210  // Resolving the variant SchedClass requires an MI to pass to
211  // SubTargetInfo::resolveSchedClass.
212  if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
213  return NoInformationAvailable;
214 
215  // Compute output latency.
216  int16_t Latency = 0;
217  for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
218  DefIdx != DefEnd; ++DefIdx) {
219  // Lookup the definition's write latency in SubtargetInfo.
220  const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
221  DefIdx);
222  Latency = std::max(Latency, WLEntry->Cycles);
223  }
224 
225  return Latency;
226 }
227 
228 /// Emits latency information in DC->CommentStream for \p Inst, based
229 /// on the information available in \p DC.
230 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
231  int Latency = getLatency(DC, Inst);
232 
233  // Report only interesting latencies.
234  if (Latency < 2)
235  return;
236 
237  DC->CommentStream << "Latency: " << Latency << '\n';
238 }
239 
240 //
241 // LLVMDisasmInstruction() disassembles a single instruction using the
242 // disassembler context specified in the parameter DC. The bytes of the
243 // instruction are specified in the parameter Bytes, and contains at least
244 // BytesSize number of bytes. The instruction is at the address specified by
245 // the PC parameter. If a valid instruction can be disassembled its string is
246 // returned indirectly in OutString which whos size is specified in the
247 // parameter OutStringSize. This function returns the number of bytes in the
248 // instruction or zero if there was no valid instruction. If this function
249 // returns zero the caller will have to pick how many bytes they want to step
250 // over by printing a .byte, .long etc. to continue.
251 //
252 size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
253  uint64_t BytesSize, uint64_t PC, char *OutString,
254  size_t OutStringSize){
255  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
256  // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
257  ArrayRef<uint8_t> Data(Bytes, BytesSize);
258 
259  uint64_t Size;
260  MCInst Inst;
261  const MCDisassembler *DisAsm = DC->getDisAsm();
262  MCInstPrinter *IP = DC->getIP();
264  SmallVector<char, 64> InsnStr;
266  S = DisAsm->getInstruction(Inst, Size, Data, PC, Annotations);
267  switch (S) {
270  // FIXME: Do something different for soft failure modes?
271  return 0;
272 
274  StringRef AnnotationsStr = Annotations.str();
275 
276  SmallVector<char, 64> InsnStr;
277  raw_svector_ostream OS(InsnStr);
278  formatted_raw_ostream FormattedOS(OS);
279  IP->printInst(&Inst, PC, AnnotationsStr, *DC->getSubtargetInfo(),
280  FormattedOS);
281 
282  if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
283  emitLatency(DC, Inst);
284 
285  emitComments(DC, FormattedOS);
286 
287  assert(OutStringSize != 0 && "Output buffer cannot be zero size");
288  size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
289  std::memcpy(OutString, InsnStr.data(), OutputSize);
290  OutString[OutputSize] = '\0'; // Terminate string.
291 
292  return Size;
293  }
294  }
295  llvm_unreachable("Invalid DecodeStatus!");
296 }
297 
298 //
299 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
300 // can set all the Options and 0 otherwise.
301 //
302 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
303  if (Options & LLVMDisassembler_Option_UseMarkup){
304  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
305  MCInstPrinter *IP = DC->getIP();
306  IP->setUseMarkup(true);
309  }
311  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
312  MCInstPrinter *IP = DC->getIP();
313  IP->setPrintImmHex(true);
316  }
318  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
319  // Try to set up the new instruction printer.
320  const MCAsmInfo *MAI = DC->getAsmInfo();
321  const MCInstrInfo *MII = DC->getInstrInfo();
322  const MCRegisterInfo *MRI = DC->getRegisterInfo();
323  int AsmPrinterVariant = MAI->getAssemblerDialect();
324  AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
325  MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
326  Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
327  if (IP) {
328  DC->setIP(IP);
331  }
332  }
334  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
335  MCInstPrinter *IP = DC->getIP();
336  IP->setCommentStream(DC->CommentStream);
339  }
340  if (Options & LLVMDisassembler_Option_PrintLatency) {
341  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
344  }
345  return (Options == 0);
346 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MCWriteLatencyEntry::Cycles
int16_t Cycles
Definition: MCSchedule.h:79
llvm
Definition: AllocatorList.h:23
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:574
llvm::MCSchedClassDesc::NumWriteLatencyEntries
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:124
LLVMDisasmInstruction
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC.
Definition: Disassembler.cpp:252
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
MCTargetOptions.h
MCDisassembler.h
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:32
MCInstrDesc.h
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:162
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::StringRef::find
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:318
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
LLVMDisasmDispose
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
Definition: Disassembler.cpp:132
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:613
llvm::Target::createMCAsmInfo
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple, const MCTargetOptions &Options) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
Definition: TargetRegistry.h:339
ErrorHandling.h
LLVMCreateDisasm
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
Definition: Disassembler.cpp:122
emitComments
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
Definition: Disassembler.cpp:139
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
Disassembler.h
llvm::Target::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
Definition: TargetRegistry.h:565
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:102
LLVMDisassembler_Option_PrintImmHex
#define LLVMDisassembler_Option_PrintImmHex
Definition: Disassembler.h:77
llvm::MCSubtargetInfo::getInstrItineraryForCPU
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Definition: MCSubtargetInfo.cpp:328
llvm::MCAsmInfo::getAssemblerDialect
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:601
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::TargetRegistry::lookupTarget
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.
Definition: TargetRegistry.cpp:62
llvm::InstrItineraryData::getOperandCycle
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
Definition: MCInstrItineraries.h:167
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:207
llvm::Data
@ Data
Definition: SIMachineScheduler.h:56
LLVMDisassembler_Option_UseMarkup
#define LLVMDisassembler_Option_UseMarkup
Definition: Disassembler.h:75
llvm::MCSchedClassDesc::isValid
bool isValid() const
Definition: MCSchedule.h:128
llvm::Target::createMCInstrInfo
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
Definition: TargetRegistry.h:348
llvm::Annotations
Annotations lets you mark points and ranges inside source code, for tests:
Definition: Annotations.h:46
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:612
llvm::Target::createMCRegInfo
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
Definition: TargetRegistry.h:364
FormattedStream.h
MCInstrItineraries.h
llvm::formatted_raw_ostream::PadToColumn
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Definition: FormattedStream.cpp:115
LLVMDisassembler_Option_PrintLatency
#define LLVMDisassembler_Option_PrintLatency
Definition: Disassembler.h:83
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:42
LLVMDisassembler_Option_SetInstrComments
#define LLVMDisassembler_Option_SetInstrComments
Definition: Disassembler.h:81
MCContext.h
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:110
getLatency
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
Definition: Disassembler.cpp:194
MCInstrInfo.h
LLVMCreateDisasmCPU
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
Definition: Disassembler.cpp:115
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
IP
Definition: NVPTXLowerArgs.cpp:166
MCInst.h
getItineraryLatency
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information.
Definition: Disassembler.cpp:169
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
MCSubtargetInfo.h
llvm::LLVMDisasmContext
Definition: Disassembler.h:38
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:183
llvm::MCSubtargetInfo::getWriteLatencyEntry
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
Definition: MCSubtargetInfo.h:175
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
MCInstPrinter.h
MCSchedule.h
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:112
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVMDisassembler_Option_AsmPrinterVariant
#define LLVMDisassembler_Option_AsmPrinterVariant
Definition: Disassembler.h:79
llvm::MCWriteLatencyEntry
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
llvm::Target::createMCSymbolizer
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
Definition: TargetRegistry.h:585
MCRegisterInfo.h
llvm::Target::createMCDisassembler
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
Definition: TargetRegistry.h:437
ArrayRef.h
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
memcpy
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
MCSymbolizer.h
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
Triple.h
llvm::ArrayRef< uint8_t >
emitLatency
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC.
Definition: Disassembler.cpp:230
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
DC
static ManagedStatic< DebugCounter > DC
Definition: DebugCounter.cpp:55
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Target::createMCSubtargetInfo
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
Definition: TargetRegistry.h:379
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::Target::createMCInstPrinter
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
Definition: TargetRegistry.h:444
LLVMDisasmContextRef
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
Definition: DisassemblerTypes.h:23
llvm::MCSchedClassDesc::isVariant
bool isVariant() const
Definition: MCSchedule.h:131
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
MCRelocationInfo.h
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:197
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:245
SmallVector.h
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
LLVMCreateDisasmCPUFeatures
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
Definition: Disassembler.cpp:46
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:647
llvm::MCSchedModel::getSchedClassDesc
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:347
llvm::MCAsmInfo::getCommentColumn
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
Definition: MCAsmInfo.h:572
LLVMSetDisasmOptions
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler's options.
Definition: Disassembler.cpp:302
llvm::MCSchedModel::hasInstrSchedModel
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:321
raw_ostream.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109