28#define DEBUG_TYPE "regalloc"
31const InterferenceCache::BlockInterference
32 InterferenceCache::Cursor::NoInterference;
43 if (PhysRegEntriesCount == TRI->
getNumRegs())
return;
46 PhysRegEntries =
static_cast<unsigned char*
>(
47 safe_calloc(PhysRegEntriesCount,
sizeof(
unsigned char)));
59 for (Entry &
E : Entries)
60 E.clear(mf, indexes, lis);
63InterferenceCache::Entry *InterferenceCache::get(
MCRegister PhysReg) {
64 unsigned char E = PhysRegEntries[PhysReg.
id()];
65 if (
E < CacheEntries && Entries[
E].getPhysReg() == PhysReg) {
66 if (!Entries[
E].valid(LIUArray, TRI))
67 Entries[
E].revalidate(LIUArray, TRI);
72 if (++RoundRobin == CacheEntries)
74 for (
unsigned i = 0; i != CacheEntries; ++i) {
76 if (Entries[
E].hasRefs()) {
77 if (++
E == CacheEntries)
81 Entries[
E].reset(PhysReg, LIUArray, TRI, MF);
82 PhysRegEntries[PhysReg] =
E;
97 RegUnits[i++].VirtTag = LIUArray[Unit].
getTag();
100void InterferenceCache::Entry::reset(
MCRegister physReg,
104 assert(!hasRefs() &&
"Cannot reset cache entry with references");
114 RegUnits.push_back(LIUArray[Unit]);
115 RegUnits.back().Fixed = &LIS->getRegUnit(Unit);
121 unsigned i = 0,
e = RegUnits.size();
125 if (LIUArray[Unit].changedSince(RegUnits[i].VirtTag))
132void InterferenceCache::Entry::update(
unsigned MBBNum) {
134 std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
137 if (PrevPos != Start) {
138 if (!PrevPos.isValid() || Start < PrevPos) {
139 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
140 RegUnitInfo &RUI = RegUnits[i];
141 RUI.VirtI.find(Start);
142 RUI.FixedI = RUI.Fixed->find(Start);
145 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
146 RegUnitInfo &RUI = RegUnits[i];
147 RUI.VirtI.advanceTo(Start);
148 if (RUI.FixedI != RUI.Fixed->end())
149 RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
157 BlockInterference *BI = &
Blocks[MBBNum];
165 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
172 if (!BI->First.isValid() || StartI < BI->
First)
177 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
185 if (!BI->First.isValid() || StartI < BI->
First)
190 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
191 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
193 for (
unsigned i = 0, e = RegMaskSlots.
size();
194 i != e && RegMaskSlots[i] < Limit; ++i)
197 BI->First = RegMaskSlots[i];
202 if (BI->First.isValid())
206 if (++MFI == MF->
end())
208 MBBNum = MFI->getNumber();
212 std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
216 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
218 if (!
I.valid() ||
I.start() >= Stop)
221 bool Backup = !
I.valid() ||
I.start() >= Stop;
225 if (!BI->Last.isValid() || StopI > BI->Last)
232 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
235 if (
I == LR->
end() ||
I->start >= Stop)
238 bool Backup =
I == LR->
end() ||
I->start >= Stop;
242 if (!BI->Last.isValid() || StopI > BI->Last)
250 for (
unsigned i = RegMaskSlots.
size();
251 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
255 BI->Last = RegMaskSlots[i-1].getDeadSlot();
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DenseMap< Block *, BlockRelaxAux > Blocks
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
void init(MachineFunction *mf, LiveIntervalUnion *liuarray, SlotIndexes *indexes, LiveIntervals *lis, const TargetRegisterInfo *tri)
init - Prepare cache for a new function.
void reinitPhysRegEntries()
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
LiveSegments::iterator SegmentIter
unsigned getTag() const
getTag - Return an opaque tag representing the current state of the union.
This class represents the liveness of a register, stack slot, etc.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
BasicBlockListType::const_iterator const_iterator
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
SlotIndex - An opaque wrapper around machine indexes.
bool isValid() const
Returns true if this is a valid index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.