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30 #define GET_REGINFO_TARGET_DESC
31 #include "LanaiGenRegisterInfo.inc"
73 case Lanai::ADD_F_I_LO:
74 case Lanai::SUB_F_I_LO:
75 case Lanai::ADDC_I_LO:
76 case Lanai::SUBB_I_LO:
77 case Lanai::ADDC_F_I_LO:
78 case Lanai::SUBB_F_I_LO:
88 return Lanai::SUB_I_LO;
90 return Lanai::ADD_I_LO;
91 case Lanai::ADD_F_I_LO:
92 return Lanai::SUB_F_I_LO;
93 case Lanai::SUB_F_I_LO:
94 return Lanai::ADD_F_I_LO;
95 case Lanai::ADDC_I_LO:
96 return Lanai::SUBB_I_LO;
97 case Lanai::SUBB_I_LO:
98 return Lanai::ADDC_I_LO;
99 case Lanai::ADDC_F_I_LO:
100 return Lanai::SUBB_F_I_LO;
101 case Lanai::SUBB_F_I_LO:
102 return Lanai::ADDC_F_I_LO;
111 return Lanai::LDBs_RR;
113 return Lanai::LDBz_RR;
115 return Lanai::LDHs_RR;
117 return Lanai::LDHz_RR;
119 return Lanai::LDW_RR;
121 return Lanai::STB_RR;
123 return Lanai::STH_RR;
132 int SPAdj,
unsigned FIOperandNum,
134 assert(SPAdj == 0 &&
"Unexpected");
140 bool HasFP = TFI->
hasFP(MF);
143 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
146 MI.getOperand(FIOperandNum + 1).getImm();
150 if (!HasFP || (hasStackRealignment(MF) &&
FrameIndex >= 0))
157 else if (hasStackRealignment(MF))
158 FrameReg = Lanai::SP;
167 assert(RS &&
"Register scavenging must be on");
171 assert(
Reg &&
"Register scavenger failed");
173 bool HasNegOffset =
false;
195 if (
MI.getOpcode() == Lanai::ADD_I_LO) {
197 HasNegOffset ?
TII->get(Lanai::SUB_R) :
TII->get(Lanai::ADD_R),
198 MI.getOperand(0).getReg())
202 MI.eraseFromParent();
211 "Unexpected ALU op in RRM instruction");
217 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false);
218 MI.getOperand(FIOperandNum + 1)
219 .ChangeToRegister(
Reg,
false,
false,
234 MI.getOperand(0).getReg())
237 MI.eraseFromParent();
239 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false);
240 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Information about stack frame layout on the target.
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Reg
All possible values of the reg field in the ModR/M byte.
static unsigned getOppositeALULoOpcode(unsigned Opcode)
static unsigned getRRMOpcodeVariant(unsigned Opcode)
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
TargetInstrInfo - Interface to description of machine instruction set.
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override
const HexagonInstrInfo * TII
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool hasBasePointer(const MachineFunction &MF) const
static bool isRMOpcode(unsigned Opcode)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static bool isSPLSOpcode(unsigned Opcode)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
BitVector getReservedRegs(const MachineFunction &MF) const override
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getBaseRegister() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Register getFrameRegister(const MachineFunction &MF) const override
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Wrapper class representing virtual and physical registers.
virtual const TargetFrameLowering * getFrameLowering() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isALUArithLoOpcode(unsigned Opcode)
unsigned getRARegister() const