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47 #define DEBUG_TYPE "reg-scavenging"
49 STATISTIC(NumScavengedRegs,
"Number of frame index regs scavenged");
68 KillRegUnits.
resize(NumRegUnits);
69 DefRegUnits.
resize(NumRegUnits);
70 TmpRegUnits.
resize(NumRegUnits);
74 for (ScavengedInfo &
SI : Scavenged) {
108 void RegScavenger::determineKillsAndDefs() {
109 assert(Tracking &&
"Must be tracking to determine kills and defs");
112 assert(!
MI.isDebugInstr() &&
"Debug values have no kills or defs");
116 KillRegUnits.
reset();
119 if (MO.isRegMask()) {
123 if (MO.clobbersPhysReg(*RURI)) {
131 KillRegUnits |= TmpRegUnits;
135 if (!MO.getReg().isPhysical() || isReserved(MO.getReg()))
168 for (ScavengedInfo &
I : Scavenged) {
169 if (
I.Restore != &
MI)
176 if (
MI.isDebugOrPseudoInstr())
179 determineKillsAndDefs();
201 bool SubUsed =
false;
207 bool SuperUsed =
false;
214 if (!SubUsed && !SuperUsed) {
228 "Re-defining a live register!");
235 setUnused(KillRegUnits);
236 setUsed(DefRegUnits);
240 assert(Tracking &&
"Must be tracking to determine kills and defs");
246 for (ScavengedInfo &
I : Scavenged) {
247 if (
I.Restore == &
MI) {
262 return includeReserved;
290 assert(Survivor > 0 &&
"No candidates for scavenging");
293 assert(StartMI != ME &&
"MI already at terminator");
297 bool inVirtLiveRange =
false;
299 if (
MI->isDebugOrPseudoInstr()) {
303 bool isVirtKillInsn =
false;
304 bool isVirtDefInsn =
false;
309 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
313 isVirtDefInsn =
true;
314 else if (MO.isKill())
315 isVirtKillInsn =
true;
319 Candidates.
reset(*AI);
323 if (!inVirtLiveRange) RestorePointMI =
MI;
326 if (isVirtKillInsn) inVirtLiveRange =
false;
327 if (isVirtDefInsn) inVirtLiveRange =
true;
330 if (Candidates.
test(Survivor))
334 if (Candidates.
none())
340 if (
MI == ME) RestorePointMI = ME;
341 assert(RestorePointMI != StartMI &&
342 "No available scavenger restore location!");
345 UseMI = RestorePointMI;
356 static std::pair<MCPhysReg, MachineBasicBlock::iterator>
361 bool FoundTo =
false;
370 assert(
From->getParent() == To->getParent() &&
371 "Target instruction is in other than current basic block, use "
372 "enterBasicBlockEnd first");
394 Used.accumulate(*std::next(
From));
397 if (Survivor == 0 || !Used.available(Survivor)) {
405 if (AvilableReg == 0)
407 Survivor = AvilableReg;
409 if (--InstrCountDown == 0)
414 bool FoundVReg =
false;
429 "iterating backwards");
432 return std::make_pair(Survivor, Pos);
437 while (!
MI.getOperand(
i).isFI()) {
439 assert(
i <
MI.getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
444 RegScavenger::ScavengedInfo &
457 for (
unsigned I = 0;
I < Scavenged.size(); ++
I) {
458 if (Scavenged[
I].
Reg != 0)
461 int FI = Scavenged[
I].FrameIndex;
462 if (FI < FIB || FI >= FIE)
466 if (NeedSize >
S || NeedAlign > A)
474 unsigned D = (
S - NeedSize) + (
A.value() - NeedAlign.
value());
481 if (
SI == Scavenged.size()) {
484 Scavenged.push_back(ScavengedInfo(FIE));
488 Scavenged[
SI].Reg =
Reg;
494 int FI = Scavenged[
SI].FrameIndex;
495 if (FI < FIB || FI >= FIE) {
499 ": Cannot scavenge register without an emergency "
510 II = std::prev(
UseMI);
515 return Scavenged[
SI];
520 int SPAdj,
bool AllowSpill) {
528 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
531 Candidates.
reset(*AI);
538 for (ScavengedInfo &
SI : Scavenged) {
543 " from scavenging candidates since it was already scavenged\n");
545 Candidates.
reset(*AI);
571 for (ScavengedInfo &
SI : Scavenged) {
572 assert(
SI.Reg != SReg &&
"scavenged a previously scavenged register");
576 ScavengedInfo &Scavenged =
spill(SReg, *RC, SPAdj,
I,
UseMI);
577 Scavenged.Restore = &*std::prev(
UseMI);
587 bool RestoreAfter,
int SPAdj,
595 std::pair<MCPhysReg, MachineBasicBlock::iterator>
P =
601 if (
Reg != 0 && SpillBefore ==
MBB.
end()) {
610 assert(
Reg != 0 &&
"No register left to scavenge!");
613 RestoreAfter ? std::next(
MBBI) :
MBBI;
615 if (ReloadBefore !=
MBB.
end())
617 ScavengedInfo &Scavenged =
spill(
Reg, RC, SPAdj, SpillBefore, ReloadBefore);
618 Scavenged.Restore = &*std::prev(SpillBefore);
621 <<
" until " << *SpillBefore);
640 if (CommonMBB ==
nullptr)
642 assert(
MBB == CommonMBB &&
"All defs+uses must be in the same basic block");
645 if (!
MI.readsRegister(VReg, &
TRI)) {
646 assert((!RealDef || RealDef == &
MI) &&
647 "Can have at most one definition which is not a redefinition");
652 assert(RealDef !=
nullptr &&
"Must have at least 1 Def");
663 return !MO.getParent()->readsRegister(VReg, &TRI);
666 "Must have one definition that does not redefine vreg");
674 ReserveAfter, SPAdj);
690 bool NextInstructionReadsVReg =
false;
697 if (NextInstructionReadsVReg) {
714 N->addRegisterKilled(SReg, &
TRI,
false);
720 NextInstructionReadsVReg =
false;
733 assert(!MO.isInternalRead() &&
"Cannot assign inside bundles");
734 assert((!MO.isUndef() || MO.isDef()) &&
"Cannot handle undef uses");
736 NextInstructionReadsVReg =
true;
740 I->addRegisterDead(SReg, &
TRI,
false);
748 assert(!MO.isInternalRead() &&
"Cannot assign inside bundles");
749 assert((!MO.isUndef() || MO.isDef()) &&
"Cannot handle undef uses");
750 assert(!MO.readsReg() &&
"Vreg use in first instruction not allowed");
775 LLVM_DEBUG(
dbgs() <<
"Warning: Required two scavenging passes for block "
822 "Scavenge virtual registers inside basic blocks",
false,
false)
This is an optimization pass for GlobalISel generic memory operations.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
MachineInstrBuilder & UseMI
Information about stack frame layout on the target.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
bool none() const
none - Returns true if none of the bits are set.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Reg
All possible values of the reg field in the ModR/M byte.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
const TargetRegisterInfo * getTargetRegisterInfo() const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV, MCRegister Reg)
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned const TargetRegisterInfo * TRI
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
static std::pair< MCPhysReg, MachineBasicBlock::iterator > findSurvivorBackwards(const MachineRegisterInfo &MRI, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const LiveRegUnits &LiveOut, ArrayRef< MCPhysReg > AllocationOrder, bool RestoreAfter)
Given the bitvector Available of free register units at position From.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
@ Available
We know the block is fully available. This is a fixpoint.
static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS, Register VReg, bool ReserveAfter)
Allocate a register for the virtual register VReg.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunctionProperties & getProperties() const
Get the function properties.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
void backward()
Update internal register state and move MBB iterator backwards.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
STATISTIC(NumFunctions, "Total number of functions")
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
A set of register units used to track register liveness.
This struct is a compact representation of a valid (non-zero power of two) alignment.
void removeReg(MCPhysReg Reg)
Removes all register units covered by physical register Reg.
int getObjectIndexBegin() const
Return the minimum frame object index.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isValid() const
Check if the iterator is at the end of the list.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Representation of each machine instruction.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS)
Replaces all frame index virtual registers with physical registers.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
initializer< Ty > init(const Ty &Val)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
StandardInstrumentations SI(Debug, VerifyEach)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCSuperRegIterator enumerates all super-registers of Reg.
static def_iterator def_end()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
MachineInstrBundleIterator< MachineInstr > iterator
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static unsigned getFrameIndexOperandNum(MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
MachineBasicBlock MachineBasicBlock::iterator MBBI
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
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TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
iterator_range< def_iterator > def_operands(Register Reg) const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool test(unsigned Idx) const
virtual const TargetFrameLowering * getFrameLowering() const
uint64_t value() const
This is a hole in the type system and should not be abused.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
void forward()
Move the internal MBB iterator and update register states.
MCRegUnitRootIterator enumerates the root registers of a register unit.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
MachineInstrBuilder MachineInstrBuilder & DefMI
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
BlockVerifier::State From
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator_range< mop_iterator > operands()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI, RegScavenger &RS, MachineBasicBlock &MBB)
Allocate (scavenge) vregs inside a single basic block.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.