LLVM  15.0.0git
RegisterScavenging.cpp
Go to the documentation of this file.
1 //===- RegisterScavenging.cpp - Machine register scavenging ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the machine register scavenger. It can provide
11 /// information, such as unused registers, at any point in a machine basic
12 /// block. It also provides a mechanism to make registers available by evicting
13 /// them to spill slots.
14 //
15 //===----------------------------------------------------------------------===//
16 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Pass.h"
37 #include "llvm/Support/Debug.h"
40 #include <cassert>
41 #include <iterator>
42 #include <limits>
43 #include <utility>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "reg-scavenging"
48 
49 STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
50 
52  LiveUnits.addRegMasked(Reg, LaneMask);
53 }
54 
55 void RegScavenger::init(MachineBasicBlock &MBB) {
56  MachineFunction &MF = *MBB.getParent();
57  TII = MF.getSubtarget().getInstrInfo();
59  MRI = &MF.getRegInfo();
60  LiveUnits.init(*TRI);
61 
62  assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
63  "Target changed?");
64 
65  // Self-initialize.
66  if (!this->MBB) {
67  NumRegUnits = TRI->getNumRegUnits();
68  KillRegUnits.resize(NumRegUnits);
69  DefRegUnits.resize(NumRegUnits);
70  TmpRegUnits.resize(NumRegUnits);
71  }
72  this->MBB = &MBB;
73 
74  for (ScavengedInfo &SI : Scavenged) {
75  SI.Reg = 0;
76  SI.Restore = nullptr;
77  }
78 
79  Tracking = false;
80 }
81 
83  init(MBB);
84  LiveUnits.addLiveIns(MBB);
85 }
86 
88  init(MBB);
89  LiveUnits.addLiveOuts(MBB);
90 
91  // Move internal iterator at the last instruction of the block.
92  if (!MBB.empty()) {
93  MBBI = std::prev(MBB.end());
94  Tracking = true;
95  }
96 }
97 
98 void RegScavenger::addRegUnits(BitVector &BV, MCRegister Reg) {
99  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
100  BV.set(*RUI);
101 }
102 
103 void RegScavenger::removeRegUnits(BitVector &BV, MCRegister Reg) {
104  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
105  BV.reset(*RUI);
106 }
107 
108 void RegScavenger::determineKillsAndDefs() {
109  assert(Tracking && "Must be tracking to determine kills and defs");
110 
111  MachineInstr &MI = *MBBI;
112  assert(!MI.isDebugInstr() && "Debug values have no kills or defs");
113 
114  // Find out which registers are early clobbered, killed, defined, and marked
115  // def-dead in this instruction.
116  KillRegUnits.reset();
117  DefRegUnits.reset();
118  for (const MachineOperand &MO : MI.operands()) {
119  if (MO.isRegMask()) {
120  TmpRegUnits.reset();
121  for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
122  for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
123  if (MO.clobbersPhysReg(*RURI)) {
124  TmpRegUnits.set(RU);
125  break;
126  }
127  }
128  }
129 
130  // Apply the mask.
131  KillRegUnits |= TmpRegUnits;
132  }
133  if (!MO.isReg())
134  continue;
135  if (!MO.getReg().isPhysical() || isReserved(MO.getReg()))
136  continue;
137  MCRegister Reg = MO.getReg().asMCReg();
138 
139  if (MO.isUse()) {
140  // Ignore undef uses.
141  if (MO.isUndef())
142  continue;
143  if (MO.isKill())
144  addRegUnits(KillRegUnits, Reg);
145  } else {
146  assert(MO.isDef());
147  if (MO.isDead())
148  addRegUnits(KillRegUnits, Reg);
149  else
150  addRegUnits(DefRegUnits, Reg);
151  }
152  }
153 }
154 
156  // Move ptr forward.
157  if (!Tracking) {
158  MBBI = MBB->begin();
159  Tracking = true;
160  } else {
161  assert(MBBI != MBB->end() && "Already past the end of the basic block!");
162  MBBI = std::next(MBBI);
163  }
164  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
165 
166  MachineInstr &MI = *MBBI;
167 
168  for (ScavengedInfo &I : Scavenged) {
169  if (I.Restore != &MI)
170  continue;
171 
172  I.Reg = 0;
173  I.Restore = nullptr;
174  }
175 
176  if (MI.isDebugOrPseudoInstr())
177  return;
178 
179  determineKillsAndDefs();
180 
181  // Verify uses and defs.
182 #ifndef NDEBUG
183  for (const MachineOperand &MO : MI.operands()) {
184  if (!MO.isReg())
185  continue;
186  Register Reg = MO.getReg();
187  if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
188  continue;
189  if (MO.isUse()) {
190  if (MO.isUndef())
191  continue;
192  if (!isRegUsed(Reg)) {
193  // Check if it's partial live: e.g.
194  // D0 = insert_subreg undef D0, S0
195  // ... D0
196  // The problem is the insert_subreg could be eliminated. The use of
197  // D0 is using a partially undef value. This is not *incorrect* since
198  // S1 is can be freely clobbered.
199  // Ideally we would like a way to model this, but leaving the
200  // insert_subreg around causes both correctness and performance issues.
201  bool SubUsed = false;
202  for (const MCPhysReg &SubReg : TRI->subregs(Reg))
203  if (isRegUsed(SubReg)) {
204  SubUsed = true;
205  break;
206  }
207  bool SuperUsed = false;
208  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
209  if (isRegUsed(*SR)) {
210  SuperUsed = true;
211  break;
212  }
213  }
214  if (!SubUsed && !SuperUsed) {
215  MBB->getParent()->verify(nullptr, "In Register Scavenger");
216  llvm_unreachable("Using an undefined register!");
217  }
218  (void)SubUsed;
219  (void)SuperUsed;
220  }
221  } else {
222  assert(MO.isDef());
223 #if 0
224  // FIXME: Enable this once we've figured out how to correctly transfer
225  // implicit kills during codegen passes like the coalescer.
226  assert((KillRegs.test(Reg) || isUnused(Reg) ||
227  isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
228  "Re-defining a live register!");
229 #endif
230  }
231  }
232 #endif // NDEBUG
233 
234  // Commit the changes.
235  setUnused(KillRegUnits);
236  setUsed(DefRegUnits);
237 }
238 
240  assert(Tracking && "Must be tracking to determine kills and defs");
241 
242  const MachineInstr &MI = *MBBI;
243  LiveUnits.stepBackward(MI);
244 
245  // Expire scavenge spill frameindex uses.
246  for (ScavengedInfo &I : Scavenged) {
247  if (I.Restore == &MI) {
248  I.Reg = 0;
249  I.Restore = nullptr;
250  }
251  }
252 
253  if (MBBI == MBB->begin()) {
255  Tracking = false;
256  } else
257  --MBBI;
258 }
259 
260 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
261  if (isReserved(Reg))
262  return includeReserved;
263  return !LiveUnits.available(Reg);
264 }
265 
267  for (Register Reg : *RC) {
268  if (!isRegUsed(Reg)) {
269  LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
270  << "\n");
271  return Reg;
272  }
273  }
274  return 0;
275 }
276 
279  for (Register Reg : *RC)
280  if (!isRegUsed(Reg))
281  Mask.set(Reg);
282  return Mask;
283 }
284 
285 Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
286  BitVector &Candidates,
287  unsigned InstrLimit,
289  int Survivor = Candidates.find_first();
290  assert(Survivor > 0 && "No candidates for scavenging");
291 
293  assert(StartMI != ME && "MI already at terminator");
294  MachineBasicBlock::iterator RestorePointMI = StartMI;
296 
297  bool inVirtLiveRange = false;
298  for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
299  if (MI->isDebugOrPseudoInstr()) {
300  ++InstrLimit; // Don't count debug instructions
301  continue;
302  }
303  bool isVirtKillInsn = false;
304  bool isVirtDefInsn = false;
305  // Remove any candidates touched by instruction.
306  for (const MachineOperand &MO : MI->operands()) {
307  if (MO.isRegMask())
308  Candidates.clearBitsNotInMask(MO.getRegMask());
309  if (!MO.isReg() || MO.isUndef() || !MO.getReg())
310  continue;
311  if (Register::isVirtualRegister(MO.getReg())) {
312  if (MO.isDef())
313  isVirtDefInsn = true;
314  else if (MO.isKill())
315  isVirtKillInsn = true;
316  continue;
317  }
318  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
319  Candidates.reset(*AI);
320  }
321  // If we're not in a virtual reg's live range, this is a valid
322  // restore point.
323  if (!inVirtLiveRange) RestorePointMI = MI;
324 
325  // Update whether we're in the live range of a virtual register
326  if (isVirtKillInsn) inVirtLiveRange = false;
327  if (isVirtDefInsn) inVirtLiveRange = true;
328 
329  // Was our survivor untouched by this instruction?
330  if (Candidates.test(Survivor))
331  continue;
332 
333  // All candidates gone?
334  if (Candidates.none())
335  break;
336 
337  Survivor = Candidates.find_first();
338  }
339  // If we ran off the end, that's where we want to restore.
340  if (MI == ME) RestorePointMI = ME;
341  assert(RestorePointMI != StartMI &&
342  "No available scavenger restore location!");
343 
344  // We ran out of candidates, so stop the search.
345  UseMI = RestorePointMI;
346  return Survivor;
347 }
348 
349 /// Given the bitvector \p Available of free register units at position
350 /// \p From. Search backwards to find a register that is part of \p
351 /// Candidates and not used/clobbered until the point \p To. If there is
352 /// multiple candidates continue searching and pick the one that is not used/
353 /// clobbered for the longest time.
354 /// Returns the register and the earliest position we know it to be free or
355 /// the position MBB.end() if no register is available.
356 static std::pair<MCPhysReg, MachineBasicBlock::iterator>
360  bool RestoreAfter) {
361  bool FoundTo = false;
362  MCPhysReg Survivor = 0;
364  MachineBasicBlock &MBB = *From->getParent();
365  unsigned InstrLimit = 25;
366  unsigned InstrCountDown = InstrLimit;
368  LiveRegUnits Used(TRI);
369 
370  assert(From->getParent() == To->getParent() &&
371  "Target instruction is in other than current basic block, use "
372  "enterBasicBlockEnd first");
373 
374  for (MachineBasicBlock::iterator I = From;; --I) {
375  const MachineInstr &MI = *I;
376 
377  Used.accumulate(MI);
378 
379  if (I == To) {
380  // See if one of the registers in RC wasn't used so far.
381  for (MCPhysReg Reg : AllocationOrder) {
382  if (!MRI.isReserved(Reg) && Used.available(Reg) &&
383  LiveOut.available(Reg))
384  return std::make_pair(Reg, MBB.end());
385  }
386  // Otherwise we will continue up to InstrLimit instructions to find
387  // the register which is not defined/used for the longest time.
388  FoundTo = true;
389  Pos = To;
390  // Note: It was fine so far to start our search at From, however now that
391  // we have to spill, and can only place the restore after From then
392  // add the regs used/defed by std::next(From) to the set.
393  if (RestoreAfter)
394  Used.accumulate(*std::next(From));
395  }
396  if (FoundTo) {
397  if (Survivor == 0 || !Used.available(Survivor)) {
398  MCPhysReg AvilableReg = 0;
399  for (MCPhysReg Reg : AllocationOrder) {
400  if (!MRI.isReserved(Reg) && Used.available(Reg)) {
401  AvilableReg = Reg;
402  break;
403  }
404  }
405  if (AvilableReg == 0)
406  break;
407  Survivor = AvilableReg;
408  }
409  if (--InstrCountDown == 0)
410  break;
411 
412  // Keep searching when we find a vreg since the spilled register will
413  // be usefull for this other vreg as well later.
414  bool FoundVReg = false;
415  for (const MachineOperand &MO : MI.operands()) {
416  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
417  FoundVReg = true;
418  break;
419  }
420  }
421  if (FoundVReg) {
422  InstrCountDown = InstrLimit;
423  Pos = I;
424  }
425  if (I == MBB.begin())
426  break;
427  }
428  assert(I != MBB.begin() && "Did not find target instruction while "
429  "iterating backwards");
430  }
431 
432  return std::make_pair(Survivor, Pos);
433 }
434 
436  unsigned i = 0;
437  while (!MI.getOperand(i).isFI()) {
438  ++i;
439  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
440  }
441  return i;
442 }
443 
444 RegScavenger::ScavengedInfo &
445 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
448  // Find an available scavenging slot with size and alignment matching
449  // the requirements of the class RC.
450  const MachineFunction &MF = *Before->getMF();
451  const MachineFrameInfo &MFI = MF.getFrameInfo();
452  unsigned NeedSize = TRI->getSpillSize(RC);
453  Align NeedAlign = TRI->getSpillAlign(RC);
454 
455  unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();
456  int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
457  for (unsigned I = 0; I < Scavenged.size(); ++I) {
458  if (Scavenged[I].Reg != 0)
459  continue;
460  // Verify that this slot is valid for this register.
461  int FI = Scavenged[I].FrameIndex;
462  if (FI < FIB || FI >= FIE)
463  continue;
464  unsigned S = MFI.getObjectSize(FI);
465  Align A = MFI.getObjectAlign(FI);
466  if (NeedSize > S || NeedAlign > A)
467  continue;
468  // Avoid wasting slots with large size and/or large alignment. Pick one
469  // that is the best fit for this register class (in street metric).
470  // Picking a larger slot than necessary could happen if a slot for a
471  // larger register is reserved before a slot for a smaller one. When
472  // trying to spill a smaller register, the large slot would be found
473  // first, thus making it impossible to spill the larger register later.
474  unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value());
475  if (D < Diff) {
476  SI = I;
477  Diff = D;
478  }
479  }
480 
481  if (SI == Scavenged.size()) {
482  // We need to scavenge a register but have no spill slot, the target
483  // must know how to do it (if not, we'll assert below).
484  Scavenged.push_back(ScavengedInfo(FIE));
485  }
486 
487  // Avoid infinite regress
488  Scavenged[SI].Reg = Reg;
489 
490  // If the target knows how to save/restore the register, let it do so;
491  // otherwise, use the emergency stack spill slot.
492  if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
493  // Spill the scavenged register before \p Before.
494  int FI = Scavenged[SI].FrameIndex;
495  if (FI < FIB || FI >= FIE) {
496  report_fatal_error(Twine("Error while trying to spill ") +
497  TRI->getName(Reg) + " from class " +
498  TRI->getRegClassName(&RC) +
499  ": Cannot scavenge register without an emergency "
500  "spill slot!");
501  }
502  TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI);
503  MachineBasicBlock::iterator II = std::prev(Before);
504 
505  unsigned FIOperandNum = getFrameIndexOperandNum(*II);
506  TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
507 
508  // Restore the scavenged register before its use (or first terminator).
509  TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI);
510  II = std::prev(UseMI);
511 
512  FIOperandNum = getFrameIndexOperandNum(*II);
513  TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
514  }
515  return Scavenged[SI];
516 }
517 
520  int SPAdj, bool AllowSpill) {
521  MachineInstr &MI = *I;
522  const MachineFunction &MF = *MI.getMF();
523  // Consider all allocatable registers in the register class initially
524  BitVector Candidates = TRI->getAllocatableSet(MF, RC);
525 
526  // Exclude all the registers being used by the instruction.
527  for (const MachineOperand &MO : MI.operands()) {
528  if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
529  !Register::isVirtualRegister(MO.getReg()))
530  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
531  Candidates.reset(*AI);
532  }
533 
534  // If we have already scavenged some registers, remove them from the
535  // candidates. If we end up recursively calling eliminateFrameIndex, we don't
536  // want to be clobbering previously scavenged registers or their associated
537  // stack slots.
538  for (ScavengedInfo &SI : Scavenged) {
539  if (SI.Reg) {
540  if (isRegUsed(SI.Reg)) {
541  LLVM_DEBUG(
542  dbgs() << "Removing " << printReg(SI.Reg, TRI) <<
543  " from scavenging candidates since it was already scavenged\n");
544  for (MCRegAliasIterator AI(SI.Reg, TRI, true); AI.isValid(); ++AI)
545  Candidates.reset(*AI);
546  }
547  }
548  }
549 
550  // Try to find a register that's unused if there is one, as then we won't
551  // have to spill.
553  Available &= Candidates;
554  if (Available.any())
555  Candidates = Available;
556 
557  // Find the register whose use is furthest away.
559  Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
560 
561  // If we found an unused register there is no reason to spill it.
562  if (!isRegUsed(SReg)) {
563  LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
564  return SReg;
565  }
566 
567  if (!AllowSpill)
568  return 0;
569 
570 #ifndef NDEBUG
571  for (ScavengedInfo &SI : Scavenged) {
572  assert(SI.Reg != SReg && "scavenged a previously scavenged register");
573  }
574 #endif
575 
576  ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
577  Scavenged.Restore = &*std::prev(UseMI);
578 
579  LLVM_DEBUG(dbgs() << "Scavenged register (with spill): "
580  << printReg(SReg, TRI) << "\n");
581 
582  return SReg;
583 }
584 
587  bool RestoreAfter, int SPAdj,
588  bool AllowSpill) {
589  const MachineBasicBlock &MBB = *To->getParent();
590  const MachineFunction &MF = *MBB.getParent();
591 
592  // Find the register whose use is furthest away.
595  std::pair<MCPhysReg, MachineBasicBlock::iterator> P =
596  findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder,
597  RestoreAfter);
598  MCPhysReg Reg = P.first;
599  MachineBasicBlock::iterator SpillBefore = P.second;
600  // Found an available register?
601  if (Reg != 0 && SpillBefore == MBB.end()) {
602  LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
603  << '\n');
604  return Reg;
605  }
606 
607  if (!AllowSpill)
608  return 0;
609 
610  assert(Reg != 0 && "No register left to scavenge!");
611 
612  MachineBasicBlock::iterator ReloadAfter =
613  RestoreAfter ? std::next(MBBI) : MBBI;
614  MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
615  if (ReloadBefore != MBB.end())
616  LLVM_DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
617  ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
618  Scavenged.Restore = &*std::prev(SpillBefore);
619  LiveUnits.removeReg(Reg);
620  LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
621  << " until " << *SpillBefore);
622  return Reg;
623 }
624 
625 /// Allocate a register for the virtual register \p VReg. The last use of
626 /// \p VReg is around the current position of the register scavenger \p RS.
627 /// \p ReserveAfter controls whether the scavenged register needs to be reserved
628 /// after the current instruction, otherwise it will only be reserved before the
629 /// current instruction.
631  Register VReg, bool ReserveAfter) {
633 #ifndef NDEBUG
634  // Verify that all definitions and uses are in the same basic block.
635  const MachineBasicBlock *CommonMBB = nullptr;
636  // Real definition for the reg, re-definitions are not considered.
637  const MachineInstr *RealDef = nullptr;
638  for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {
639  MachineBasicBlock *MBB = MO.getParent()->getParent();
640  if (CommonMBB == nullptr)
641  CommonMBB = MBB;
642  assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");
643  if (MO.isDef()) {
644  const MachineInstr &MI = *MO.getParent();
645  if (!MI.readsRegister(VReg, &TRI)) {
646  assert((!RealDef || RealDef == &MI) &&
647  "Can have at most one definition which is not a redefinition");
648  RealDef = &MI;
649  }
650  }
651  }
652  assert(RealDef != nullptr && "Must have at least 1 Def");
653 #endif
654 
655  // We should only have one definition of the register. However to accommodate
656  // the requirements of two address code we also allow definitions in
657  // subsequent instructions provided they also read the register. That way
658  // we get a single contiguous lifetime.
659  //
660  // Definitions in MRI.def_begin() are unordered, search for the first.
662  MRI.def_operands(VReg), [VReg, &TRI](const MachineOperand &MO) {
663  return !MO.getParent()->readsRegister(VReg, &TRI);
664  });
665  assert(FirstDef != MRI.def_end() &&
666  "Must have one definition that does not redefine vreg");
667  MachineInstr &DefMI = *FirstDef->getParent();
668 
669  // The register scavenger will report a free register inserting an emergency
670  // spill/reload if necessary.
671  int SPAdj = 0;
672  const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
673  Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
674  ReserveAfter, SPAdj);
675  MRI.replaceRegWith(VReg, SReg);
676  ++NumScavengedRegs;
677  return SReg;
678 }
679 
680 /// Allocate (scavenge) vregs inside a single basic block.
681 /// Returns true if the target spill callback created new vregs and a 2nd pass
682 /// is necessary.
684  RegScavenger &RS,
688 
689  unsigned InitialNumVirtRegs = MRI.getNumVirtRegs();
690  bool NextInstructionReadsVReg = false;
691  for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {
692  --I;
693  // Move RegScavenger to the position between *I and *std::next(I).
694  RS.backward(I);
695 
696  // Look for unassigned vregs in the uses of *std::next(I).
697  if (NextInstructionReadsVReg) {
698  MachineBasicBlock::iterator N = std::next(I);
699  const MachineInstr &NMI = *N;
700  for (const MachineOperand &MO : NMI.operands()) {
701  if (!MO.isReg())
702  continue;
703  Register Reg = MO.getReg();
704  // We only care about virtual registers and ignore virtual registers
705  // created by the target callbacks in the process (those will be handled
706  // in a scavenging round).
708  Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
709  continue;
710  if (!MO.readsReg())
711  continue;
712 
713  Register SReg = scavengeVReg(MRI, RS, Reg, true);
714  N->addRegisterKilled(SReg, &TRI, false);
715  RS.setRegUsed(SReg);
716  }
717  }
718 
719  // Look for unassigned vregs in the defs of *I.
720  NextInstructionReadsVReg = false;
721  const MachineInstr &MI = *I;
722  for (const MachineOperand &MO : MI.operands()) {
723  if (!MO.isReg())
724  continue;
725  Register Reg = MO.getReg();
726  // Only vregs, no newly created vregs (see above).
728  Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
729  continue;
730  // We have to look at all operands anyway so we can precalculate here
731  // whether there is a reading operand. This allows use to skip the use
732  // step in the next iteration if there was none.
733  assert(!MO.isInternalRead() && "Cannot assign inside bundles");
734  assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
735  if (MO.readsReg()) {
736  NextInstructionReadsVReg = true;
737  }
738  if (MO.isDef()) {
739  Register SReg = scavengeVReg(MRI, RS, Reg, false);
740  I->addRegisterDead(SReg, &TRI, false);
741  }
742  }
743  }
744 #ifndef NDEBUG
745  for (const MachineOperand &MO : MBB.front().operands()) {
746  if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
747  continue;
748  assert(!MO.isInternalRead() && "Cannot assign inside bundles");
749  assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
750  assert(!MO.readsReg() && "Vreg use in first instruction not allowed");
751  }
752 #endif
753 
754  return MRI.getNumVirtRegs() != InitialNumVirtRegs;
755 }
756 
758  // FIXME: Iterating over the instruction stream is unnecessary. We can simply
759  // iterate over the vreg use list, which at this point only contains machine
760  // operands for which eliminateFrameIndex need a new scratch reg.
762  // Shortcut.
763  if (MRI.getNumVirtRegs() == 0) {
765  return;
766  }
767 
768  // Run through the instructions and find any virtual registers.
769  for (MachineBasicBlock &MBB : MF) {
770  if (MBB.empty())
771  continue;
772 
773  bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);
774  if (Again) {
775  LLVM_DEBUG(dbgs() << "Warning: Required two scavenging passes for block "
776  << MBB.getName() << '\n');
778  // The target required a 2nd run (because it created new vregs while
779  // spilling). Refuse to do another pass to keep compiletime in check.
780  if (Again)
781  report_fatal_error("Incomplete scavenging after 2nd pass");
782  }
783  }
784 
785  MRI.clearVirtRegs();
786  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
787 }
788 
789 namespace {
790 
791 /// This class runs register scavenging independ of the PrologEpilogInserter.
792 /// This is used in for testing.
793 class ScavengerTest : public MachineFunctionPass {
794 public:
795  static char ID;
796 
797  ScavengerTest() : MachineFunctionPass(ID) {}
798 
799  bool runOnMachineFunction(MachineFunction &MF) override {
800  const TargetSubtargetInfo &STI = MF.getSubtarget();
801  const TargetFrameLowering &TFL = *STI.getFrameLowering();
802 
803  RegScavenger RS;
804  // Let's hope that calling those outside of PrologEpilogueInserter works
805  // well enough to initialize the scavenger with some emergency spillslots
806  // for the target.
807  BitVector SavedRegs;
808  TFL.determineCalleeSaves(MF, SavedRegs, &RS);
810 
811  // Let's scavenge the current function
812  scavengeFrameVirtualRegs(MF, RS);
813  return true;
814  }
815 };
816 
817 } // end anonymous namespace
818 
819 char ScavengerTest::ID;
820 
821 INITIALIZE_PASS(ScavengerTest, "scavenger-test",
822  "Scavenge virtual registers inside basic blocks", false, false)
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::RegScavenger::scavengeRegisterBackwards
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Definition: RegisterScavenging.cpp:585
llvm::BitVector::none
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:181
Statistic.h
ErrorHandling.h
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:256
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::LiveRegUnits::available
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:116
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:334
TargetInstrInfo.h
addRegUnits
static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV, MCRegister Reg)
Definition: GCNHazardRecognizer.cpp:571
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:765
InstrLimit
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
llvm::LiveRegUnits::addLiveIns
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
Definition: LiveRegUnits.cpp:141
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::LiveRegUnits::addRegMasked
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
Definition: LiveRegUnits.h:93
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:409
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::RegScavenger::FindUnusedReg
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
Definition: RegisterScavenging.cpp:266
findSurvivorBackwards
static std::pair< MCPhysReg, MachineBasicBlock::iterator > findSurvivorBackwards(const MachineRegisterInfo &MRI, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const LiveRegUnits &LiveOut, ArrayRef< MCPhysReg > AllocationOrder, bool RestoreAfter)
Given the bitvector Available of free register units at position From.
Definition: RegisterScavenging.cpp:357
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::RegScavenger::isRegUsed
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Definition: RegisterScavenging.cpp:260
llvm::MCRegisterInfo::subregs
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
Definition: MCRegisterInfo.h:309
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetFrameLowering::processFunctionBeforeFrameFinalized
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: TargetFrameLowering.h:366
llvm::LiveRegUnits::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
Definition: LiveRegUnits.cpp:124
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::RegScavenger::scavengeRegister
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
Definition: RegisterScavenging.cpp:518
AvailabilityState::Available
@ Available
We know the block is fully available. This is a fixpoint.
scavengeVReg
static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS, Register VReg, bool ReserveAfter)
Allocate a register for the virtual register VReg.
Definition: RegisterScavenging.cpp:630
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:200
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:747
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:345
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::RegScavenger::backward
void backward()
Update internal register state and move MBB iterator backwards.
Definition: RegisterScavenging.cpp:239
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::RegScavenger::enterBasicBlockEnd
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
Definition: RegisterScavenging.cpp:87
BitVector.h
llvm::BitVector::clearBitsNotInMask
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
Definition: BitVector.h:718
llvm::BitVector
Definition: BitVector.h:75
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:339
llvm::LiveRegUnits
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::LiveRegUnits::removeReg
void removeReg(MCPhysReg Reg)
Removes all register units covered by physical register Reg.
Definition: LiveRegUnits.h:102
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:406
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCRegUnitRootIterator::isValid
bool isValid() const
Check if the iterator is at the end of the list.
Definition: MCRegisterInfo.h:773
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:289
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::AllocationOrder
Definition: AllocationOrder.h:30
llvm::LiveRegUnits::stepBackward
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
Definition: LiveRegUnits.cpp:40
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::TargetRegisterInfo::saveScavengerRegister
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition: TargetRegisterInfo.h:1002
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:756
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:955
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::scavengeFrameVirtualRegs
void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS)
Replaces all frame index virtual registers with physical registers.
Definition: RegisterScavenging.cpp:757
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
MCRegisterInfo.h
ArrayRef.h
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::LiveRegUnits::init
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition: LiveRegUnits.h:73
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:395
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
getFrameIndexOperandNum
static unsigned getFrameIndexOperandNum(MachineInstr &MI)
Definition: RegisterScavenging.cpp:435
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1000
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
TargetSubtargetInfo.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
LiveRegUnits.h
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:82
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineRegisterInfo::def_operands
iterator_range< def_iterator > def_operands(Register Reg) const
Definition: MachineRegisterInfo.h:397
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
uint16_t
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::RegScavenger::setRegUsed
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Definition: RegisterScavenging.cpp:51
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:257
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:200
llvm::RegScavenger::forward
void forward()
Move the internal MBB iterator and update register states.
Definition: RegisterScavenging.cpp:155
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:385
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:754
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::RegScavenger::getRegsAvailable
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Definition: RegisterScavenging.cpp:277
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:293
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:250
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:274
MachineOperand.h
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
spill
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Definition: README-SSE.txt:489
RegisterScavenging.h
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:619
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:310
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
scavengeFrameVirtualRegsInBlock
static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI, RegScavenger &RS, MachineBasicBlock &MBB)
Allocate (scavenge) vregs inside a single basic block.
Definition: RegisterScavenging.cpp:683
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38