LLVM  13.0.0git
RegisterScavenging.cpp
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1 //===- RegisterScavenging.cpp - Machine register scavenging ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the machine register scavenger. It can provide
11 /// information, such as unused registers, at any point in a machine basic
12 /// block. It also provides a mechanism to make registers available by evicting
13 /// them to spill slots.
14 //
15 //===----------------------------------------------------------------------===//
16 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Pass.h"
37 #include "llvm/Support/Debug.h"
40 #include <algorithm>
41 #include <cassert>
42 #include <iterator>
43 #include <limits>
44 #include <string>
45 #include <utility>
46 
47 using namespace llvm;
48 
49 #define DEBUG_TYPE "reg-scavenging"
50 
51 STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
52 
54  LiveUnits.addRegMasked(Reg, LaneMask);
55 }
56 
57 void RegScavenger::init(MachineBasicBlock &MBB) {
58  MachineFunction &MF = *MBB.getParent();
59  TII = MF.getSubtarget().getInstrInfo();
61  MRI = &MF.getRegInfo();
62  LiveUnits.init(*TRI);
63 
64  assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
65  "Target changed?");
66 
67  // Self-initialize.
68  if (!this->MBB) {
69  NumRegUnits = TRI->getNumRegUnits();
70  KillRegUnits.resize(NumRegUnits);
71  DefRegUnits.resize(NumRegUnits);
72  TmpRegUnits.resize(NumRegUnits);
73  }
74  this->MBB = &MBB;
75 
76  for (ScavengedInfo &SI : Scavenged) {
77  SI.Reg = 0;
78  SI.Restore = nullptr;
79  }
80 
81  Tracking = false;
82 }
83 
85  init(MBB);
86  LiveUnits.addLiveIns(MBB);
87 }
88 
90  init(MBB);
91  LiveUnits.addLiveOuts(MBB);
92 
93  // Move internal iterator at the last instruction of the block.
94  if (!MBB.empty()) {
95  MBBI = std::prev(MBB.end());
96  Tracking = true;
97  }
98 }
99 
100 void RegScavenger::addRegUnits(BitVector &BV, MCRegister Reg) {
101  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
102  BV.set(*RUI);
103 }
104 
105 void RegScavenger::removeRegUnits(BitVector &BV, MCRegister Reg) {
106  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
107  BV.reset(*RUI);
108 }
109 
110 void RegScavenger::determineKillsAndDefs() {
111  assert(Tracking && "Must be tracking to determine kills and defs");
112 
113  MachineInstr &MI = *MBBI;
114  assert(!MI.isDebugInstr() && "Debug values have no kills or defs");
115 
116  // Find out which registers are early clobbered, killed, defined, and marked
117  // def-dead in this instruction.
118  KillRegUnits.reset();
119  DefRegUnits.reset();
120  for (const MachineOperand &MO : MI.operands()) {
121  if (MO.isRegMask()) {
122  TmpRegUnits.reset();
123  for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
124  for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
125  if (MO.clobbersPhysReg(*RURI)) {
126  TmpRegUnits.set(RU);
127  break;
128  }
129  }
130  }
131 
132  // Apply the mask.
133  KillRegUnits |= TmpRegUnits;
134  }
135  if (!MO.isReg())
136  continue;
137  if (!MO.getReg().isPhysical() || isReserved(MO.getReg()))
138  continue;
139  MCRegister Reg = MO.getReg().asMCReg();
140 
141  if (MO.isUse()) {
142  // Ignore undef uses.
143  if (MO.isUndef())
144  continue;
145  if (MO.isKill())
146  addRegUnits(KillRegUnits, Reg);
147  } else {
148  assert(MO.isDef());
149  if (MO.isDead())
150  addRegUnits(KillRegUnits, Reg);
151  else
152  addRegUnits(DefRegUnits, Reg);
153  }
154  }
155 }
156 
158  // Move ptr forward.
159  if (!Tracking) {
160  MBBI = MBB->begin();
161  Tracking = true;
162  } else {
163  assert(MBBI != MBB->end() && "Already past the end of the basic block!");
164  MBBI = std::next(MBBI);
165  }
166  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
167 
168  MachineInstr &MI = *MBBI;
169 
170  for (ScavengedInfo &I : Scavenged) {
171  if (I.Restore != &MI)
172  continue;
173 
174  I.Reg = 0;
175  I.Restore = nullptr;
176  }
177 
178  if (MI.isDebugOrPseudoInstr())
179  return;
180 
181  determineKillsAndDefs();
182 
183  // Verify uses and defs.
184 #ifndef NDEBUG
185  for (const MachineOperand &MO : MI.operands()) {
186  if (!MO.isReg())
187  continue;
188  Register Reg = MO.getReg();
189  if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
190  continue;
191  if (MO.isUse()) {
192  if (MO.isUndef())
193  continue;
194  if (!isRegUsed(Reg)) {
195  // Check if it's partial live: e.g.
196  // D0 = insert_subreg undef D0, S0
197  // ... D0
198  // The problem is the insert_subreg could be eliminated. The use of
199  // D0 is using a partially undef value. This is not *incorrect* since
200  // S1 is can be freely clobbered.
201  // Ideally we would like a way to model this, but leaving the
202  // insert_subreg around causes both correctness and performance issues.
203  bool SubUsed = false;
204  for (const MCPhysReg &SubReg : TRI->subregs(Reg))
205  if (isRegUsed(SubReg)) {
206  SubUsed = true;
207  break;
208  }
209  bool SuperUsed = false;
210  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
211  if (isRegUsed(*SR)) {
212  SuperUsed = true;
213  break;
214  }
215  }
216  if (!SubUsed && !SuperUsed) {
217  MBB->getParent()->verify(nullptr, "In Register Scavenger");
218  llvm_unreachable("Using an undefined register!");
219  }
220  (void)SubUsed;
221  (void)SuperUsed;
222  }
223  } else {
224  assert(MO.isDef());
225 #if 0
226  // FIXME: Enable this once we've figured out how to correctly transfer
227  // implicit kills during codegen passes like the coalescer.
228  assert((KillRegs.test(Reg) || isUnused(Reg) ||
229  isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
230  "Re-defining a live register!");
231 #endif
232  }
233  }
234 #endif // NDEBUG
235 
236  // Commit the changes.
237  setUnused(KillRegUnits);
238  setUsed(DefRegUnits);
239 }
240 
242  assert(Tracking && "Must be tracking to determine kills and defs");
243 
244  const MachineInstr &MI = *MBBI;
245  LiveUnits.stepBackward(MI);
246 
247  // Expire scavenge spill frameindex uses.
248  for (ScavengedInfo &I : Scavenged) {
249  if (I.Restore == &MI) {
250  I.Reg = 0;
251  I.Restore = nullptr;
252  }
253  }
254 
255  if (MBBI == MBB->begin()) {
257  Tracking = false;
258  } else
259  --MBBI;
260 }
261 
262 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
263  if (isReserved(Reg))
264  return includeReserved;
265  return !LiveUnits.available(Reg);
266 }
267 
269  for (Register Reg : *RC) {
270  if (!isRegUsed(Reg)) {
271  LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
272  << "\n");
273  return Reg;
274  }
275  }
276  return 0;
277 }
278 
281  for (Register Reg : *RC)
282  if (!isRegUsed(Reg))
283  Mask.set(Reg);
284  return Mask;
285 }
286 
287 Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
288  BitVector &Candidates,
289  unsigned InstrLimit,
291  int Survivor = Candidates.find_first();
292  assert(Survivor > 0 && "No candidates for scavenging");
293 
295  assert(StartMI != ME && "MI already at terminator");
296  MachineBasicBlock::iterator RestorePointMI = StartMI;
298 
299  bool inVirtLiveRange = false;
300  for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
301  if (MI->isDebugOrPseudoInstr()) {
302  ++InstrLimit; // Don't count debug instructions
303  continue;
304  }
305  bool isVirtKillInsn = false;
306  bool isVirtDefInsn = false;
307  // Remove any candidates touched by instruction.
308  for (const MachineOperand &MO : MI->operands()) {
309  if (MO.isRegMask())
310  Candidates.clearBitsNotInMask(MO.getRegMask());
311  if (!MO.isReg() || MO.isUndef() || !MO.getReg())
312  continue;
313  if (Register::isVirtualRegister(MO.getReg())) {
314  if (MO.isDef())
315  isVirtDefInsn = true;
316  else if (MO.isKill())
317  isVirtKillInsn = true;
318  continue;
319  }
320  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
321  Candidates.reset(*AI);
322  }
323  // If we're not in a virtual reg's live range, this is a valid
324  // restore point.
325  if (!inVirtLiveRange) RestorePointMI = MI;
326 
327  // Update whether we're in the live range of a virtual register
328  if (isVirtKillInsn) inVirtLiveRange = false;
329  if (isVirtDefInsn) inVirtLiveRange = true;
330 
331  // Was our survivor untouched by this instruction?
332  if (Candidates.test(Survivor))
333  continue;
334 
335  // All candidates gone?
336  if (Candidates.none())
337  break;
338 
339  Survivor = Candidates.find_first();
340  }
341  // If we ran off the end, that's where we want to restore.
342  if (MI == ME) RestorePointMI = ME;
343  assert(RestorePointMI != StartMI &&
344  "No available scavenger restore location!");
345 
346  // We ran out of candidates, so stop the search.
347  UseMI = RestorePointMI;
348  return Survivor;
349 }
350 
351 /// Given the bitvector \p Available of free register units at position
352 /// \p From. Search backwards to find a register that is part of \p
353 /// Candidates and not used/clobbered until the point \p To. If there is
354 /// multiple candidates continue searching and pick the one that is not used/
355 /// clobbered for the longest time.
356 /// Returns the register and the earliest position we know it to be free or
357 /// the position MBB.end() if no register is available.
358 static std::pair<MCPhysReg, MachineBasicBlock::iterator>
362  bool RestoreAfter) {
363  bool FoundTo = false;
364  MCPhysReg Survivor = 0;
366  MachineBasicBlock &MBB = *From->getParent();
367  unsigned InstrLimit = 25;
368  unsigned InstrCountDown = InstrLimit;
370  LiveRegUnits Used(TRI);
371 
372  assert(From->getParent() == To->getParent() &&
373  "Target instruction is in other than current basic block, use "
374  "enterBasicBlockEnd first");
375 
376  for (MachineBasicBlock::iterator I = From;; --I) {
377  const MachineInstr &MI = *I;
378 
379  Used.accumulate(MI);
380 
381  if (I == To) {
382  // See if one of the registers in RC wasn't used so far.
383  for (MCPhysReg Reg : AllocationOrder) {
384  if (!MRI.isReserved(Reg) && Used.available(Reg) &&
385  LiveOut.available(Reg))
386  return std::make_pair(Reg, MBB.end());
387  }
388  // Otherwise we will continue up to InstrLimit instructions to find
389  // the register which is not defined/used for the longest time.
390  FoundTo = true;
391  Pos = To;
392  // Note: It was fine so far to start our search at From, however now that
393  // we have to spill, and can only place the restore after From then
394  // add the regs used/defed by std::next(From) to the set.
395  if (RestoreAfter)
396  Used.accumulate(*std::next(From));
397  }
398  if (FoundTo) {
399  if (Survivor == 0 || !Used.available(Survivor)) {
400  MCPhysReg AvilableReg = 0;
401  for (MCPhysReg Reg : AllocationOrder) {
402  if (!MRI.isReserved(Reg) && Used.available(Reg)) {
403  AvilableReg = Reg;
404  break;
405  }
406  }
407  if (AvilableReg == 0)
408  break;
409  Survivor = AvilableReg;
410  }
411  if (--InstrCountDown == 0)
412  break;
413 
414  // Keep searching when we find a vreg since the spilled register will
415  // be usefull for this other vreg as well later.
416  bool FoundVReg = false;
417  for (const MachineOperand &MO : MI.operands()) {
418  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
419  FoundVReg = true;
420  break;
421  }
422  }
423  if (FoundVReg) {
424  InstrCountDown = InstrLimit;
425  Pos = I;
426  }
427  if (I == MBB.begin())
428  break;
429  }
430  assert(I != MBB.begin() && "Did not find target instruction while "
431  "iterating backwards");
432  }
433 
434  return std::make_pair(Survivor, Pos);
435 }
436 
438  unsigned i = 0;
439  while (!MI.getOperand(i).isFI()) {
440  ++i;
441  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
442  }
443  return i;
444 }
445 
446 RegScavenger::ScavengedInfo &
447 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
450  // Find an available scavenging slot with size and alignment matching
451  // the requirements of the class RC.
452  const MachineFunction &MF = *Before->getMF();
453  const MachineFrameInfo &MFI = MF.getFrameInfo();
454  unsigned NeedSize = TRI->getSpillSize(RC);
455  Align NeedAlign = TRI->getSpillAlign(RC);
456 
457  unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();
458  int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
459  for (unsigned I = 0; I < Scavenged.size(); ++I) {
460  if (Scavenged[I].Reg != 0)
461  continue;
462  // Verify that this slot is valid for this register.
463  int FI = Scavenged[I].FrameIndex;
464  if (FI < FIB || FI >= FIE)
465  continue;
466  unsigned S = MFI.getObjectSize(FI);
467  Align A = MFI.getObjectAlign(FI);
468  if (NeedSize > S || NeedAlign > A)
469  continue;
470  // Avoid wasting slots with large size and/or large alignment. Pick one
471  // that is the best fit for this register class (in street metric).
472  // Picking a larger slot than necessary could happen if a slot for a
473  // larger register is reserved before a slot for a smaller one. When
474  // trying to spill a smaller register, the large slot would be found
475  // first, thus making it impossible to spill the larger register later.
476  unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value());
477  if (D < Diff) {
478  SI = I;
479  Diff = D;
480  }
481  }
482 
483  if (SI == Scavenged.size()) {
484  // We need to scavenge a register but have no spill slot, the target
485  // must know how to do it (if not, we'll assert below).
486  Scavenged.push_back(ScavengedInfo(FIE));
487  }
488 
489  // Avoid infinite regress
490  Scavenged[SI].Reg = Reg;
491 
492  // If the target knows how to save/restore the register, let it do so;
493  // otherwise, use the emergency stack spill slot.
494  if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
495  // Spill the scavenged register before \p Before.
496  int FI = Scavenged[SI].FrameIndex;
497  if (FI < FIB || FI >= FIE) {
498  std::string Msg = std::string("Error while trying to spill ") +
499  TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +
500  ": Cannot scavenge register without an emergency spill slot!";
501  report_fatal_error(Msg.c_str());
502  }
503  TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,
504  &RC, TRI);
505  MachineBasicBlock::iterator II = std::prev(Before);
506 
507  unsigned FIOperandNum = getFrameIndexOperandNum(*II);
508  TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
509 
510  // Restore the scavenged register before its use (or first terminator).
512  &RC, TRI);
513  II = std::prev(UseMI);
514 
515  FIOperandNum = getFrameIndexOperandNum(*II);
516  TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
517  }
518  return Scavenged[SI];
519 }
520 
523  int SPAdj, bool AllowSpill) {
524  MachineInstr &MI = *I;
525  const MachineFunction &MF = *MI.getMF();
526  // Consider all allocatable registers in the register class initially
527  BitVector Candidates = TRI->getAllocatableSet(MF, RC);
528 
529  // Exclude all the registers being used by the instruction.
530  for (const MachineOperand &MO : MI.operands()) {
531  if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
532  !Register::isVirtualRegister(MO.getReg()))
533  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
534  Candidates.reset(*AI);
535  }
536 
537  // Try to find a register that's unused if there is one, as then we won't
538  // have to spill.
540  Available &= Candidates;
541  if (Available.any())
542  Candidates = Available;
543 
544  // Find the register whose use is furthest away.
546  Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
547 
548  // If we found an unused register there is no reason to spill it.
549  if (!isRegUsed(SReg)) {
550  LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
551  return SReg;
552  }
553 
554  if (!AllowSpill)
555  return 0;
556 
557  ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
558  Scavenged.Restore = &*std::prev(UseMI);
559 
560  LLVM_DEBUG(dbgs() << "Scavenged register (with spill): "
561  << printReg(SReg, TRI) << "\n");
562 
563  return SReg;
564 }
565 
568  bool RestoreAfter, int SPAdj,
569  bool AllowSpill) {
570  const MachineBasicBlock &MBB = *To->getParent();
571  const MachineFunction &MF = *MBB.getParent();
572 
573  // Find the register whose use is furthest away.
576  std::pair<MCPhysReg, MachineBasicBlock::iterator> P =
577  findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder,
578  RestoreAfter);
579  MCPhysReg Reg = P.first;
580  MachineBasicBlock::iterator SpillBefore = P.second;
581  // Found an available register?
582  if (Reg != 0 && SpillBefore == MBB.end()) {
583  LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
584  << '\n');
585  return Reg;
586  }
587 
588  if (!AllowSpill)
589  return 0;
590 
591  assert(Reg != 0 && "No register left to scavenge!");
592 
593  MachineBasicBlock::iterator ReloadAfter =
594  RestoreAfter ? std::next(MBBI) : MBBI;
595  MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
596  if (ReloadBefore != MBB.end())
597  LLVM_DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
598  ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
599  Scavenged.Restore = &*std::prev(SpillBefore);
600  LiveUnits.removeReg(Reg);
601  LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
602  << " until " << *SpillBefore);
603  return Reg;
604 }
605 
606 /// Allocate a register for the virtual register \p VReg. The last use of
607 /// \p VReg is around the current position of the register scavenger \p RS.
608 /// \p ReserveAfter controls whether the scavenged register needs to be reserved
609 /// after the current instruction, otherwise it will only be reserved before the
610 /// current instruction.
612  Register VReg, bool ReserveAfter) {
614 #ifndef NDEBUG
615  // Verify that all definitions and uses are in the same basic block.
616  const MachineBasicBlock *CommonMBB = nullptr;
617  // Real definition for the reg, re-definitions are not considered.
618  const MachineInstr *RealDef = nullptr;
619  for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {
620  MachineBasicBlock *MBB = MO.getParent()->getParent();
621  if (CommonMBB == nullptr)
622  CommonMBB = MBB;
623  assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");
624  if (MO.isDef()) {
625  const MachineInstr &MI = *MO.getParent();
626  if (!MI.readsRegister(VReg, &TRI)) {
627  assert((!RealDef || RealDef == &MI) &&
628  "Can have at most one definition which is not a redefinition");
629  RealDef = &MI;
630  }
631  }
632  }
633  assert(RealDef != nullptr && "Must have at least 1 Def");
634 #endif
635 
636  // We should only have one definition of the register. However to accommodate
637  // the requirements of two address code we also allow definitions in
638  // subsequent instructions provided they also read the register. That way
639  // we get a single contiguous lifetime.
640  //
641  // Definitions in MRI.def_begin() are unordered, search for the first.
643  MRI.def_operands(VReg), [VReg, &TRI](const MachineOperand &MO) {
644  return !MO.getParent()->readsRegister(VReg, &TRI);
645  });
646  assert(FirstDef != MRI.def_end() &&
647  "Must have one definition that does not redefine vreg");
648  MachineInstr &DefMI = *FirstDef->getParent();
649 
650  // The register scavenger will report a free register inserting an emergency
651  // spill/reload if necessary.
652  int SPAdj = 0;
653  const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
654  Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
655  ReserveAfter, SPAdj);
656  MRI.replaceRegWith(VReg, SReg);
657  ++NumScavengedRegs;
658  return SReg;
659 }
660 
661 /// Allocate (scavenge) vregs inside a single basic block.
662 /// Returns true if the target spill callback created new vregs and a 2nd pass
663 /// is necessary.
665  RegScavenger &RS,
669 
670  unsigned InitialNumVirtRegs = MRI.getNumVirtRegs();
671  bool NextInstructionReadsVReg = false;
672  for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {
673  --I;
674  // Move RegScavenger to the position between *I and *std::next(I).
675  RS.backward(I);
676 
677  // Look for unassigned vregs in the uses of *std::next(I).
678  if (NextInstructionReadsVReg) {
679  MachineBasicBlock::iterator N = std::next(I);
680  const MachineInstr &NMI = *N;
681  for (const MachineOperand &MO : NMI.operands()) {
682  if (!MO.isReg())
683  continue;
684  Register Reg = MO.getReg();
685  // We only care about virtual registers and ignore virtual registers
686  // created by the target callbacks in the process (those will be handled
687  // in a scavenging round).
689  Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
690  continue;
691  if (!MO.readsReg())
692  continue;
693 
694  Register SReg = scavengeVReg(MRI, RS, Reg, true);
695  N->addRegisterKilled(SReg, &TRI, false);
696  RS.setRegUsed(SReg);
697  }
698  }
699 
700  // Look for unassigned vregs in the defs of *I.
701  NextInstructionReadsVReg = false;
702  const MachineInstr &MI = *I;
703  for (const MachineOperand &MO : MI.operands()) {
704  if (!MO.isReg())
705  continue;
706  Register Reg = MO.getReg();
707  // Only vregs, no newly created vregs (see above).
709  Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
710  continue;
711  // We have to look at all operands anyway so we can precalculate here
712  // whether there is a reading operand. This allows use to skip the use
713  // step in the next iteration if there was none.
714  assert(!MO.isInternalRead() && "Cannot assign inside bundles");
715  assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
716  if (MO.readsReg()) {
717  NextInstructionReadsVReg = true;
718  }
719  if (MO.isDef()) {
720  Register SReg = scavengeVReg(MRI, RS, Reg, false);
721  I->addRegisterDead(SReg, &TRI, false);
722  }
723  }
724  }
725 #ifndef NDEBUG
726  for (const MachineOperand &MO : MBB.front().operands()) {
727  if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
728  continue;
729  assert(!MO.isInternalRead() && "Cannot assign inside bundles");
730  assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
731  assert(!MO.readsReg() && "Vreg use in first instruction not allowed");
732  }
733 #endif
734 
735  return MRI.getNumVirtRegs() != InitialNumVirtRegs;
736 }
737 
739  // FIXME: Iterating over the instruction stream is unnecessary. We can simply
740  // iterate over the vreg use list, which at this point only contains machine
741  // operands for which eliminateFrameIndex need a new scratch reg.
743  // Shortcut.
744  if (MRI.getNumVirtRegs() == 0) {
746  return;
747  }
748 
749  // Run through the instructions and find any virtual registers.
750  for (MachineBasicBlock &MBB : MF) {
751  if (MBB.empty())
752  continue;
753 
754  bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);
755  if (Again) {
756  LLVM_DEBUG(dbgs() << "Warning: Required two scavenging passes for block "
757  << MBB.getName() << '\n');
759  // The target required a 2nd run (because it created new vregs while
760  // spilling). Refuse to do another pass to keep compiletime in check.
761  if (Again)
762  report_fatal_error("Incomplete scavenging after 2nd pass");
763  }
764  }
765 
766  MRI.clearVirtRegs();
767  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
768 }
769 
770 namespace {
771 
772 /// This class runs register scavenging independ of the PrologEpilogInserter.
773 /// This is used in for testing.
774 class ScavengerTest : public MachineFunctionPass {
775 public:
776  static char ID;
777 
778  ScavengerTest() : MachineFunctionPass(ID) {}
779 
780  bool runOnMachineFunction(MachineFunction &MF) override {
781  const TargetSubtargetInfo &STI = MF.getSubtarget();
782  const TargetFrameLowering &TFL = *STI.getFrameLowering();
783 
784  RegScavenger RS;
785  // Let's hope that calling those outside of PrologEpilogueInserter works
786  // well enough to initialize the scavenger with some emergency spillslots
787  // for the target.
788  BitVector SavedRegs;
789  TFL.determineCalleeSaves(MF, SavedRegs, &RS);
791 
792  // Let's scavenge the current function
793  scavengeFrameVirtualRegs(MF, RS);
794  return true;
795  }
796 };
797 
798 } // end anonymous namespace
799 
800 char ScavengerTest::ID;
801 
802 INITIALIZE_PASS(ScavengerTest, "scavenger-test",
803  "Scavenge virtual registers inside basic blocks", false, false)
llvm::LaneBitmask
Definition: LaneBitmask.h:39
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:42
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::RegScavenger::scavengeRegisterBackwards
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Definition: RegisterScavenging.cpp:566
llvm::BitVector::none
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:180
Statistic.h
ErrorHandling.h
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:238
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::LiveRegUnits::available
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:116
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
TargetInstrInfo.h
addRegUnits
static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV, MCRegister Reg)
Definition: GCNHazardRecognizer.cpp:503
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
InstrLimit
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
llvm::LiveRegUnits::addLiveIns
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
Definition: LiveRegUnits.cpp:141
llvm::LiveRegUnits::addRegMasked
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
Definition: LiveRegUnits.h:93
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:391
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RegScavenger::FindUnusedReg
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
Definition: RegisterScavenging.cpp:268
findSurvivorBackwards
static std::pair< MCPhysReg, MachineBasicBlock::iterator > findSurvivorBackwards(const MachineRegisterInfo &MRI, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const LiveRegUnits &LiveOut, ArrayRef< MCPhysReg > AllocationOrder, bool RestoreAfter)
Given the bitvector Available of free register units at position From.
Definition: RegisterScavenging.cpp:359
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
MachineRegisterInfo.h
llvm::RegScavenger::isRegUsed
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Definition: RegisterScavenging.cpp:262
llvm::MCRegisterInfo::subregs
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
Definition: MCRegisterInfo.h:309
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::TargetFrameLowering::processFunctionBeforeFrameFinalized
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: TargetFrameLowering.h:352
llvm::LiveRegUnits::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
Definition: LiveRegUnits.cpp:124
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::LiveRegUnits::accumulate
void accumulate(const MachineInstr &MI)
Adds all register units used, defined or clobbered in MI.
Definition: LiveRegUnits.cpp:60
llvm::RegScavenger::scavengeRegister
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
Definition: RegisterScavenging.cpp:521
AvailabilityState::Available
@ Available
We know the block is fully available. This is a fixpoint.
scavengeVReg
static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS, Register VReg, bool ReserveAfter)
Allocate a register for the virtual register VReg.
Definition: RegisterScavenging.cpp:611
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:900
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:197
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
SI
@ SI
Definition: SIInstrInfo.cpp:7344
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:646
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:337
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:166
llvm::RegScavenger::backward
void backward()
Update internal register state and move MBB iterator backwards.
Definition: RegisterScavenging.cpp:241
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::RegScavenger::enterBasicBlockEnd
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
Definition: RegisterScavenging.cpp:89
BitVector.h
llvm::BitVector::clearBitsNotInMask
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
Definition: BitVector.h:705
llvm::BitVector
Definition: BitVector.h:74
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:321
llvm::LiveRegUnits
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::LiveRegUnits::removeReg
void removeReg(MCPhysReg Reg)
Removes all register units covered by physical register Reg.
Definition: LiveRegUnits.h:102
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:388
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCRegUnitRootIterator::isValid
bool isValid() const
Check if the iterator is at the end of the list.
Definition: MCRegisterInfo.h:765
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::AllocationOrder
Definition: AllocationOrder.h:30
llvm::LiveRegUnits::stepBackward
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
Definition: LiveRegUnits.cpp:40
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::TargetRegisterInfo::saveScavengerRegister
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition: TargetRegisterInfo.h:975
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:729
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:913
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
llvm::scavengeFrameVirtualRegs
void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS)
Replaces all frame index virtual registers with physical registers.
Definition: RegisterScavenging.cpp:738
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:471
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
MCRegisterInfo.h
ArrayRef.h
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::LiveRegUnits::init
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition: LiveRegUnits.h:73
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:387
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
getFrameIndexOperandNum
static unsigned getFrameIndexOperandNum(MachineInstr &MI)
Definition: RegisterScavenging.cpp:437
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:958
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
TargetSubtargetInfo.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
LiveRegUnits.h
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1532
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:84
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:380
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineRegisterInfo::def_operands
iterator_range< def_iterator > def_operands(Register Reg) const
Definition: MachineRegisterInfo.h:389
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
uint16_t
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::RegScavenger::setRegUsed
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Definition: RegisterScavenging.cpp:53
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:202
llvm::RegScavenger::forward
void forward()
Move the internal MBB iterator and update register states.
Definition: RegisterScavenging.cpp:157
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:384
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:746
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::RegScavenger::getRegsAvailable
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Definition: RegisterScavenging.cpp:279
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:292
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:101
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:266
MachineOperand.h
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:78
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
spill
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Definition: README-SSE.txt:489
RegisterScavenging.h
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:607
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:313
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
scavengeFrameVirtualRegsInBlock
static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI, RegScavenger &RS, MachineBasicBlock &MBB)
Allocate (scavenge) vregs inside a single basic block.
Definition: RegisterScavenging.cpp:664
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38