LLVM  13.0.0git
Mips16InstrInfo.h
Go to the documentation of this file.
1 //===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips16 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
14 #define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
15 
16 #include "Mips16RegisterInfo.h"
17 #include "MipsInstrInfo.h"
20 #include <cstdint>
21 
22 namespace llvm {
23 
24 class MCInstrDesc;
25 class MipsSubtarget;
26 
28  const Mips16RegisterInfo RI;
29 
30 public:
31  explicit Mips16InstrInfo(const MipsSubtarget &STI);
32 
33  const MipsRegisterInfo &getRegisterInfo() const override;
34 
35  /// isLoadFromStackSlot - If the specified machine instruction is a direct
36  /// load from a stack slot, return the virtual or physical register number of
37  /// the destination along with the FrameIndex of the loaded stack slot. If
38  /// not, return 0. This predicate must return 0 if the instruction has
39  /// any side effects other than loading from the stack slot.
40  unsigned isLoadFromStackSlot(const MachineInstr &MI,
41  int &FrameIndex) const override;
42 
43  /// isStoreToStackSlot - If the specified machine instruction is a direct
44  /// store to a stack slot, return the virtual or physical register number of
45  /// the source reg along with the FrameIndex of the loaded stack slot. If
46  /// not, return 0. This predicate must return 0 if the instruction has
47  /// any side effects other than storing to the stack slot.
48  unsigned isStoreToStackSlot(const MachineInstr &MI,
49  int &FrameIndex) const override;
50 
52  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
53  bool KillSrc) const override;
54 
57  Register SrcReg, bool isKill, int FrameIndex,
58  const TargetRegisterClass *RC,
59  const TargetRegisterInfo *TRI,
60  int64_t Offset) const override;
61 
64  Register DestReg, int FrameIndex,
65  const TargetRegisterClass *RC,
66  const TargetRegisterInfo *TRI,
67  int64_t Offset) const override;
68 
69  bool expandPostRAPseudo(MachineInstr &MI) const override;
70 
71  unsigned getOppositeBranchOpc(unsigned Opc) const override;
72 
73  // Adjust SP by FrameSize bytes. Save RA, S0, S1
74  void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
76 
77  // Adjust SP by FrameSize bytes. Restore RA, S0, S1
78  void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
80 
81  /// Adjust SP by Amount bytes.
82  void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
83  MachineBasicBlock::iterator I) const override;
84 
85  /// Emit a series of instructions to load an immediate.
86  // This is to adjust some FrameReg. We return the new register to be used
87  // in place of FrameReg and the adjusted immediate field (&NewImm)
88  unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
90  unsigned &NewImm) const;
91 
92  static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
93 
94  static bool validSpImm8(int offset) {
95  return ((offset & 7) == 0) && isInt<11>(offset);
96  }
97 
98  // build the proper one based on the Imm field
99 
100  const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
101 
102  void BuildAddiuSpImm
103  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
104 
105 protected:
106  /// If the specific machine instruction is a instruction that moves/copies
107  /// value from one register to another register return destination and source
108  /// registers as machine operands.
110 
111 private:
112  unsigned getAnalyzableBrOpc(unsigned Opc) const override;
113 
114  void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115  unsigned Opc) const;
116 
117  // Adjust SP by Amount bytes where bytes can be up to 32bit number.
118  void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
120  unsigned Reg1, unsigned Reg2) const;
121 
122  // Adjust SP by Amount bytes where bytes can be up to 32bit number.
123  void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
126 };
127 
128 } // end namespace llvm
129 
130 #endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
llvm::Mips16InstrInfo::adjustStackPtr
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
Definition: Mips16InstrInfo.cpp:306
Mips16RegisterInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MathExtras.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::Mips16InstrInfo::restoreFrame
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Definition: Mips16InstrInfo.cpp:240
llvm::Mips16InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: Mips16InstrInfo.cpp:64
llvm::Mips16InstrInfo::getRegisterInfo
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: Mips16InstrInfo.cpp:45
llvm::Mips16InstrInfo::AddiuSpImm
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
Definition: Mips16InstrInfo.cpp:455
llvm::Mips16InstrInfo::loadRegFromStack
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
Definition: Mips16InstrInfo.cpp:124
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::Mips16InstrInfo::getOppositeBranchOpc
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
Definition: Mips16InstrInfo.cpp:158
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::Mips16InstrInfo::Mips16InstrInfo
Mips16InstrInfo(const MipsSubtarget &STI)
Definition: Mips16InstrInfo.cpp:42
llvm::Mips16InstrInfo::validImmediate
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
Definition: Mips16InstrInfo.cpp:472
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::Mips16RegisterInfo
Definition: Mips16RegisterInfo.h:20
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MipsInstrInfo
Definition: MipsInstrInfo.h:41
llvm::Mips16InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: Mips16InstrInfo.cpp:69
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Mips16InstrInfo
Definition: Mips16InstrInfo.h:27
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Mips16InstrInfo::validSpImm8
static bool validSpImm8(int offset)
Definition: Mips16InstrInfo.h:94
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MipsRegisterInfo
Definition: MipsRegisterInfo.h:27
llvm::Mips16InstrInfo::loadImmediate
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
Definition: Mips16InstrInfo.cpp:320
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Mips16InstrInfo::makeFrame
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Definition: Mips16InstrInfo.cpp:210
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::Mips16InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition: Mips16InstrInfo.cpp:54
llvm::Mips16InstrInfo::storeRegToStack
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
Definition: Mips16InstrInfo.cpp:106
llvm::Mips16InstrInfo::BuildAddiuSpImm
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
Definition: Mips16InstrInfo.cpp:463
llvm::Mips16InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: Mips16InstrInfo.cpp:100
MipsInstrInfo.h
llvm::Mips16InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: Mips16InstrInfo.cpp:142
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23