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40 #define DEBUG_TYPE "mips16-instrinfo"
75 if (Mips::CPU16RegsRegClass.
contains(DestReg) &&
76 Mips::GPR32RegClass.
contains(SrcReg))
77 Opc = Mips::MoveR3216;
78 else if (Mips::GPR32RegClass.
contains(DestReg) &&
79 Mips::CPU16RegsRegClass.
contains(SrcReg))
80 Opc = Mips::Move32R16;
81 else if ((SrcReg == Mips::HI0) &&
82 (Mips::CPU16RegsRegClass.
contains(DestReg)))
83 Opc = Mips::Mfhi16, SrcReg = 0;
84 else if ((SrcReg == Mips::LO0) &&
85 (Mips::CPU16RegsRegClass.
contains(DestReg)))
86 Opc = Mips::Mflo16, SrcReg = 0;
88 assert(Opc &&
"Cannot copy registers");
108 Register SrcReg,
bool isKill,
int FI,
116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
117 Opc = Mips::SwRxSpImmX16;
118 assert(Opc &&
"Register class not handled!");
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
136 Opc = Mips::LwRxSpImmX16;
137 assert(Opc &&
"Register class not handled!");
144 switch (
MI.getDesc().getOpcode()) {
148 ExpandRetRA16(
MBB,
MI, Mips::JrcRa16);
160 case Mips::BeqzRxImmX16:
return Mips::BnezRxImmX16;
161 case Mips::BnezRxImmX16:
return Mips::BeqzRxImmX16;
162 case Mips::BeqzRxImm16:
return Mips::BnezRxImm16;
163 case Mips::BnezRxImm16:
return Mips::BeqzRxImm16;
164 case Mips::BteqzT8CmpX16:
return Mips::BtnezT8CmpX16;
165 case Mips::BteqzT8SltX16:
return Mips::BtnezT8SltX16;
166 case Mips::BteqzT8SltiX16:
return Mips::BtnezT8SltiX16;
167 case Mips::Btnez16:
return Mips::Bteqz16;
168 case Mips::BtnezX16:
return Mips::BteqzX16;
169 case Mips::BtnezT8CmpiX16:
return Mips::BteqzT8CmpiX16;
170 case Mips::BtnezT8SltuX16:
return Mips::BteqzT8SltuX16;
171 case Mips::BtnezT8SltiuX16:
return Mips::BteqzT8SltiuX16;
172 case Mips::Bteqz16:
return Mips::Btnez16;
173 case Mips::BteqzX16:
return Mips::BtnezX16;
174 case Mips::BteqzT8CmpiX16:
return Mips::BtnezT8CmpiX16;
175 case Mips::BteqzT8SltuX16:
return Mips::BtnezT8SltuX16;
176 case Mips::BteqzT8SltiuX16:
return Mips::BtnezT8SltiuX16;
177 case Mips::BtnezT8CmpX16:
return Mips::BteqzT8CmpX16;
178 case Mips::BtnezT8SltX16:
return Mips::BteqzT8SltX16;
179 case Mips::BtnezT8SltiX16:
return Mips::BteqzT8SltiX16;
186 unsigned Flags = 0) {
187 for (
unsigned i = 0,
e = CSI.
size();
i !=
e; ++
i) {
193 unsigned Reg = CSI[
e-
i-1].getReg();
219 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
225 if (isUInt<11>(FrameSize))
230 int64_t Remainder = FrameSize - Base;
235 adjustStackPtrBig(SP, -Remainder,
MBB,
I, Mips::V0, Mips::V1);
249 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
250 Mips::Restore16:Mips::RestoreX16;
252 if (!isUInt<11>(FrameSize)) {
253 unsigned Base = 2040;
254 int64_t Remainder = FrameSize - Base;
261 adjustStackPtrBig(SP, Remainder,
MBB,
I, Mips::A0, Mips::A1);
275 void Mips16InstrInfo::adjustStackPtrBig(
unsigned SP, int64_t Amount,
278 unsigned Reg1,
unsigned Reg2)
const {
299 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
315 adjustStackPtrBigUnrestricted(SP, Amount,
MBB,
I);
324 unsigned &NewImm)
const {
338 int32_t lo = Imm & 0xFFFF;
352 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
354 for (
unsigned i = 0,
e = II->getNumOperands();
i !=
e; ++
i) {
370 for (
unsigned i = 0,
e = II->getNumOperands();
i !=
e; ++
i) {
384 unsigned FirstRegSaved =0, SecondRegSaved=0;
385 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
394 FirstRegSavedTo = Mips::T0;
402 if (FrameReg == Mips::SP) {
407 if (DefReg!= SpReg) {
408 SecondRegSaved = SpReg;
424 if (FirstRegSaved || SecondRegSaved) {
434 unsigned Mips16InstrInfo::getAnalyzableBrOpc(
unsigned Opc)
const {
435 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
436 Opc == Mips::Bimm16 ||
437 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
438 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
439 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
440 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
441 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
442 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
443 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
444 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
445 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
446 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
451 unsigned Opc)
const {
457 return get(Mips::AddiuSpImm16);
459 return get(Mips::AddiuSpImmX16);
475 case Mips::LbRxRyOffMemX16:
476 case Mips::LbuRxRyOffMemX16:
477 case Mips::LhRxRyOffMemX16:
478 case Mips::LhuRxRyOffMemX16:
479 case Mips::SbRxRyOffMemX16:
480 case Mips::ShRxRyOffMemX16:
481 case Mips::LwRxRyOffMemX16:
482 case Mips::SwRxRyOffMemX16:
483 case Mips::SwRxSpImmX16:
484 case Mips::LwRxSpImmX16:
486 case Mips::AddiuRxRyOffMemX16:
487 if ((
Reg == Mips::PC) || (
Reg == Mips::SP))
489 return isInt<15>(Amount);
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
return AArch64::GPR64RegClass contains(Reg)
static void addSaveRestoreRegs(MachineInstrBuilder &MIB, ArrayRef< CalleeSavedInfo > CSI, unsigned Flags=0)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A description of a memory reference used in the backend.
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
unsigned const TargetRegisterInfo * TRI
Mips16InstrInfo(const MipsSubtarget &STI)
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
@ Available
We know the block is fully available. This is a fixpoint.
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
@ Define
Register definition.
@ Kill
The last use of a register.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
static bool validSpImm8(int offset)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
SI optimize exec mask operations pre RA
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ MOLoad
The memory access reads data.
Wrapper class representing virtual and physical registers.
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
constexpr bool isInt< 16 >(int64_t x)
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
Should compile to something r4 addze r3 instead we get
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
void forward()
Move the internal MBB iterator and update register states.
@ MOStore
The memory access writes data.
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
size_t size() const
size - Get the array size.
bool expandPostRAPseudo(MachineInstr &MI) const override
Wrapper class representing physical registers. Should be passed by value.