#include "Target/Mips/Mips16InstrInfo.h"

Inheritance diagram for llvm::Mips16InstrInfo:

Public Member Functions
	Mips16InstrInfo (const MipsSubtarget &STI)
const Mips16RegisterInfo &	getRegisterInfo () const
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool	expandPostRAPseudo (MachineInstr &MI) const override
unsigned	getOppositeBranchOpc (unsigned Opc) const override
	GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
void	makeFrame (unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
void	restoreFrame (unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
void	adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
	Adjust SP by Amount bytes.
unsigned	loadImmediate (unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
	Emit a series of instructions to load an immediate.
const MCInstrDesc &	AddiuSpImm (int64_t Imm) const
void	BuildAddiuSpImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
Public Member Functions inherited from llvm::MipsInstrInfo
	MipsInstrInfo (const MipsSubtarget &STI, const MipsRegisterInfo &RI, unsigned UncondBrOpc)
MCInst	getNop () const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
	Branch Analysis.
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
	reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
BranchType	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const
unsigned	getEquivalentCompactForm (const MachineBasicBlock::iterator I) const
	Determine the opcode of a non-delay slot form for a branch if one exists.
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
	Determine if the branch target is in range.
bool	SafeAfterMflo (const MachineInstr &MI) const
bool	SafeInForbiddenSlot (const MachineInstr &MI) const
	Predicate to determine if an instruction can go in a forbidden slot.
bool	SafeInFPUDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
	Predicate to determine if an instruction can go in an FPU delay slot.
bool	SafeInLoadDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
	Predicate to determine if an instruction can go in a load delay slot.
bool	IsMfloOrMfhi (const MachineInstr &MI) const
bool	HasForbiddenSlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has a forbidden slot.
bool	HasFPUDelaySlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has an FPU delay slot.
bool	HasLoadDelaySlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has a load delay slot.
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
	Insert nop instruction when hazard condition is found.
MachineInstrBuilder	insertNop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
	Insert an ISA appropriate nop.
const MipsRegisterInfo &	getRegisterInfo () const
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
virtual bool	isBranchWithImm (unsigned Opc) const
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	Return the number of bytes of code the specified instruction may be.
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
MachineInstrBuilder	genInstrWithNewOpc (unsigned NewOpc, MachineBasicBlock::iterator I) const
	Create an instruction which has the same operands and memory operands as MI but has a new opcode.
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
	Perform target specific instruction verification.
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
std::optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override
std::optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override

Static Public Member Functions
static bool	validImmediate (unsigned Opcode, unsigned Reg, int64_t Amount)
static bool	validSpImm8 (int offset)
Static Public Member Functions inherited from llvm::MipsInstrInfo
static const MipsInstrInfo *	create (MipsSubtarget &STI)

Protected Member Functions
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Protected Member Functions inherited from llvm::MipsInstrInfo
bool	isZeroImm (const MachineOperand &op) const
MachineMemOperand *	GetMemOperand (MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const

Additional Inherited Members
Public Types inherited from llvm::MipsInstrInfo
enum	BranchType { BT_None , BT_NoBranch , BT_Uncond , BT_Cond , BT_CondUncond , BT_Indirect }
Protected Attributes inherited from llvm::MipsInstrInfo
const MipsSubtarget &	Subtarget
unsigned	UncondBrOpc

Detailed Description

Definition at line 27 of file Mips16InstrInfo.h.

Constructor & Destructor Documentation

◆ Mips16InstrInfo()

Mips16InstrInfo::Mips16InstrInfo ( const MipsSubtarget & STI )

explicit

Definition at line 39 of file Mips16InstrInfo.cpp.

References llvm::MipsInstrInfo::MipsInstrInfo().

Member Function Documentation

◆ AddiuSpImm()

const MCInstrDesc & Mips16InstrInfo::AddiuSpImm ( int64_t Imm ) const

Definition at line 447 of file Mips16InstrInfo.cpp.

References llvm::get(), and validSpImm8().

Referenced by BuildAddiuSpImm().

◆ adjustStackPtr()

void Mips16InstrInfo::adjustStackPtr	(	unsigned	SP,
		int64_t	Amount,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I ) const

overridevirtual

Adjust SP by Amount bytes.

Implements llvm::MipsInstrInfo.

Definition at line 300 of file Mips16InstrInfo.cpp.

References BuildAddiuSpImm(), I, llvm::isInt(), and MBB.

◆ BuildAddiuSpImm()

void Mips16InstrInfo::BuildAddiuSpImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		int64_t	Imm ) const

Definition at line 454 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), AddiuSpImm(), llvm::BuildMI(), DL, I, and MBB.

Referenced by adjustStackPtr(), makeFrame(), and restoreFrame().

◆ copyPhysReg()

void Mips16InstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		Register	DestReg,
		Register	SrcReg,
		bool	KillSrc,
		bool	RenamableDest = false,
		bool	RenamableSrc = false ) const

override

Definition at line 62 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::RegState::Define, DL, llvm::get(), llvm::getKillRegState(), I, MBB, and Opc.

Referenced by loadImmediate().

◆ expandPostRAPseudo()

bool Mips16InstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 136 of file Mips16InstrInfo.cpp.

References MBB, and MI.

◆ getOppositeBranchOpc()

unsigned Mips16InstrInfo::getOppositeBranchOpc ( unsigned Opc ) const

overridevirtual

GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.

turning BEQ to BNE.

Implements llvm::MipsInstrInfo.

Definition at line 152 of file Mips16InstrInfo.cpp.

References llvm_unreachable, and Opc.

◆ getRegisterInfo()

const Mips16RegisterInfo & llvm::Mips16InstrInfo::getRegisterInfo ( ) const

inline

Definition at line 33 of file Mips16InstrInfo.h.

◆ isCopyInstrImpl()

std::optional< DestSourcePair > Mips16InstrInfo::isCopyInstrImpl ( const MachineInstr & MI ) const

overrideprotected

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 94 of file Mips16InstrInfo.cpp.

References MI.

◆ isLoadFromStackSlot()

Register Mips16InstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex ) const

override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 47 of file Mips16InstrInfo.cpp.

References MI.

◆ isStoreToStackSlot()

Register Mips16InstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex ) const

override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 57 of file Mips16InstrInfo.cpp.

References MI.

◆ loadImmediate()

unsigned Mips16InstrInfo::loadImmediate	(	unsigned	FrameReg,
		int64_t	Imm,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		unsigned &	NewImm ) const

Emit a series of instructions to load an immediate.

This function generates the sequence of instructions needed to get the result of adding register REG and immediate IMM.

Definition at line 314 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), Available, llvm::RegScavenger::backward(), llvm::BuildMI(), copyPhysReg(), DL, llvm::RegScavenger::enterBasicBlockEnd(), llvm::BitVector::find_first(), llvm::get(), llvm::RegScavenger::getRegsAvailable(), II, llvm::RegState::Kill, MBB, and llvm::BitVector::reset().

◆ loadRegFromStack()

void Mips16InstrInfo::loadRegFromStack	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		Register	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		int64_t	Offset,
		MachineInstr::MIFlag	Flags = MachineInstr::NoFlags ) const

overridevirtual

Implements llvm::MipsInstrInfo.

Definition at line 118 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MipsInstrInfo::GetMemOperand(), I, MBB, llvm::MachineMemOperand::MOLoad, llvm::Offset, and Opc.

◆ makeFrame()

void Mips16InstrInfo::makeFrame	(	unsigned	SP,
		int64_t	FrameSize,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I ) const

Definition at line 204 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), addSaveRestoreRegs(), llvm::sampleprof::Base, BuildAddiuSpImm(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineFrameInfo::getCalleeSavedInfo(), llvm::MachineFunction::getFrameInfo(), I, llvm::isInt(), llvm::isUInt(), MBB, Opc, and llvm::Reserved.

◆ restoreFrame()

void Mips16InstrInfo::restoreFrame	(	unsigned	SP,
		int64_t	FrameSize,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I ) const

◆ storeRegToStack()

void Mips16InstrInfo::storeRegToStack	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		Register	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		int64_t	Offset,
		MachineInstr::MIFlag	Flags = MachineInstr::NoFlags ) const

overridevirtual

Implements llvm::MipsInstrInfo.

Definition at line 100 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::getKillRegState(), llvm::MipsInstrInfo::GetMemOperand(), I, MBB, llvm::MachineMemOperand::MOStore, llvm::Offset, and Opc.

◆ validImmediate()

bool Mips16InstrInfo::validImmediate	(	unsigned	Opcode,
		unsigned	Reg,
		int64_t	Amount )

static

Definition at line 464 of file Mips16InstrInfo.cpp.

References llvm::isInt(), and llvm_unreachable.

◆ validSpImm8()

bool llvm::Mips16InstrInfo::validSpImm8 ( int offset )

inlinestatic

Definition at line 94 of file Mips16InstrInfo.h.

References llvm::isInt().

Referenced by AddiuSpImm().

The documentation for this class was generated from the following files:

lib/Target/Mips/Mips16InstrInfo.h
lib/Target/Mips/Mips16InstrInfo.cpp

Public Member Functions

Static Public Member Functions

Protected Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ Mips16InstrInfo()

Member Function Documentation

◆ AddiuSpImm()

◆ adjustStackPtr()

◆ BuildAddiuSpImm()

◆ copyPhysReg()

◆ expandPostRAPseudo()

◆ getOppositeBranchOpc()

◆ getRegisterInfo()

◆ isCopyInstrImpl()

◆ isLoadFromStackSlot()

◆ isStoreToStackSlot()

◆ loadImmediate()

◆ loadRegFromStack()

◆ makeFrame()

◆ restoreFrame()

◆ storeRegToStack()

◆ validImmediate()

◆ validSpImm8()