#include "Target/Mips/Mips16InstrInfo.h"

Inheritance diagram for llvm::Mips16InstrInfo:

Collaboration diagram for llvm::Mips16InstrInfo:

[legend]

Public Member Functions
	Mips16InstrInfo (const MipsSubtarget &STI)

const MipsRegisterInfo &	getRegisterInfo () const override
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...

unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More...

unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override

void	storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset) const override

void	loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, int64_t Offset) const override

bool	expandPostRAPseudo (MachineInstr &MI) const override

unsigned	getOppositeBranchOpc (unsigned Opc) const override
	GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g. More...

void	makeFrame (unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const

void	restoreFrame (unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const

void	adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
	Adjust SP by Amount bytes. More...

unsigned	loadImmediate (unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
	Emit a series of instructions to load an immediate. More...

const MCInstrDesc &	AddiuSpImm (int64_t Imm) const

void	BuildAddiuSpImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const

Public Member Functions inherited from llvm::MipsInstrInfo
	MipsInstrInfo (const MipsSubtarget &STI, unsigned UncondBrOpc)

bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
	Branch Analysis. More...

unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
	reverseBranchCondition - Return the inverse opcode of the specified Branch instruction. More...

BranchType	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const

unsigned	getEquivalentCompactForm (const MachineBasicBlock::iterator I) const
	Determine the opcode of a non-delay slot form for a branch if one exists. More...

bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
	Determine if the branch target is in range. More...

bool	SafeInForbiddenSlot (const MachineInstr &MI) const
	Predicate to determine if an instruction can go in a forbidden slot. More...

bool	SafeInFPUDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
	Predicate to determine if an instruction can go in an FPU delay slot. More...

bool	SafeInLoadDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
	Predicate to determine if an instruction can go in a load delay slot. More...

bool	HasForbiddenSlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has a forbidden slot. More...

bool	HasFPUDelaySlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has an FPU delay slot. More...

bool	HasLoadDelaySlot (const MachineInstr &MI) const
	Predicate to determine if an instruction has a load delay slot. More...

void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
	Insert nop instruction when hazard condition is found. More...

MachineInstrBuilder	insertNop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
	Insert an ISA appropriate `nop`. More...

virtual bool	isBranchWithImm (unsigned Opc) const

unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	Return the number of bytes of code the specified instruction may be. More...

void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const override

void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const override

MachineInstrBuilder	genInstrWithNewOpc (unsigned NewOpc, MachineBasicBlock::iterator I) const
	Create an instruction which has the same operands and memory operands as MI but has a new opcode. More...

bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
	Perform target specific instruction verification. More...

std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override

ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override

Optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override

Optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override

Static Public Member Functions
static bool	validImmediate (unsigned Opcode, unsigned Reg, int64_t Amount)

static bool	validSpImm8 (int offset)

Static Public Member Functions inherited from llvm::MipsInstrInfo
static const MipsInstrInfo *	create (MipsSubtarget &STI)

Protected Member Functions
Optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. More...

Protected Member Functions inherited from llvm::MipsInstrInfo
bool	isZeroImm (const MachineOperand &op) const

MachineMemOperand *	GetMemOperand (MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const

Additional Inherited Members
Public Types inherited from llvm::MipsInstrInfo
enum	BranchType { BT_None, BT_NoBranch, BT_Uncond, BT_Cond, BT_CondUncond, BT_Indirect }

Protected Attributes inherited from llvm::MipsInstrInfo
const MipsSubtarget &	Subtarget

unsigned	UncondBrOpc

Detailed Description

Definition at line 27 of file Mips16InstrInfo.h.

Constructor & Destructor Documentation

◆ Mips16InstrInfo()

Mips16InstrInfo::Mips16InstrInfo ( const MipsSubtarget & STI )

explicit

Definition at line 42 of file Mips16InstrInfo.cpp.

Member Function Documentation

◆ AddiuSpImm()

const MCInstrDesc & Mips16InstrInfo::AddiuSpImm ( int64_t Imm ) const

Definition at line 455 of file Mips16InstrInfo.cpp.

References get, llvm::RISCVMatInt::Imm, and validSpImm8().

◆ adjustStackPtr()

void Mips16InstrInfo::adjustStackPtr	(	unsigned	SP,
		int64_t	Amount,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I
	)		const

overridevirtual

Adjust SP by Amount bytes.

Implements llvm::MipsInstrInfo.

Definition at line 306 of file Mips16InstrInfo.cpp.

References BuildAddiuSpImm(), I, llvm::isInt< 16 >(), and MBB.

◆ BuildAddiuSpImm()

void Mips16InstrInfo::BuildAddiuSpImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		int64_t	Imm
	)		const

Definition at line 463 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, I, llvm::RISCVMatInt::Imm, and MBB.

Referenced by adjustStackPtr(), makeFrame(), and restoreFrame().

◆ copyPhysReg()

void Mips16InstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc
	)		const

override

Definition at line 69 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::RegState::Define, DL, get, llvm::getKillRegState(), I, and MBB.

Referenced by loadImmediate().

◆ expandPostRAPseudo()

bool Mips16InstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 142 of file Mips16InstrInfo.cpp.

References llvm::MachineBasicBlock::erase(), MBB, and MI.

◆ getOppositeBranchOpc()

unsigned Mips16InstrInfo::getOppositeBranchOpc ( unsigned Opc ) const

overridevirtual

GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.

turning BEQ to BNE.

Implements llvm::MipsInstrInfo.

Definition at line 158 of file Mips16InstrInfo.cpp.

References llvm_unreachable.

◆ getRegisterInfo()

const MipsRegisterInfo & Mips16InstrInfo::getRegisterInfo ( ) const

overridevirtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implements llvm::MipsInstrInfo.

Definition at line 45 of file Mips16InstrInfo.cpp.

◆ isCopyInstrImpl()

Optional< DestSourcePair > Mips16InstrInfo::isCopyInstrImpl ( const MachineInstr & MI ) const

overrideprotected

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 100 of file Mips16InstrInfo.cpp.

References MI, and llvm::None.

◆ isLoadFromStackSlot()

unsigned Mips16InstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 54 of file Mips16InstrInfo.cpp.

◆ isStoreToStackSlot()

unsigned Mips16InstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 64 of file Mips16InstrInfo.cpp.

◆ loadImmediate()

unsigned Mips16InstrInfo::loadImmediate	(	unsigned	FrameReg,
		int64_t	Imm,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		unsigned &	NewImm
	)		const

Emit a series of instructions to load an immediate.

This function generates the sequence of instructions needed to get the result of adding register REG and immediate IMM.

Definition at line 320 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), Available, llvm::BuildMI(), copyPhysReg(), DL, llvm::numbers::e, llvm::RegScavenger::enterBasicBlock(), llvm::BitVector::find_first(), llvm::RegScavenger::forward(), get, llvm::MachineOperand::getReg(), llvm::RegScavenger::getRegsAvailable(), i, llvm::RISCVMatInt::Imm, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::Register::isVirtualRegister(), llvm::RegState::Kill, MBB, llvm::BitVector::reset(), and T1.

◆ loadRegFromStack()

void Mips16InstrInfo::loadRegFromStack	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		Register	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		int64_t	Offset
	)		const

overridevirtual

Implements llvm::MipsInstrInfo.

Definition at line 124 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), get, llvm::MipsInstrInfo::GetMemOperand(), I, MBB, and llvm::MachineMemOperand::MOLoad.

◆ makeFrame()

void Mips16InstrInfo::makeFrame	(	unsigned	SP,
		int64_t	FrameSize,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I
	)		const

Definition at line 210 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), addSaveRestoreRegs(), llvm::sampleprof::Base, BuildAddiuSpImm(), llvm::BuildMI(), DL, get, llvm::MachineFrameInfo::getCalleeSavedInfo(), llvm::MachineFunction::getFrameInfo(), llvm::MachineBasicBlock::getParent(), llvm::MipsRegisterInfo::getReservedRegs(), I, llvm::isInt< 16 >(), and MBB.

◆ restoreFrame()

void Mips16InstrInfo::restoreFrame	(	unsigned	SP,
		int64_t	FrameSize,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I
	)		const

Definition at line 240 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), addSaveRestoreRegs(), llvm::sampleprof::Base, BuildAddiuSpImm(), llvm::BuildMI(), llvm::RegState::Define, DL, llvm::MachineBasicBlock::end(), get, llvm::MachineFrameInfo::getCalleeSavedInfo(), llvm::MachineFunction::getFrameInfo(), llvm::MachineBasicBlock::getParent(), llvm::MipsRegisterInfo::getReservedRegs(), I, llvm::isInt< 16 >(), and MBB.

◆ storeRegToStack()

void Mips16InstrInfo::storeRegToStack	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		Register	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		int64_t	Offset
	)		const

overridevirtual

Implements llvm::MipsInstrInfo.

Definition at line 106 of file Mips16InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), get, llvm::getKillRegState(), llvm::MipsInstrInfo::GetMemOperand(), I, MBB, and llvm::MachineMemOperand::MOStore.

◆ validImmediate()

bool Mips16InstrInfo::validImmediate	(	unsigned	Opcode,
		unsigned	Reg,
		int64_t	Amount
	)

static

Definition at line 472 of file Mips16InstrInfo.cpp.

References llvm::isInt< 16 >(), and llvm_unreachable.

◆ validSpImm8()

static bool llvm::Mips16InstrInfo::validSpImm8 ( int offset )

inlinestatic

Definition at line 94 of file Mips16InstrInfo.h.

Referenced by AddiuSpImm().

The documentation for this class was generated from the following files:

lib/Target/Mips/Mips16InstrInfo.h
lib/Target/Mips/Mips16InstrInfo.cpp

Public Member Functions

Static Public Member Functions

Protected Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ Mips16InstrInfo()

Member Function Documentation

◆ AddiuSpImm()

◆ adjustStackPtr()

◆ BuildAddiuSpImm()

◆ copyPhysReg()

◆ expandPostRAPseudo()

◆ getOppositeBranchOpc()

◆ getRegisterInfo()

◆ isCopyInstrImpl()

◆ isLoadFromStackSlot()

◆ isStoreToStackSlot()

◆ loadImmediate()

◆ loadRegFromStack()

◆ makeFrame()

◆ restoreFrame()

◆ storeRegToStack()

◆ validImmediate()

◆ validSpImm8()