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19 #include "llvm/IR/IntrinsicsRISCV.h"
22 #define DEBUG_TYPE "riscv-isel"
26 #define GET_GLOBALISEL_PREDICATE_BITSET
27 #include "RISCVGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
54 #define GET_GLOBALISEL_PREDICATES_DECL
55 #include "RISCVGenGlobalISel.inc"
56 #undef GET_GLOBALISEL_PREDICATES_DECL
58 #define GET_GLOBALISEL_TEMPORARIES_DECL
59 #include "RISCVGenGlobalISel.inc"
60 #undef GET_GLOBALISEL_TEMPORARIES_DECL
65 #define GET_GLOBALISEL_IMPL
66 #include "RISCVGenGlobalISel.inc"
67 #undef GET_GLOBALISEL_IMPL
69 RISCVInstructionSelector::RISCVInstructionSelector(
72 : STI(STI),
TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
75 #
include "RISCVGenGlobalISel.inc"
78 #
include "RISCVGenGlobalISel.inc"
101 return new RISCVInstructionSelector(
TM, Subtarget, RBI);
static StringRef getName(Value *V)
This is an optimization pass for GlobalISel generic memory operations.
This class provides the information for the target register banks.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
unsigned const TargetRegisterInfo * TRI
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C the select is being which prevents the dag combiner from turning select(load CPI1)
const HexagonInstrInfo * TII
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
const char LLVMTargetMachineRef TM
static uint64_t selectImpl(uint64_t CandidateMask, uint64_t &NextInSequenceMask)