LLVM  14.0.0git
RISCVInstructionSelector.cpp
Go to the documentation of this file.
1 //===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// RISCV.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVRegisterBankInfo.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
19 #include "llvm/IR/IntrinsicsRISCV.h"
20 #include "llvm/Support/Debug.h"
21 
22 #define DEBUG_TYPE "riscv-isel"
23 
24 using namespace llvm;
25 
26 #define GET_GLOBALISEL_PREDICATE_BITSET
27 #include "RISCVGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 
30 namespace {
31 
32 class RISCVInstructionSelector : public InstructionSelector {
33 public:
34  RISCVInstructionSelector(const RISCVTargetMachine &TM,
35  const RISCVSubtarget &STI,
36  const RISCVRegisterBankInfo &RBI);
37 
38  bool select(MachineInstr &I) override;
39  static const char *getName() { return DEBUG_TYPE; }
40 
41 private:
42  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
43 
44  const RISCVSubtarget &STI;
45  const RISCVInstrInfo &TII;
46  const RISCVRegisterInfo &TRI;
47  const RISCVRegisterBankInfo &RBI;
48 
49  // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
50  // uses "STI." in the code generated by TableGen. We need to unify the name of
51  // Subtarget variable.
52  const RISCVSubtarget *Subtarget = &STI;
53 
54 #define GET_GLOBALISEL_PREDICATES_DECL
55 #include "RISCVGenGlobalISel.inc"
56 #undef GET_GLOBALISEL_PREDICATES_DECL
57 
58 #define GET_GLOBALISEL_TEMPORARIES_DECL
59 #include "RISCVGenGlobalISel.inc"
60 #undef GET_GLOBALISEL_TEMPORARIES_DECL
61 };
62 
63 } // end anonymous namespace
64 
65 #define GET_GLOBALISEL_IMPL
66 #include "RISCVGenGlobalISel.inc"
67 #undef GET_GLOBALISEL_IMPL
68 
69 RISCVInstructionSelector::RISCVInstructionSelector(
70  const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
71  const RISCVRegisterBankInfo &RBI)
72  : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
73  TRI(*STI.getRegisterInfo()), RBI(RBI),
74 
76 #include "RISCVGenGlobalISel.inc"
79 #include "RISCVGenGlobalISel.inc"
81 {
82 }
83 
85 
86  if (!isPreISelGenericOpcode(I.getOpcode())) {
87  // Certain non-generic instructions also need some special handling.
88  return true;
89  }
90 
91  if (selectImpl(I, *CoverageInfo))
92  return true;
93 
94  return false;
95 }
96 
97 namespace llvm {
100  RISCVSubtarget &Subtarget,
101  RISCVRegisterBankInfo &RBI) {
102  return new RISCVInstructionSelector(TM, Subtarget, RBI);
103 }
104 } // end namespace llvm
DEBUG_TYPE
#define DEBUG_TYPE
Definition: RISCVInstructionSelector.cpp:22
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::RISCVRegisterBankInfo
This class provides the information for the target register banks.
Definition: RISCVRegisterBankInfo.h:32
include
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
Definition: CMakeLists.txt:1
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
select
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C the select is being which prevents the dag combiner from turning select(load CPI1)
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
InstructionSelector.h
llvm::createRISCVInstructionSelector
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
Definition: RISCVInstructionSelector.cpp:99
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:43
InstructionSelectorImpl.h
GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_PREDICATES_INIT
RISCVSubtarget.h
GET_GLOBALISEL_TEMPORARIES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::mca::selectImpl
static uint64_t selectImpl(uint64_t CandidateMask, uint64_t &NextInSequenceMask)
Definition: ResourceManager.cpp:26
Debug.h
RISCVRegisterBankInfo.h
RISCVTargetMachine.h