LLVM 17.0.0git
RISCVInstructionSelector.cpp
Go to the documentation of this file.
1//===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the InstructionSelector class for
10/// RISCV.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
15#include "RISCVSubtarget.h"
16#include "RISCVTargetMachine.h"
19#include "llvm/IR/IntrinsicsRISCV.h"
20#include "llvm/Support/Debug.h"
21
22#define DEBUG_TYPE "riscv-isel"
23
24using namespace llvm;
25
26#define GET_GLOBALISEL_PREDICATE_BITSET
27#include "RISCVGenGlobalISel.inc"
28#undef GET_GLOBALISEL_PREDICATE_BITSET
29
30namespace {
31
32class RISCVInstructionSelector : public InstructionSelector {
33public:
34 RISCVInstructionSelector(const RISCVTargetMachine &TM,
35 const RISCVSubtarget &STI,
36 const RISCVRegisterBankInfo &RBI);
37
38 bool select(MachineInstr &I) override;
39 static const char *getName() { return DEBUG_TYPE; }
40
41private:
42 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
43
44 const RISCVSubtarget &STI;
45 const RISCVInstrInfo &TII;
47 const RISCVRegisterBankInfo &RBI;
48
49 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
50 // uses "STI." in the code generated by TableGen. We need to unify the name of
51 // Subtarget variable.
52 const RISCVSubtarget *Subtarget = &STI;
53
54#define GET_GLOBALISEL_PREDICATES_DECL
55#include "RISCVGenGlobalISel.inc"
56#undef GET_GLOBALISEL_PREDICATES_DECL
57
58#define GET_GLOBALISEL_TEMPORARIES_DECL
59#include "RISCVGenGlobalISel.inc"
60#undef GET_GLOBALISEL_TEMPORARIES_DECL
61};
62
63} // end anonymous namespace
64
65#define GET_GLOBALISEL_IMPL
66#include "RISCVGenGlobalISel.inc"
67#undef GET_GLOBALISEL_IMPL
68
69RISCVInstructionSelector::RISCVInstructionSelector(
70 const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
71 const RISCVRegisterBankInfo &RBI)
72 : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
73
75#include "RISCVGenGlobalISel.inc"
78#include "RISCVGenGlobalISel.inc"
80{
81}
82
83bool RISCVInstructionSelector::select(MachineInstr &I) {
84
85 if (!isPreISelGenericOpcode(I.getOpcode())) {
86 // Certain non-generic instructions also need some special handling.
87 return true;
88 }
89
90 if (selectImpl(I, *CoverageInfo))
91 return true;
92
93 return false;
94}
95
96namespace llvm {
99 RISCVSubtarget &Subtarget,
101 return new RISCVInstructionSelector(TM, Subtarget, RBI);
102}
103} // end namespace llvm
#define DEBUG_TYPE
const HexagonInstrInfo * TII
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
static StringRef getName(Value *V)
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
This file declares the targeting of the RegisterBankInfo class for RISCV.
Provides the logic to select generic machine instructions.
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
Representation of each machine instruction.
Definition: MachineInstr.h:68
This class provides the information for the target register banks.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI)