19#include "llvm/IR/IntrinsicsRISCV.h"
22#define DEBUG_TYPE "riscv-isel"
26#define GET_GLOBALISEL_PREDICATE_BITSET
27#include "RISCVGenGlobalISel.inc"
28#undef GET_GLOBALISEL_PREDICATE_BITSET
54#define GET_GLOBALISEL_PREDICATES_DECL
55#include "RISCVGenGlobalISel.inc"
56#undef GET_GLOBALISEL_PREDICATES_DECL
58#define GET_GLOBALISEL_TEMPORARIES_DECL
59#include "RISCVGenGlobalISel.inc"
60#undef GET_GLOBALISEL_TEMPORARIES_DECL
65#define GET_GLOBALISEL_IMPL
66#include "RISCVGenGlobalISel.inc"
67#undef GET_GLOBALISEL_IMPL
69RISCVInstructionSelector::RISCVInstructionSelector(
72 : STI(STI),
TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
75#include
"RISCVGenGlobalISel.inc"
78#include
"RISCVGenGlobalISel.inc"
90 if (selectImpl(
I, *CoverageInfo))
101 return new RISCVInstructionSelector(
TM, Subtarget, RBI);
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
static StringRef getName(Value *V)
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
This file declares the targeting of the RegisterBankInfo class for RISCV.
Provides the logic to select generic machine instructions.
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
Representation of each machine instruction.
This class provides the information for the target register banks.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI)