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22 #define DEBUG_TYPE "machine-scheduler"
29 for (
auto &SU : *
this) {
51 PredMBB = (Pred ==
MBB ? nullptr : Pred);
55 &&
"Loop MBB should not consider predecessor outside of loop.");
60 void SystemZPostRASchedStrategy::
64 ((LastEmittedMI !=
nullptr && LastEmittedMI->getParent() == MBB) ?
65 std::next(LastEmittedMI) : MBB->
begin());
67 for (;
I != NextBegin; ++
I) {
68 if (
I->isPosition() ||
I->isDebugInstr())
80 assert ((SchedStates.find(NextMBB) == SchedStates.end()) &&
81 "Entering MBB twice?");
97 if (SinglePredMBB ==
nullptr ||
98 SchedStates.find(SinglePredMBB) == SchedStates.end())
104 HazardRec->
copyState(SchedStates[SinglePredMBB]);
111 bool TakenBranch = (
MI.isBranch() &&
132 (
C->MF->getSubtarget().getInstrInfo())),
133 MBB(nullptr), HazardRec(nullptr) {
140 for (
auto I : SchedStates) {
148 unsigned NumRegionInstrs) {
150 if (Begin->isTerminator())
162 if (Available.empty())
166 if (Available.size() == 1) {
169 return *Available.begin();
173 LLVM_DEBUG(
dbgs() <<
"** Available: "; Available.dump(*HazardRec););
176 for (
auto *SU : Available) {
179 Candidate
c(SU, *HazardRec);
182 if (Best.SU ==
nullptr ||
c < Best) {
188 dbgs() <<
" Height:" <<
c.SU->getHeight();
dbgs() <<
"\n";);
192 if (!SU->isScheduleHigh && Best.noCost())
196 assert (Best.SU !=
nullptr);
200 SystemZPostRASchedStrategy::Candidate::
217 if (GroupingCost < other.GroupingCost)
219 if (GroupingCost > other.GroupingCost)
223 if (ResourcesCost < other.ResourcesCost)
225 if (ResourcesCost > other.ResourcesCost)
229 if (SU->getHeight() > other.SU->getHeight())
231 if (SU->getHeight() < other.SU->getHeight())
235 if (SU->NodeNum < other.SU->NodeNum)
243 if (Available.size() == 1)
dbgs() <<
"(only one) ";
244 Candidate
c(SU, *HazardRec);
c.dumpCosts();
dbgs() <<
"\n";);
255 bool AffectsGrouping = (
SC->isValid() && (
SC->BeginGroup ||
SC->EndGroup));
259 Available.insert(SU);
void leaveMBB() override
Tell the strategy that current MBB is done.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
pred_iterator pred_begin()
This is an optimization pass for GlobalISel generic memory operations.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
reverse_iterator rbegin(StringRef path, Style style=Style::native)
Get reverse begin iterator over path.
void enterMBB(MachineBasicBlock *NextMBB) override
Tell the strategy that MBB is about to be processed.
Represents a single loop in the control flow graph.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
SystemZHazardRecognizer maintains the state for one MBB during scheduling.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned pred_size() const
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
bool isUnbuffered
Uses an unbuffered resource.
bool isScheduleHigh
True if preferable to schedule high.
SystemZPostRASchedStrategy(const MachineSchedContext *C)
(vector float) vec_cmpeq(*A, *B) C
unsigned NodeNum
Entry # of node in the node vector.
Summarize the scheduling resources required for an instruction of a particular scheduling class.
const HexagonInstrInfo * TII
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
MachineBasicBlock * getMBBTarget()
void releaseTopNode(SUnit *SU) override
SU has had all predecessor dependencies resolved.
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
void copyState(SystemZHazardRecognizer *Incoming)
Copy counters from end of single predecessor.
void emitInstruction(MachineInstr *MI, bool TakenBranch=false)
Wrap a non-scheduled instruction in an SU and emit it.
Representation of each machine instruction.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule, or return NULL.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
iterator_range< pred_iterator > predecessors()
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
MachineBasicBlock::iterator getLastEmittedMI()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
int groupingCost(SUnit *SU) const
Return the cost of decoder grouping for SU.
int resourcesCost(SUnit *SU)
Return the cost of SU in regards to processor resources usage.
if(llvm_vc STREQUAL "") set(fake_version_inc "$
virtual ~SystemZPostRASchedStrategy()
TargetSubtargetInfo - Generic base class for all target subtargets.
static MachineBasicBlock * getSingleSchedPred(MachineBasicBlock *MBB, const MachineLoop *Loop)
bool operator<(const DeltaInfo &LHS, int64_t Delta)
BlockT * getHeader() const
void dumpSU(SUnit *SU, raw_ostream &OS) const
void schedNode(SUnit *SU, bool IsTopNode) override
ScheduleDAGMI has scheduled an instruction - tell HazardRec about it.
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) override
Called for a region before scheduling.
Scheduling unit. This is a node in the scheduling DAG.