47 #define GET_INSTRINFO_CTOR_DTOR
48 #define GET_INSTRMAP_INFO
49 #include "SystemZGenInstrInfo.inc"
51 #define DEBUG_TYPE "systemz-II"
55 return Count == 0 ? 0 : (
uint64_t(1) << (Count - 1) << 1) - 1;
59 void SystemZInstrInfo::anchor() {}
63 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
69 unsigned NewOpcode)
const {
84 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
85 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
112 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
115 MI->setDesc(
get(LowOpcode));
131 assert(NewOpcode &&
"No support for huge argument lists yet");
132 MI->setDesc(
get(NewOpcode));
142 void SystemZInstrInfo::expandRIPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
144 bool ConvertHigh)
const {
147 MI.setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
148 if (IsHigh && ConvertHigh)
149 MI.getOperand(1).setImm(
uint32_t(
MI.getOperand(1).getImm()));
156 void SystemZInstrInfo::expandRIEPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
158 unsigned HighOpcode)
const {
163 if (!DestIsHigh && !SrcIsHigh)
164 MI.setDesc(
get(LowOpcodeK));
166 if (DestReg != SrcReg) {
167 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(), DestReg, SrcReg,
168 SystemZ::LR, 32,
MI.getOperand(1).isKill(),
169 MI.getOperand(1).isUndef());
170 MI.getOperand(1).setReg(DestReg);
172 MI.setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
173 MI.tieOperands(0, 1);
180 void SystemZInstrInfo::expandRXYPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
181 unsigned HighOpcode)
const {
185 MI.getOperand(2).getImm());
186 MI.setDesc(
get(Opcode));
192 void SystemZInstrInfo::expandLOCPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
193 unsigned HighOpcode)
const {
196 MI.setDesc(
get(Opcode));
202 void SystemZInstrInfo::expandZExtPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
203 unsigned Size)
const {
205 emitGRX32Move(*
MI.getParent(),
MI,
MI.getDebugLoc(),
206 MI.getOperand(0).getReg(),
MI.getOperand(1).getReg(), LowOpcode,
207 Size,
MI.getOperand(1).isKill(),
MI.getOperand(1).isUndef());
213 MI.eraseFromParent();
216 void SystemZInstrInfo::expandLoadStackGuard(
MachineInstr *
MI)
const {
219 const Register Reg64 =
MI->getOperand(0).getReg();
220 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
241 MI->setDesc(
get(SystemZ::LG));
254 unsigned SrcReg,
unsigned LowLowOpcode,
255 unsigned Size,
bool KillSrc,
256 bool UndefSrc)
const {
260 if (DestIsHigh && SrcIsHigh)
261 Opcode = SystemZ::RISBHH;
262 else if (DestIsHigh && !SrcIsHigh)
263 Opcode = SystemZ::RISBHL;
264 else if (!DestIsHigh && SrcIsHigh)
265 Opcode = SystemZ::RISBLH;
270 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
280 unsigned OpIdx2)
const {
283 return *
MI.getParent()->getParent()->CloneMachineInstr(&
MI);
287 switch (
MI.getOpcode()) {
288 case SystemZ::SELRMux:
289 case SystemZ::SELFHR:
292 case SystemZ::LOCRMux:
293 case SystemZ::LOCFHR:
295 case SystemZ::LOCGR: {
296 auto &WorkingMI = cloneIfNew(
MI);
298 unsigned CCValid = WorkingMI.getOperand(3).getImm();
299 unsigned CCMask = WorkingMI.getOperand(4).getImm();
300 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
318 MI.getOperand(2).getImm() == 0 &&
MI.getOperand(3).getReg() == 0) {
320 return MI.getOperand(0).getReg();
337 int &SrcFrameIndex)
const {
341 MI.getOperand(1).getImm() != 0 || !
MI.getOperand(3).isFI() ||
342 MI.getOperand(4).getImm() != 0)
346 int64_t Length =
MI.getOperand(2).getImm();
347 unsigned FI1 =
MI.getOperand(0).getIndex();
348 unsigned FI2 =
MI.getOperand(3).getIndex();
353 DestFrameIndex = FI1;
362 bool AllowModify)
const {
370 if (
I->isDebugInstr())
375 if (!isUnpredicatedTerminator(*
I))
385 if (!
Branch.hasMBBTarget())
395 TBB =
Branch.getMBBTarget();
400 while (std::next(
I) !=
MBB.
end())
401 std::next(
I)->eraseFromParent();
409 I->eraseFromParent();
415 TBB =
Branch.getMBBTarget();
423 TBB =
Branch.getMBBTarget();
430 assert(
Cond.size() == 2 && TBB &&
"Should have seen a conditional branch");
434 if (TBB !=
Branch.getMBBTarget())
438 unsigned OldCCValid =
Cond[0].getImm();
439 unsigned OldCCMask =
Cond[1].getImm();
440 if (OldCCValid ==
Branch.CCValid && OldCCMask ==
Branch.CCMask)
451 int *BytesRemoved)
const {
452 assert(!BytesRemoved &&
"code size not handled");
460 if (
I->isDebugInstr())
467 I->eraseFromParent();
477 assert(
Cond.size() == 2 &&
"Invalid condition");
487 int *BytesAdded)
const {
493 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
495 "SystemZ branch conditions have one component!");
496 assert(!BytesAdded &&
"code size not handled");
500 assert(!FBB &&
"Unconditional branch with multiple successors!");
507 unsigned CCValid =
Cond[0].getImm();
508 unsigned CCMask =
Cond[1].getImm();
523 int64_t &
Value)
const {
524 assert(
MI.isCompare() &&
"Caller should have checked for a comparison");
526 if (
MI.getNumExplicitOperands() == 2 &&
MI.getOperand(0).isReg() &&
527 MI.getOperand(1).isImm()) {
528 SrcReg =
MI.getOperand(0).getReg();
530 Value =
MI.getOperand(1).getImm();
543 int &FalseCycles)
const {
547 if (Pred.
size() != 2)
559 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
560 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
561 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
581 assert(Pred.
size() == 2 &&
"Invalid condition");
582 unsigned CCValid = Pred[0].getImm();
583 unsigned CCMask = Pred[1].getImm();
586 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
588 Opc = SystemZ::SELRMux;
590 Opc = SystemZ::LOCRMux;
601 }
else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
603 Opc = SystemZ::SELGR;
605 Opc = SystemZ::LOCGR;
617 unsigned DefOpc =
DefMI.getOpcode();
618 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
619 DefOpc != SystemZ::LGHI)
623 int32_t ImmVal = (int32_t)
DefMI.getOperand(1).getImm();
625 unsigned UseOpc =
UseMI.getOpcode();
631 case SystemZ::SELRMux:
634 case SystemZ::LOCRMux:
637 NewUseOpc = SystemZ::LOCHIMux;
641 UseIdx = 2, CommuteIdx = 1;
651 NewUseOpc = SystemZ::LOCGHI;
655 UseIdx = 2, CommuteIdx = 1;
663 if (CommuteIdx != -1)
664 if (!commuteInstruction(
UseMI,
false, CommuteIdx, UseIdx))
670 UseMI.tieOperands(0, 1);
671 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
673 DefMI.eraseFromParent();
679 unsigned Opcode =
MI.getOpcode();
680 if (Opcode == SystemZ::Return ||
681 Opcode == SystemZ::Return_XPLINK ||
682 Opcode == SystemZ::Trap ||
683 Opcode == SystemZ::CallJG ||
684 Opcode == SystemZ::CallBR)
691 unsigned NumCycles,
unsigned ExtraPredCycles,
705 return NumCycles == 1;
710 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
712 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
722 return NumCycles == 1;
727 assert(Pred.
size() == 2 &&
"Invalid condition");
728 unsigned CCValid = Pred[0].getImm();
729 unsigned CCMask = Pred[1].getImm();
730 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
731 unsigned Opcode =
MI.getOpcode();
732 if (Opcode == SystemZ::Trap) {
733 MI.setDesc(
get(SystemZ::CondTrap));
739 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
740 MI.setDesc(
get(Opcode == SystemZ::Return ? SystemZ::CondReturn
741 : SystemZ::CondReturn_XPLINK));
748 if (Opcode == SystemZ::CallJG) {
750 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
753 MI.setDesc(
get(SystemZ::CallBRCL));
762 if (Opcode == SystemZ::CallBR) {
764 const uint32_t *RegMask =
MI.getOperand(1).getRegMask();
767 MI.setDesc(
get(SystemZ::CallBCR));
785 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
787 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
791 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
797 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
798 emitGRX32Move(
MBB,
MBBI,
DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
804 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
805 SystemZ::FP128BitRegClass.
contains(SrcReg)) {
807 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
808 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
810 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
811 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
818 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
819 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
821 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
822 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
824 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
825 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
827 if (DestRegHi != SrcReg)
835 if (DestReg == SystemZ::CC) {
837 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
846 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
847 Opcode = SystemZ::LGR;
848 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
850 Opcode = STI.
hasVector() ? SystemZ::LDR32 : SystemZ::LER;
851 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
853 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
854 Opcode = SystemZ::LXR;
855 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
856 Opcode = SystemZ::VLR32;
857 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
858 Opcode = SystemZ::VLR64;
859 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
860 Opcode = SystemZ::VLR;
861 else if (SystemZ::AR32BitRegClass.
contains(DestReg, SrcReg))
862 Opcode = SystemZ::CPYA;
878 unsigned LoadOpcode, StoreOpcode;
893 unsigned LoadOpcode, StoreOpcode;
904 isUInt<12>(
MI->getOperand(2).getImm()) &&
905 MI->getOperand(3).getReg() == 0);
912 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
913 :
RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
915 explicit operator bool()
const {
return RegSize; }
919 unsigned ImmSize = 0;
926 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
927 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
928 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
929 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
930 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
931 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
932 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
933 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
934 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
935 default:
return LogicOp();
942 if (CCDef !=
nullptr)
967 if (
And.RegSize == 64) {
968 NewOpcode = SystemZ::RISBG;
971 NewOpcode = SystemZ::RISBGN;
973 NewOpcode = SystemZ::RISBMux;
989 unsigned NumOps =
MI.getNumOperands();
990 for (
unsigned I = 1;
I < NumOps; ++
I) {
992 if (
Op.isReg() &&
Op.isKill())
1013 unsigned Opcode =
MI.getOpcode();
1019 bool CCLiveAtMI =
true;
1023 CCLiveAtMI = CCLiveRange->
liveAt(MISlot);
1028 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1029 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1030 isInt<8>(
MI.getOperand(2).getImm()) && !
MI.getOperand(3).getReg()) {
1033 MI.getDebugLoc(),
get(SystemZ::AGSI))
1036 .
addImm(
MI.getOperand(2).getImm());
1045 if (Ops.
size() != 1)
1048 unsigned OpNum = Ops[0];
1052 "Invalid size combination");
1054 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1057 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1059 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1062 .
addImm(
MI.getOperand(2).getImm());
1068 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1069 isInt<8>((int32_t)
MI.getOperand(2).getImm())) ||
1070 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1071 isInt<8>((int64_t)
MI.getOperand(2).getImm()))) {
1073 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1075 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1078 .
addImm((int8_t)
MI.getOperand(2).getImm());
1083 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1084 isInt<8>((int32_t)-
MI.getOperand(2).getImm())) ||
1085 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1086 isInt<8>((int64_t)-
MI.getOperand(2).getImm()))) {
1088 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1090 BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
get(Opcode))
1093 .
addImm((int8_t)-
MI.getOperand(2).getImm());
1098 unsigned MemImmOpc = 0;
1100 case SystemZ::LHIMux:
1101 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI;
break;
1102 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI;
break;
1103 case SystemZ::CHIMux:
1104 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI;
break;
1105 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI;
break;
1106 case SystemZ::CLFIMux:
1109 MemImmOpc = SystemZ::CLFHSI;
1111 case SystemZ::CLGFI:
1113 MemImmOpc = SystemZ::CLGHSI;
1118 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1122 .
addImm(
MI.getOperand(1).getImm());
1124 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1125 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1126 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1130 unsigned StoreOpcode = Op1IsGPR ?
SystemZ::STG : SystemZ::STD;
1131 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1133 .
add(
MI.getOperand(1))
1141 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG :
SystemZ::LD;
1142 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1144 .
add(
MI.getOperand(0))
1164 if (OpNum == 0 &&
MI.hasOneMemOperand()) {
1169 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1174 .
add(
MI.getOperand(1))
1180 return BuildMI(*InsertPt->getParent(), InsertPt,
MI.getDebugLoc(),
1182 .
add(
MI.getOperand(1))
1195 unsigned NumOps =
MI.getNumExplicitOperands();
1196 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1197 if (MemOpcode == -1 ||
1198 (CCLiveAtMI && !
MI.definesRegister(SystemZ::CC) &&
1199 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1210 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1216 !(SystemZ::FP32BitRegClass.
contains(PhysReg) ||
1217 SystemZ::FP64BitRegClass.
contains(PhysReg) ||
1218 SystemZ::VF128BitRegClass.
contains(PhysReg)))
1223 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1224 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1228 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1233 bool NeedsCommute =
false;
1234 if ((
MI.getOpcode() == SystemZ::CR ||
MI.getOpcode() == SystemZ::CGR ||
1235 MI.getOpcode() == SystemZ::CLR ||
MI.getOpcode() == SystemZ::CLGR ||
1236 MI.getOpcode() == SystemZ::WFCDB ||
MI.getOpcode() == SystemZ::WFCSB ||
1237 MI.getOpcode() == SystemZ::WFKDB ||
MI.getOpcode() == SystemZ::WFKSB) &&
1239 NeedsCommute =
true;
1241 bool CCOperands =
false;
1242 if (
MI.getOpcode() == SystemZ::LOCRMux ||
MI.getOpcode() == SystemZ::LOCGR ||
1243 MI.getOpcode() == SystemZ::SELRMux ||
MI.getOpcode() == SystemZ::SELGR) {
1244 assert(
MI.getNumOperands() == 6 && NumOps == 5 &&
1245 "LOCR/SELR instruction operands corrupt?");
1261 Register SrcReg = (OpNum == 2 ?
MI.getOperand(1).getReg()
1262 : ((OpNum == 1 &&
MI.isCommutable())
1263 ?
MI.getOperand(2).getReg()
1265 if (DstPhys && !SystemZ::GRH32BitRegClass.
contains(DstPhys) && SrcReg &&
1267 DstPhys == VRM->
getPhys(SrcReg))
1268 NeedsCommute = (OpNum == 1);
1274 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1277 assert(AccessBytes != 0 &&
"Size of access should be known");
1278 assert(AccessBytes <= Size &&
"Access outside the frame index");
1279 uint64_t Offset = Size - AccessBytes;
1281 MI.getDebugLoc(),
get(MemOpcode));
1282 if (
MI.isCompare()) {
1283 assert(NumOps == 2 &&
"Expected 2 register operands for a compare.");
1284 MIB.
add(
MI.getOperand(NeedsCommute ? 1 : 0));
1286 else if (FusedFPOp) {
1287 MIB.
add(
MI.getOperand(0));
1288 MIB.
add(
MI.getOperand(3));
1289 MIB.
add(
MI.getOperand(OpNum == 1 ? 2 : 1));
1292 MIB.
add(
MI.getOperand(0));
1294 MIB.
add(
MI.getOperand(2));
1296 for (
unsigned I = 1;
I < OpNum; ++
I)
1297 MIB.
add(
MI.getOperand(
I));
1303 unsigned CCValid =
MI.getOperand(NumOps).getImm();
1304 unsigned CCMask =
MI.getOperand(NumOps + 1).getImm();
1306 MIB.
addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1309 (!
MI.definesRegister(SystemZ::CC) ||
1310 MI.registerDefIsDead(SystemZ::CC))) {
1345 switch (
MI.getOpcode()) {
1347 splitMove(
MI, SystemZ::LG);
1350 case SystemZ::ST128:
1359 splitMove(
MI, SystemZ::STD);
1362 case SystemZ::LBMux:
1363 expandRXYPseudo(
MI, SystemZ::LB, SystemZ::LBH);
1366 case SystemZ::LHMux:
1367 expandRXYPseudo(
MI, SystemZ::LH, SystemZ::LHH);
1370 case SystemZ::LLCRMux:
1371 expandZExtPseudo(
MI, SystemZ::LLCR, 8);
1374 case SystemZ::LLHRMux:
1375 expandZExtPseudo(
MI, SystemZ::LLHR, 16);
1378 case SystemZ::LLCMux:
1379 expandRXYPseudo(
MI, SystemZ::LLC, SystemZ::LLCH);
1382 case SystemZ::LLHMux:
1383 expandRXYPseudo(
MI, SystemZ::LLH, SystemZ::LLHH);
1387 expandRXYPseudo(
MI, SystemZ::L, SystemZ::LFH);
1390 case SystemZ::LOCMux:
1391 expandLOCPseudo(
MI, SystemZ::LOC, SystemZ::LOCFH);
1394 case SystemZ::LOCHIMux:
1395 expandLOCPseudo(
MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1398 case SystemZ::STCMux:
1399 expandRXYPseudo(
MI, SystemZ::STC, SystemZ::STCH);
1402 case SystemZ::STHMux:
1403 expandRXYPseudo(
MI, SystemZ::STH, SystemZ::STHH);
1406 case SystemZ::STMux:
1410 case SystemZ::STOCMux:
1411 expandLOCPseudo(
MI, SystemZ::STOC, SystemZ::STOCFH);
1414 case SystemZ::LHIMux:
1415 expandRIPseudo(
MI, SystemZ::LHI, SystemZ::IIHF,
true);
1418 case SystemZ::IIFMux:
1419 expandRIPseudo(
MI, SystemZ::IILF, SystemZ::IIHF,
false);
1422 case SystemZ::IILMux:
1423 expandRIPseudo(
MI, SystemZ::IILL, SystemZ::IIHL,
false);
1426 case SystemZ::IIHMux:
1427 expandRIPseudo(
MI, SystemZ::IILH, SystemZ::IIHH,
false);
1430 case SystemZ::NIFMux:
1431 expandRIPseudo(
MI, SystemZ::NILF, SystemZ::NIHF,
false);
1434 case SystemZ::NILMux:
1435 expandRIPseudo(
MI, SystemZ::NILL, SystemZ::NIHL,
false);
1438 case SystemZ::NIHMux:
1439 expandRIPseudo(
MI, SystemZ::NILH, SystemZ::NIHH,
false);
1442 case SystemZ::OIFMux:
1443 expandRIPseudo(
MI, SystemZ::OILF, SystemZ::OIHF,
false);
1446 case SystemZ::OILMux:
1447 expandRIPseudo(
MI, SystemZ::OILL, SystemZ::OIHL,
false);
1450 case SystemZ::OIHMux:
1451 expandRIPseudo(
MI, SystemZ::OILH, SystemZ::OIHH,
false);
1454 case SystemZ::XIFMux:
1455 expandRIPseudo(
MI, SystemZ::XILF, SystemZ::XIHF,
false);
1458 case SystemZ::TMLMux:
1459 expandRIPseudo(
MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1462 case SystemZ::TMHMux:
1463 expandRIPseudo(
MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1466 case SystemZ::AHIMux:
1467 expandRIPseudo(
MI, SystemZ::AHI, SystemZ::AIH,
false);
1470 case SystemZ::AHIMuxK:
1471 expandRIEPseudo(
MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1474 case SystemZ::AFIMux:
1475 expandRIPseudo(
MI, SystemZ::AFI, SystemZ::AIH,
false);
1478 case SystemZ::CHIMux:
1479 expandRIPseudo(
MI, SystemZ::CHI, SystemZ::CIH,
false);
1482 case SystemZ::CFIMux:
1483 expandRIPseudo(
MI, SystemZ::CFI, SystemZ::CIH,
false);
1486 case SystemZ::CLFIMux:
1487 expandRIPseudo(
MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1494 case SystemZ::CLMux:
1495 expandRXYPseudo(
MI, SystemZ::CL, SystemZ::CLHF);
1498 case SystemZ::RISBMux: {
1501 if (SrcIsHigh == DestIsHigh)
1502 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1504 MI.setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1505 MI.getOperand(5).setImm(
MI.getOperand(5).getImm() ^ 32);
1511 splitAdjDynAlloc(
MI);
1514 case TargetOpcode::LOAD_STACK_GUARD:
1515 expandLoadStackGuard(&
MI);
1524 if (
MI.isInlineAsm()) {
1526 const char *AsmStr =
MI.getOperand(0).getSymbolName();
1529 else if (
MI.getOpcode() == SystemZ::PATCHPOINT)
1531 else if (
MI.getOpcode() == SystemZ::STACKMAP)
1532 return MI.getOperand(1).getImm();
1533 else if (
MI.getOpcode() == SystemZ::FENTRY_CALL)
1536 return MI.getDesc().getSize();
1541 switch (
MI.getOpcode()) {
1552 MI.getOperand(1).getImm(), &
MI.getOperand(2));
1555 case SystemZ::BRCTH:
1559 case SystemZ::BRCTG:
1566 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1571 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1576 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1578 case SystemZ::CLGIJ:
1579 case SystemZ::CLGRJ:
1581 MI.getOperand(2).getImm(), &
MI.getOperand(3));
1593 unsigned &LoadOpcode,
1594 unsigned &StoreOpcode)
const {
1595 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1596 LoadOpcode = SystemZ::L;
1598 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1599 LoadOpcode = SystemZ::LFH;
1600 StoreOpcode = SystemZ::STFH;
1601 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1602 LoadOpcode = SystemZ::LMux;
1603 StoreOpcode = SystemZ::STMux;
1604 }
else if (RC == &SystemZ::GR64BitRegClass ||
1605 RC == &SystemZ::ADDR64BitRegClass) {
1606 LoadOpcode = SystemZ::LG;
1608 }
else if (RC == &SystemZ::GR128BitRegClass ||
1609 RC == &SystemZ::ADDR128BitRegClass) {
1610 LoadOpcode = SystemZ::L128;
1611 StoreOpcode = SystemZ::ST128;
1612 }
else if (RC == &SystemZ::FP32BitRegClass) {
1614 StoreOpcode = SystemZ::STE;
1615 }
else if (RC == &SystemZ::FP64BitRegClass) {
1617 StoreOpcode = SystemZ::STD;
1618 }
else if (RC == &SystemZ::FP128BitRegClass) {
1619 LoadOpcode = SystemZ::LX;
1620 StoreOpcode = SystemZ::STX;
1621 }
else if (RC == &SystemZ::VR32BitRegClass) {
1622 LoadOpcode = SystemZ::VL32;
1623 StoreOpcode = SystemZ::VST32;
1624 }
else if (RC == &SystemZ::VR64BitRegClass) {
1625 LoadOpcode = SystemZ::VL64;
1626 StoreOpcode = SystemZ::VST64;
1627 }
else if (RC == &SystemZ::VF128BitRegClass ||
1628 RC == &SystemZ::VR128BitRegClass) {
1629 LoadOpcode = SystemZ::VL;
1630 StoreOpcode = SystemZ::VST;
1636 int64_t Offset)
const {
1639 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1641 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1642 if (Disp12Opcode >= 0)
1643 return Disp12Opcode;
1649 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1651 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1652 if (Disp20Opcode >= 0)
1653 return Disp20Opcode;
1665 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1666 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1673 case SystemZ::LG:
return SystemZ::LTG;
1674 case SystemZ::LGF:
return SystemZ::LTGF;
1675 case SystemZ::LR:
return SystemZ::LTR;
1676 case SystemZ::LGFR:
return SystemZ::LTGFR;
1677 case SystemZ::LGR:
return SystemZ::LTGR;
1678 case SystemZ::LER:
return SystemZ::LTEBR;
1680 case SystemZ::LXR:
return SystemZ::LTXBR;
1681 case SystemZ::LCDFR:
return SystemZ::LCDBR;
1682 case SystemZ::LPDFR:
return SystemZ::LPDBR;
1683 case SystemZ::LNDFR:
return SystemZ::LNDBR;
1684 case SystemZ::LCDFR_32:
return SystemZ::LCEBR;
1685 case SystemZ::LPDFR_32:
return SystemZ::LPEBR;
1686 case SystemZ::LNDFR_32:
return SystemZ::LNEBR;
1691 case SystemZ::RISBGN:
return SystemZ::RISBG;
1702 if ((Top & -Top) == Top) {
1711 unsigned &Start,
unsigned &End)
const {
1719 unsigned LSB, Length;
1721 Start = 63 - (LSB + Length - 1);
1729 assert(LSB > 0 &&
"Bottom bit must be set");
1730 assert(LSB + Length < BitSize &&
"Top bit must be set");
1731 Start = 63 - (LSB - 1);
1732 End = 63 - (LSB + Length);
1749 case SystemZ::CLGFI:
1757 if (!(
MI &&
MI->getOperand(3).getReg() == 0))
1765 return SystemZ::CRJ;
1767 return SystemZ::CGRJ;
1769 return SystemZ::CIJ;
1771 return SystemZ::CGIJ;
1773 return SystemZ::CLRJ;
1775 return SystemZ::CLGRJ;
1777 return SystemZ::CLIJ;
1778 case SystemZ::CLGFI:
1779 return SystemZ::CLGIJ;
1786 return SystemZ::CRBReturn;
1788 return SystemZ::CGRBReturn;
1790 return SystemZ::CIBReturn;
1792 return SystemZ::CGIBReturn;
1794 return SystemZ::CLRBReturn;
1796 return SystemZ::CLGRBReturn;
1798 return SystemZ::CLIBReturn;
1799 case SystemZ::CLGFI:
1800 return SystemZ::CLGIBReturn;
1807 return SystemZ::CRBCall;
1809 return SystemZ::CGRBCall;
1811 return SystemZ::CIBCall;
1813 return SystemZ::CGIBCall;
1815 return SystemZ::CLRBCall;
1817 return SystemZ::CLGRBCall;
1819 return SystemZ::CLIBCall;
1820 case SystemZ::CLGFI:
1821 return SystemZ::CLGIBCall;
1828 return SystemZ::CRT;
1830 return SystemZ::CGRT;
1832 return SystemZ::CIT;
1834 return SystemZ::CGIT;
1836 return SystemZ::CLRT;
1838 return SystemZ::CLGRT;
1840 return SystemZ::CLFIT;
1841 case SystemZ::CLGFI:
1842 return SystemZ::CLGIT;
1844 return SystemZ::CLT;
1846 return SystemZ::CLGT;
1857 MBBI->getOperand(1).isReg() && !
MBBI->mayLoad() &&
1858 "Not a compare reg/reg.");
1864 Itr !=
MBB->
end(); ++Itr) {
1865 if (Itr->readsRegister(SystemZ::CC)) {
1866 unsigned Flags = Itr->getDesc().TSFlags;
1868 CCUsers.push_back(&*Itr);
1872 if (Itr->definesRegister(SystemZ::CC)) {
1880 if (LiveRegs.
contains(SystemZ::CC))
1885 for (
unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
1886 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1888 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
1889 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
1891 CCMaskMO.
setImm(NewCCMask);
1934 return SystemZ::LAT;
1936 return SystemZ::LGAT;
1938 return SystemZ::LFHAT;
1940 return SystemZ::LLGFAT;
1942 return SystemZ::LLGTAT;
1951 unsigned Opcode = 0;
1953 Opcode = SystemZ::LGHI;
1955 Opcode = SystemZ::LLILL;
1957 Opcode = SystemZ::LLILH;
1961 Opcode = SystemZ::LGFI;
1968 assert (
MRI.
isSSA() &&
"Huge values only handled before reg-alloc .");
1981 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
1992 ErrInfo =
"Addressing mode operands corrupt!";
2015 bool SameVal = (VALa && VALb && (VALa == VALb));
2019 if (PSVa && PSVb && (PSVa == PSVb))
2025 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2026 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2027 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2028 if (LowOffset + LowWidth <= HighOffset)