LLVM  15.0.0git
SystemZInstrInfo.cpp
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1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SystemZInstrInfo.h"
15 #include "SystemZ.h"
16 #include "SystemZInstrBuilder.h"
17 #include "SystemZSubtarget.h"
18 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
35 #include "llvm/MC/MCInstrDesc.h"
36 #include "llvm/MC/MCRegisterInfo.h"
41 #include <cassert>
42 #include <cstdint>
43 #include <iterator>
44 
45 using namespace llvm;
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #define GET_INSTRMAP_INFO
49 #include "SystemZGenInstrInfo.inc"
50 
51 #define DEBUG_TYPE "systemz-II"
52 
53 // Return a mask with Count low bits set.
54 static uint64_t allOnes(unsigned int Count) {
55  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
56 }
57 
58 // Pin the vtable to this file.
59 void SystemZInstrInfo::anchor() {}
60 
62  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
63  RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
64  STI(sti) {}
65 
66 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
67 // each having the opcode given by NewOpcode.
68 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
69  unsigned NewOpcode) const {
70  MachineBasicBlock *MBB = MI->getParent();
71  MachineFunction &MF = *MBB->getParent();
72 
73  // Get two load or store instructions. Use the original instruction for one
74  // of them (arbitrarily the second here) and create a clone for the other.
75  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
76  MBB->insert(MI, EarlierMI);
77 
78  // Set up the two 64-bit registers and remember super reg and its flags.
79  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
80  MachineOperand &LowRegOp = MI->getOperand(0);
81  Register Reg128 = LowRegOp.getReg();
82  unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
83  unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
84  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
85  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
86 
87  if (MI->mayStore()) {
88  // Add implicit uses of the super register in case one of the subregs is
89  // undefined. We could track liveness and skip storing an undefined
90  // subreg, but this is hopefully rare (discovered with llvm-stress).
91  // If Reg128 was killed, set kill flag on MI.
92  unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
93  MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
94  MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
95  }
96 
97  // The address in the first (high) instruction is already correct.
98  // Adjust the offset in the second (low) instruction.
99  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
100  MachineOperand &LowOffsetOp = MI->getOperand(2);
101  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
102 
103  // Clear the kill flags on the registers in the first instruction.
104  if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
105  EarlierMI->getOperand(0).setIsKill(false);
106  EarlierMI->getOperand(1).setIsKill(false);
107  EarlierMI->getOperand(3).setIsKill(false);
108 
109  // Set the opcodes.
110  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
111  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
112  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
113 
114  EarlierMI->setDesc(get(HighOpcode));
115  MI->setDesc(get(LowOpcode));
116 }
117 
118 // Split ADJDYNALLOC instruction MI.
119 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
120  MachineBasicBlock *MBB = MI->getParent();
121  MachineFunction &MF = *MBB->getParent();
122  MachineFrameInfo &MFFrame = MF.getFrameInfo();
123  MachineOperand &OffsetMO = MI->getOperand(2);
125 
126  uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
127  Regs->getCallFrameSize() +
128  Regs->getStackPointerBias() +
129  OffsetMO.getImm());
130  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
131  assert(NewOpcode && "No support for huge argument lists yet");
132  MI->setDesc(get(NewOpcode));
133  OffsetMO.setImm(Offset);
134 }
135 
136 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
137 // if the first operand is a low GR32 and HighOpcode if the first operand
138 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
139 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
140 // MI has the same kind of operand as LowOpcode, so needs to be converted
141 // if HighOpcode is used.
142 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
143  unsigned HighOpcode,
144  bool ConvertHigh) const {
145  Register Reg = MI.getOperand(0).getReg();
146  bool IsHigh = SystemZ::isHighReg(Reg);
147  MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
148  if (IsHigh && ConvertHigh)
149  MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
150 }
151 
152 // MI is a three-operand RIE-style pseudo instruction. Replace it with
153 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
154 // followed by HighOpcode or LowOpcode, depending on whether the target
155 // is a high or low GR32.
156 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
157  unsigned LowOpcodeK,
158  unsigned HighOpcode) const {
159  Register DestReg = MI.getOperand(0).getReg();
160  Register SrcReg = MI.getOperand(1).getReg();
161  bool DestIsHigh = SystemZ::isHighReg(DestReg);
162  bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
163  if (!DestIsHigh && !SrcIsHigh)
164  MI.setDesc(get(LowOpcodeK));
165  else {
166  if (DestReg != SrcReg) {
167  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
168  SystemZ::LR, 32, MI.getOperand(1).isKill(),
169  MI.getOperand(1).isUndef());
170  MI.getOperand(1).setReg(DestReg);
171  }
172  MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
173  MI.tieOperands(0, 1);
174  }
175 }
176 
177 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
178 // if the first operand is a low GR32 and HighOpcode if the first operand
179 // is a high GR32.
180 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
181  unsigned HighOpcode) const {
182  Register Reg = MI.getOperand(0).getReg();
183  unsigned Opcode = getOpcodeForOffset(
184  SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
185  MI.getOperand(2).getImm());
186  MI.setDesc(get(Opcode));
187 }
188 
189 // MI is a load-on-condition pseudo instruction with a single register
190 // (source or destination) operand. Replace it with LowOpcode if the
191 // register is a low GR32 and HighOpcode if the register is a high GR32.
192 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
193  unsigned HighOpcode) const {
194  Register Reg = MI.getOperand(0).getReg();
195  unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
196  MI.setDesc(get(Opcode));
197 }
198 
199 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
200 // of one GRX32 into another. Replace it with LowOpcode if both operands
201 // are low registers, otherwise use RISB[LH]G.
202 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
203  unsigned Size) const {
204  MachineInstrBuilder MIB =
205  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
206  MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
207  Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
208 
209  // Keep the remaining operands as-is.
210  for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
211  MIB.add(MO);
212 
213  MI.eraseFromParent();
214 }
215 
216 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
217  MachineBasicBlock *MBB = MI->getParent();
218  MachineFunction &MF = *MBB->getParent();
219  const Register Reg64 = MI->getOperand(0).getReg();
220  const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
221 
222  // EAR can only load the low subregister so us a shift for %a0 to produce
223  // the GR containing %a0 and %a1.
224 
225  // ear <reg>, %a0
226  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
227  .addReg(SystemZ::A0)
229 
230  // sllg <reg>, <reg>, 32
231  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
232  .addReg(Reg64)
233  .addReg(0)
234  .addImm(32);
235 
236  // ear <reg>, %a1
237  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
238  .addReg(SystemZ::A1);
239 
240  // lg <reg>, 40(<reg>)
241  MI->setDesc(get(SystemZ::LG));
242  MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
243 }
244 
245 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
246 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
247 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
248 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
249 // KillSrc is true if this move is the last use of SrcReg.
251 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
253  const DebugLoc &DL, unsigned DestReg,
254  unsigned SrcReg, unsigned LowLowOpcode,
255  unsigned Size, bool KillSrc,
256  bool UndefSrc) const {
257  unsigned Opcode;
258  bool DestIsHigh = SystemZ::isHighReg(DestReg);
259  bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
260  if (DestIsHigh && SrcIsHigh)
261  Opcode = SystemZ::RISBHH;
262  else if (DestIsHigh && !SrcIsHigh)
263  Opcode = SystemZ::RISBHL;
264  else if (!DestIsHigh && SrcIsHigh)
265  Opcode = SystemZ::RISBLH;
266  else {
267  return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
268  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
269  }
270  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
271  return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
272  .addReg(DestReg, RegState::Undef)
273  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
274  .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
275 }
276 
278  bool NewMI,
279  unsigned OpIdx1,
280  unsigned OpIdx2) const {
281  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
282  if (NewMI)
283  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
284  return MI;
285  };
286 
287  switch (MI.getOpcode()) {
288  case SystemZ::SELRMux:
289  case SystemZ::SELFHR:
290  case SystemZ::SELR:
291  case SystemZ::SELGR:
292  case SystemZ::LOCRMux:
293  case SystemZ::LOCFHR:
294  case SystemZ::LOCR:
295  case SystemZ::LOCGR: {
296  auto &WorkingMI = cloneIfNew(MI);
297  // Invert condition.
298  unsigned CCValid = WorkingMI.getOperand(3).getImm();
299  unsigned CCMask = WorkingMI.getOperand(4).getImm();
300  WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
301  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
302  OpIdx1, OpIdx2);
303  }
304  default:
305  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
306  }
307 }
308 
309 // If MI is a simple load or store for a frame object, return the register
310 // it loads or stores and set FrameIndex to the index of the frame object.
311 // Return 0 otherwise.
312 //
313 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
314 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
315  unsigned Flag) {
316  const MCInstrDesc &MCID = MI.getDesc();
317  if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
318  MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
319  FrameIndex = MI.getOperand(1).getIndex();
320  return MI.getOperand(0).getReg();
321  }
322  return 0;
323 }
324 
326  int &FrameIndex) const {
328 }
329 
331  int &FrameIndex) const {
333 }
334 
336  int &DestFrameIndex,
337  int &SrcFrameIndex) const {
338  // Check for MVC 0(Length,FI1),0(FI2)
339  const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
340  if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
341  MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
342  MI.getOperand(4).getImm() != 0)
343  return false;
344 
345  // Check that Length covers the full slots.
346  int64_t Length = MI.getOperand(2).getImm();
347  unsigned FI1 = MI.getOperand(0).getIndex();
348  unsigned FI2 = MI.getOperand(3).getIndex();
349  if (MFI.getObjectSize(FI1) != Length ||
350  MFI.getObjectSize(FI2) != Length)
351  return false;
352 
353  DestFrameIndex = FI1;
354  SrcFrameIndex = FI2;
355  return true;
356 }
357 
359  MachineBasicBlock *&TBB,
360  MachineBasicBlock *&FBB,
362  bool AllowModify) const {
363  // Most of the code and comments here are boilerplate.
364 
365  // Start from the bottom of the block and work up, examining the
366  // terminator instructions.
368  while (I != MBB.begin()) {
369  --I;
370  if (I->isDebugInstr())
371  continue;
372 
373  // Working from the bottom, when we see a non-terminator instruction, we're
374  // done.
375  if (!isUnpredicatedTerminator(*I))
376  break;
377 
378  // A terminator that isn't a branch can't easily be handled by this
379  // analysis.
380  if (!I->isBranch())
381  return true;
382 
383  // Can't handle indirect branches.
385  if (!Branch.hasMBBTarget())
386  return true;
387 
388  // Punt on compound branches.
389  if (Branch.Type != SystemZII::BranchNormal)
390  return true;
391 
392  if (Branch.CCMask == SystemZ::CCMASK_ANY) {
393  // Handle unconditional branches.
394  if (!AllowModify) {
395  TBB = Branch.getMBBTarget();
396  continue;
397  }
398 
399  // If the block has any instructions after a JMP, delete them.
400  while (std::next(I) != MBB.end())
401  std::next(I)->eraseFromParent();
402 
403  Cond.clear();
404  FBB = nullptr;
405 
406  // Delete the JMP if it's equivalent to a fall-through.
407  if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
408  TBB = nullptr;
409  I->eraseFromParent();
410  I = MBB.end();
411  continue;
412  }
413 
414  // TBB is used to indicate the unconditinal destination.
415  TBB = Branch.getMBBTarget();
416  continue;
417  }
418 
419  // Working from the bottom, handle the first conditional branch.
420  if (Cond.empty()) {
421  // FIXME: add X86-style branch swap
422  FBB = TBB;
423  TBB = Branch.getMBBTarget();
424  Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
425  Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
426  continue;
427  }
428 
429  // Handle subsequent conditional branches.
430  assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
431 
432  // Only handle the case where all conditional branches branch to the same
433  // destination.
434  if (TBB != Branch.getMBBTarget())
435  return true;
436 
437  // If the conditions are the same, we can leave them alone.
438  unsigned OldCCValid = Cond[0].getImm();
439  unsigned OldCCMask = Cond[1].getImm();
440  if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
441  continue;
442 
443  // FIXME: Try combining conditions like X86 does. Should be easy on Z!
444  return false;
445  }
446 
447  return false;
448 }
449 
451  int *BytesRemoved) const {
452  assert(!BytesRemoved && "code size not handled");
453 
454  // Most of the code and comments here are boilerplate.
456  unsigned Count = 0;
457 
458  while (I != MBB.begin()) {
459  --I;
460  if (I->isDebugInstr())
461  continue;
462  if (!I->isBranch())
463  break;
464  if (!getBranchInfo(*I).hasMBBTarget())
465  break;
466  // Remove the branch.
467  I->eraseFromParent();
468  I = MBB.end();
469  ++Count;
470  }
471 
472  return Count;
473 }
474 
477  assert(Cond.size() == 2 && "Invalid condition");
478  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
479  return false;
480 }
481 
483  MachineBasicBlock *TBB,
484  MachineBasicBlock *FBB,
486  const DebugLoc &DL,
487  int *BytesAdded) const {
488  // In this function we output 32-bit branches, which should always
489  // have enough range. They can be shortened and relaxed by later code
490  // in the pipeline, if desired.
491 
492  // Shouldn't be a fall through.
493  assert(TBB && "insertBranch must not be told to insert a fallthrough");
494  assert((Cond.size() == 2 || Cond.size() == 0) &&
495  "SystemZ branch conditions have one component!");
496  assert(!BytesAdded && "code size not handled");
497 
498  if (Cond.empty()) {
499  // Unconditional branch?
500  assert(!FBB && "Unconditional branch with multiple successors!");
501  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
502  return 1;
503  }
504 
505  // Conditional branch.
506  unsigned Count = 0;
507  unsigned CCValid = Cond[0].getImm();
508  unsigned CCMask = Cond[1].getImm();
509  BuildMI(&MBB, DL, get(SystemZ::BRC))
510  .addImm(CCValid).addImm(CCMask).addMBB(TBB);
511  ++Count;
512 
513  if (FBB) {
514  // Two-way Conditional branch. Insert the second branch.
515  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
516  ++Count;
517  }
518  return Count;
519 }
520 
522  Register &SrcReg2, int64_t &Mask,
523  int64_t &Value) const {
524  assert(MI.isCompare() && "Caller should have checked for a comparison");
525 
526  if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
527  MI.getOperand(1).isImm()) {
528  SrcReg = MI.getOperand(0).getReg();
529  SrcReg2 = 0;
530  Value = MI.getOperand(1).getImm();
531  Mask = ~0;
532  return true;
533  }
534 
535  return false;
536 }
537 
540  Register DstReg, Register TrueReg,
541  Register FalseReg, int &CondCycles,
542  int &TrueCycles,
543  int &FalseCycles) const {
544  // Not all subtargets have LOCR instructions.
545  if (!STI.hasLoadStoreOnCond())
546  return false;
547  if (Pred.size() != 2)
548  return false;
549 
550  // Check register classes.
552  const TargetRegisterClass *RC =
553  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
554  if (!RC)
555  return false;
556 
557  // We have LOCR instructions for 32 and 64 bit general purpose registers.
558  if ((STI.hasLoadStoreOnCond2() &&
559  SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
560  SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
561  SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
562  CondCycles = 2;
563  TrueCycles = 2;
564  FalseCycles = 2;
565  return true;
566  }
567 
568  // Can't do anything else.
569  return false;
570 }
571 
574  const DebugLoc &DL, Register DstReg,
576  Register TrueReg,
577  Register FalseReg) const {
579  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
580 
581  assert(Pred.size() == 2 && "Invalid condition");
582  unsigned CCValid = Pred[0].getImm();
583  unsigned CCMask = Pred[1].getImm();
584 
585  unsigned Opc;
586  if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
587  if (STI.hasMiscellaneousExtensions3())
588  Opc = SystemZ::SELRMux;
589  else if (STI.hasLoadStoreOnCond2())
590  Opc = SystemZ::LOCRMux;
591  else {
592  Opc = SystemZ::LOCR;
593  MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
594  Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
595  Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
596  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
597  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
598  TrueReg = TReg;
599  FalseReg = FReg;
600  }
601  } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
602  if (STI.hasMiscellaneousExtensions3())
603  Opc = SystemZ::SELGR;
604  else
605  Opc = SystemZ::LOCGR;
606  } else
607  llvm_unreachable("Invalid register class");
608 
609  BuildMI(MBB, I, DL, get(Opc), DstReg)
610  .addReg(FalseReg).addReg(TrueReg)
611  .addImm(CCValid).addImm(CCMask);
612 }
613 
615  Register Reg,
616  MachineRegisterInfo *MRI) const {
617  unsigned DefOpc = DefMI.getOpcode();
618  if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
619  DefOpc != SystemZ::LGHI)
620  return false;
621  if (DefMI.getOperand(0).getReg() != Reg)
622  return false;
623  int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
624 
625  unsigned UseOpc = UseMI.getOpcode();
626  unsigned NewUseOpc;
627  unsigned UseIdx;
628  int CommuteIdx = -1;
629  bool TieOps = false;
630  switch (UseOpc) {
631  case SystemZ::SELRMux:
632  TieOps = true;
634  case SystemZ::LOCRMux:
635  if (!STI.hasLoadStoreOnCond2())
636  return false;
637  NewUseOpc = SystemZ::LOCHIMux;
638  if (UseMI.getOperand(2).getReg() == Reg)
639  UseIdx = 2;
640  else if (UseMI.getOperand(1).getReg() == Reg)
641  UseIdx = 2, CommuteIdx = 1;
642  else
643  return false;
644  break;
645  case SystemZ::SELGR:
646  TieOps = true;
648  case SystemZ::LOCGR:
649  if (!STI.hasLoadStoreOnCond2())
650  return false;
651  NewUseOpc = SystemZ::LOCGHI;
652  if (UseMI.getOperand(2).getReg() == Reg)
653  UseIdx = 2;
654  else if (UseMI.getOperand(1).getReg() == Reg)
655  UseIdx = 2, CommuteIdx = 1;
656  else
657  return false;
658  break;
659  default:
660  return false;
661  }
662 
663  if (CommuteIdx != -1)
664  if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
665  return false;
666 
667  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
668  UseMI.setDesc(get(NewUseOpc));
669  if (TieOps)
670  UseMI.tieOperands(0, 1);
671  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
672  if (DeleteDef)
673  DefMI.eraseFromParent();
674 
675  return true;
676 }
677 
679  unsigned Opcode = MI.getOpcode();
680  if (Opcode == SystemZ::Return ||
681  Opcode == SystemZ::Return_XPLINK ||
682  Opcode == SystemZ::Trap ||
683  Opcode == SystemZ::CallJG ||
684  Opcode == SystemZ::CallBR)
685  return true;
686  return false;
687 }
688 
691  unsigned NumCycles, unsigned ExtraPredCycles,
692  BranchProbability Probability) const {
693  // Avoid using conditional returns at the end of a loop (since then
694  // we'd need to emit an unconditional branch to the beginning anyway,
695  // making the loop body longer). This doesn't apply for low-probability
696  // loops (eg. compare-and-swap retry), so just decide based on branch
697  // probability instead of looping structure.
698  // However, since Compare and Trap instructions cost the same as a regular
699  // Compare instruction, we should allow the if conversion to convert this
700  // into a Conditional Compare regardless of the branch probability.
701  if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
702  MBB.succ_empty() && Probability < BranchProbability(1, 8))
703  return false;
704  // For now only convert single instructions.
705  return NumCycles == 1;
706 }
707 
710  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
711  MachineBasicBlock &FMBB,
712  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
713  BranchProbability Probability) const {
714  // For now avoid converting mutually-exclusive cases.
715  return false;
716 }
717 
720  BranchProbability Probability) const {
721  // For now only duplicate single instructions.
722  return NumCycles == 1;
723 }
724 
727  assert(Pred.size() == 2 && "Invalid condition");
728  unsigned CCValid = Pred[0].getImm();
729  unsigned CCMask = Pred[1].getImm();
730  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
731  unsigned Opcode = MI.getOpcode();
732  if (Opcode == SystemZ::Trap) {
733  MI.setDesc(get(SystemZ::CondTrap));
734  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
735  .addImm(CCValid).addImm(CCMask)
736  .addReg(SystemZ::CC, RegState::Implicit);
737  return true;
738  }
739  if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
740  MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
741  : SystemZ::CondReturn_XPLINK));
742  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
743  .addImm(CCValid)
744  .addImm(CCMask)
745  .addReg(SystemZ::CC, RegState::Implicit);
746  return true;
747  }
748  if (Opcode == SystemZ::CallJG) {
749  MachineOperand FirstOp = MI.getOperand(0);
750  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
751  MI.removeOperand(1);
752  MI.removeOperand(0);
753  MI.setDesc(get(SystemZ::CallBRCL));
754  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
755  .addImm(CCValid)
756  .addImm(CCMask)
757  .add(FirstOp)
758  .addRegMask(RegMask)
759  .addReg(SystemZ::CC, RegState::Implicit);
760  return true;
761  }
762  if (Opcode == SystemZ::CallBR) {
763  MachineOperand Target = MI.getOperand(0);
764  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
765  MI.removeOperand(1);
766  MI.removeOperand(0);
767  MI.setDesc(get(SystemZ::CallBCR));
768  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
769  .addImm(CCValid).addImm(CCMask)
770  .add(Target)
771  .addRegMask(RegMask)
772  .addReg(SystemZ::CC, RegState::Implicit);
773  return true;
774  }
775  return false;
776 }
777 
780  const DebugLoc &DL, MCRegister DestReg,
781  MCRegister SrcReg, bool KillSrc) const {
782  // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
783  // super register in case one of the subregs is undefined.
784  // This handles ADDR128 too.
785  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
786  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
787  RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
788  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
789  .addReg(SrcReg, RegState::Implicit);
790  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
791  RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
792  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
793  .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
794  return;
795  }
796 
797  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
798  emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
799  false);
800  return;
801  }
802 
803  // Move 128-bit floating-point values between VR128 and FP128.
804  if (SystemZ::VR128BitRegClass.contains(DestReg) &&
805  SystemZ::FP128BitRegClass.contains(SrcReg)) {
806  MCRegister SrcRegHi =
807  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
808  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
809  MCRegister SrcRegLo =
810  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
811  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
812 
813  BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
814  .addReg(SrcRegHi, getKillRegState(KillSrc))
815  .addReg(SrcRegLo, getKillRegState(KillSrc));
816  return;
817  }
818  if (SystemZ::FP128BitRegClass.contains(DestReg) &&
819  SystemZ::VR128BitRegClass.contains(SrcReg)) {
820  MCRegister DestRegHi =
821  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
822  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
823  MCRegister DestRegLo =
824  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
825  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
826 
827  if (DestRegHi != SrcReg)
828  copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
829  BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
830  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
831  return;
832  }
833 
834  // Move CC value from a GR32.
835  if (DestReg == SystemZ::CC) {
836  unsigned Opcode =
837  SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
838  BuildMI(MBB, MBBI, DL, get(Opcode))
839  .addReg(SrcReg, getKillRegState(KillSrc))
840  .addImm(3 << (SystemZ::IPM_CC - 16));
841  return;
842  }
843 
844  // Everything else needs only one instruction.
845  unsigned Opcode;
846  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
847  Opcode = SystemZ::LGR;
848  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
849  // For z13 we prefer LDR over LER to avoid partial register dependencies.
850  Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
851  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
852  Opcode = SystemZ::LDR;
853  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
854  Opcode = SystemZ::LXR;
855  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
856  Opcode = SystemZ::VLR32;
857  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
858  Opcode = SystemZ::VLR64;
859  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
860  Opcode = SystemZ::VLR;
861  else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
862  Opcode = SystemZ::CPYA;
863  else
864  llvm_unreachable("Impossible reg-to-reg copy");
865 
866  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
867  .addReg(SrcReg, getKillRegState(KillSrc));
868 }
869 
872  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
873  const TargetRegisterInfo *TRI) const {
874  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
875 
876  // Callers may expect a single instruction, so keep 128-bit moves
877  // together for now and lower them after register allocation.
878  unsigned LoadOpcode, StoreOpcode;
879  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
880  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
881  .addReg(SrcReg, getKillRegState(isKill)),
882  FrameIdx);
883 }
884 
887  int FrameIdx, const TargetRegisterClass *RC,
888  const TargetRegisterInfo *TRI) const {
889  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
890 
891  // Callers may expect a single instruction, so keep 128-bit moves
892  // together for now and lower them after register allocation.
893  unsigned LoadOpcode, StoreOpcode;
894  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
895  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
896  FrameIdx);
897 }
898 
899 // Return true if MI is a simple load or store with a 12-bit displacement
900 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
901 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
902  const MCInstrDesc &MCID = MI->getDesc();
903  return ((MCID.TSFlags & Flag) &&
904  isUInt<12>(MI->getOperand(2).getImm()) &&
905  MI->getOperand(3).getReg() == 0);
906 }
907 
908 namespace {
909 
910 struct LogicOp {
911  LogicOp() = default;
912  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
913  : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
914 
915  explicit operator bool() const { return RegSize; }
916 
917  unsigned RegSize = 0;
918  unsigned ImmLSB = 0;
919  unsigned ImmSize = 0;
920 };
921 
922 } // end anonymous namespace
923 
924 static LogicOp interpretAndImmediate(unsigned Opcode) {
925  switch (Opcode) {
926  case SystemZ::NILMux: return LogicOp(32, 0, 16);
927  case SystemZ::NIHMux: return LogicOp(32, 16, 16);
928  case SystemZ::NILL64: return LogicOp(64, 0, 16);
929  case SystemZ::NILH64: return LogicOp(64, 16, 16);
930  case SystemZ::NIHL64: return LogicOp(64, 32, 16);
931  case SystemZ::NIHH64: return LogicOp(64, 48, 16);
932  case SystemZ::NIFMux: return LogicOp(32, 0, 32);
933  case SystemZ::NILF64: return LogicOp(64, 0, 32);
934  case SystemZ::NIHF64: return LogicOp(64, 32, 32);
935  default: return LogicOp();
936  }
937 }
938 
939 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
940  if (OldMI->registerDefIsDead(SystemZ::CC)) {
941  MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
942  if (CCDef != nullptr)
943  CCDef->setIsDead(true);
944  }
945 }
946 
947 static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
949  if (OldMI->getFlag(Flag))
950  NewMI->setFlag(Flag);
951 }
952 
953 MachineInstr *
955  LiveIntervals *LIS) const {
956  MachineBasicBlock *MBB = MI.getParent();
957 
958  // Try to convert an AND into an RISBG-type instruction.
959  // TODO: It might be beneficial to select RISBG and shorten to AND instead.
960  if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
961  uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
962  // AND IMMEDIATE leaves the other bits of the register unchanged.
963  Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
964  unsigned Start, End;
965  if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
966  unsigned NewOpcode;
967  if (And.RegSize == 64) {
968  NewOpcode = SystemZ::RISBG;
969  // Prefer RISBGN if available, since it does not clobber CC.
970  if (STI.hasMiscellaneousExtensions())
971  NewOpcode = SystemZ::RISBGN;
972  } else {
973  NewOpcode = SystemZ::RISBMux;
974  Start &= 31;
975  End &= 31;
976  }
977  MachineOperand &Dest = MI.getOperand(0);
978  MachineOperand &Src = MI.getOperand(1);
979  MachineInstrBuilder MIB =
980  BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
981  .add(Dest)
982  .addReg(0)
983  .addReg(Src.getReg(), getKillRegState(Src.isKill()),
984  Src.getSubReg())
985  .addImm(Start)
986  .addImm(End + 128)
987  .addImm(0);
988  if (LV) {
989  unsigned NumOps = MI.getNumOperands();
990  for (unsigned I = 1; I < NumOps; ++I) {
991  MachineOperand &Op = MI.getOperand(I);
992  if (Op.isReg() && Op.isKill())
993  LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
994  }
995  }
996  if (LIS)
997  LIS->ReplaceMachineInstrInMaps(MI, *MIB);
998  transferDeadCC(&MI, MIB);
999  return MIB;
1000  }
1001  }
1002  return nullptr;
1003 }
1004 
1008  LiveIntervals *LIS, VirtRegMap *VRM) const {
1011  const MachineFrameInfo &MFI = MF.getFrameInfo();
1012  unsigned Size = MFI.getObjectSize(FrameIndex);
1013  unsigned Opcode = MI.getOpcode();
1014 
1015  // Check CC liveness if new instruction introduces a dead def of CC.
1016  MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
1017  SlotIndex MISlot = SlotIndex();
1018  LiveRange *CCLiveRange = nullptr;
1019  bool CCLiveAtMI = true;
1020  if (LIS) {
1021  MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1022  CCLiveRange = &LIS->getRegUnit(*CCUnit);
1023  CCLiveAtMI = CCLiveRange->liveAt(MISlot);
1024  }
1025  ++CCUnit;
1026  assert(!CCUnit.isValid() && "CC only has one reg unit.");
1027 
1028  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1029  if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1030  isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1031  // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1032  MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1033  MI.getDebugLoc(), get(SystemZ::AGSI))
1035  .addImm(0)
1036  .addImm(MI.getOperand(2).getImm());
1037  BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1038  CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1039  return BuiltMI;
1040  }
1041  return nullptr;
1042  }
1043 
1044  // All other cases require a single operand.
1045  if (Ops.size() != 1)
1046  return nullptr;
1047 
1048  unsigned OpNum = Ops[0];
1049  assert(Size * 8 ==
1051  .getRegClass(MI.getOperand(OpNum).getReg())) &&
1052  "Invalid size combination");
1053 
1054  if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1055  isInt<8>(MI.getOperand(2).getImm())) {
1056  // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1057  Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1058  MachineInstr *BuiltMI =
1059  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1061  .addImm(0)
1062  .addImm(MI.getOperand(2).getImm());
1063  transferDeadCC(&MI, BuiltMI);
1065  return BuiltMI;
1066  }
1067 
1068  if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1069  isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1070  (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1071  isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1072  // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1073  Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1074  MachineInstr *BuiltMI =
1075  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1077  .addImm(0)
1078  .addImm((int8_t)MI.getOperand(2).getImm());
1079  transferDeadCC(&MI, BuiltMI);
1080  return BuiltMI;
1081  }
1082 
1083  if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1084  isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1085  (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1086  isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1087  // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1088  Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1089  MachineInstr *BuiltMI =
1090  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1092  .addImm(0)
1093  .addImm((int8_t)-MI.getOperand(2).getImm());
1094  transferDeadCC(&MI, BuiltMI);
1095  return BuiltMI;
1096  }
1097 
1098  unsigned MemImmOpc = 0;
1099  switch (Opcode) {
1100  case SystemZ::LHIMux:
1101  case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;
1102  case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;
1103  case SystemZ::CHIMux:
1104  case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;
1105  case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;
1106  case SystemZ::CLFIMux:
1107  case SystemZ::CLFI:
1108  if (isUInt<16>(MI.getOperand(1).getImm()))
1109  MemImmOpc = SystemZ::CLFHSI;
1110  break;
1111  case SystemZ::CLGFI:
1112  if (isUInt<16>(MI.getOperand(1).getImm()))
1113  MemImmOpc = SystemZ::CLGHSI;
1114  break;
1115  default: break;
1116  }
1117  if (MemImmOpc)
1118  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1119  get(MemImmOpc))
1121  .addImm(0)
1122  .addImm(MI.getOperand(1).getImm());
1123 
1124  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1125  bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1126  bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1127  // If we're spilling the destination of an LDGR or LGDR, store the
1128  // source register instead.
1129  if (OpNum == 0) {
1130  unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1131  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1132  get(StoreOpcode))
1133  .add(MI.getOperand(1))
1135  .addImm(0)
1136  .addReg(0);
1137  }
1138  // If we're spilling the source of an LDGR or LGDR, load the
1139  // destination register instead.
1140  if (OpNum == 1) {
1141  unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1142  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1143  get(LoadOpcode))
1144  .add(MI.getOperand(0))
1146  .addImm(0)
1147  .addReg(0);
1148  }
1149  }
1150 
1151  // Look for cases where the source of a simple store or the destination
1152  // of a simple load is being spilled. Try to use MVC instead.
1153  //
1154  // Although MVC is in practice a fast choice in these cases, it is still
1155  // logically a bytewise copy. This means that we cannot use it if the
1156  // load or store is volatile. We also wouldn't be able to use MVC if
1157  // the two memories partially overlap, but that case cannot occur here,
1158  // because we know that one of the memories is a full frame index.
1159  //
1160  // For performance reasons, we also want to avoid using MVC if the addresses
1161  // might be equal. We don't worry about that case here, because spill slot
1162  // coloring happens later, and because we have special code to remove
1163  // MVCs that turn out to be redundant.
1164  if (OpNum == 0 && MI.hasOneMemOperand()) {
1165  MachineMemOperand *MMO = *MI.memoperands_begin();
1166  if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1167  // Handle conversion of loads.
1169  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1170  get(SystemZ::MVC))
1172  .addImm(0)
1173  .addImm(Size)
1174  .add(MI.getOperand(1))
1175  .addImm(MI.getOperand(2).getImm())
1176  .addMemOperand(MMO);
1177  }
1178  // Handle conversion of stores.
1180  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1181  get(SystemZ::MVC))
1182  .add(MI.getOperand(1))
1183  .addImm(MI.getOperand(2).getImm())
1184  .addImm(Size)
1186  .addImm(0)
1187  .addMemOperand(MMO);
1188  }
1189  }
1190  }
1191 
1192  // If the spilled operand is the final one or the instruction is
1193  // commutable, try to change <INSN>R into <INSN>. Don't introduce a def of
1194  // CC if it is live and MI does not define it.
1195  unsigned NumOps = MI.getNumExplicitOperands();
1196  int MemOpcode = SystemZ::getMemOpcode(Opcode);
1197  if (MemOpcode == -1 ||
1198  (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) &&
1199  get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1200  return nullptr;
1201 
1202  // Check if all other vregs have a usable allocation in the case of vector
1203  // to FP conversion.
1204  const MCInstrDesc &MCID = MI.getDesc();
1205  for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
1206  const MCOperandInfo &MCOI = MCID.OpInfo[I];
1207  if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
1208  continue;
1209  const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
1210  if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1211  Register Reg = MI.getOperand(I).getReg();
1213  ? (VRM ? Register(VRM->getPhys(Reg)) : Register())
1214  : Reg;
1215  if (!PhysReg ||
1216  !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
1217  SystemZ::FP64BitRegClass.contains(PhysReg) ||
1218  SystemZ::VF128BitRegClass.contains(PhysReg)))
1219  return nullptr;
1220  }
1221  }
1222  // Fused multiply and add/sub need to have the same dst and accumulator reg.
1223  bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1224  Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1225  if (FusedFPOp) {
1226  Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
1227  Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
1228  if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1229  return nullptr;
1230  }
1231 
1232  // Try to swap compare operands if possible.
1233  bool NeedsCommute = false;
1234  if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1235  MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1236  MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1237  MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1238  OpNum == 0 && prepareCompareSwapOperands(MI))
1239  NeedsCommute = true;
1240 
1241  bool CCOperands = false;
1242  if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1243  MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1244  assert(MI.getNumOperands() == 6 && NumOps == 5 &&
1245  "LOCR/SELR instruction operands corrupt?");
1246  NumOps -= 2;
1247  CCOperands = true;
1248  }
1249 
1250  // See if this is a 3-address instruction that is convertible to 2-address
1251  // and suitable for folding below. Only try this with virtual registers
1252  // and a provided VRM (during regalloc).
1253  if (NumOps == 3 && SystemZ::getTargetMemOpcode(MemOpcode) != -1) {
1254  if (VRM == nullptr)
1255  return nullptr;
1256  else {
1257  Register DstReg = MI.getOperand(0).getReg();
1258  Register DstPhys =
1259  (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
1260  : DstReg);
1261  Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1262  : ((OpNum == 1 && MI.isCommutable())
1263  ? MI.getOperand(2).getReg()
1264  : Register()));
1265  if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
1266  Register::isVirtualRegister(SrcReg) &&
1267  DstPhys == VRM->getPhys(SrcReg))
1268  NeedsCommute = (OpNum == 1);
1269  else
1270  return nullptr;
1271  }
1272  }
1273 
1274  if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1275  const MCInstrDesc &MemDesc = get(MemOpcode);
1276  uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1277  assert(AccessBytes != 0 && "Size of access should be known");
1278  assert(AccessBytes <= Size && "Access outside the frame index");
1279  uint64_t Offset = Size - AccessBytes;
1280  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1281  MI.getDebugLoc(), get(MemOpcode));
1282  if (MI.isCompare()) {
1283  assert(NumOps == 2 && "Expected 2 register operands for a compare.");
1284  MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
1285  }
1286  else if (FusedFPOp) {
1287  MIB.add(MI.getOperand(0));
1288  MIB.add(MI.getOperand(3));
1289  MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
1290  }
1291  else {
1292  MIB.add(MI.getOperand(0));
1293  if (NeedsCommute)
1294  MIB.add(MI.getOperand(2));
1295  else
1296  for (unsigned I = 1; I < OpNum; ++I)
1297  MIB.add(MI.getOperand(I));
1298  }
1299  MIB.addFrameIndex(FrameIndex).addImm(Offset);
1300  if (MemDesc.TSFlags & SystemZII::HasIndex)
1301  MIB.addReg(0);
1302  if (CCOperands) {
1303  unsigned CCValid = MI.getOperand(NumOps).getImm();
1304  unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
1305  MIB.addImm(CCValid);
1306  MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1307  }
1308  if (MIB->definesRegister(SystemZ::CC) &&
1309  (!MI.definesRegister(SystemZ::CC) ||
1310  MI.registerDefIsDead(SystemZ::CC))) {
1311  MIB->addRegisterDead(SystemZ::CC, TRI);
1312  if (CCLiveRange)
1313  CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1314  }
1315  // Constrain the register classes if converted from a vector opcode. The
1316  // allocated regs are in an FP reg-class per previous check above.
1317  for (const MachineOperand &MO : MIB->operands())
1318  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1319  Register Reg = MO.getReg();
1320  if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1321  MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1322  else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1323  MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1324  else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1325  MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1326  }
1327 
1328  transferDeadCC(&MI, MIB);
1331  return MIB;
1332  }
1333 
1334  return nullptr;
1335 }
1336 
1339  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1340  LiveIntervals *LIS) const {
1341  return nullptr;
1342 }
1343 
1345  switch (MI.getOpcode()) {
1346  case SystemZ::L128:
1347  splitMove(MI, SystemZ::LG);
1348  return true;
1349 
1350  case SystemZ::ST128:
1351  splitMove(MI, SystemZ::STG);
1352  return true;
1353 
1354  case SystemZ::LX:
1355  splitMove(MI, SystemZ::LD);
1356  return true;
1357 
1358  case SystemZ::STX:
1359  splitMove(MI, SystemZ::STD);
1360  return true;
1361 
1362  case SystemZ::LBMux:
1363  expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1364  return true;
1365 
1366  case SystemZ::LHMux:
1367  expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1368  return true;
1369 
1370  case SystemZ::LLCRMux:
1371  expandZExtPseudo(MI, SystemZ::LLCR, 8);
1372  return true;
1373 
1374  case SystemZ::LLHRMux:
1375  expandZExtPseudo(MI, SystemZ::LLHR, 16);
1376  return true;
1377 
1378  case SystemZ::LLCMux:
1379  expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1380  return true;
1381 
1382  case SystemZ::LLHMux:
1383  expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1384  return true;
1385 
1386  case SystemZ::LMux:
1387  expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1388  return true;
1389 
1390  case SystemZ::LOCMux:
1391  expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1392  return true;
1393 
1394  case SystemZ::LOCHIMux:
1395  expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1396  return true;
1397 
1398  case SystemZ::STCMux:
1399  expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1400  return true;
1401 
1402  case SystemZ::STHMux:
1403  expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1404  return true;
1405 
1406  case SystemZ::STMux:
1407  expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1408  return true;
1409 
1410  case SystemZ::STOCMux:
1411  expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1412  return true;
1413 
1414  case SystemZ::LHIMux:
1415  expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1416  return true;
1417 
1418  case SystemZ::IIFMux:
1419  expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1420  return true;
1421 
1422  case SystemZ::IILMux:
1423  expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1424  return true;
1425 
1426  case SystemZ::IIHMux:
1427  expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1428  return true;
1429 
1430  case SystemZ::NIFMux:
1431  expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1432  return true;
1433 
1434  case SystemZ::NILMux:
1435  expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1436  return true;
1437 
1438  case SystemZ::NIHMux:
1439  expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1440  return true;
1441 
1442  case SystemZ::OIFMux:
1443  expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1444  return true;
1445 
1446  case SystemZ::OILMux:
1447  expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1448  return true;
1449 
1450  case SystemZ::OIHMux:
1451  expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1452  return true;
1453 
1454  case SystemZ::XIFMux:
1455  expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1456  return true;
1457 
1458  case SystemZ::TMLMux:
1459  expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1460  return true;
1461 
1462  case SystemZ::TMHMux:
1463  expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1464  return true;
1465 
1466  case SystemZ::AHIMux:
1467  expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1468  return true;
1469 
1470  case SystemZ::AHIMuxK:
1471  expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1472  return true;
1473 
1474  case SystemZ::AFIMux:
1475  expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1476  return true;
1477 
1478  case SystemZ::CHIMux:
1479  expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1480  return true;
1481 
1482  case SystemZ::CFIMux:
1483  expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1484  return true;
1485 
1486  case SystemZ::CLFIMux:
1487  expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1488  return true;
1489 
1490  case SystemZ::CMux:
1491  expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1492  return true;
1493 
1494  case SystemZ::CLMux:
1495  expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1496  return true;
1497 
1498  case SystemZ::RISBMux: {
1499  bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1500  bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1501  if (SrcIsHigh == DestIsHigh)
1502  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1503  else {
1504  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1505  MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1506  }
1507  return true;
1508  }
1509 
1510  case SystemZ::ADJDYNALLOC:
1511  splitAdjDynAlloc(MI);
1512  return true;
1513 
1514  case TargetOpcode::LOAD_STACK_GUARD:
1515  expandLoadStackGuard(&MI);
1516  return true;
1517 
1518  default:
1519  return false;
1520  }
1521 }
1522 
1524  if (MI.isInlineAsm()) {
1525  const MachineFunction *MF = MI.getParent()->getParent();
1526  const char *AsmStr = MI.getOperand(0).getSymbolName();
1527  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1528  }
1529  else if (MI.getOpcode() == SystemZ::PATCHPOINT)
1530  return PatchPointOpers(&MI).getNumPatchBytes();
1531  else if (MI.getOpcode() == SystemZ::STACKMAP)
1532  return MI.getOperand(1).getImm();
1533  else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
1534  return 6;
1535 
1536  return MI.getDesc().getSize();
1537 }
1538 
1541  switch (MI.getOpcode()) {
1542  case SystemZ::BR:
1543  case SystemZ::BI:
1544  case SystemZ::J:
1545  case SystemZ::JG:
1547  SystemZ::CCMASK_ANY, &MI.getOperand(0));
1548 
1549  case SystemZ::BRC:
1550  case SystemZ::BRCL:
1551  return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1552  MI.getOperand(1).getImm(), &MI.getOperand(2));
1553 
1554  case SystemZ::BRCT:
1555  case SystemZ::BRCTH:
1557  SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1558 
1559  case SystemZ::BRCTG:
1561  SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1562 
1563  case SystemZ::CIJ:
1564  case SystemZ::CRJ:
1566  MI.getOperand(2).getImm(), &MI.getOperand(3));
1567 
1568  case SystemZ::CLIJ:
1569  case SystemZ::CLRJ:
1571  MI.getOperand(2).getImm(), &MI.getOperand(3));
1572 
1573  case SystemZ::CGIJ:
1574  case SystemZ::CGRJ:
1576  MI.getOperand(2).getImm(), &MI.getOperand(3));
1577 
1578  case SystemZ::CLGIJ:
1579  case SystemZ::CLGRJ:
1581  MI.getOperand(2).getImm(), &MI.getOperand(3));
1582 
1583  case SystemZ::INLINEASM_BR:
1584  // Don't try to analyze asm goto, so pass nullptr as branch target argument.
1585  return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);
1586 
1587  default:
1588  llvm_unreachable("Unrecognized branch opcode");
1589  }
1590 }
1591 
1593  unsigned &LoadOpcode,
1594  unsigned &StoreOpcode) const {
1595  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1596  LoadOpcode = SystemZ::L;
1597  StoreOpcode = SystemZ::ST;
1598  } else if (RC == &SystemZ::GRH32BitRegClass) {
1599  LoadOpcode = SystemZ::LFH;
1600  StoreOpcode = SystemZ::STFH;
1601  } else if (RC == &SystemZ::GRX32BitRegClass) {
1602  LoadOpcode = SystemZ::LMux;
1603  StoreOpcode = SystemZ::STMux;
1604  } else if (RC == &SystemZ::GR64BitRegClass ||
1605  RC == &SystemZ::ADDR64BitRegClass) {
1606  LoadOpcode = SystemZ::LG;
1607  StoreOpcode = SystemZ::STG;
1608  } else if (RC == &SystemZ::GR128BitRegClass ||
1609  RC == &SystemZ::ADDR128BitRegClass) {
1610  LoadOpcode = SystemZ::L128;
1611  StoreOpcode = SystemZ::ST128;
1612  } else if (RC == &SystemZ::FP32BitRegClass) {
1613  LoadOpcode = SystemZ::LE;
1614  StoreOpcode = SystemZ::STE;
1615  } else if (RC == &SystemZ::FP64BitRegClass) {
1616  LoadOpcode = SystemZ::LD;
1617  StoreOpcode = SystemZ::STD;
1618  } else if (RC == &SystemZ::FP128BitRegClass) {
1619  LoadOpcode = SystemZ::LX;
1620  StoreOpcode = SystemZ::STX;
1621  } else if (RC == &SystemZ::VR32BitRegClass) {
1622  LoadOpcode = SystemZ::VL32;
1623  StoreOpcode = SystemZ::VST32;
1624  } else if (RC == &SystemZ::VR64BitRegClass) {
1625  LoadOpcode = SystemZ::VL64;
1626  StoreOpcode = SystemZ::VST64;
1627  } else if (RC == &SystemZ::VF128BitRegClass ||
1628  RC == &SystemZ::VR128BitRegClass) {
1629  LoadOpcode = SystemZ::VL;
1630  StoreOpcode = SystemZ::VST;
1631  } else
1632  llvm_unreachable("Unsupported regclass to load or store");
1633 }
1634 
1635 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1636  int64_t Offset) const {
1637  const MCInstrDesc &MCID = get(Opcode);
1638  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1639  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1640  // Get the instruction to use for unsigned 12-bit displacements.
1641  int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1642  if (Disp12Opcode >= 0)
1643  return Disp12Opcode;
1644 
1645  // All address-related instructions can use unsigned 12-bit
1646  // displacements.
1647  return Opcode;
1648  }
1649  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1650  // Get the instruction to use for signed 20-bit displacements.
1651  int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1652  if (Disp20Opcode >= 0)
1653  return Disp20Opcode;
1654 
1655  // Check whether Opcode allows signed 20-bit displacements.
1657  return Opcode;
1658  }
1659  return 0;
1660 }
1661 
1662 bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
1663  const MCInstrDesc &MCID = get(Opcode);
1665  return SystemZ::getDisp12Opcode(Opcode) >= 0;
1666  return SystemZ::getDisp20Opcode(Opcode) >= 0;
1667 }
1668 
1669 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1670  switch (Opcode) {
1671  case SystemZ::L: return SystemZ::LT;
1672  case SystemZ::LY: return SystemZ::LT;
1673  case SystemZ::LG: return SystemZ::LTG;
1674  case SystemZ::LGF: return SystemZ::LTGF;
1675  case SystemZ::LR: return SystemZ::LTR;
1676  case SystemZ::LGFR: return SystemZ::LTGFR;
1677  case SystemZ::LGR: return SystemZ::LTGR;
1678  case SystemZ::LER: return SystemZ::LTEBR;
1679  case SystemZ::LDR: return SystemZ::LTDBR;
1680  case SystemZ::LXR: return SystemZ::LTXBR;
1681  case SystemZ::LCDFR: return SystemZ::LCDBR;
1682  case SystemZ::LPDFR: return SystemZ::LPDBR;
1683  case SystemZ::LNDFR: return SystemZ::LNDBR;
1684  case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1685  case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1686  case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1687  // On zEC12 we prefer to use RISBGN. But if there is a chance to
1688  // actually use the condition code, we may turn it back into RISGB.
1689  // Note that RISBG is not really a "load-and-test" instruction,
1690  // but sets the same condition code values, so is OK to use here.
1691  case SystemZ::RISBGN: return SystemZ::RISBG;
1692  default: return 0;
1693  }
1694 }
1695 
1696 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1697 // have already been filtered out. Store the first set bit in LSB and
1698 // the number of set bits in Length if so.
1699 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1700  unsigned First = findFirstSet(Mask);
1701  uint64_t Top = (Mask >> First) + 1;
1702  if ((Top & -Top) == Top) {
1703  LSB = First;
1704  Length = findFirstSet(Top);
1705  return true;
1706  }
1707  return false;
1708 }
1709 
1711  unsigned &Start, unsigned &End) const {
1712  // Reject trivial all-zero masks.
1713  Mask &= allOnes(BitSize);
1714  if (Mask == 0)
1715  return false;
1716 
1717  // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1718  // the msb and End specifies the index of the lsb.
1719  unsigned LSB, Length;
1720  if (isStringOfOnes(Mask, LSB, Length)) {
1721  Start = 63 - (LSB + Length - 1);
1722  End = 63 - LSB;
1723  return true;
1724  }
1725 
1726  // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1727  // of the low 1s and End specifies the lsb of the high 1s.
1728  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1729  assert(LSB > 0 && "Bottom bit must be set");
1730  assert(LSB + Length < BitSize && "Top bit must be set");
1731  Start = 63 - (LSB - 1);
1732  End = 63 - (LSB + Length);
1733  return true;
1734  }
1735 
1736  return false;
1737 }
1738 
1739 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1741  const MachineInstr *MI) const {
1742  switch (Opcode) {
1743  case SystemZ::CHI:
1744  case SystemZ::CGHI:
1745  if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1746  return 0;
1747  break;
1748  case SystemZ::CLFI:
1749  case SystemZ::CLGFI:
1750  if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1751  return 0;
1752  break;
1753  case SystemZ::CL:
1754  case SystemZ::CLG:
1755  if (!STI.hasMiscellaneousExtensions())
1756  return 0;
1757  if (!(MI && MI->getOperand(3).getReg() == 0))
1758  return 0;
1759  break;
1760  }
1761  switch (Type) {
1763  switch (Opcode) {
1764  case SystemZ::CR:
1765  return SystemZ::CRJ;
1766  case SystemZ::CGR:
1767  return SystemZ::CGRJ;
1768  case SystemZ::CHI:
1769  return SystemZ::CIJ;
1770  case SystemZ::CGHI:
1771  return SystemZ::CGIJ;
1772  case SystemZ::CLR:
1773  return SystemZ::CLRJ;
1774  case SystemZ::CLGR:
1775  return SystemZ::CLGRJ;
1776  case SystemZ::CLFI:
1777  return SystemZ::CLIJ;
1778  case SystemZ::CLGFI:
1779  return SystemZ::CLGIJ;
1780  default:
1781  return 0;
1782  }
1784  switch (Opcode) {
1785  case SystemZ::CR:
1786  return SystemZ::CRBReturn;
1787  case SystemZ::CGR:
1788  return SystemZ::CGRBReturn;
1789  case SystemZ::CHI:
1790  return SystemZ::CIBReturn;
1791  case SystemZ::CGHI:
1792  return SystemZ::CGIBReturn;
1793  case SystemZ::CLR:
1794  return SystemZ::CLRBReturn;
1795  case SystemZ::CLGR:
1796  return SystemZ::CLGRBReturn;
1797  case SystemZ::CLFI:
1798  return SystemZ::CLIBReturn;
1799  case SystemZ::CLGFI:
1800  return SystemZ::CLGIBReturn;
1801  default:
1802  return 0;
1803  }
1805  switch (Opcode) {
1806  case SystemZ::CR:
1807  return SystemZ::CRBCall;
1808  case SystemZ::CGR:
1809  return SystemZ::CGRBCall;
1810  case SystemZ::CHI:
1811  return SystemZ::CIBCall;
1812  case SystemZ::CGHI:
1813  return SystemZ::CGIBCall;
1814  case SystemZ::CLR:
1815  return SystemZ::CLRBCall;
1816  case SystemZ::CLGR:
1817  return SystemZ::CLGRBCall;
1818  case SystemZ::CLFI:
1819  return SystemZ::CLIBCall;
1820  case SystemZ::CLGFI:
1821  return SystemZ::CLGIBCall;
1822  default:
1823  return 0;
1824  }
1826  switch (Opcode) {
1827  case SystemZ::CR:
1828  return SystemZ::CRT;
1829  case SystemZ::CGR:
1830  return SystemZ::CGRT;
1831  case SystemZ::CHI:
1832  return SystemZ::CIT;
1833  case SystemZ::CGHI:
1834  return SystemZ::CGIT;
1835  case SystemZ::CLR:
1836  return SystemZ::CLRT;
1837  case SystemZ::CLGR:
1838  return SystemZ::CLGRT;
1839  case SystemZ::CLFI:
1840  return SystemZ::CLFIT;
1841  case SystemZ::CLGFI:
1842  return SystemZ::CLGIT;
1843  case SystemZ::CL:
1844  return SystemZ::CLT;
1845  case SystemZ::CLG:
1846  return SystemZ::CLGT;
1847  default:
1848  return 0;
1849  }
1850  }
1851  return 0;
1852 }
1853 
1854 bool SystemZInstrInfo::
1856  assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&
1857  MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&
1858  "Not a compare reg/reg.");
1859 
1861  bool CCLive = true;
1863  for (MachineBasicBlock::iterator Itr = std::next(MBBI);
1864  Itr != MBB->end(); ++Itr) {
1865  if (Itr->readsRegister(SystemZ::CC)) {
1866  unsigned Flags = Itr->getDesc().TSFlags;
1867  if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
1868  CCUsers.push_back(&*Itr);
1869  else
1870  return false;
1871  }
1872  if (Itr->definesRegister(SystemZ::CC)) {
1873  CCLive = false;
1874  break;
1875  }
1876  }
1877  if (CCLive) {
1879  LiveRegs.addLiveOuts(*MBB);
1880  if (LiveRegs.contains(SystemZ::CC))
1881  return false;
1882  }
1883 
1884  // Update all CC users.
1885  for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
1886  unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1887  unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
1888  0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
1889  MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
1890  unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
1891  CCMaskMO.setImm(NewCCMask);
1892  }
1893 
1894  return true;
1895 }
1896 
1897 unsigned SystemZ::reverseCCMask(unsigned CCMask) {
1898  return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1901  (CCMask & SystemZ::CCMASK_CMP_UO));
1902 }
1903 
1905  MachineFunction &MF = *MBB->getParent();
1907  MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
1908  return NewMBB;
1909 }
1910 
1914  NewMBB->splice(NewMBB->begin(), MBB,
1915  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1917  return NewMBB;
1918 }
1919 
1923  NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
1925  return NewMBB;
1926 }
1927 
1928 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1929  if (!STI.hasLoadAndTrap())
1930  return 0;
1931  switch (Opcode) {
1932  case SystemZ::L:
1933  case SystemZ::LY:
1934  return SystemZ::LAT;
1935  case SystemZ::LG:
1936  return SystemZ::LGAT;
1937  case SystemZ::LFH:
1938  return SystemZ::LFHAT;
1939  case SystemZ::LLGF:
1940  return SystemZ::LLGFAT;
1941  case SystemZ::LLGT:
1942  return SystemZ::LLGTAT;
1943  }
1944  return 0;
1945 }
1946 
1949  unsigned Reg, uint64_t Value) const {
1950  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1951  unsigned Opcode = 0;
1952  if (isInt<16>(Value))
1953  Opcode = SystemZ::LGHI;
1954  else if (SystemZ::isImmLL(Value))
1955  Opcode = SystemZ::LLILL;
1956  else if (SystemZ::isImmLH(Value)) {
1957  Opcode = SystemZ::LLILH;
1958  Value >>= 16;
1959  }
1960  else if (isInt<32>(Value))
1961  Opcode = SystemZ::LGFI;
1962  if (Opcode) {
1963  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1964  return;
1965  }
1966 
1968  assert (MRI.isSSA() && "Huge values only handled before reg-alloc .");
1969  Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1970  Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1971  BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0);
1972  BuildMI(MBB, MBBI, DL, get(SystemZ::IIHF64), Reg1)
1973  .addReg(Reg0).addImm(Value >> 32);
1974  BuildMI(MBB, MBBI, DL, get(SystemZ::IILF64), Reg)
1975  .addReg(Reg1).addImm(Value & ((uint64_t(1) << 32) - 1));
1976 }
1977 
1979  StringRef &ErrInfo) const {
1980  const MCInstrDesc &MCID = MI.getDesc();
1981  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
1982  if (I >= MCID.getNumOperands())
1983  break;
1984  const MachineOperand &Op = MI.getOperand(I);
1985  const MCOperandInfo &MCOI = MCID.OpInfo[I];
1986  // Addressing modes have register and immediate operands. Op should be a
1987  // register (or frame index) operand if MCOI.RegClass contains a valid
1988  // register class, or an immediate otherwise.
1989  if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
1990  ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
1991  (MCOI.RegClass == -1 && !Op.isImm()))) {
1992  ErrInfo = "Addressing mode operands corrupt!";
1993  return false;
1994  }
1995  }
1996 
1997  return true;
1998 }
1999 
2000 bool SystemZInstrInfo::
2002  const MachineInstr &MIb) const {
2003 
2004  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
2005  return false;
2006 
2007  // If mem-operands show that the same address Value is used by both
2008  // instructions, check for non-overlapping offsets and widths. Not
2009  // sure if a register based analysis would be an improvement...
2010 
2011  MachineMemOperand *MMOa = *MIa.memoperands_begin();
2012  MachineMemOperand *MMOb = *MIb.memoperands_begin();
2013  const Value *VALa = MMOa->getValue();
2014  const Value *VALb = MMOb->getValue();
2015  bool SameVal = (VALa && VALb && (VALa == VALb));
2016  if (!SameVal) {
2017  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
2018  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
2019  if (PSVa && PSVb && (PSVa == PSVb))
2020  SameVal = true;
2021  }
2022  if (SameVal) {
2023  int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
2024  int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
2025  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2026  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2027  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2028  if (LowOffset + LowWidth <= HighOffset)
2029  return true;
2030  }
2031 
2032  return false;
2033 }
llvm::SystemZ::isImmLH
static bool isImmLH(uint64_t Val)
Definition: SystemZ.h:166
llvm::SystemZInstrInfo::isRxSBGMask
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
Definition: SystemZInstrInfo.cpp:1710
llvm::SystemZInstrInfo::prepareCompareSwapOperands
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
Definition: SystemZInstrInfo.cpp:1855
llvm::SystemZInstrInfo::getFusedCompare
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
Definition: SystemZInstrInfo.cpp:1739
llvm::SystemZInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:719
SystemZInstrBuilder.h
llvm::findFirstSet
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
Definition: MathExtras.h:239
llvm::SystemZInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SystemZInstrInfo.cpp:572
llvm::SystemZSubtarget::hasMiscellaneousExtensions
bool hasMiscellaneousExtensions() const
Definition: SystemZSubtarget.h:177
llvm::SystemZInstrInfo::hasDisplacementPairInsn
bool hasDisplacementPairInsn(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1662
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1908
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::SystemZSubtarget::hasLoadStoreOnCond2
bool hasLoadStoreOnCond2() const
Definition: SystemZSubtarget.h:146
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:280
llvm::SystemZInstrInfo::getLoadStoreOpcodes
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Definition: SystemZInstrInfo.cpp:1592
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:211
llvm::SystemZII::Is128Bit
@ Is128Bit
Definition: SystemZInstrInfo.h:40
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:205
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::SystemZII::CompareAndReturn
@ CompareAndReturn
Definition: SystemZInstrInfo.h:145
llvm::SystemZInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: SystemZInstrInfo.cpp:954
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:126
llvm::MCRegister::from
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Definition: MCRegister.h:67
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::SystemZSubtarget::hasVector
bool hasVector() const
Definition: SystemZSubtarget.h:212
llvm::SystemZII::SimpleBDXStore
@ SimpleBDXStore
Definition: SystemZInstrInfo.h:37
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:710
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:61
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::SystemZII::BranchCTG
@ BranchCTG
Definition: SystemZInstrInfo.h:105
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::SystemZ::splitBlockAfter
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1911
isStringOfOnes
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
Definition: SystemZInstrInfo.cpp:1699
llvm::SmallVector< MachineInstr *, 4 >
Statistic.h
llvm::SystemZ::emitBlockAfter
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1904
llvm::SystemZII::Branch::hasMBBTarget
bool hasMBBTarget()
Definition: SystemZInstrInfo.h:131
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:225
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SystemZ::CCMASK_CMP_LT
const unsigned CCMASK_CMP_LT
Definition: SystemZ.h:36
llvm::SystemZInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SystemZInstrInfo.cpp:476
llvm::SystemZSubtarget::hasLoadAndTrap
bool hasLoadAndTrap() const
Definition: SystemZSubtarget.h:185
llvm::AArch64ISD::STG
@ STG
Definition: AArch64ISelLowering.h:440
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::SystemZ::splitBlockBefore
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1920
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::SystemZII::CompareAndBranch
@ CompareAndBranch
Definition: SystemZInstrInfo.h:142
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:841
llvm::LivePhysRegs::contains
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:108
llvm::SystemZInstrInfo::loadImmediate
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
Definition: SystemZInstrInfo.cpp:1947
SystemZMCTargetDesc.h
SystemZGenInstrInfo
llvm::SystemZII::CCMaskLast
@ CCMaskLast
Definition: SystemZInstrInfo.h:48
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::SystemZInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SystemZInstrInfo.cpp:482
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:725
llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SystemZInstrInfo.cpp:2001
llvm::SystemZ::CCMASK_CMP_EQ
const unsigned CCMASK_CMP_EQ
Definition: SystemZ.h:35
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:514
MachineRegisterInfo.h
llvm::SystemZInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: SystemZInstrInfo.cpp:614
llvm::SystemZII::SimpleBDXLoad
@ SimpleBDXLoad
Definition: SystemZInstrInfo.h:36
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
isSimpleBD12Move
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
Definition: SystemZInstrInfo.cpp:901
isSimpleMove
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
Definition: SystemZInstrInfo.cpp:314
llvm::SystemZInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SystemZInstrInfo.cpp:1978
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::SystemZSubtarget::hasMiscellaneousExtensions3
bool hasMiscellaneousExtensions3() const
Definition: SystemZSubtarget.h:242
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:165
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
SystemZInstrInfo.h
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::SystemZInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:690
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:209
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::SystemZII::CompareAndTrap
@ CompareAndTrap
Definition: SystemZInstrInfo.h:151
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::LivePhysRegs::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Definition: LivePhysRegs.cpp:232
llvm::SystemZInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MBBI) const override
Definition: SystemZInstrInfo.cpp:1344
LiveVariables.h
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::SystemZInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SystemZInstrInfo.cpp:1005
llvm::LiveVariables::replaceKillInstruction
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
Definition: LiveVariables.cpp:752
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::SystemZInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:885
llvm::SystemZInstrInfo::getLoadAndTrap
unsigned getLoadAndTrap(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1928
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:384
llvm::AArch64CC::LE
@ LE
Definition: AArch64BaseInfo.h:268
llvm::SystemZInstrInfo::getBranchInfo
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
Definition: SystemZInstrInfo.cpp:1540
llvm::SystemZ::isHighReg
bool isHighReg(unsigned int Reg)
Definition: SystemZRegisterInfo.h:35
SystemZ.h
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:106
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::SystemZII::Branch
Definition: SystemZInstrInfo.h:112
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1377
llvm::SystemZ::CCMASK_CMP_GT
const unsigned CCMASK_CMP_GT
Definition: SystemZ.h:37
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
BranchProbability.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SystemZ::reverseCCMask
unsigned reverseCCMask(unsigned CCMask)
Definition: SystemZInstrInfo.cpp:1897
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:183
transferMIFlag
static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)
Definition: SystemZInstrInfo.cpp:947
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::SystemZ::CCMASK_CMP_NE
const unsigned CCMASK_CMP_NE
Definition: SystemZ.h:38
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::SystemZII::BranchCG
@ BranchCG
Definition: SystemZInstrInfo.h:93
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::PatchPointOpers::getNumPatchBytes
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:280
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:406
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SystemZ::isImmLL
static bool isImmLL(uint64_t Val)
Definition: SystemZ.h:161
llvm::SystemZ::CCMASK_ANY
const unsigned CCMASK_ANY
Definition: SystemZ.h:31
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
LiveIntervals.h
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:332
llvm::SystemZ::CCMASK_ICMP
const unsigned CCMASK_ICMP
Definition: SystemZ.h:47
llvm::SystemZII::BranchC
@ BranchC
Definition: SystemZInstrInfo.h:85
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:118
llvm::SystemZII::BranchNormal
@ BranchNormal
Definition: SystemZInstrInfo.h:81
llvm::SystemZII::FusedCompareType
FusedCompareType
Definition: SystemZInstrInfo.h:140
VirtRegMap.h
llvm::MachineFunction::CloneMachineInstr
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
Definition: MachineFunction.cpp:385
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::SystemZII::BranchCT
@ BranchCT
Definition: SystemZInstrInfo.h:101
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
MCRegisterInfo.h
llvm::SystemZInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SystemZInstrInfo.cpp:450
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:441
llvm::SystemZII::HasIndex
@ HasIndex
Definition: SystemZInstrInfo.h:39
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:263
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SystemZCallingConventionRegisters::getStackPointerBias
virtual int getStackPointerBias()=0
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::SystemZInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:870
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::SystemZ::CCMASK_CMP_UO
const unsigned CCMASK_CMP_UO
Definition: SystemZ.h:43
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::SystemZInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: SystemZInstrInfo.cpp:358
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:253
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SystemZInstrInfo::SystemZInstrInfo
SystemZInstrInfo(SystemZSubtarget &STI)
Definition: SystemZInstrInfo.cpp:61
SystemZSubtarget.h
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:356
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:205
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::LiveRange::createDeadDef
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
Definition: LiveInterval.cpp:370
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
allOnes
static uint64_t allOnes(unsigned int Count)
Definition: SystemZInstrInfo.cpp:54
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::SystemZII::Has20BitOffset
@ Has20BitOffset
Definition: SystemZInstrInfo.h:38
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:29
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: SystemZInstrInfo.cpp:538
llvm::SystemZ::getTargetMemOpcode
int getTargetMemOpcode(uint16_t Opcode)
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZCallingConventionRegisters
A SystemZ-specific class detailing special use registers particular for calling conventions.
Definition: SystemZRegisterInfo.h:47
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::SystemZII::getAccessSize
static unsigned getAccessSize(unsigned int Flags)
Definition: SystemZInstrInfo.h:54
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:288
llvm::SystemZSubtarget::hasLoadStoreOnCond
bool hasLoadStoreOnCond() const
Definition: SystemZSubtarget.h:143
llvm::SystemZII::CompareAndSibcall
@ CompareAndSibcall
Definition: SystemZInstrInfo.h:148
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:277
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::SystemZInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: SystemZInstrInfo.cpp:725
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:338
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:975
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1308
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:234
llvm::SystemZCallingConventionRegisters::getCallFrameSize
virtual int getCallFrameSize()=0
llvm::SystemZII::BranchCL
@ BranchCL
Definition: SystemZInstrInfo.h:89
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:158
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1021
llvm::MipsISD::LDR
@ LDR
Definition: MipsISelLowering.h:253
llvm::SystemZ::IPM_CC
const unsigned IPM_CC
Definition: SystemZ.h:112
StackMaps.h
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:295
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SystemZInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:1523
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:913
llvm::SystemZInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:678
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1720
llvm::SystemZInstrInfo::getLoadAndTest
unsigned getLoadAndTest(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1669
LiveInterval.h
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
llvm::SystemZII::AsmGoto
@ AsmGoto
Definition: SystemZInstrInfo.h:108
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::SystemZInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: SystemZInstrInfo.cpp:521
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
interpretAndImmediate
static LogicOp interpretAndImmediate(unsigned Opcode)
Definition: SystemZInstrInfo.cpp:924
llvm::SystemZInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:325
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SystemZInstrInfo::getOpcodeForOffset
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
Definition: SystemZInstrInfo.cpp:1635
MachineOperand.h
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:886
llvm::SystemZII::BranchCLG
@ BranchCLG
Definition: SystemZInstrInfo.h:97
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
SlotIndexes.h
llvm::SystemZInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:330
llvm::SystemZInstrInfo::isStackSlotCopy
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
Definition: SystemZInstrInfo.cpp:335
llvm::SystemZII::CCMaskFirst
@ CCMaskFirst
Definition: SystemZInstrInfo.h:47
llvm::SystemZInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SystemZInstrInfo.cpp:778
MachineFunction.h
llvm::SystemZSubtarget::getSpecialRegisters
SystemZCallingConventionRegisters * getSpecialRegisters() const
Definition: SystemZSubtarget.h:94
llvm::MachineInstr::registerDefIsDead
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:1393
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1436
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:620
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:284
llvm::LanaiISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: LanaiISelLowering.h:27
llvm::SystemZInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Definition: SystemZInstrInfo.cpp:277
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:337
llvm::LiveIntervals::getRegUnit
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Definition: LiveIntervals.h:393
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:211
transferDeadCC
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
Definition: SystemZInstrInfo.cpp:939
LivePhysRegs.h