LLVM  16.0.0git
SystemZInstrInfo.cpp
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1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SystemZInstrInfo.h"
15 #include "SystemZ.h"
16 #include "SystemZInstrBuilder.h"
17 #include "SystemZSubtarget.h"
18 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
35 #include "llvm/MC/MCInstrDesc.h"
36 #include "llvm/MC/MCRegisterInfo.h"
41 #include <cassert>
42 #include <cstdint>
43 #include <iterator>
44 
45 using namespace llvm;
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #define GET_INSTRMAP_INFO
49 #include "SystemZGenInstrInfo.inc"
50 
51 #define DEBUG_TYPE "systemz-II"
52 
53 // Return a mask with Count low bits set.
54 static uint64_t allOnes(unsigned int Count) {
55  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
56 }
57 
58 // Pin the vtable to this file.
59 void SystemZInstrInfo::anchor() {}
60 
62  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
63  RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
64  STI(sti) {}
65 
66 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
67 // each having the opcode given by NewOpcode.
68 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
69  unsigned NewOpcode) const {
70  MachineBasicBlock *MBB = MI->getParent();
71  MachineFunction &MF = *MBB->getParent();
72 
73  // Get two load or store instructions. Use the original instruction for one
74  // of them (arbitrarily the second here) and create a clone for the other.
75  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
76  MBB->insert(MI, EarlierMI);
77 
78  // Set up the two 64-bit registers and remember super reg and its flags.
79  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
80  MachineOperand &LowRegOp = MI->getOperand(0);
81  Register Reg128 = LowRegOp.getReg();
82  unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
83  unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
84  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
85  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
86 
87  if (MI->mayStore()) {
88  // Add implicit uses of the super register in case one of the subregs is
89  // undefined. We could track liveness and skip storing an undefined
90  // subreg, but this is hopefully rare (discovered with llvm-stress).
91  // If Reg128 was killed, set kill flag on MI.
92  unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
93  MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
94  MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
95  }
96 
97  // The address in the first (high) instruction is already correct.
98  // Adjust the offset in the second (low) instruction.
99  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
100  MachineOperand &LowOffsetOp = MI->getOperand(2);
101  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
102 
103  // Clear the kill flags on the registers in the first instruction.
104  if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
105  EarlierMI->getOperand(0).setIsKill(false);
106  EarlierMI->getOperand(1).setIsKill(false);
107  EarlierMI->getOperand(3).setIsKill(false);
108 
109  // Set the opcodes.
110  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
111  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
112  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
113 
114  EarlierMI->setDesc(get(HighOpcode));
115  MI->setDesc(get(LowOpcode));
116 }
117 
118 // Split ADJDYNALLOC instruction MI.
119 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
120  MachineBasicBlock *MBB = MI->getParent();
121  MachineFunction &MF = *MBB->getParent();
122  MachineFrameInfo &MFFrame = MF.getFrameInfo();
123  MachineOperand &OffsetMO = MI->getOperand(2);
125 
126  uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
127  Regs->getCallFrameSize() +
128  Regs->getStackPointerBias() +
129  OffsetMO.getImm());
130  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
131  assert(NewOpcode && "No support for huge argument lists yet");
132  MI->setDesc(get(NewOpcode));
133  OffsetMO.setImm(Offset);
134 }
135 
136 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
137 // if the first operand is a low GR32 and HighOpcode if the first operand
138 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
139 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
140 // MI has the same kind of operand as LowOpcode, so needs to be converted
141 // if HighOpcode is used.
142 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
143  unsigned HighOpcode,
144  bool ConvertHigh) const {
145  Register Reg = MI.getOperand(0).getReg();
146  bool IsHigh = SystemZ::isHighReg(Reg);
147  MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
148  if (IsHigh && ConvertHigh)
149  MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
150 }
151 
152 // MI is a three-operand RIE-style pseudo instruction. Replace it with
153 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
154 // followed by HighOpcode or LowOpcode, depending on whether the target
155 // is a high or low GR32.
156 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
157  unsigned LowOpcodeK,
158  unsigned HighOpcode) const {
159  Register DestReg = MI.getOperand(0).getReg();
160  Register SrcReg = MI.getOperand(1).getReg();
161  bool DestIsHigh = SystemZ::isHighReg(DestReg);
162  bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
163  if (!DestIsHigh && !SrcIsHigh)
164  MI.setDesc(get(LowOpcodeK));
165  else {
166  if (DestReg != SrcReg) {
167  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
168  SystemZ::LR, 32, MI.getOperand(1).isKill(),
169  MI.getOperand(1).isUndef());
170  MI.getOperand(1).setReg(DestReg);
171  }
172  MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
173  MI.tieOperands(0, 1);
174  }
175 }
176 
177 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
178 // if the first operand is a low GR32 and HighOpcode if the first operand
179 // is a high GR32.
180 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
181  unsigned HighOpcode) const {
182  Register Reg = MI.getOperand(0).getReg();
183  unsigned Opcode = getOpcodeForOffset(
184  SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
185  MI.getOperand(2).getImm());
186  MI.setDesc(get(Opcode));
187 }
188 
189 // MI is a load-on-condition pseudo instruction with a single register
190 // (source or destination) operand. Replace it with LowOpcode if the
191 // register is a low GR32 and HighOpcode if the register is a high GR32.
192 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
193  unsigned HighOpcode) const {
194  Register Reg = MI.getOperand(0).getReg();
195  unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
196  MI.setDesc(get(Opcode));
197 }
198 
199 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
200 // of one GRX32 into another. Replace it with LowOpcode if both operands
201 // are low registers, otherwise use RISB[LH]G.
202 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
203  unsigned Size) const {
204  MachineInstrBuilder MIB =
205  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
206  MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
207  Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
208 
209  // Keep the remaining operands as-is.
210  for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
211  MIB.add(MO);
212 
213  MI.eraseFromParent();
214 }
215 
216 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
217  MachineBasicBlock *MBB = MI->getParent();
218  MachineFunction &MF = *MBB->getParent();
219  const Register Reg64 = MI->getOperand(0).getReg();
220  const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
221 
222  // EAR can only load the low subregister so us a shift for %a0 to produce
223  // the GR containing %a0 and %a1.
224 
225  // ear <reg>, %a0
226  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
227  .addReg(SystemZ::A0)
229 
230  // sllg <reg>, <reg>, 32
231  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
232  .addReg(Reg64)
233  .addReg(0)
234  .addImm(32);
235 
236  // ear <reg>, %a1
237  BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
238  .addReg(SystemZ::A1);
239 
240  // lg <reg>, 40(<reg>)
241  MI->setDesc(get(SystemZ::LG));
242  MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
243 }
244 
245 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
246 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
247 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
248 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
249 // KillSrc is true if this move is the last use of SrcReg.
251 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
253  const DebugLoc &DL, unsigned DestReg,
254  unsigned SrcReg, unsigned LowLowOpcode,
255  unsigned Size, bool KillSrc,
256  bool UndefSrc) const {
257  unsigned Opcode;
258  bool DestIsHigh = SystemZ::isHighReg(DestReg);
259  bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
260  if (DestIsHigh && SrcIsHigh)
261  Opcode = SystemZ::RISBHH;
262  else if (DestIsHigh && !SrcIsHigh)
263  Opcode = SystemZ::RISBHL;
264  else if (!DestIsHigh && SrcIsHigh)
265  Opcode = SystemZ::RISBLH;
266  else {
267  return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
268  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
269  }
270  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
271  return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
272  .addReg(DestReg, RegState::Undef)
273  .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
274  .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
275 }
276 
278  bool NewMI,
279  unsigned OpIdx1,
280  unsigned OpIdx2) const {
281  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
282  if (NewMI)
283  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
284  return MI;
285  };
286 
287  switch (MI.getOpcode()) {
288  case SystemZ::SELRMux:
289  case SystemZ::SELFHR:
290  case SystemZ::SELR:
291  case SystemZ::SELGR:
292  case SystemZ::LOCRMux:
293  case SystemZ::LOCFHR:
294  case SystemZ::LOCR:
295  case SystemZ::LOCGR: {
296  auto &WorkingMI = cloneIfNew(MI);
297  // Invert condition.
298  unsigned CCValid = WorkingMI.getOperand(3).getImm();
299  unsigned CCMask = WorkingMI.getOperand(4).getImm();
300  WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
301  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
302  OpIdx1, OpIdx2);
303  }
304  default:
305  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
306  }
307 }
308 
309 // If MI is a simple load or store for a frame object, return the register
310 // it loads or stores and set FrameIndex to the index of the frame object.
311 // Return 0 otherwise.
312 //
313 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
314 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
315  unsigned Flag) {
316  const MCInstrDesc &MCID = MI.getDesc();
317  if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
318  MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
319  FrameIndex = MI.getOperand(1).getIndex();
320  return MI.getOperand(0).getReg();
321  }
322  return 0;
323 }
324 
326  int &FrameIndex) const {
328 }
329 
331  int &FrameIndex) const {
333 }
334 
336  int &DestFrameIndex,
337  int &SrcFrameIndex) const {
338  // Check for MVC 0(Length,FI1),0(FI2)
339  const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
340  if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
341  MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
342  MI.getOperand(4).getImm() != 0)
343  return false;
344 
345  // Check that Length covers the full slots.
346  int64_t Length = MI.getOperand(2).getImm();
347  unsigned FI1 = MI.getOperand(0).getIndex();
348  unsigned FI2 = MI.getOperand(3).getIndex();
349  if (MFI.getObjectSize(FI1) != Length ||
350  MFI.getObjectSize(FI2) != Length)
351  return false;
352 
353  DestFrameIndex = FI1;
354  SrcFrameIndex = FI2;
355  return true;
356 }
357 
360  MachineBasicBlock *&FBB,
362  bool AllowModify) const {
363  // Most of the code and comments here are boilerplate.
364 
365  // Start from the bottom of the block and work up, examining the
366  // terminator instructions.
368  while (I != MBB.begin()) {
369  --I;
370  if (I->isDebugInstr())
371  continue;
372 
373  // Working from the bottom, when we see a non-terminator instruction, we're
374  // done.
375  if (!isUnpredicatedTerminator(*I))
376  break;
377 
378  // A terminator that isn't a branch can't easily be handled by this
379  // analysis.
380  if (!I->isBranch())
381  return true;
382 
383  // Can't handle indirect branches.
385  if (!Branch.hasMBBTarget())
386  return true;
387 
388  // Punt on compound branches.
389  if (Branch.Type != SystemZII::BranchNormal)
390  return true;
391 
392  if (Branch.CCMask == SystemZ::CCMASK_ANY) {
393  // Handle unconditional branches.
394  if (!AllowModify) {
395  TBB = Branch.getMBBTarget();
396  continue;
397  }
398 
399  // If the block has any instructions after a JMP, delete them.
400  MBB.erase(std::next(I), MBB.end());
401 
402  Cond.clear();
403  FBB = nullptr;
404 
405  // Delete the JMP if it's equivalent to a fall-through.
406  if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
407  TBB = nullptr;
408  I->eraseFromParent();
409  I = MBB.end();
410  continue;
411  }
412 
413  // TBB is used to indicate the unconditinal destination.
414  TBB = Branch.getMBBTarget();
415  continue;
416  }
417 
418  // Working from the bottom, handle the first conditional branch.
419  if (Cond.empty()) {
420  // FIXME: add X86-style branch swap
421  FBB = TBB;
422  TBB = Branch.getMBBTarget();
423  Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
424  Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
425  continue;
426  }
427 
428  // Handle subsequent conditional branches.
429  assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
430 
431  // Only handle the case where all conditional branches branch to the same
432  // destination.
433  if (TBB != Branch.getMBBTarget())
434  return true;
435 
436  // If the conditions are the same, we can leave them alone.
437  unsigned OldCCValid = Cond[0].getImm();
438  unsigned OldCCMask = Cond[1].getImm();
439  if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
440  continue;
441 
442  // FIXME: Try combining conditions like X86 does. Should be easy on Z!
443  return false;
444  }
445 
446  return false;
447 }
448 
450  int *BytesRemoved) const {
451  assert(!BytesRemoved && "code size not handled");
452 
453  // Most of the code and comments here are boilerplate.
455  unsigned Count = 0;
456 
457  while (I != MBB.begin()) {
458  --I;
459  if (I->isDebugInstr())
460  continue;
461  if (!I->isBranch())
462  break;
463  if (!getBranchInfo(*I).hasMBBTarget())
464  break;
465  // Remove the branch.
466  I->eraseFromParent();
467  I = MBB.end();
468  ++Count;
469  }
470 
471  return Count;
472 }
473 
476  assert(Cond.size() == 2 && "Invalid condition");
477  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
478  return false;
479 }
480 
483  MachineBasicBlock *FBB,
485  const DebugLoc &DL,
486  int *BytesAdded) const {
487  // In this function we output 32-bit branches, which should always
488  // have enough range. They can be shortened and relaxed by later code
489  // in the pipeline, if desired.
490 
491  // Shouldn't be a fall through.
492  assert(TBB && "insertBranch must not be told to insert a fallthrough");
493  assert((Cond.size() == 2 || Cond.size() == 0) &&
494  "SystemZ branch conditions have one component!");
495  assert(!BytesAdded && "code size not handled");
496 
497  if (Cond.empty()) {
498  // Unconditional branch?
499  assert(!FBB && "Unconditional branch with multiple successors!");
500  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
501  return 1;
502  }
503 
504  // Conditional branch.
505  unsigned Count = 0;
506  unsigned CCValid = Cond[0].getImm();
507  unsigned CCMask = Cond[1].getImm();
508  BuildMI(&MBB, DL, get(SystemZ::BRC))
509  .addImm(CCValid).addImm(CCMask).addMBB(TBB);
510  ++Count;
511 
512  if (FBB) {
513  // Two-way Conditional branch. Insert the second branch.
514  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
515  ++Count;
516  }
517  return Count;
518 }
519 
521  Register &SrcReg2, int64_t &Mask,
522  int64_t &Value) const {
523  assert(MI.isCompare() && "Caller should have checked for a comparison");
524 
525  if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
526  MI.getOperand(1).isImm()) {
527  SrcReg = MI.getOperand(0).getReg();
528  SrcReg2 = 0;
529  Value = MI.getOperand(1).getImm();
530  Mask = ~0;
531  return true;
532  }
533 
534  return false;
535 }
536 
539  Register DstReg, Register TrueReg,
540  Register FalseReg, int &CondCycles,
541  int &TrueCycles,
542  int &FalseCycles) const {
543  // Not all subtargets have LOCR instructions.
544  if (!STI.hasLoadStoreOnCond())
545  return false;
546  if (Pred.size() != 2)
547  return false;
548 
549  // Check register classes.
551  const TargetRegisterClass *RC =
552  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
553  if (!RC)
554  return false;
555 
556  // We have LOCR instructions for 32 and 64 bit general purpose registers.
557  if ((STI.hasLoadStoreOnCond2() &&
558  SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
559  SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
560  SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
561  CondCycles = 2;
562  TrueCycles = 2;
563  FalseCycles = 2;
564  return true;
565  }
566 
567  // Can't do anything else.
568  return false;
569 }
570 
573  const DebugLoc &DL, Register DstReg,
575  Register TrueReg,
576  Register FalseReg) const {
578  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
579 
580  assert(Pred.size() == 2 && "Invalid condition");
581  unsigned CCValid = Pred[0].getImm();
582  unsigned CCMask = Pred[1].getImm();
583 
584  unsigned Opc;
585  if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
586  if (STI.hasMiscellaneousExtensions3())
587  Opc = SystemZ::SELRMux;
588  else if (STI.hasLoadStoreOnCond2())
589  Opc = SystemZ::LOCRMux;
590  else {
591  Opc = SystemZ::LOCR;
592  MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
593  Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
594  Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
595  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
596  BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
597  TrueReg = TReg;
598  FalseReg = FReg;
599  }
600  } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
601  if (STI.hasMiscellaneousExtensions3())
602  Opc = SystemZ::SELGR;
603  else
604  Opc = SystemZ::LOCGR;
605  } else
606  llvm_unreachable("Invalid register class");
607 
608  BuildMI(MBB, I, DL, get(Opc), DstReg)
609  .addReg(FalseReg).addReg(TrueReg)
610  .addImm(CCValid).addImm(CCMask);
611 }
612 
614  Register Reg,
615  MachineRegisterInfo *MRI) const {
616  unsigned DefOpc = DefMI.getOpcode();
617  if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
618  DefOpc != SystemZ::LGHI)
619  return false;
620  if (DefMI.getOperand(0).getReg() != Reg)
621  return false;
622  int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
623 
624  unsigned UseOpc = UseMI.getOpcode();
625  unsigned NewUseOpc;
626  unsigned UseIdx;
627  int CommuteIdx = -1;
628  bool TieOps = false;
629  switch (UseOpc) {
630  case SystemZ::SELRMux:
631  TieOps = true;
632  [[fallthrough]];
633  case SystemZ::LOCRMux:
634  if (!STI.hasLoadStoreOnCond2())
635  return false;
636  NewUseOpc = SystemZ::LOCHIMux;
637  if (UseMI.getOperand(2).getReg() == Reg)
638  UseIdx = 2;
639  else if (UseMI.getOperand(1).getReg() == Reg)
640  UseIdx = 2, CommuteIdx = 1;
641  else
642  return false;
643  break;
644  case SystemZ::SELGR:
645  TieOps = true;
646  [[fallthrough]];
647  case SystemZ::LOCGR:
648  if (!STI.hasLoadStoreOnCond2())
649  return false;
650  NewUseOpc = SystemZ::LOCGHI;
651  if (UseMI.getOperand(2).getReg() == Reg)
652  UseIdx = 2;
653  else if (UseMI.getOperand(1).getReg() == Reg)
654  UseIdx = 2, CommuteIdx = 1;
655  else
656  return false;
657  break;
658  default:
659  return false;
660  }
661 
662  if (CommuteIdx != -1)
663  if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
664  return false;
665 
666  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
667  UseMI.setDesc(get(NewUseOpc));
668  if (TieOps)
669  UseMI.tieOperands(0, 1);
670  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
671  if (DeleteDef)
672  DefMI.eraseFromParent();
673 
674  return true;
675 }
676 
678  unsigned Opcode = MI.getOpcode();
679  if (Opcode == SystemZ::Return ||
680  Opcode == SystemZ::Return_XPLINK ||
681  Opcode == SystemZ::Trap ||
682  Opcode == SystemZ::CallJG ||
683  Opcode == SystemZ::CallBR)
684  return true;
685  return false;
686 }
687 
690  unsigned NumCycles, unsigned ExtraPredCycles,
691  BranchProbability Probability) const {
692  // Avoid using conditional returns at the end of a loop (since then
693  // we'd need to emit an unconditional branch to the beginning anyway,
694  // making the loop body longer). This doesn't apply for low-probability
695  // loops (eg. compare-and-swap retry), so just decide based on branch
696  // probability instead of looping structure.
697  // However, since Compare and Trap instructions cost the same as a regular
698  // Compare instruction, we should allow the if conversion to convert this
699  // into a Conditional Compare regardless of the branch probability.
700  if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
701  MBB.succ_empty() && Probability < BranchProbability(1, 8))
702  return false;
703  // For now only convert single instructions.
704  return NumCycles == 1;
705 }
706 
709  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
710  MachineBasicBlock &FMBB,
711  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
712  BranchProbability Probability) const {
713  // For now avoid converting mutually-exclusive cases.
714  return false;
715 }
716 
719  BranchProbability Probability) const {
720  // For now only duplicate single instructions.
721  return NumCycles == 1;
722 }
723 
726  assert(Pred.size() == 2 && "Invalid condition");
727  unsigned CCValid = Pred[0].getImm();
728  unsigned CCMask = Pred[1].getImm();
729  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
730  unsigned Opcode = MI.getOpcode();
731  if (Opcode == SystemZ::Trap) {
732  MI.setDesc(get(SystemZ::CondTrap));
733  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
734  .addImm(CCValid).addImm(CCMask)
736  return true;
737  }
738  if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
739  MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
740  : SystemZ::CondReturn_XPLINK));
741  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
742  .addImm(CCValid)
743  .addImm(CCMask)
745  return true;
746  }
747  if (Opcode == SystemZ::CallJG) {
748  MachineOperand FirstOp = MI.getOperand(0);
749  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
750  MI.removeOperand(1);
751  MI.removeOperand(0);
752  MI.setDesc(get(SystemZ::CallBRCL));
753  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
754  .addImm(CCValid)
755  .addImm(CCMask)
756  .add(FirstOp)
757  .addRegMask(RegMask)
759  return true;
760  }
761  if (Opcode == SystemZ::CallBR) {
762  MachineOperand Target = MI.getOperand(0);
763  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
764  MI.removeOperand(1);
765  MI.removeOperand(0);
766  MI.setDesc(get(SystemZ::CallBCR));
767  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
768  .addImm(CCValid).addImm(CCMask)
769  .add(Target)
770  .addRegMask(RegMask)
772  return true;
773  }
774  return false;
775 }
776 
779  const DebugLoc &DL, MCRegister DestReg,
780  MCRegister SrcReg, bool KillSrc) const {
781  // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
782  // super register in case one of the subregs is undefined.
783  // This handles ADDR128 too.
784  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
785  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
786  RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
787  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
788  .addReg(SrcReg, RegState::Implicit);
789  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
790  RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
791  MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
792  .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
793  return;
794  }
795 
796  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
797  emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
798  false);
799  return;
800  }
801 
802  // Move 128-bit floating-point values between VR128 and FP128.
803  if (SystemZ::VR128BitRegClass.contains(DestReg) &&
804  SystemZ::FP128BitRegClass.contains(SrcReg)) {
805  MCRegister SrcRegHi =
806  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
807  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
808  MCRegister SrcRegLo =
809  RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
810  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
811 
812  BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
813  .addReg(SrcRegHi, getKillRegState(KillSrc))
814  .addReg(SrcRegLo, getKillRegState(KillSrc));
815  return;
816  }
817  if (SystemZ::FP128BitRegClass.contains(DestReg) &&
818  SystemZ::VR128BitRegClass.contains(SrcReg)) {
819  MCRegister DestRegHi =
820  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
821  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
822  MCRegister DestRegLo =
823  RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
824  SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
825 
826  if (DestRegHi != SrcReg)
827  copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
828  BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
829  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
830  return;
831  }
832 
833  // Move CC value from a GR32.
834  if (DestReg == SystemZ::CC) {
835  unsigned Opcode =
836  SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
837  BuildMI(MBB, MBBI, DL, get(Opcode))
838  .addReg(SrcReg, getKillRegState(KillSrc))
839  .addImm(3 << (SystemZ::IPM_CC - 16));
840  return;
841  }
842 
843  // Everything else needs only one instruction.
844  unsigned Opcode;
845  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
846  Opcode = SystemZ::LGR;
847  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
848  // For z13 we prefer LDR over LER to avoid partial register dependencies.
849  Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
850  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
851  Opcode = SystemZ::LDR;
852  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
853  Opcode = SystemZ::LXR;
854  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
855  Opcode = SystemZ::VLR32;
856  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
857  Opcode = SystemZ::VLR64;
858  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
859  Opcode = SystemZ::VLR;
860  else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
861  Opcode = SystemZ::CPYA;
862  else
863  llvm_unreachable("Impossible reg-to-reg copy");
864 
865  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
866  .addReg(SrcReg, getKillRegState(KillSrc));
867 }
868 
871  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
872  const TargetRegisterInfo *TRI) const {
873  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
874 
875  // Callers may expect a single instruction, so keep 128-bit moves
876  // together for now and lower them after register allocation.
877  unsigned LoadOpcode, StoreOpcode;
878  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
879  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
880  .addReg(SrcReg, getKillRegState(isKill)),
881  FrameIdx);
882 }
883 
886  int FrameIdx, const TargetRegisterClass *RC,
887  const TargetRegisterInfo *TRI) const {
888  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
889 
890  // Callers may expect a single instruction, so keep 128-bit moves
891  // together for now and lower them after register allocation.
892  unsigned LoadOpcode, StoreOpcode;
893  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
894  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
895  FrameIdx);
896 }
897 
898 // Return true if MI is a simple load or store with a 12-bit displacement
899 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
900 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
901  const MCInstrDesc &MCID = MI->getDesc();
902  return ((MCID.TSFlags & Flag) &&
903  isUInt<12>(MI->getOperand(2).getImm()) &&
904  MI->getOperand(3).getReg() == 0);
905 }
906 
907 namespace {
908 
909 struct LogicOp {
910  LogicOp() = default;
911  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
912  : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
913 
914  explicit operator bool() const { return RegSize; }
915 
916  unsigned RegSize = 0;
917  unsigned ImmLSB = 0;
918  unsigned ImmSize = 0;
919 };
920 
921 } // end anonymous namespace
922 
923 static LogicOp interpretAndImmediate(unsigned Opcode) {
924  switch (Opcode) {
925  case SystemZ::NILMux: return LogicOp(32, 0, 16);
926  case SystemZ::NIHMux: return LogicOp(32, 16, 16);
927  case SystemZ::NILL64: return LogicOp(64, 0, 16);
928  case SystemZ::NILH64: return LogicOp(64, 16, 16);
929  case SystemZ::NIHL64: return LogicOp(64, 32, 16);
930  case SystemZ::NIHH64: return LogicOp(64, 48, 16);
931  case SystemZ::NIFMux: return LogicOp(32, 0, 32);
932  case SystemZ::NILF64: return LogicOp(64, 0, 32);
933  case SystemZ::NIHF64: return LogicOp(64, 32, 32);
934  default: return LogicOp();
935  }
936 }
937 
938 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
939  if (OldMI->registerDefIsDead(SystemZ::CC)) {
941  if (CCDef != nullptr)
942  CCDef->setIsDead(true);
943  }
944 }
945 
946 static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
948  if (OldMI->getFlag(Flag))
949  NewMI->setFlag(Flag);
950 }
951 
952 MachineInstr *
954  LiveIntervals *LIS) const {
955  MachineBasicBlock *MBB = MI.getParent();
956 
957  // Try to convert an AND into an RISBG-type instruction.
958  // TODO: It might be beneficial to select RISBG and shorten to AND instead.
959  if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
960  uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
961  // AND IMMEDIATE leaves the other bits of the register unchanged.
962  Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
963  unsigned Start, End;
964  if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
965  unsigned NewOpcode;
966  if (And.RegSize == 64) {
967  NewOpcode = SystemZ::RISBG;
968  // Prefer RISBGN if available, since it does not clobber CC.
969  if (STI.hasMiscellaneousExtensions())
970  NewOpcode = SystemZ::RISBGN;
971  } else {
972  NewOpcode = SystemZ::RISBMux;
973  Start &= 31;
974  End &= 31;
975  }
976  MachineOperand &Dest = MI.getOperand(0);
977  MachineOperand &Src = MI.getOperand(1);
978  MachineInstrBuilder MIB =
979  BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
980  .add(Dest)
981  .addReg(0)
982  .addReg(Src.getReg(), getKillRegState(Src.isKill()),
983  Src.getSubReg())
984  .addImm(Start)
985  .addImm(End + 128)
986  .addImm(0);
987  if (LV) {
988  unsigned NumOps = MI.getNumOperands();
989  for (unsigned I = 1; I < NumOps; ++I) {
990  MachineOperand &Op = MI.getOperand(I);
991  if (Op.isReg() && Op.isKill())
992  LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
993  }
994  }
995  if (LIS)
996  LIS->ReplaceMachineInstrInMaps(MI, *MIB);
997  transferDeadCC(&MI, MIB);
998  return MIB;
999  }
1000  }
1001  return nullptr;
1002 }
1003 
1007  LiveIntervals *LIS, VirtRegMap *VRM) const {
1010  const MachineFrameInfo &MFI = MF.getFrameInfo();
1011  unsigned Size = MFI.getObjectSize(FrameIndex);
1012  unsigned Opcode = MI.getOpcode();
1013 
1014  // Check CC liveness if new instruction introduces a dead def of CC.
1016  SlotIndex MISlot = SlotIndex();
1017  LiveRange *CCLiveRange = nullptr;
1018  bool CCLiveAtMI = true;
1019  if (LIS) {
1020  MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1021  CCLiveRange = &LIS->getRegUnit(*CCUnit);
1022  CCLiveAtMI = CCLiveRange->liveAt(MISlot);
1023  }
1024  ++CCUnit;
1025  assert(!CCUnit.isValid() && "CC only has one reg unit.");
1026 
1027  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1028  if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1029  isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1030  // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1031  MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1032  MI.getDebugLoc(), get(SystemZ::AGSI))
1034  .addImm(0)
1035  .addImm(MI.getOperand(2).getImm());
1036  BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1037  CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1038  return BuiltMI;
1039  }
1040  return nullptr;
1041  }
1042 
1043  // All other cases require a single operand.
1044  if (Ops.size() != 1)
1045  return nullptr;
1046 
1047  unsigned OpNum = Ops[0];
1048  assert(Size * 8 ==
1050  .getRegClass(MI.getOperand(OpNum).getReg())) &&
1051  "Invalid size combination");
1052 
1053  if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1054  isInt<8>(MI.getOperand(2).getImm())) {
1055  // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1056  Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1057  MachineInstr *BuiltMI =
1058  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1060  .addImm(0)
1061  .addImm(MI.getOperand(2).getImm());
1062  transferDeadCC(&MI, BuiltMI);
1064  return BuiltMI;
1065  }
1066 
1067  if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1068  isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1069  (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1070  isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1071  // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1072  Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1073  MachineInstr *BuiltMI =
1074  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1076  .addImm(0)
1077  .addImm((int8_t)MI.getOperand(2).getImm());
1078  transferDeadCC(&MI, BuiltMI);
1079  return BuiltMI;
1080  }
1081 
1082  if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1083  isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1084  (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1085  isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1086  // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1087  Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1088  MachineInstr *BuiltMI =
1089  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1091  .addImm(0)
1092  .addImm((int8_t)-MI.getOperand(2).getImm());
1093  transferDeadCC(&MI, BuiltMI);
1094  return BuiltMI;
1095  }
1096 
1097  unsigned MemImmOpc = 0;
1098  switch (Opcode) {
1099  case SystemZ::LHIMux:
1100  case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;
1101  case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;
1102  case SystemZ::CHIMux:
1103  case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;
1104  case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;
1105  case SystemZ::CLFIMux:
1106  case SystemZ::CLFI:
1107  if (isUInt<16>(MI.getOperand(1).getImm()))
1108  MemImmOpc = SystemZ::CLFHSI;
1109  break;
1110  case SystemZ::CLGFI:
1111  if (isUInt<16>(MI.getOperand(1).getImm()))
1112  MemImmOpc = SystemZ::CLGHSI;
1113  break;
1114  default: break;
1115  }
1116  if (MemImmOpc)
1117  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1118  get(MemImmOpc))
1120  .addImm(0)
1121  .addImm(MI.getOperand(1).getImm());
1122 
1123  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1124  bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1125  bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1126  // If we're spilling the destination of an LDGR or LGDR, store the
1127  // source register instead.
1128  if (OpNum == 0) {
1129  unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1130  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1131  get(StoreOpcode))
1132  .add(MI.getOperand(1))
1134  .addImm(0)
1135  .addReg(0);
1136  }
1137  // If we're spilling the source of an LDGR or LGDR, load the
1138  // destination register instead.
1139  if (OpNum == 1) {
1140  unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1141  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1142  get(LoadOpcode))
1143  .add(MI.getOperand(0))
1145  .addImm(0)
1146  .addReg(0);
1147  }
1148  }
1149 
1150  // Look for cases where the source of a simple store or the destination
1151  // of a simple load is being spilled. Try to use MVC instead.
1152  //
1153  // Although MVC is in practice a fast choice in these cases, it is still
1154  // logically a bytewise copy. This means that we cannot use it if the
1155  // load or store is volatile. We also wouldn't be able to use MVC if
1156  // the two memories partially overlap, but that case cannot occur here,
1157  // because we know that one of the memories is a full frame index.
1158  //
1159  // For performance reasons, we also want to avoid using MVC if the addresses
1160  // might be equal. We don't worry about that case here, because spill slot
1161  // coloring happens later, and because we have special code to remove
1162  // MVCs that turn out to be redundant.
1163  if (OpNum == 0 && MI.hasOneMemOperand()) {
1164  MachineMemOperand *MMO = *MI.memoperands_begin();
1165  if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1166  // Handle conversion of loads.
1168  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1169  get(SystemZ::MVC))
1171  .addImm(0)
1172  .addImm(Size)
1173  .add(MI.getOperand(1))
1174  .addImm(MI.getOperand(2).getImm())
1175  .addMemOperand(MMO);
1176  }
1177  // Handle conversion of stores.
1179  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1180  get(SystemZ::MVC))
1181  .add(MI.getOperand(1))
1182  .addImm(MI.getOperand(2).getImm())
1183  .addImm(Size)
1185  .addImm(0)
1186  .addMemOperand(MMO);
1187  }
1188  }
1189  }
1190 
1191  // If the spilled operand is the final one or the instruction is
1192  // commutable, try to change <INSN>R into <INSN>. Don't introduce a def of
1193  // CC if it is live and MI does not define it.
1194  unsigned NumOps = MI.getNumExplicitOperands();
1195  int MemOpcode = SystemZ::getMemOpcode(Opcode);
1196  if (MemOpcode == -1 ||
1197  (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) &&
1198  get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)))
1199  return nullptr;
1200 
1201  // Check if all other vregs have a usable allocation in the case of vector
1202  // to FP conversion.
1203  const MCInstrDesc &MCID = MI.getDesc();
1204  for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
1205  const MCOperandInfo &MCOI = MCID.OpInfo[I];
1206  if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
1207  continue;
1208  const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
1209  if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1210  Register Reg = MI.getOperand(I).getReg();
1212  ? (VRM ? Register(VRM->getPhys(Reg)) : Register())
1213  : Reg;
1214  if (!PhysReg ||
1215  !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
1216  SystemZ::FP64BitRegClass.contains(PhysReg) ||
1217  SystemZ::VF128BitRegClass.contains(PhysReg)))
1218  return nullptr;
1219  }
1220  }
1221  // Fused multiply and add/sub need to have the same dst and accumulator reg.
1222  bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1223  Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1224  if (FusedFPOp) {
1225  Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
1226  Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
1227  if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1228  return nullptr;
1229  }
1230 
1231  // Try to swap compare operands if possible.
1232  bool NeedsCommute = false;
1233  if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1234  MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1235  MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1236  MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1237  OpNum == 0 && prepareCompareSwapOperands(MI))
1238  NeedsCommute = true;
1239 
1240  bool CCOperands = false;
1241  if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1242  MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1243  assert(MI.getNumOperands() == 6 && NumOps == 5 &&
1244  "LOCR/SELR instruction operands corrupt?");
1245  NumOps -= 2;
1246  CCOperands = true;
1247  }
1248 
1249  // See if this is a 3-address instruction that is convertible to 2-address
1250  // and suitable for folding below. Only try this with virtual registers
1251  // and a provided VRM (during regalloc).
1252  if (NumOps == 3 && SystemZ::getTargetMemOpcode(MemOpcode) != -1) {
1253  if (VRM == nullptr)
1254  return nullptr;
1255  else {
1256  Register DstReg = MI.getOperand(0).getReg();
1257  Register DstPhys =
1258  (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
1259  : DstReg);
1260  Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1261  : ((OpNum == 1 && MI.isCommutable())
1262  ? MI.getOperand(2).getReg()
1263  : Register()));
1264  if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
1265  Register::isVirtualRegister(SrcReg) &&
1266  DstPhys == VRM->getPhys(SrcReg))
1267  NeedsCommute = (OpNum == 1);
1268  else
1269  return nullptr;
1270  }
1271  }
1272 
1273  if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1274  const MCInstrDesc &MemDesc = get(MemOpcode);
1275  uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1276  assert(AccessBytes != 0 && "Size of access should be known");
1277  assert(AccessBytes <= Size && "Access outside the frame index");
1278  uint64_t Offset = Size - AccessBytes;
1279  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1280  MI.getDebugLoc(), get(MemOpcode));
1281  if (MI.isCompare()) {
1282  assert(NumOps == 2 && "Expected 2 register operands for a compare.");
1283  MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
1284  }
1285  else if (FusedFPOp) {
1286  MIB.add(MI.getOperand(0));
1287  MIB.add(MI.getOperand(3));
1288  MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
1289  }
1290  else {
1291  MIB.add(MI.getOperand(0));
1292  if (NeedsCommute)
1293  MIB.add(MI.getOperand(2));
1294  else
1295  for (unsigned I = 1; I < OpNum; ++I)
1296  MIB.add(MI.getOperand(I));
1297  }
1298  MIB.addFrameIndex(FrameIndex).addImm(Offset);
1299  if (MemDesc.TSFlags & SystemZII::HasIndex)
1300  MIB.addReg(0);
1301  if (CCOperands) {
1302  unsigned CCValid = MI.getOperand(NumOps).getImm();
1303  unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
1304  MIB.addImm(CCValid);
1305  MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
1306  }
1307  if (MIB->definesRegister(SystemZ::CC) &&
1308  (!MI.definesRegister(SystemZ::CC) ||
1309  MI.registerDefIsDead(SystemZ::CC))) {
1311  if (CCLiveRange)
1312  CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator());
1313  }
1314  // Constrain the register classes if converted from a vector opcode. The
1315  // allocated regs are in an FP reg-class per previous check above.
1316  for (const MachineOperand &MO : MIB->operands())
1317  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1318  Register Reg = MO.getReg();
1319  if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1320  MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1321  else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1322  MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1323  else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1324  MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
1325  }
1326 
1327  transferDeadCC(&MI, MIB);
1330  return MIB;
1331  }
1332 
1333  return nullptr;
1334 }
1335 
1338  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1339  LiveIntervals *LIS) const {
1340  return nullptr;
1341 }
1342 
1344  switch (MI.getOpcode()) {
1345  case SystemZ::L128:
1346  splitMove(MI, SystemZ::LG);
1347  return true;
1348 
1349  case SystemZ::ST128:
1350  splitMove(MI, SystemZ::STG);
1351  return true;
1352 
1353  case SystemZ::LX:
1354  splitMove(MI, SystemZ::LD);
1355  return true;
1356 
1357  case SystemZ::STX:
1358  splitMove(MI, SystemZ::STD);
1359  return true;
1360 
1361  case SystemZ::LBMux:
1362  expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1363  return true;
1364 
1365  case SystemZ::LHMux:
1366  expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1367  return true;
1368 
1369  case SystemZ::LLCRMux:
1370  expandZExtPseudo(MI, SystemZ::LLCR, 8);
1371  return true;
1372 
1373  case SystemZ::LLHRMux:
1374  expandZExtPseudo(MI, SystemZ::LLHR, 16);
1375  return true;
1376 
1377  case SystemZ::LLCMux:
1378  expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1379  return true;
1380 
1381  case SystemZ::LLHMux:
1382  expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1383  return true;
1384 
1385  case SystemZ::LMux:
1386  expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1387  return true;
1388 
1389  case SystemZ::LOCMux:
1390  expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1391  return true;
1392 
1393  case SystemZ::LOCHIMux:
1394  expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1395  return true;
1396 
1397  case SystemZ::STCMux:
1398  expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1399  return true;
1400 
1401  case SystemZ::STHMux:
1402  expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1403  return true;
1404 
1405  case SystemZ::STMux:
1406  expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1407  return true;
1408 
1409  case SystemZ::STOCMux:
1410  expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1411  return true;
1412 
1413  case SystemZ::LHIMux:
1414  expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1415  return true;
1416 
1417  case SystemZ::IIFMux:
1418  expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1419  return true;
1420 
1421  case SystemZ::IILMux:
1422  expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1423  return true;
1424 
1425  case SystemZ::IIHMux:
1426  expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1427  return true;
1428 
1429  case SystemZ::NIFMux:
1430  expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1431  return true;
1432 
1433  case SystemZ::NILMux:
1434  expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1435  return true;
1436 
1437  case SystemZ::NIHMux:
1438  expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1439  return true;
1440 
1441  case SystemZ::OIFMux:
1442  expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1443  return true;
1444 
1445  case SystemZ::OILMux:
1446  expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1447  return true;
1448 
1449  case SystemZ::OIHMux:
1450  expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1451  return true;
1452 
1453  case SystemZ::XIFMux:
1454  expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1455  return true;
1456 
1457  case SystemZ::TMLMux:
1458  expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1459  return true;
1460 
1461  case SystemZ::TMHMux:
1462  expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1463  return true;
1464 
1465  case SystemZ::AHIMux:
1466  expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1467  return true;
1468 
1469  case SystemZ::AHIMuxK:
1470  expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1471  return true;
1472 
1473  case SystemZ::AFIMux:
1474  expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1475  return true;
1476 
1477  case SystemZ::CHIMux:
1478  expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1479  return true;
1480 
1481  case SystemZ::CFIMux:
1482  expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1483  return true;
1484 
1485  case SystemZ::CLFIMux:
1486  expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1487  return true;
1488 
1489  case SystemZ::CMux:
1490  expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1491  return true;
1492 
1493  case SystemZ::CLMux:
1494  expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1495  return true;
1496 
1497  case SystemZ::RISBMux: {
1498  bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1499  bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1500  if (SrcIsHigh == DestIsHigh)
1501  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1502  else {
1503  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1504  MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1505  }
1506  return true;
1507  }
1508 
1509  case SystemZ::ADJDYNALLOC:
1510  splitAdjDynAlloc(MI);
1511  return true;
1512 
1513  case TargetOpcode::LOAD_STACK_GUARD:
1514  expandLoadStackGuard(&MI);
1515  return true;
1516 
1517  default:
1518  return false;
1519  }
1520 }
1521 
1523  if (MI.isInlineAsm()) {
1524  const MachineFunction *MF = MI.getParent()->getParent();
1525  const char *AsmStr = MI.getOperand(0).getSymbolName();
1526  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1527  }
1528  else if (MI.getOpcode() == SystemZ::PATCHPOINT)
1529  return PatchPointOpers(&MI).getNumPatchBytes();
1530  else if (MI.getOpcode() == SystemZ::STACKMAP)
1531  return MI.getOperand(1).getImm();
1532  else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
1533  return 6;
1534 
1535  return MI.getDesc().getSize();
1536 }
1537 
1540  switch (MI.getOpcode()) {
1541  case SystemZ::BR:
1542  case SystemZ::BI:
1543  case SystemZ::J:
1544  case SystemZ::JG:
1546  SystemZ::CCMASK_ANY, &MI.getOperand(0));
1547 
1548  case SystemZ::BRC:
1549  case SystemZ::BRCL:
1550  return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1551  MI.getOperand(1).getImm(), &MI.getOperand(2));
1552 
1553  case SystemZ::BRCT:
1554  case SystemZ::BRCTH:
1556  SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1557 
1558  case SystemZ::BRCTG:
1560  SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1561 
1562  case SystemZ::CIJ:
1563  case SystemZ::CRJ:
1565  MI.getOperand(2).getImm(), &MI.getOperand(3));
1566 
1567  case SystemZ::CLIJ:
1568  case SystemZ::CLRJ:
1570  MI.getOperand(2).getImm(), &MI.getOperand(3));
1571 
1572  case SystemZ::CGIJ:
1573  case SystemZ::CGRJ:
1575  MI.getOperand(2).getImm(), &MI.getOperand(3));
1576 
1577  case SystemZ::CLGIJ:
1578  case SystemZ::CLGRJ:
1580  MI.getOperand(2).getImm(), &MI.getOperand(3));
1581 
1582  case SystemZ::INLINEASM_BR:
1583  // Don't try to analyze asm goto, so pass nullptr as branch target argument.
1584  return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);
1585 
1586  default:
1587  llvm_unreachable("Unrecognized branch opcode");
1588  }
1589 }
1590 
1592  unsigned &LoadOpcode,
1593  unsigned &StoreOpcode) const {
1594  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1595  LoadOpcode = SystemZ::L;
1596  StoreOpcode = SystemZ::ST;
1597  } else if (RC == &SystemZ::GRH32BitRegClass) {
1598  LoadOpcode = SystemZ::LFH;
1599  StoreOpcode = SystemZ::STFH;
1600  } else if (RC == &SystemZ::GRX32BitRegClass) {
1601  LoadOpcode = SystemZ::LMux;
1602  StoreOpcode = SystemZ::STMux;
1603  } else if (RC == &SystemZ::GR64BitRegClass ||
1604  RC == &SystemZ::ADDR64BitRegClass) {
1605  LoadOpcode = SystemZ::LG;
1606  StoreOpcode = SystemZ::STG;
1607  } else if (RC == &SystemZ::GR128BitRegClass ||
1608  RC == &SystemZ::ADDR128BitRegClass) {
1609  LoadOpcode = SystemZ::L128;
1610  StoreOpcode = SystemZ::ST128;
1611  } else if (RC == &SystemZ::FP32BitRegClass) {
1612  LoadOpcode = SystemZ::LE;
1613  StoreOpcode = SystemZ::STE;
1614  } else if (RC == &SystemZ::FP64BitRegClass) {
1615  LoadOpcode = SystemZ::LD;
1616  StoreOpcode = SystemZ::STD;
1617  } else if (RC == &SystemZ::FP128BitRegClass) {
1618  LoadOpcode = SystemZ::LX;
1619  StoreOpcode = SystemZ::STX;
1620  } else if (RC == &SystemZ::VR32BitRegClass) {
1621  LoadOpcode = SystemZ::VL32;
1622  StoreOpcode = SystemZ::VST32;
1623  } else if (RC == &SystemZ::VR64BitRegClass) {
1624  LoadOpcode = SystemZ::VL64;
1625  StoreOpcode = SystemZ::VST64;
1626  } else if (RC == &SystemZ::VF128BitRegClass ||
1627  RC == &SystemZ::VR128BitRegClass) {
1628  LoadOpcode = SystemZ::VL;
1629  StoreOpcode = SystemZ::VST;
1630  } else
1631  llvm_unreachable("Unsupported regclass to load or store");
1632 }
1633 
1634 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1635  int64_t Offset,
1636  const MachineInstr *MI) const {
1637  const MCInstrDesc &MCID = get(Opcode);
1638  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1639  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1640  // Get the instruction to use for unsigned 12-bit displacements.
1641  int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1642  if (Disp12Opcode >= 0)
1643  return Disp12Opcode;
1644 
1645  // All address-related instructions can use unsigned 12-bit
1646  // displacements.
1647  return Opcode;
1648  }
1649  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1650  // Get the instruction to use for signed 20-bit displacements.
1651  int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1652  if (Disp20Opcode >= 0)
1653  return Disp20Opcode;
1654 
1655  // Check whether Opcode allows signed 20-bit displacements.
1657  return Opcode;
1658 
1659  // If a VR32/VR64 reg ended up in an FP register, use the FP opcode.
1660  if (MI && MI->getOperand(0).isReg()) {
1661  Register Reg = MI->getOperand(0).getReg();
1662  if (Reg.isPhysical() && SystemZMC::getFirstReg(Reg) < 16) {
1663  switch (Opcode) {
1664  case SystemZ::VL32:
1665  return SystemZ::LEY;
1666  case SystemZ::VST32:
1667  return SystemZ::STEY;
1668  case SystemZ::VL64:
1669  return SystemZ::LDY;
1670  case SystemZ::VST64:
1671  return SystemZ::STDY;
1672  default: break;
1673  }
1674  }
1675  }
1676  }
1677  return 0;
1678 }
1679 
1680 bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
1681  const MCInstrDesc &MCID = get(Opcode);
1683  return SystemZ::getDisp12Opcode(Opcode) >= 0;
1684  return SystemZ::getDisp20Opcode(Opcode) >= 0;
1685 }
1686 
1687 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1688  switch (Opcode) {
1689  case SystemZ::L: return SystemZ::LT;
1690  case SystemZ::LY: return SystemZ::LT;
1691  case SystemZ::LG: return SystemZ::LTG;
1692  case SystemZ::LGF: return SystemZ::LTGF;
1693  case SystemZ::LR: return SystemZ::LTR;
1694  case SystemZ::LGFR: return SystemZ::LTGFR;
1695  case SystemZ::LGR: return SystemZ::LTGR;
1696  case SystemZ::LER: return SystemZ::LTEBR;
1697  case SystemZ::LDR: return SystemZ::LTDBR;
1698  case SystemZ::LXR: return SystemZ::LTXBR;
1699  case SystemZ::LCDFR: return SystemZ::LCDBR;
1700  case SystemZ::LPDFR: return SystemZ::LPDBR;
1701  case SystemZ::LNDFR: return SystemZ::LNDBR;
1702  case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1703  case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1704  case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1705  // On zEC12 we prefer to use RISBGN. But if there is a chance to
1706  // actually use the condition code, we may turn it back into RISGB.
1707  // Note that RISBG is not really a "load-and-test" instruction,
1708  // but sets the same condition code values, so is OK to use here.
1709  case SystemZ::RISBGN: return SystemZ::RISBG;
1710  default: return 0;
1711  }
1712 }
1713 
1714 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1715 // have already been filtered out. Store the first set bit in LSB and
1716 // the number of set bits in Length if so.
1717 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1718  unsigned First = findFirstSet(Mask);
1719  uint64_t Top = (Mask >> First) + 1;
1720  if ((Top & -Top) == Top) {
1721  LSB = First;
1722  Length = findFirstSet(Top);
1723  return true;
1724  }
1725  return false;
1726 }
1727 
1729  unsigned &Start, unsigned &End) const {
1730  // Reject trivial all-zero masks.
1731  Mask &= allOnes(BitSize);
1732  if (Mask == 0)
1733  return false;
1734 
1735  // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1736  // the msb and End specifies the index of the lsb.
1737  unsigned LSB, Length;
1738  if (isStringOfOnes(Mask, LSB, Length)) {
1739  Start = 63 - (LSB + Length - 1);
1740  End = 63 - LSB;
1741  return true;
1742  }
1743 
1744  // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1745  // of the low 1s and End specifies the lsb of the high 1s.
1746  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1747  assert(LSB > 0 && "Bottom bit must be set");
1748  assert(LSB + Length < BitSize && "Top bit must be set");
1749  Start = 63 - (LSB - 1);
1750  End = 63 - (LSB + Length);
1751  return true;
1752  }
1753 
1754  return false;
1755 }
1756 
1757 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1759  const MachineInstr *MI) const {
1760  switch (Opcode) {
1761  case SystemZ::CHI:
1762  case SystemZ::CGHI:
1763  if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1764  return 0;
1765  break;
1766  case SystemZ::CLFI:
1767  case SystemZ::CLGFI:
1768  if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1769  return 0;
1770  break;
1771  case SystemZ::CL:
1772  case SystemZ::CLG:
1773  if (!STI.hasMiscellaneousExtensions())
1774  return 0;
1775  if (!(MI && MI->getOperand(3).getReg() == 0))
1776  return 0;
1777  break;
1778  }
1779  switch (Type) {
1781  switch (Opcode) {
1782  case SystemZ::CR:
1783  return SystemZ::CRJ;
1784  case SystemZ::CGR:
1785  return SystemZ::CGRJ;
1786  case SystemZ::CHI:
1787  return SystemZ::CIJ;
1788  case SystemZ::CGHI:
1789  return SystemZ::CGIJ;
1790  case SystemZ::CLR:
1791  return SystemZ::CLRJ;
1792  case SystemZ::CLGR:
1793  return SystemZ::CLGRJ;
1794  case SystemZ::CLFI:
1795  return SystemZ::CLIJ;
1796  case SystemZ::CLGFI:
1797  return SystemZ::CLGIJ;
1798  default:
1799  return 0;
1800  }
1802  switch (Opcode) {
1803  case SystemZ::CR:
1804  return SystemZ::CRBReturn;
1805  case SystemZ::CGR:
1806  return SystemZ::CGRBReturn;
1807  case SystemZ::CHI:
1808  return SystemZ::CIBReturn;
1809  case SystemZ::CGHI:
1810  return SystemZ::CGIBReturn;
1811  case SystemZ::CLR:
1812  return SystemZ::CLRBReturn;
1813  case SystemZ::CLGR:
1814  return SystemZ::CLGRBReturn;
1815  case SystemZ::CLFI:
1816  return SystemZ::CLIBReturn;
1817  case SystemZ::CLGFI:
1818  return SystemZ::CLGIBReturn;
1819  default:
1820  return 0;
1821  }
1823  switch (Opcode) {
1824  case SystemZ::CR:
1825  return SystemZ::CRBCall;
1826  case SystemZ::CGR:
1827  return SystemZ::CGRBCall;
1828  case SystemZ::CHI:
1829  return SystemZ::CIBCall;
1830  case SystemZ::CGHI:
1831  return SystemZ::CGIBCall;
1832  case SystemZ::CLR:
1833  return SystemZ::CLRBCall;
1834  case SystemZ::CLGR:
1835  return SystemZ::CLGRBCall;
1836  case SystemZ::CLFI:
1837  return SystemZ::CLIBCall;
1838  case SystemZ::CLGFI:
1839  return SystemZ::CLGIBCall;
1840  default:
1841  return 0;
1842  }
1844  switch (Opcode) {
1845  case SystemZ::CR:
1846  return SystemZ::CRT;
1847  case SystemZ::CGR:
1848  return SystemZ::CGRT;
1849  case SystemZ::CHI:
1850  return SystemZ::CIT;
1851  case SystemZ::CGHI:
1852  return SystemZ::CGIT;
1853  case SystemZ::CLR:
1854  return SystemZ::CLRT;
1855  case SystemZ::CLGR:
1856  return SystemZ::CLGRT;
1857  case SystemZ::CLFI:
1858  return SystemZ::CLFIT;
1859  case SystemZ::CLGFI:
1860  return SystemZ::CLGIT;
1861  case SystemZ::CL:
1862  return SystemZ::CLT;
1863  case SystemZ::CLG:
1864  return SystemZ::CLGT;
1865  default:
1866  return 0;
1867  }
1868  }
1869  return 0;
1870 }
1871 
1872 bool SystemZInstrInfo::
1874  assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&
1875  MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&
1876  "Not a compare reg/reg.");
1877 
1879  bool CCLive = true;
1881  for (MachineInstr &MI : llvm::make_range(std::next(MBBI), MBB->end())) {
1882  if (MI.readsRegister(SystemZ::CC)) {
1883  unsigned Flags = MI.getDesc().TSFlags;
1884  if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
1885  CCUsers.push_back(&MI);
1886  else
1887  return false;
1888  }
1889  if (MI.definesRegister(SystemZ::CC)) {
1890  CCLive = false;
1891  break;
1892  }
1893  }
1894  if (CCLive) {
1896  LiveRegs.addLiveOuts(*MBB);
1897  if (LiveRegs.contains(SystemZ::CC))
1898  return false;
1899  }
1900 
1901  // Update all CC users.
1902  for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
1903  unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1904  unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
1905  0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
1906  MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
1907  unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
1908  CCMaskMO.setImm(NewCCMask);
1909  }
1910 
1911  return true;
1912 }
1913 
1914 unsigned SystemZ::reverseCCMask(unsigned CCMask) {
1915  return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1918  (CCMask & SystemZ::CCMASK_CMP_UO));
1919 }
1920 
1922  MachineFunction &MF = *MBB->getParent();
1924  MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
1925  return NewMBB;
1926 }
1927 
1931  NewMBB->splice(NewMBB->begin(), MBB,
1932  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1934  return NewMBB;
1935 }
1936 
1940  NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
1942  return NewMBB;
1943 }
1944 
1945 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1946  if (!STI.hasLoadAndTrap())
1947  return 0;
1948  switch (Opcode) {
1949  case SystemZ::L:
1950  case SystemZ::LY:
1951  return SystemZ::LAT;
1952  case SystemZ::LG:
1953  return SystemZ::LGAT;
1954  case SystemZ::LFH:
1955  return SystemZ::LFHAT;
1956  case SystemZ::LLGF:
1957  return SystemZ::LLGFAT;
1958  case SystemZ::LLGT:
1959  return SystemZ::LLGTAT;
1960  }
1961  return 0;
1962 }
1963 
1966  unsigned Reg, uint64_t Value) const {
1967  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1968  unsigned Opcode = 0;
1969  if (isInt<16>(Value))
1970  Opcode = SystemZ::LGHI;
1971  else if (SystemZ::isImmLL(Value))
1972  Opcode = SystemZ::LLILL;
1973  else if (SystemZ::isImmLH(Value)) {
1974  Opcode = SystemZ::LLILH;
1975  Value >>= 16;
1976  }
1977  else if (isInt<32>(Value))
1978  Opcode = SystemZ::LGFI;
1979  if (Opcode) {
1980  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1981  return;
1982  }
1983 
1985  assert (MRI.isSSA() && "Huge values only handled before reg-alloc .");
1986  Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1987  Register Reg1 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
1988  BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0);
1989  BuildMI(MBB, MBBI, DL, get(SystemZ::IIHF64), Reg1)
1990  .addReg(Reg0).addImm(Value >> 32);
1991  BuildMI(MBB, MBBI, DL, get(SystemZ::IILF64), Reg)
1992  .addReg(Reg1).addImm(Value & ((uint64_t(1) << 32) - 1));
1993 }
1994 
1996  StringRef &ErrInfo) const {
1997  const MCInstrDesc &MCID = MI.getDesc();
1998  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
1999  if (I >= MCID.getNumOperands())
2000  break;
2001  const MachineOperand &Op = MI.getOperand(I);
2002  const MCOperandInfo &MCOI = MCID.OpInfo[I];
2003  // Addressing modes have register and immediate operands. Op should be a
2004  // register (or frame index) operand if MCOI.RegClass contains a valid
2005  // register class, or an immediate otherwise.
2006  if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
2007  ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
2008  (MCOI.RegClass == -1 && !Op.isImm()))) {
2009  ErrInfo = "Addressing mode operands corrupt!";
2010  return false;
2011  }
2012  }
2013 
2014  return true;
2015 }
2016 
2017 bool SystemZInstrInfo::
2019  const MachineInstr &MIb) const {
2020 
2021  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
2022  return false;
2023 
2024  // If mem-operands show that the same address Value is used by both
2025  // instructions, check for non-overlapping offsets and widths. Not
2026  // sure if a register based analysis would be an improvement...
2027 
2028  MachineMemOperand *MMOa = *MIa.memoperands_begin();
2029  MachineMemOperand *MMOb = *MIb.memoperands_begin();
2030  const Value *VALa = MMOa->getValue();
2031  const Value *VALb = MMOb->getValue();
2032  bool SameVal = (VALa && VALb && (VALa == VALb));
2033  if (!SameVal) {
2034  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
2035  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
2036  if (PSVa && PSVb && (PSVa == PSVb))
2037  SameVal = true;
2038  }
2039  if (SameVal) {
2040  int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
2041  int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
2042  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2043  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2044  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2045  if (LowOffset + LowWidth <= HighOffset)
2046  return true;
2047  }
2048 
2049  return false;
2050 }
llvm::SystemZ::isImmLH
static bool isImmLH(uint64_t Val)
Definition: SystemZ.h:166
llvm::SystemZInstrInfo::isRxSBGMask
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
Definition: SystemZInstrInfo.cpp:1728
llvm::SystemZInstrInfo::prepareCompareSwapOperands
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
Definition: SystemZInstrInfo.cpp:1873
llvm::SystemZInstrInfo::getFusedCompare
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
Definition: SystemZInstrInfo.cpp:1757
llvm::SystemZInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:718
SystemZInstrBuilder.h
llvm::findFirstSet
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
Definition: MathExtras.h:233
llvm::SystemZInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SystemZInstrInfo.cpp:571
llvm::SystemZSubtarget::hasMiscellaneousExtensions
bool hasMiscellaneousExtensions() const
Definition: SystemZSubtarget.h:179
llvm::SystemZInstrInfo::hasDisplacementPairInsn
bool hasDisplacementPairInsn(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1680
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1956
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::SystemZSubtarget::hasLoadStoreOnCond2
bool hasLoadStoreOnCond2() const
Definition: SystemZSubtarget.h:148
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:387
llvm::SystemZInstrInfo::getLoadStoreOpcodes
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Definition: SystemZInstrInfo.cpp:1591
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:209
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::SystemZII::CompareAndReturn
@ CompareAndReturn
Definition: SystemZInstrInfo.h:144
llvm::SystemZInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: SystemZInstrInfo.cpp:953
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:123
llvm::MCRegister::from
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Definition: MCRegister.h:67
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::SystemZSubtarget::hasVector
bool hasVector() const
Definition: SystemZSubtarget.h:214
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:731
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:61
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::SystemZII::BranchCTG
@ BranchCTG
Definition: SystemZInstrInfo.h:104
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:150
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::SystemZ::splitBlockAfter
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1928
isStringOfOnes
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
Definition: SystemZInstrInfo.cpp:1717
llvm::SmallVector< MachineInstr *, 4 >
Statistic.h
llvm::SystemZ::emitBlockAfter
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1921
llvm::SystemZII::Branch::hasMBBTarget
bool hasMBBTarget()
Definition: SystemZInstrInfo.h:130
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SystemZ::CCMASK_CMP_LT
const unsigned CCMASK_CMP_LT
Definition: SystemZ.h:36
llvm::SystemZInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SystemZInstrInfo.cpp:475
llvm::SystemZSubtarget::hasLoadAndTrap
bool hasLoadAndTrap() const
Definition: SystemZSubtarget.h:187
llvm::AArch64ISD::STG
@ STG
Definition: AArch64ISelLowering.h:468
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::SystemZII::CCMaskFirst
@ CCMaskFirst
Definition: SystemZInstrInfo.h:47
llvm::SystemZ::splitBlockBefore
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1937
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SystemZII::CompareAndBranch
@ CompareAndBranch
Definition: SystemZInstrInfo.h:141
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:873
llvm::LivePhysRegs::contains
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:108
llvm::SystemZInstrInfo::loadImmediate
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
Definition: SystemZInstrInfo.cpp:1964
SystemZMCTargetDesc.h
SystemZGenInstrInfo
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SystemZInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SystemZInstrInfo.cpp:481
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:746
llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SystemZInstrInfo.cpp:2018
llvm::SystemZ::CCMASK_CMP_EQ
const unsigned CCMASK_CMP_EQ
Definition: SystemZ.h:35
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:552
MachineRegisterInfo.h
llvm::SystemZInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: SystemZInstrInfo.cpp:613
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
isSimpleBD12Move
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
Definition: SystemZInstrInfo.cpp:900
isSimpleMove
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
Definition: SystemZInstrInfo.cpp:314
llvm::get
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
Definition: PointerIntPair.h:234
llvm::SystemZInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SystemZInstrInfo.cpp:1995
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::SystemZII::HasIndex
@ HasIndex
Definition: SystemZInstrInfo.h:39
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::SystemZSubtarget::hasMiscellaneousExtensions3
bool hasMiscellaneousExtensions3() const
Definition: SystemZSubtarget.h:244
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:166
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
SystemZInstrInfo.h
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::SystemZInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:689
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::SystemZII::CompareAndTrap
@ CompareAndTrap
Definition: SystemZInstrInfo.h:150
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::LivePhysRegs::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Definition: LivePhysRegs.cpp:232
llvm::SystemZInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MBBI) const override
Definition: SystemZInstrInfo.cpp:1343
LiveVariables.h
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::SystemZInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SystemZInstrInfo.cpp:1004
llvm::LiveVariables::replaceKillInstruction
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
Definition: LiveVariables.cpp:752
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::SystemZInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:884
llvm::SystemZInstrInfo::getLoadAndTrap
unsigned getLoadAndTrap(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1945
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:390
llvm::AArch64CC::LE
@ LE
Definition: AArch64BaseInfo.h:268
llvm::SystemZInstrInfo::getBranchInfo
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
Definition: SystemZInstrInfo.cpp:1539
llvm::SystemZ::isHighReg
bool isHighReg(unsigned int Reg)
Definition: SystemZRegisterInfo.h:35
SystemZ.h
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:106
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::SystemZII::Branch
Definition: SystemZInstrInfo.h:111
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1420
llvm::SystemZ::CCMASK_CMP_GT
const unsigned CCMASK_CMP_GT
Definition: SystemZ.h:37
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::SystemZII::SimpleBDXLoad
@ SimpleBDXLoad
Definition: SystemZInstrInfo.h:36
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
BranchProbability.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SystemZ::reverseCCMask
unsigned reverseCCMask(unsigned CCMask)
Definition: SystemZInstrInfo.cpp:1914
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:183
transferMIFlag
static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI, MachineInstr::MIFlag Flag)
Definition: SystemZInstrInfo.cpp:946
llvm::SystemZ::CCMASK_CMP_NE
const unsigned CCMASK_CMP_NE
Definition: SystemZ.h:38
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::SystemZII::BranchCG
@ BranchCG
Definition: SystemZInstrInfo.h:92
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::PatchPointOpers::getNumPatchBytes
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:274
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:770
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:419
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SystemZ::isImmLL
static bool isImmLL(uint64_t Val)
Definition: SystemZ.h:161
llvm::SystemZ::CCMASK_ANY
const unsigned CCMASK_ANY
Definition: SystemZ.h:31
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
LiveIntervals.h
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:357
llvm::SystemZ::CCMASK_ICMP
const unsigned CCMASK_ICMP
Definition: SystemZ.h:47
llvm::SystemZII::BranchC
@ BranchC
Definition: SystemZInstrInfo.h:84
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:119
llvm::SystemZII::BranchNormal
@ BranchNormal
Definition: SystemZInstrInfo.h:80
llvm::SystemZII::FusedCompareType
FusedCompareType
Definition: SystemZInstrInfo.h:139
VirtRegMap.h
llvm::MachineFunction::CloneMachineInstr
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
Definition: MachineFunction.cpp:383
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SystemZII::BranchCT
@ BranchCT
Definition: SystemZInstrInfo.h:100
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
MCRegisterInfo.h
llvm::SystemZInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SystemZInstrInfo.cpp:449
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SystemZCallingConventionRegisters::getStackPointerBias
virtual int getStackPointerBias()=0
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
llvm::SystemZInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:869
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::SystemZ::CCMASK_CMP_UO
const unsigned CCMASK_CMP_UO
Definition: SystemZ.h:43
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::SystemZInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: SystemZInstrInfo.cpp:358
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:259
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SystemZInstrInfo::SystemZInstrInfo
SystemZInstrInfo(SystemZSubtarget &STI)
Definition: SystemZInstrInfo.cpp:61
SystemZSubtarget.h
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:384
llvm::SystemZInstrInfo::getOpcodeForOffset
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset, const MachineInstr *MI=nullptr) const
Definition: SystemZInstrInfo.cpp:1634
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:204
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::LiveRange::createDeadDef
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
Definition: LiveInterval.cpp:355
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
allOnes
static uint64_t allOnes(unsigned int Count)
Definition: SystemZInstrInfo.cpp:54
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:30
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: SystemZInstrInfo.cpp:537
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::SystemZ::getTargetMemOpcode
int getTargetMemOpcode(uint16_t Opcode)
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::RISCVISD::LA
@ LA
Definition: RISCVISelLowering.h:330
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZCallingConventionRegisters
A SystemZ-specific class detailing special use registers particular for calling conventions.
Definition: SystemZRegisterInfo.h:47
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SystemZII::getAccessSize
static unsigned getAccessSize(unsigned int Flags)
Definition: SystemZInstrInfo.h:53
llvm::SystemZII::Is128Bit
@ Is128Bit
Definition: SystemZInstrInfo.h:40
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:289
llvm::SystemZSubtarget::hasLoadStoreOnCond
bool hasLoadStoreOnCond() const
Definition: SystemZSubtarget.h:145
llvm::SystemZII::CompareAndSibcall
@ CompareAndSibcall
Definition: SystemZInstrInfo.h:147
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:279
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::SystemZInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: SystemZInstrInfo.cpp:724
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:982
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1327
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::SystemZII::Has20BitOffset
@ Has20BitOffset
Definition: SystemZInstrInfo.h:38
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::SystemZCallingConventionRegisters::getCallFrameSize
virtual int getCallFrameSize()=0
llvm::SystemZII::BranchCL
@ BranchCL
Definition: SystemZInstrInfo.h:88
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:158
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::SystemZMC::getFirstReg
unsigned getFirstReg(unsigned Reg)
Definition: SystemZMCTargetDesc.cpp:131
llvm::MipsISD::LDR
@ LDR
Definition: MipsISelLowering.h:253
llvm::SystemZ::IPM_CC
const unsigned IPM_CC
Definition: SystemZ.h:112
StackMaps.h
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:296
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::SystemZInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:1522
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:928
llvm::SystemZII::CCMaskLast
@ CCMaskLast
Definition: SystemZInstrInfo.h:48
llvm::SystemZInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:677
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1763
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SystemZInstrInfo::getLoadAndTest
unsigned getLoadAndTest(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1687
LiveInterval.h
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::SystemZII::AsmGoto
@ AsmGoto
Definition: SystemZInstrInfo.h:107
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:56
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::SystemZInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: SystemZInstrInfo.cpp:520
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:82
interpretAndImmediate
static LogicOp interpretAndImmediate(unsigned Opcode)
Definition: SystemZInstrInfo.cpp:923
llvm::SystemZInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:325
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:901
llvm::LanaiISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: LanaiISelLowering.h:27
llvm::SystemZII::BranchCLG
@ BranchCLG
Definition: SystemZInstrInfo.h:96
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
SlotIndexes.h
llvm::SystemZInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:330
llvm::SystemZInstrInfo::isStackSlotCopy
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
Definition: SystemZInstrInfo.cpp:335
llvm::SystemZInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SystemZInstrInfo.cpp:777
MachineFunction.h
llvm::SystemZSubtarget::getSpecialRegisters
SystemZCallingConventionRegisters * getSpecialRegisters() const
Definition: SystemZSubtarget.h:96
llvm::MachineInstr::registerDefIsDead
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:1436
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1479
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SystemZII::SimpleBDXStore
@ SimpleBDXStore
Definition: SystemZInstrInfo.h:37
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:278
llvm::SystemZInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Definition: SystemZInstrInfo.cpp:277
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:362
llvm::LiveIntervals::getRegUnit
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Definition: LiveIntervals.h:387
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
transferDeadCC
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
Definition: SystemZInstrInfo.cpp:938
LivePhysRegs.h