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13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
30 class SystemZSubtarget;
169 MachineBasicBlock *
MBB);
172 MachineBasicBlock *
MBB);
181 void expandRIPseudo(
MachineInstr &
MI,
unsigned LowOpcode,
unsigned HighOpcode,
182 bool ConvertHigh)
const;
184 unsigned LowOpcodeK,
unsigned HighOpcode)
const;
186 unsigned HighOpcode)
const;
188 unsigned HighOpcode)
const;
190 unsigned Size)
const;
195 const DebugLoc &
DL,
unsigned DestReg,
unsigned SrcReg,
196 unsigned LowLowOpcode,
unsigned Size,
bool KillSrc,
197 bool UndefSrc)
const;
199 virtual void anchor();
214 unsigned CommuteOpIdx1,
215 unsigned CommuteOpIdx2)
const override;
226 int &SrcFrameIndex)
const override;
230 bool AllowModify)
const override;
232 int *BytesRemoved =
nullptr)
const override;
236 int *BytesAdded =
nullptr)
const override;
239 int64_t &
Value)
const override;
242 int &)
const override;
251 unsigned ExtraPredCycles,
254 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
256 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
264 bool KillSrc)
const override;
306 unsigned &LoadOpcode,
unsigned &StoreOpcode)
const;
326 unsigned &Start,
unsigned &End)
const;
366 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
bool hasDisplacementPairInsn(unsigned Opcode) const
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder & UseMI
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Target - Wrapper for Target specific information.
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
static unsigned getCCValues(unsigned int Flags)
Reg
All possible values of the reg field in the ModR/M byte.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
unsigned const TargetRegisterInfo * TRI
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
static unsigned getCompareZeroCCMask(unsigned int Flags)
bool expandPostRAPseudo(MachineInstr &MBBI) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getLoadAndTrap(unsigned Opcode) const
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
MachineBasicBlock * getMBBTarget()
unsigned reverseCCMask(unsigned CCMask)
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Representation of each machine instruction.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
SystemZInstrInfo(SystemZSubtarget &STI)
MachineInstrBundleIterator< MachineInstr > iterator
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
int getTargetMemOpcode(uint16_t Opcode)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
static unsigned getAccessSize(unsigned int Flags)
const SystemZRegisterInfo & getRegisterInfo() const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
int getTwoOperandOpcode(uint16_t Opcode)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isPredicable(const MachineInstr &MI) const override
unsigned getLoadAndTest(unsigned Opcode) const
MachineInstrBuilder MachineInstrBuilder & DefMI
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
LLVM Value Representation.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Wrapper class representing physical registers. Should be passed by value.