LLVM  13.0.0git
SystemZInstrInfo.h
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
23 #include <cstdint>
24 
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class SystemZSubtarget;
31 
32 namespace SystemZII {
33 
34 enum {
35  // See comments in SystemZInstrFormats.td.
36  SimpleBDXLoad = (1 << 0),
37  SimpleBDXStore = (1 << 1),
38  Has20BitOffset = (1 << 2),
39  HasIndex = (1 << 3),
40  Is128Bit = (1 << 4),
41  AccessSizeMask = (31 << 5),
43  CCValuesMask = (15 << 10),
45  CompareZeroCCMaskMask = (15 << 14),
47  CCMaskFirst = (1 << 18),
48  CCMaskLast = (1 << 19),
49  IsLogical = (1 << 20),
50  CCIfNoSignedWrap = (1 << 21)
51 };
52 
53 static inline unsigned getAccessSize(unsigned int Flags) {
54  return (Flags & AccessSizeMask) >> AccessSizeShift;
55 }
56 
57 static inline unsigned getCCValues(unsigned int Flags) {
58  return (Flags & CCValuesMask) >> CCValuesShift;
59 }
60 
61 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
63 }
64 
65 // SystemZ MachineOperand target flags.
66 enum {
67  // Masks out the bits for the access model.
68  MO_SYMBOL_MODIFIER = (3 << 0),
69 
70  // @GOT (aka @GOTENT)
71  MO_GOT = (1 << 0),
72 
73  // @INDNTPOFF
74  MO_INDNTPOFF = (2 << 0)
75 };
76 
77 // Classifies a branch.
78 enum BranchType {
79  // An instruction that branches on the current value of CC.
81 
82  // An instruction that peforms a 32-bit signed comparison and branches
83  // on the result.
85 
86  // An instruction that peforms a 32-bit unsigned comparison and branches
87  // on the result.
89 
90  // An instruction that peforms a 64-bit signed comparison and branches
91  // on the result.
93 
94  // An instruction that peforms a 64-bit unsigned comparison and branches
95  // on the result.
97 
98  // An instruction that decrements a 32-bit register and branches if
99  // the result is nonzero.
101 
102  // An instruction that decrements a 64-bit register and branches if
103  // the result is nonzero.
105 
106  // An instruction representing an asm goto statement.
108 };
109 
110 // Information about a branch instruction.
111 class Branch {
112  // The target of the branch. In case of INLINEASM_BR, this is nullptr.
113  const MachineOperand *Target;
114 
115 public:
116  // The type of the branch.
118 
119  // CCMASK_<N> is set if CC might be equal to N.
120  unsigned CCValid;
121 
122  // CCMASK_<N> is set if the branch should be taken when CC == N.
123  unsigned CCMask;
124 
125  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
126  const MachineOperand *target)
127  : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
128 
129  bool isIndirect() { return Target != nullptr && Target->isReg(); }
130  bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
132  return hasMBBTarget() ? Target->getMBB() : nullptr;
133  }
134 };
135 
136 // Kinds of fused compares in compare-and-* instructions. Together with type
137 // of the converted compare, this identifies the compare-and-*
138 // instruction.
140  // Relative branch - CRJ etc.
142 
143  // Indirect branch, used for return - CRBReturn etc.
145 
146  // Indirect branch, used for sibcall - CRBCall etc.
148 
149  // Trap
151 };
152 
153 } // end namespace SystemZII
154 
155 namespace SystemZ {
156 int getTwoOperandOpcode(uint16_t Opcode);
157 int getTargetMemOpcode(uint16_t Opcode);
158 
159 // Return a version of comparison CC mask CCMask in which the LT and GT
160 // actions are swapped.
161 unsigned reverseCCMask(unsigned CCMask);
162 
163 // Create a new basic block after MBB.
164 MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB);
165 // Split MBB after MI and return the new block (the one that contains
166 // instructions after MI).
168  MachineBasicBlock *MBB);
169 // Split MBB before MI and return the new block (the one that contains MI).
171  MachineBasicBlock *MBB);
172 }
173 
175  const SystemZRegisterInfo RI;
176  SystemZSubtarget &STI;
177 
178  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
179  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
180  void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
181  bool ConvertHigh) const;
182  void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
183  unsigned LowOpcodeK, unsigned HighOpcode) const;
184  void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
185  unsigned HighOpcode) const;
186  void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
187  unsigned HighOpcode) const;
188  void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
189  unsigned Size) const;
190  void expandLoadStackGuard(MachineInstr *MI) const;
191 
194  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
195  unsigned LowLowOpcode, unsigned Size, bool KillSrc,
196  bool UndefSrc) const;
197 
198  virtual void anchor();
199 
200 protected:
201  /// Commutes the operands in the given instruction by changing the operands
202  /// order and/or changing the instruction's opcode and/or the immediate value
203  /// operand.
204  ///
205  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
206  /// to be commuted.
207  ///
208  /// Do not call this method for a non-commutable instruction or
209  /// non-commutable operands.
210  /// Even though the instruction is commutable, the method may still
211  /// fail to commute the operands, null pointer is returned in such cases.
213  unsigned CommuteOpIdx1,
214  unsigned CommuteOpIdx2) const override;
215 
216 public:
217  explicit SystemZInstrInfo(SystemZSubtarget &STI);
218 
219  // Override TargetInstrInfo.
220  unsigned isLoadFromStackSlot(const MachineInstr &MI,
221  int &FrameIndex) const override;
222  unsigned isStoreToStackSlot(const MachineInstr &MI,
223  int &FrameIndex) const override;
224  bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
225  int &SrcFrameIndex) const override;
227  MachineBasicBlock *&FBB,
229  bool AllowModify) const override;
231  int *BytesRemoved = nullptr) const override;
234  const DebugLoc &DL,
235  int *BytesAdded = nullptr) const override;
236  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
237  Register &SrcReg2, int &Mask, int &Value) const override;
239  Register, Register, Register, int &, int &,
240  int &) const override;
242  const DebugLoc &DL, Register DstReg,
244  Register FalseReg) const override;
246  MachineRegisterInfo *MRI) const override;
247  bool isPredicable(const MachineInstr &MI) const override;
248  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
249  unsigned ExtraPredCycles,
250  BranchProbability Probability) const override;
252  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
253  MachineBasicBlock &FMBB,
254  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
255  BranchProbability Probability) const override;
256  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
257  BranchProbability Probability) const override;
259  ArrayRef<MachineOperand> Pred) const override;
261  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
262  bool KillSrc) const override;
265  Register SrcReg, bool isKill, int FrameIndex,
266  const TargetRegisterClass *RC,
267  const TargetRegisterInfo *TRI) const override;
270  Register DestReg, int FrameIdx,
271  const TargetRegisterClass *RC,
272  const TargetRegisterInfo *TRI) const override;
274  MachineInstr &MI,
275  LiveVariables *LV) const override;
276  MachineInstr *
278  ArrayRef<unsigned> Ops,
280  LiveIntervals *LIS = nullptr,
281  VirtRegMap *VRM = nullptr) const override;
284  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
285  LiveIntervals *LIS = nullptr) const override;
286  bool expandPostRAPseudo(MachineInstr &MBBI) const override;
288  override;
289 
290  // Return the SystemZRegisterInfo, which this class owns.
291  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
292 
293  // Return the size in bytes of MI.
294  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
295 
296  // Return true if MI is a conditional or unconditional branch.
297  // When returning true, set Cond to the mask of condition-code
298  // values on which the instruction will branch, and set Target
299  // to the operand that contains the branch target. This target
300  // can be a register or a basic block.
302 
303  // Get the load and store opcodes for a given register class.
305  unsigned &LoadOpcode, unsigned &StoreOpcode) const;
306 
307  // Opcode is the opcode of an instruction that has an address operand,
308  // and the caller wants to perform that instruction's operation on an
309  // address that has displacement Offset. Return the opcode of a suitable
310  // instruction (which might be Opcode itself) or 0 if no such instruction
311  // exists.
312  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
313 
314  // If Opcode is a load instruction that has a LOAD AND TEST form,
315  // return the opcode for the testing form, otherwise return 0.
316  unsigned getLoadAndTest(unsigned Opcode) const;
317 
318  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
319  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
320  // significant. Set Start and End to the I3 and I4 operands if so.
321  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
322  unsigned &Start, unsigned &End) const;
323 
324  // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
325  // operation exists, return the opcode for the latter, otherwise return 0.
326  // MI, if nonnull, is the compare instruction.
327  unsigned getFusedCompare(unsigned Opcode,
329  const MachineInstr *MI = nullptr) const;
330 
331  // Try to find all CC users of the compare instruction (MBBI) and update
332  // all of them to maintain equivalent behavior after swapping the compare
333  // operands. Return false if not all users can be conclusively found and
334  // handled. The compare instruction is *not* changed.
336 
337  // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
338  // operation exists, returh the opcode for the latter, otherwise return 0.
339  unsigned getLoadAndTrap(unsigned Opcode) const;
340 
341  // Emit code before MBBI in MI to move immediate value Value into
342  // physical register Reg.
345  unsigned Reg, uint64_t Value) const;
346 
347  // Perform target specific instruction verification.
348  bool verifyInstruction(const MachineInstr &MI,
349  StringRef &ErrInfo) const override;
350 
351  // Sometimes, it is possible for the target to tell, even without
352  // aliasing information, that two MIs access different memory
353  // addresses. This function returns true if two MIs access different
354  // memory addresses and false otherwise.
355  bool
357  const MachineInstr &MIb) const override;
358 };
359 
360 } // end namespace llvm
361 
362 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SystemZII::MO_SYMBOL_MODIFIER
@ MO_SYMBOL_MODIFIER
Definition: SystemZInstrInfo.h:68
llvm::SystemZInstrInfo::isRxSBGMask
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
Definition: SystemZInstrInfo.cpp:1685
llvm::SystemZInstrInfo::prepareCompareSwapOperands
bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const
Definition: SystemZInstrInfo.cpp:1830
llvm::SystemZInstrInfo::getFusedCompare
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
Definition: SystemZInstrInfo.cpp:1714
llvm::SystemZInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:713
llvm::SystemZInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: SystemZInstrInfo.cpp:567
llvm::SystemZII::CompareZeroCCMaskShift
@ CompareZeroCCMaskShift
Definition: SystemZInstrInfo.h:46
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SystemZII::IsLogical
@ IsLogical
Definition: SystemZInstrInfo.h:49
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
llvm::SystemZInstrInfo::getLoadStoreOpcodes
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Definition: SystemZInstrInfo.cpp:1574
llvm::SystemZII::MO_INDNTPOFF
@ MO_INDNTPOFF
Definition: SystemZInstrInfo.h:74
llvm::SystemZII::CompareAndReturn
@ CompareAndReturn
Definition: SystemZInstrInfo.h:144
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SystemZII::BranchType
BranchType
Definition: SystemZInstrInfo.h:78
llvm::SystemZII::BranchCTG
@ BranchCTG
Definition: SystemZInstrInfo.h:104
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::SystemZ::splitBlockAfter
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1886
llvm::SystemZ::emitBlockAfter
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1879
llvm::SystemZII::Branch::hasMBBTarget
bool hasMBBTarget()
Definition: SystemZInstrInfo.h:130
llvm::SystemZII::getCCValues
static unsigned getCCValues(unsigned int Flags)
Definition: SystemZInstrInfo.h:57
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::SystemZII::MO_GOT
@ MO_GOT
Definition: SystemZInstrInfo.h:71
llvm::SystemZII::SimpleBDXLoad
@ SimpleBDXLoad
Definition: SystemZInstrInfo.h:36
llvm::SystemZInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SystemZInstrInfo.cpp:471
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
TargetInstrInfo.h
llvm::SystemZ::splitBlockBefore
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
Definition: SystemZInstrInfo.cpp:1895
llvm::SystemZII::CompareAndBranch
@ CompareAndBranch
Definition: SystemZInstrInfo.h:141
llvm::SystemZInstrInfo::loadImmediate
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
Definition: SystemZInstrInfo.cpp:1922
SystemZGenInstrInfo
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SystemZInstrInfo
Definition: SystemZInstrInfo.h:174
llvm::SystemZII::Is128Bit
@ Is128Bit
Definition: SystemZInstrInfo.h:40
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SystemZInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SystemZInstrInfo.cpp:477
llvm::SystemZII::Branch::Branch
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
Definition: SystemZInstrInfo.h:125
llvm::SystemZII::CompareZeroCCMaskMask
@ CompareZeroCCMaskMask
Definition: SystemZInstrInfo.h:45
llvm::SystemZII::CCValuesMask
@ CCValuesMask
Definition: SystemZInstrInfo.h:43
llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: SystemZInstrInfo.cpp:1964
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:722
llvm::SystemZInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: SystemZInstrInfo.cpp:609
llvm::SystemZInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SystemZInstrInfo.cpp:1941
llvm::SystemZII::Branch::CCValid
unsigned CCValid
Definition: SystemZInstrInfo.h:120
llvm::SystemZII::AccessSizeMask
@ AccessSizeMask
Definition: SystemZInstrInfo.h:41
llvm::SystemZInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: SystemZInstrInfo.cpp:684
llvm::SystemZII::CompareAndTrap
@ CompareAndTrap
Definition: SystemZInstrInfo.h:150
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SystemZII::getCompareZeroCCMask
static unsigned getCompareZeroCCMask(unsigned int Flags)
Definition: SystemZInstrInfo.h:61
llvm::SystemZInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MBBI) const override
Definition: SystemZInstrInfo.cpp:1333
llvm::SystemZInstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: SystemZInstrInfo.cpp:994
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SystemZII::CCMaskLast
@ CCMaskLast
Definition: SystemZInstrInfo.h:48
llvm::SystemZInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:877
llvm::SystemZInstrInfo::getLoadAndTrap
unsigned getLoadAndTrap(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1903
llvm::SystemZII::Has20BitOffset
@ Has20BitOffset
Definition: SystemZInstrInfo.h:38
llvm::SystemZII::SimpleBDXStore
@ SimpleBDXStore
Definition: SystemZInstrInfo.h:37
llvm::SystemZII::CCValuesShift
@ CCValuesShift
Definition: SystemZInstrInfo.h:44
llvm::SystemZInstrInfo::getBranchInfo
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
Definition: SystemZInstrInfo.cpp:1522
llvm::SystemZII::Branch::getMBBTarget
MachineBasicBlock * getMBBTarget()
Definition: SystemZInstrInfo.h:131
SystemZ.h
llvm::SystemZII::AccessSizeShift
@ AccessSizeShift
Definition: SystemZInstrInfo.h:42
llvm::SystemZII::Branch
Definition: SystemZInstrInfo.h:111
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SystemZ::reverseCCMask
unsigned reverseCCMask(unsigned CCMask)
Definition: SystemZInstrInfo.cpp:1872
llvm::SystemZII::BranchCG
@ BranchCG
Definition: SystemZInstrInfo.h:92
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SystemZII::BranchC
@ BranchC
Definition: SystemZInstrInfo.h:84
llvm::SystemZII::BranchNormal
@ BranchNormal
Definition: SystemZInstrInfo.h:80
llvm::SystemZII::FusedCompareType
FusedCompareType
Definition: SystemZInstrInfo.h:139
llvm::SystemZII::BranchCT
@ BranchCT
Definition: SystemZInstrInfo.h:100
llvm::SystemZII::Branch::CCMask
unsigned CCMask
Definition: SystemZInstrInfo.h:123
llvm::SystemZInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SystemZInstrInfo.cpp:445
ArrayRef.h
llvm::SystemZInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SystemZInstrInfo.cpp:862
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::SystemZInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: SystemZInstrInfo.cpp:353
llvm::SystemZII::Branch::Type
BranchType Type
Definition: SystemZInstrInfo.h:117
llvm::SystemZII::CCIfNoSignedWrap
@ CCIfNoSignedWrap
Definition: SystemZInstrInfo.h:50
llvm::SystemZInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &Mask, int &Value) const override
Definition: SystemZInstrInfo.cpp:516
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SystemZInstrInfo::SystemZInstrInfo
SystemZInstrInfo(SystemZSubtarget &STI)
Definition: SystemZInstrInfo.cpp:58
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: SystemZInstrInfo.cpp:533
llvm::SystemZ::getTargetMemOpcode
int getTargetMemOpcode(uint16_t Opcode)
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZII::CCMaskFirst
@ CCMaskFirst
Definition: SystemZInstrInfo.h:47
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SystemZII::getAccessSize
static unsigned getAccessSize(unsigned int Flags)
Definition: SystemZInstrInfo.h:53
llvm::SystemZII::CompareAndSibcall
@ CompareAndSibcall
Definition: SystemZInstrInfo.h:147
llvm::SystemZII::Branch::isIndirect
bool isIndirect()
Definition: SystemZInstrInfo.h:129
uint16_t
llvm::SystemZInstrInfo::getRegisterInfo
const SystemZRegisterInfo & getRegisterInfo() const
Definition: SystemZInstrInfo.h:291
llvm::SystemZInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: SystemZInstrInfo.cpp:719
llvm::SystemZII::BranchCL
@ BranchCL
Definition: SystemZInstrInfo.h:88
llvm::SystemZ::getTwoOperandOpcode
int getTwoOperandOpcode(uint16_t Opcode)
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SystemZInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:1512
llvm::SystemZInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Definition: SystemZInstrInfo.cpp:673
llvm::SystemZInstrInfo::getLoadAndTest
unsigned getLoadAndTest(unsigned Opcode) const
Definition: SystemZInstrInfo.cpp:1644
SystemZRegisterInfo.h
llvm::SystemZRegisterInfo
Definition: SystemZRegisterInfo.h:42
MachineInstrBuilder.h
llvm::SystemZII::AsmGoto
@ AsmGoto
Definition: SystemZInstrInfo.h:107
llvm::SystemZII::HasIndex
@ HasIndex
Definition: SystemZInstrInfo.h:39
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:101
llvm::SystemZInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:320
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SystemZInstrInfo::getOpcodeForOffset
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
Definition: SystemZInstrInfo.cpp:1617
llvm::SystemZII::BranchCLG
@ BranchCLG
Definition: SystemZInstrInfo.h:96
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SystemZInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: SystemZInstrInfo.cpp:325
llvm::SystemZInstrInfo::isStackSlotCopy
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
Definition: SystemZInstrInfo.cpp:330
llvm::SystemZInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SystemZInstrInfo.cpp:770
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SystemZInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Definition: SystemZInstrInfo.cpp:272
llvm::SystemZInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
Definition: SystemZInstrInfo.cpp:945
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22