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33 cl::desc(
"Use TargetSchedModel for latency lookup"));
36 cl::desc(
"Use InstrItineraryData for latency lookup"));
46 static unsigned gcd(
unsigned Dividend,
unsigned Divisor) {
49 unsigned Rem = Dividend % Divisor;
56 static unsigned lcm(
unsigned A,
unsigned B) {
58 assert((LCM >= A && LCM >=
B) &&
"LCM overflow");
69 ResourceFactors.
resize(NumRes);
71 for (
unsigned Idx = 0; Idx < NumRes; ++Idx) {
74 ResourceLCM =
lcm(ResourceLCM, NumUnits);
76 MicroOpFactor = ResourceLCM / SchedModel.
IssueWidth;
77 for (
unsigned Idx = 0; Idx < NumRes; ++Idx) {
79 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
90 return SC->BeginGroup;
116 return SC->NumMicroOps;
118 return MI->isTransient() ? 0 : 1;
126 return Cycles >= 0 ? Cycles : 1000;
134 unsigned SchedClass =
MI->getDesc().getSchedClass();
143 assert(++NIter < 6 &&
"Variants are nested deeper than the magic number");
158 for (
unsigned i = 0;
i != DefOperIdx; ++
i) {
174 for (
unsigned i = 0;
i != UseOperIdx; ++
i) {
200 if (OperLatency >= 0)
218 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
233 if (Advance > 0 && (
unsigned)Advance >
Latency)
243 errs() <<
"DefIdx " << DefIdx <<
" exceeds machine model writes for "
244 << *
DefMI <<
" (Try with MCSchedModel.CompleteModel set to false)";
255 TargetSchedModel::computeInstrLatency(
const MCSchedClassDesc &SCDesc)
const {
259 unsigned TargetSchedModel::computeInstrLatency(
unsigned Opcode)
const {
265 unsigned TargetSchedModel::computeInstrLatency(
const MCInst &Inst)
const {
268 return computeInstrLatency(Inst.
getOpcode());
273 bool UseDefaultDefLatency)
const {
283 return computeInstrLatency(*SCDesc);
306 return computeInstrLatency(
DefMI);
326 unsigned SchedClass =
MI->getDesc().getSchedClass();
bool mustEndGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if current group must end.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
This is an optimization pass for GlobalISel generic memory operations.
static cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
MachineInstrBuilder & UseMI
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
uint16_t NumReadAdvanceEntries
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Reg
All possible values of the reg field in the ModR/M byte.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isOutOfOrder() const
Return true if machine supports out of order execution.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Instances of this class represent a single low-level machine instruction.
const InstrItineraryData * getInstrItineraries() const
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
unsigned const TargetRegisterInfo * TRI
unsigned getNumProcResourceKinds() const
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
static unsigned lcm(unsigned A, unsigned B)
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
const MachineOperand & getOperand(unsigned i) const
Summarize the scheduling resources required for an instruction of a particular scheduling class.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
double computeReciprocalThroughput(const MachineInstr *MI) const
Compute the reciprocal throughput of the given instruction.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
bool isOptionalDef() const
Set if this operand is a optional def.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx)
Find the def index of this operand.
static unsigned capLatency(int Cycles)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Specify the latency in cpu cycles for a particular scheduling class and def index.
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCOperandInfo * OpInfo
Register getReg() const
getReg - Returns the register number.
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
static cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
Wrapper class representing virtual and physical registers.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
static unsigned gcd(unsigned Dividend, unsigned Divisor)
unsigned getOpcode() const
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
bool mustBeginGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if new group must begin.
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx)
Find the use index of this operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
bool isEmpty() const
Returns true if there are no itineraries.
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model.