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29 #include "llvm/Config/llvm-config.h"
37 #define DEBUG_TYPE "pre-RA-sched"
39 STATISTIC(LoadsClustered,
"Number of loads clustered together");
46 cl::desc(
"Roughly estimate the number of cycles that 'long latency'"
47 "instructions take for targets with no itinerary"));
51 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
77 "SUnits std::vector reallocated on the fly!");
82 (
N->isMachineOpcode() &&
83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
114 unsigned &PhysReg,
int &Cost) {
124 cast<RegisterSDNode>(
Def->getOperand(1))->getReg() ==
Reg) {
126 }
else if (
Def->isMachineOpcode()) {
143 if (ExtraOper.getNode())
144 Ops.push_back(ExtraOper);
165 if (GlueDestNode ==
N)
return false;
169 N->getOperand(
N->getNumOperands()-1).getValueType() ==
MVT::Glue) {
173 if (
N->getValueType(
N->getNumValues() - 1) ==
MVT::Glue)
return false;
188 !
N->hasAnyUseOfValue(
N->getNumValues() - 1)) &&
189 "expected an unused glue value");
200 void ScheduleDAGSDNodes::ClusterNeighboringLoads(
SDNode *Node) {
202 unsigned NumOps = Node->getNumOperands();
203 if (Node->getOperand(NumOps-1).getValueType() ==
MVT::Other)
204 Chain = Node->getOperand(NumOps-1);
211 auto hasTiedInput = [
this](
const SDNode *
N) {
226 bool Cluster =
false;
229 if (hasTiedInput(Base))
234 unsigned UseCount = 0;
236 I !=
E && UseCount < 100; ++
I, ++UseCount) {
237 if (
I.getUse().getResNo() != Chain.
getResNo())
243 int64_t Offset1, Offset2;
245 Offset1 == Offset2 ||
246 hasTiedInput(
User)) {
251 if (O2SMap.
insert(std::make_pair(Offset1, Base)).second)
255 if (Offset2 < Offset1)
270 unsigned NumLoads = 0;
272 SDNode *BaseLoad = O2SMap[BaseOff];
273 Loads.push_back(BaseLoad);
279 Loads.push_back(
Load);
292 for (
unsigned I = 1,
E = Loads.size();
I !=
E; ++
I) {
293 bool OutGlue =
I <
E - 1;
304 else if (!OutGlue && InGlue.
getNode())
311 void ScheduleDAGSDNodes::ClusterNodes() {
314 if (!Node || !Node->isMachineOpcode())
317 unsigned Opc = Node->getMachineOpcode();
321 ClusterNeighboringLoads(Node);
325 void ScheduleDAGSDNodes::BuildSchedUnits() {
329 unsigned NumNodes = 0;
340 SUnits.reserve(NumNodes * 2);
349 while (!Worklist.empty()) {
354 if (Visited.
insert(
Op.getNode()).second)
355 Worklist.push_back(
Op.getNode());
371 while (
N->getNumOperands() &&
372 N->getOperand(
N->getNumOperands()-1).getValueType() ==
MVT::Glue) {
373 N =
N->getOperand(
N->getNumOperands()-1).getNode();
374 assert(
N->getNodeId() == -1 &&
"Node already inserted!");
376 if (
N->isMachineOpcode() &&
TII->
get(
N->getMachineOpcode()).
isCall())
382 while (
N->getValueType(
N->getNumValues()-1) ==
MVT::Glue) {
386 bool HasGlueUse =
false;
389 if (GlueVal.isOperandOf(*UI)) {
391 assert(
N->getNodeId() == -1 &&
"Node already inserted!");
394 if (
N->isMachineOpcode() &&
TII->
get(
N->getMachineOpcode()).
isCall())
398 if (!HasGlueUse)
break;
402 CallSUnits.push_back(NodeSUnit);
414 assert(
N->getNodeId() == -1 &&
"Node already inserted!");
425 while (!CallSUnits.empty()) {
439 void ScheduleDAGSDNodes::AddSchedEdges() {
446 for (
unsigned su = 0,
e =
SUnits.size(); su !=
e; ++su) {
465 if (
N->isMachineOpcode() &&
469 while (NumUsed != 0 && !
N->hasAnyUseOfValue(NumUsed - 1))
475 for (
unsigned i = 0,
e =
N->getNumOperands();
i !=
e; ++
i) {
476 SDNode *OpN =
N->getOperand(
i).getNode();
477 unsigned DefIdx =
N->getOperand(
i).getResNo();
480 assert(OpSU &&
"Node has no SUnit!");
481 if (OpSU == SU)
continue;
483 EVT OpVT =
N->getOperand(
i).getValueType();
487 unsigned PhysReg = 0;
491 assert((PhysReg == 0 || !isChain) &&
492 "Chain dependence via physreg data?");
502 unsigned OpLatency = isChain ? 1 : OpSU->
Latency;
510 if (!isChain && !UnitLatencies) {
512 ST.adjustSchedDependency(OpSU, DefIdx, SU,
i, Dep);
545 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
550 if (!Node->isMachineOpcode()) {
557 unsigned POpc = Node->getMachineOpcode();
558 if (POpc == TargetOpcode::IMPLICIT_DEF) {
563 if (POpc == TargetOpcode::PATCHPOINT &&
571 unsigned NRegDefs = SchedDAG->
TII->
get(Node->getMachineOpcode()).
getNumDefs();
574 NodeNumDefs =
std::min(Node->getNumValues(), NRegDefs);
581 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
589 for (;DefIdx < NodeNumDefs; ++DefIdx) {
590 if (!Node->hasAnyUseOfValue(DefIdx))
592 ValueType = Node->getSimpleValueType(DefIdx);
596 Node = Node->getGluedNode();
630 if (
N &&
N->isMachineOpcode() &&
642 if (
N->isMachineOpcode())
647 unsigned OpIdx,
SDep& dep)
const{
655 unsigned DefIdx =
Use->getOperand(OpIdx).getResNo();
656 if (
Use->isMachineOpcode())
662 unsigned Reg = cast<RegisterSDNode>(
Use->getOperand(1))->getReg();
674 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
679 dbgs() <<
"PHYS REG COPY\n";
687 GluedNodes.push_back(
N);
688 while (!GluedNodes.empty()) {
690 GluedNodes.back()->dump(
DAG);
692 GluedNodes.pop_back();
698 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
708 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
714 dbgs() <<
"**** NOOP ****\n";
730 "The number of nodes scheduled doesn't match the expected number!");
739 if (!
N->getHasDebugValue())
744 auto HasUnknownVReg = [&VRBaseMap](
SDDbgValue *DV) {
747 VRBaseMap.
count({L.getSDNode(), L.getResNo()}) == 0)
760 unsigned DVOrder = DV->getOrder();
761 if (Order != 0 && DVOrder != Order)
768 if (HasUnknownVReg(DV))
773 Orders.push_back({DVOrder, DbgMI});
786 unsigned Order =
N->getIROrder();
787 if (!Order || Seen.
count(Order)) {
800 Orders.push_back({Order, NewInsn});
808 void ScheduleDAGSDNodes::
818 assert(VRI != VRBaseMap.
end() &&
"Node emitted out of order - late");
835 bool isNew = VRBaseMap.
insert(std::make_pair(SU, VRBase)).second;
837 assert(isNew &&
"Node emitted out of order - early");
861 [&](
SDNode *Node,
bool IsClone,
bool IsCloned,
872 Emitter.
EmitNode(Node, IsClone, IsCloned, VRBaseMap);
880 if (Before ==
BB->
end()) {
886 MI = &*std::next(Before);
889 if (
MI->isCandidateForCallSiteEntry() &&
894 MI->setFlag(MachineInstr::MIFlag::NoMerge);
904 for (; PDI != PDE; ++PDI) {
910 (*PDI)->clearIsEmitted();
927 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
933 GluedNodes.push_back(
N);
934 while (!GluedNodes.empty()) {
942 if (NewInsn && NewInsn->isCall())
943 NewInsn->setHeapAllocMarker(
MF, MD);
945 GluedNodes.pop_back();
955 if (NewInsn && NewInsn->isCall())
956 NewInsn->setHeapAllocMarker(
MF, MD);
971 return LHS->getOrder() < RHS->getOrder();
977 unsigned LastOrder = 0;
978 for (
unsigned i = 0,
e = Orders.size();
i !=
e && DI != DE; ++
i) {
979 unsigned Order = Orders[
i].first;
983 for (; DI != DE; ++DI) {
984 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
986 if ((*DI)->isEmitted())
998 MI->getParent()->insert(Pos, DbgMI);
1007 for (; DI != DE; ++DI) {
1008 if ((*DI)->isEmitted())
1010 assert((*DI)->getOrder() >= LastOrder &&
1011 "emitting DBG_VALUE out of order");
1013 DbgMIs.push_back(DbgMI);
1018 InsertBB->
insert(Pos, DbgMIs.begin(), DbgMIs.end());
1024 for (
const auto &InstrOrder : Orders) {
1025 unsigned Order = InstrOrder.first;
1031 for (; DLI != DLE &&
1032 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
1043 MI->getParent()->insert(Pos, DbgMI);
1060 if (FirstTerm != InsertBB->
end()) {
1061 assert(!FirstTerm->isDebugValue() &&
1062 "first terminator cannot be a debug value");
1065 if (!
MI.isDebugValue())
1068 if (&
MI == InsertPos)
1069 InsertPos = std::prev(InsertPos->getIterator());
1073 MI.getOperand(0).ChangeToRegister(0,
false);
1074 MI.moveBefore(&*FirstTerm);
virtual void computeLatency(SUnit *SU)
computeLatency - Compute node latency.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
MachineRegisterInfo & MRI
Virtual/real register map.
Holds the information from a dbg_value node through SDISel.
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
bool isScheduleLow
True if preferable to schedule low.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDNode * getNode() const
get the SDNode which holds the desired result
void VerifyScheduledSequence(bool isBottomUp)
VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of sc...
iterator_range< value_op_iterator > op_values() const
SmallVectorImpl< SDDbgLabel * >::iterator DbgLabelIterator
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
An SDNode that represents everything that will be needed to construct a MachineInstr.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
mmo_iterator memoperands_begin() const
bool isCommutable
Is a commutable instruction.
static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost)
CheckForPhysRegDependency - Check if the dependency between def and use of a specified operand is a p...
bool getNoMergeSiteInfo(const SDNode *Node)
bool isCall
Is a function call.
Represents one node in the SelectionDAG.
bool hasDebugValues() const
Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
This class provides iterator support for SDUse operands that use a specific SDNode.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
SmallVector< SDep, 4 > Succs
All sunit successors.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SUnit * newSUnit(SDNode *N)
NewSUnit - Creates a new SUnit and return a ptr to it.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Holds the information for a single machine location through SDISel; either an SDNode,...
LLVM_NODISCARD T pop_back_val()
unsigned const TargetRegisterInfo * TRI
ScheduleDAGSDNodes(MachineFunction &mf)
SDDbgInfo::DbgIterator DbgBegin() const
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD)
< i1 > br i1 label label bb bb
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
TargetInstrInfo - Interface to description of machine instruction set.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isScheduleHigh
True if preferable to schedule high.
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
const TargetLowering & getTargetLoweringInfo() const
unsigned short Latency
Node latency.
Function object to check whether the first component of a std::pair compares less than the first comp...
std::string getDAGName() const override
Return the basic block label.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
const InstrItineraryData * InstrItins
unsigned NodeNum
Entry # of node in the node vector.
MachineBasicBlock::iterator getInsertPos()
getInsertPos - Return the current insertion position.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
SDDbgInfo::DbgLabelIterator DbgLabelBegin() const
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef< EVT > VTs, SDValue ExtraOper=SDValue())
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
STATISTIC(NumFunctions, "Total number of functions")
@ Data
Regular data dependence (aka true-dependence).
bool isVRegCycle
May use and def the same vreg.
SUnit * OrigNode
If not this, the node from which this node was cloned.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
bool hasPhysRegClobbers
Has any physreg defs, used or not.
bool isCallOp
Is a function call operand.
unsigned VerifyScheduledDAG(bool isBottomUp)
Verifies that all SUnits were scheduled and that their state is consistent.
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
virtual void computeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
virtual bool forceUnitLatencies() const
ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one.
CallSiteInfo getSDCallSiteInfo(const SDNode *CallNode)
static cl::opt< int > HighLatencyCycles("sched-high-latency-cycles", cl::Hidden, cl::init(10), cl::desc("Roughly estimate the number of cycles that 'long latency'" "instructions take for targets with no itinerary"))
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SDDbgInfo::DbgIterator ByvalParmDbgBegin() const
bool mayLoad() const
Return true if this instruction could possibly read memory.
SUnit * Clone(SUnit *Old)
Clone - Creates a clone of the specified SUnit.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
MachineBasicBlock * getBlock()
getBlock - Return the current basic block.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
void addCallArgsForwardingRegs(const MachineInstr *CallI, CallSiteInfoImpl &&CallInfo)
Start tracking the arguments passed to the call CallI.
const TargetRegisterClass * CopyDstRC
Is a special copy node if != nullptr.
Representation of each machine instruction.
unsigned short NumRegDefsLeft
bool isCall() const
Return true if the instruction is a call.
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
void setNode(SDNode *N)
Assigns the representative SDNode for this SUnit.
const SDValue & getOperand(unsigned Num) const
unsigned getReg() const
Returns the register associated with this edge.
iterator_range< allnodes_iterator > allnodes()
initializer< Ty > init(const Ty &Val)
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
void dump() const
Dump this node, for debugging.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int getNodeId() const
Return the unique node id.
unsigned getResNo() const
get the index which selects a specific result in the SDNode
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
void dumpNodeAll(const SUnit &SU) const
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, SmallVectorImpl< std::pair< unsigned, MachineInstr * > > &Orders, DenseMap< SDValue, Register > &VRBaseMap, unsigned Order)
ProcessSDDbgValues - Process SDDbgValues associated with this node.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
const TargetRegisterInfo * TRI
Target processor register info.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
static use_iterator use_end()
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
MachineFunction & MF
Machine function.
@ Barrier
An unknown scheduling barrier.
static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, DenseMap< SDValue, Register > &VRBaseMap, SmallVectorImpl< std::pair< unsigned, MachineInstr * >> &Orders, SmallSet< Register, 8 > &Seen, MachineInstr *NewInsn)
SUnit EntrySU
Special node for the region entry.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
TargetSubtargetInfo - Generic base class for all target subtargets.
Sched::Preference SchedulingPref
Scheduling preference.
MachineInstr & instr_front()
Wrapper class representing virtual and physical registers.
RegDefIter - In place iteration over the values defined by an SUnit.
void dumpSchedule() const
unsigned EmitCallSiteInfo
The flag enables call site info production.
SDDbgInfo::DbgIterator ByvalParmDbgEnd() const
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap< SDValue, Register > &VRBaseMap)
EmitNode - Generate machine code for a node and needed dependencies.
std::vector< SUnit > SUnits
The scheduling units.
void stable_sort(R &&Range)
void assign(size_type NumElts, ValueParamT Elt)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Iterator for intrusive lists based on ilist_node.
SDNode * getNode() const
Returns the representative SDNode for this SUnit.
void setLatency(unsigned Lat)
Sets the latency for this edge.
const TargetInstrInfo * TII
Target instruction information.
void sort(IteratorTy Start, IteratorTy End)
@ SDNODE
Value is the result of an expression.
mmo_iterator memoperands_end() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
bool hasPhysRegDefs
Has physreg defs that are being used.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
bool isTwoAddress
Is a two-address instruction.
bool isCloned
True if this node has been cloned.
SDDbgInfo::DbgIterator DbgEnd() const
Kind getKind() const
Returns an enum value representing the kind of the dependence.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG)
void dump() const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void dumpNode(const SUnit &SU) const override
void dumpNodeName(const SUnit &SU) const
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Scheduling unit. This is a node in the scheduling DAG.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MDNode * getHeapAllocSite(const SDNode *Node)
Return the HeapAllocSite type associated with the SDNode, if it exists.
Value * getOperand(unsigned i) const
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
std::vector< SUnit * > Sequence
The schedule. Null SUnit*'s represent noop instructions.
SmallVectorImpl< SDDbgValue * >::iterator DbgIterator
void BuildSchedGraph(AAResults *AA)
BuildSchedGraph - Build the SUnit graph from the selection dag that we are input.
void InitNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
bool isEmpty() const
Returns true if there are no itineraries.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
static bool isPassiveNode(SDNode *Node)
isPassiveNode - Return true if the node is a non-scheduled leaf.
bool isCtrl() const
Shorthand for getKind() != SDep::Data.
void clearDAG()
Clears the DAG state (between regions).
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const TargetMachine & getTarget() const
SUnit ExitSU
Special node for the region exit.
SDDbgInfo::DbgLabelIterator DbgLabelEnd() const
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
SDNode * getGluedNode() const
If this node has a glue operand, return the node to which the glue operand points.
A Use represents the edge between a Value definition and its users.
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG)