LLVM  15.0.0git
ScheduleDAGSDNodes.cpp
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1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the ScheduleDAG class, which is a base class used by
10 // scheduling implementation classes.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ScheduleDAGSDNodes.h"
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Config/llvm-config.h"
32 #include "llvm/Support/Debug.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "pre-RA-sched"
38 
39 STATISTIC(LoadsClustered, "Number of loads clustered together");
40 
41 // This allows the latency-based scheduler to notice high latency instructions
42 // without a target itinerary. The choice of number here has more to do with
43 // balancing scheduler heuristics than with the actual machine latency.
45  "sched-high-latency-cycles", cl::Hidden, cl::init(10),
46  cl::desc("Roughly estimate the number of cycles that 'long latency'"
47  "instructions take for targets with no itinerary"));
48 
50  : ScheduleDAG(mf), InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
51 
52 /// Run - perform scheduling.
53 ///
55  BB = bb;
56  DAG = dag;
57 
58  // Clear the scheduler's SUnit DAG.
60  Sequence.clear();
61 
62  // Invoke the target's selection of scheduler.
63  Schedule();
64 }
65 
66 /// NewSUnit - Creates a new SUnit and return a ptr to it.
67 ///
69 #ifndef NDEBUG
70  const SUnit *Addr = nullptr;
71  if (!SUnits.empty())
72  Addr = &SUnits[0];
73 #endif
74  SUnits.emplace_back(N, (unsigned)SUnits.size());
75  assert((Addr == nullptr || Addr == &SUnits[0]) &&
76  "SUnits std::vector reallocated on the fly!");
77  SUnits.back().OrigNode = &SUnits.back();
78  SUnit *SU = &SUnits.back();
80  if (!N ||
81  (N->isMachineOpcode() &&
82  N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
84  else
86  return SU;
87 }
88 
90  SUnit *SU = newSUnit(Old->getNode());
91  SU->OrigNode = Old->OrigNode;
92  SU->Latency = Old->Latency;
93  SU->isVRegCycle = Old->isVRegCycle;
94  SU->isCall = Old->isCall;
95  SU->isCallOp = Old->isCallOp;
96  SU->isTwoAddress = Old->isTwoAddress;
97  SU->isCommutable = Old->isCommutable;
98  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
100  SU->isScheduleHigh = Old->isScheduleHigh;
101  SU->isScheduleLow = Old->isScheduleLow;
102  SU->SchedulingPref = Old->SchedulingPref;
103  Old->isCloned = true;
104  return SU;
105 }
106 
107 /// CheckForPhysRegDependency - Check if the dependency between def and use of
108 /// a specified operand is a physical register dependency. If so, returns the
109 /// register and the cost of copying the register.
111  const TargetRegisterInfo *TRI,
112  const TargetInstrInfo *TII,
113  unsigned &PhysReg, int &Cost) {
114  if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
115  return;
116 
117  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119  return;
120 
121  unsigned ResNo = User->getOperand(2).getResNo();
122  if (Def->getOpcode() == ISD::CopyFromReg &&
123  cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
124  PhysReg = Reg;
125  } else if (Def->isMachineOpcode()) {
126  const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
127  if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg))
128  PhysReg = Reg;
129  }
130 
131  if (PhysReg != 0) {
132  const TargetRegisterClass *RC =
133  TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
134  Cost = RC->getCopyCost();
135  }
136 }
137 
138 // Helper for AddGlue to clone node operands.
140  SDValue ExtraOper = SDValue()) {
141  SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
142  if (ExtraOper.getNode())
143  Ops.push_back(ExtraOper);
144 
145  SDVTList VTList = DAG->getVTList(VTs);
146  MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
147 
148  // Store memory references.
150  if (MN)
151  MMOs.assign(MN->memoperands_begin(), MN->memoperands_end());
152 
153  DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
154 
155  // Reset the memory references
156  if (MN)
157  DAG->setNodeMemRefs(MN, MMOs);
158 }
159 
160 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
161  SDNode *GlueDestNode = Glue.getNode();
162 
163  // Don't add glue from a node to itself.
164  if (GlueDestNode == N) return false;
165 
166  // Don't add a glue operand to something that already uses glue.
167  if (GlueDestNode &&
168  N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
169  return false;
170  }
171  // Don't add glue to something that already has a glue value.
172  if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
173 
174  SmallVector<EVT, 4> VTs(N->values());
175  if (AddGlue)
176  VTs.push_back(MVT::Glue);
177 
178  CloneNodeWithValues(N, DAG, VTs, Glue);
179 
180  return true;
181 }
182 
183 // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
184 // node even though simply shrinking the value list is sufficient.
185 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
186  assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
187  !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
188  "expected an unused glue value");
189 
190  CloneNodeWithValues(N, DAG,
191  makeArrayRef(N->value_begin(), N->getNumValues() - 1));
192 }
193 
194 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
195 /// This function finds loads of the same base and different offsets. If the
196 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
197 /// outputs to ensure they are scheduled together and in order. This
198 /// optimization may benefit some targets by improving cache locality.
199 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
200  SDValue Chain;
201  unsigned NumOps = Node->getNumOperands();
202  if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
203  Chain = Node->getOperand(NumOps-1);
204  if (!Chain)
205  return;
206 
207  // Skip any load instruction that has a tied input. There may be an additional
208  // dependency requiring a different order than by increasing offsets, and the
209  // added glue may introduce a cycle.
210  auto hasTiedInput = [this](const SDNode *N) {
211  const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
212  for (unsigned I = 0; I != MCID.getNumOperands(); ++I) {
213  if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1)
214  return true;
215  }
216 
217  return false;
218  };
219 
220  // Look for other loads of the same chain. Find loads that are loading from
221  // the same base pointer and different offsets.
222  SmallPtrSet<SDNode*, 16> Visited;
224  DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
225  bool Cluster = false;
226  SDNode *Base = Node;
227 
228  if (hasTiedInput(Base))
229  return;
230 
231  // This algorithm requires a reasonably low use count before finding a match
232  // to avoid uselessly blowing up compile time in large blocks.
233  unsigned UseCount = 0;
234  for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
235  I != E && UseCount < 100; ++I, ++UseCount) {
236  if (I.getUse().getResNo() != Chain.getResNo())
237  continue;
238 
239  SDNode *User = *I;
240  if (User == Node || !Visited.insert(User).second)
241  continue;
242  int64_t Offset1, Offset2;
243  if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
244  Offset1 == Offset2 ||
245  hasTiedInput(User)) {
246  // FIXME: Should be ok if they addresses are identical. But earlier
247  // optimizations really should have eliminated one of the loads.
248  continue;
249  }
250  if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
251  Offsets.push_back(Offset1);
252  O2SMap.insert(std::make_pair(Offset2, User));
253  Offsets.push_back(Offset2);
254  if (Offset2 < Offset1)
255  Base = User;
256  Cluster = true;
257  // Reset UseCount to allow more matches.
258  UseCount = 0;
259  }
260 
261  if (!Cluster)
262  return;
263 
264  // Sort them in increasing order.
266 
267  // Check if the loads are close enough.
269  unsigned NumLoads = 0;
270  int64_t BaseOff = Offsets[0];
271  SDNode *BaseLoad = O2SMap[BaseOff];
272  Loads.push_back(BaseLoad);
273  for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
274  int64_t Offset = Offsets[i];
275  SDNode *Load = O2SMap[Offset];
276  if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
277  break; // Stop right here. Ignore loads that are further away.
278  Loads.push_back(Load);
279  ++NumLoads;
280  }
281 
282  if (NumLoads == 0)
283  return;
284 
285  // Cluster loads by adding MVT::Glue outputs and inputs. This also
286  // ensure they are scheduled in order of increasing addresses.
287  SDNode *Lead = Loads[0];
288  SDValue InGlue;
289  if (AddGlue(Lead, InGlue, true, DAG))
290  InGlue = SDValue(Lead, Lead->getNumValues() - 1);
291  for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
292  bool OutGlue = I < E - 1;
293  SDNode *Load = Loads[I];
294 
295  // If AddGlue fails, we could leave an unsused glue value. This should not
296  // cause any
297  if (AddGlue(Load, InGlue, OutGlue, DAG)) {
298  if (OutGlue)
299  InGlue = SDValue(Load, Load->getNumValues() - 1);
300 
301  ++LoadsClustered;
302  }
303  else if (!OutGlue && InGlue.getNode())
304  RemoveUnusedGlue(InGlue.getNode(), DAG);
305  }
306 }
307 
308 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
309 ///
310 void ScheduleDAGSDNodes::ClusterNodes() {
311  for (SDNode &NI : DAG->allnodes()) {
312  SDNode *Node = &NI;
313  if (!Node || !Node->isMachineOpcode())
314  continue;
315 
316  unsigned Opc = Node->getMachineOpcode();
317  const MCInstrDesc &MCID = TII->get(Opc);
318  if (MCID.mayLoad())
319  // Cluster loads from "near" addresses into combined SUnits.
320  ClusterNeighboringLoads(Node);
321  }
322 }
323 
324 void ScheduleDAGSDNodes::BuildSchedUnits() {
325  // During scheduling, the NodeId field of SDNode is used to map SDNodes
326  // to their associated SUnits by holding SUnits table indices. A value
327  // of -1 means the SDNode does not yet have an associated SUnit.
328  unsigned NumNodes = 0;
329  for (SDNode &NI : DAG->allnodes()) {
330  NI.setNodeId(-1);
331  ++NumNodes;
332  }
333 
334  // Reserve entries in the vector for each of the SUnits we are creating. This
335  // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
336  // invalidated.
337  // FIXME: Multiply by 2 because we may clone nodes during scheduling.
338  // This is a temporary workaround.
339  SUnits.reserve(NumNodes * 2);
340 
341  // Add all nodes in depth first order.
342  SmallVector<SDNode*, 64> Worklist;
343  SmallPtrSet<SDNode*, 32> Visited;
344  Worklist.push_back(DAG->getRoot().getNode());
345  Visited.insert(DAG->getRoot().getNode());
346 
347  SmallVector<SUnit*, 8> CallSUnits;
348  while (!Worklist.empty()) {
349  SDNode *NI = Worklist.pop_back_val();
350 
351  // Add all operands to the worklist unless they've already been added.
352  for (const SDValue &Op : NI->op_values())
353  if (Visited.insert(Op.getNode()).second)
354  Worklist.push_back(Op.getNode());
355 
356  if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
357  continue;
358 
359  // If this node has already been processed, stop now.
360  if (NI->getNodeId() != -1) continue;
361 
362  SUnit *NodeSUnit = newSUnit(NI);
363 
364  // See if anything is glued to this node, if so, add them to glued
365  // nodes. Nodes can have at most one glue input and one glue output. Glue
366  // is required to be the last operand and result of a node.
367 
368  // Scan up to find glued preds.
369  SDNode *N = NI;
370  while (N->getNumOperands() &&
371  N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
372  N = N->getOperand(N->getNumOperands()-1).getNode();
373  assert(N->getNodeId() == -1 && "Node already inserted!");
374  N->setNodeId(NodeSUnit->NodeNum);
375  if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
376  NodeSUnit->isCall = true;
377  }
378 
379  // Scan down to find any glued succs.
380  N = NI;
381  while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
382  SDValue GlueVal(N, N->getNumValues()-1);
383 
384  // There are either zero or one users of the Glue result.
385  bool HasGlueUse = false;
386  for (SDNode *U : N->uses())
387  if (GlueVal.isOperandOf(U)) {
388  HasGlueUse = true;
389  assert(N->getNodeId() == -1 && "Node already inserted!");
390  N->setNodeId(NodeSUnit->NodeNum);
391  N = U;
392  if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
393  NodeSUnit->isCall = true;
394  break;
395  }
396  if (!HasGlueUse) break;
397  }
398 
399  if (NodeSUnit->isCall)
400  CallSUnits.push_back(NodeSUnit);
401 
402  // Schedule zero-latency TokenFactor below any nodes that may increase the
403  // schedule height. Otherwise, ancestors of the TokenFactor may appear to
404  // have false stalls.
405  if (NI->getOpcode() == ISD::TokenFactor)
406  NodeSUnit->isScheduleLow = true;
407 
408  // If there are glue operands involved, N is now the bottom-most node
409  // of the sequence of nodes that are glued together.
410  // Update the SUnit.
411  NodeSUnit->setNode(N);
412  assert(N->getNodeId() == -1 && "Node already inserted!");
413  N->setNodeId(NodeSUnit->NodeNum);
414 
415  // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
416  InitNumRegDefsLeft(NodeSUnit);
417 
418  // Assign the Latency field of NodeSUnit using target-provided information.
419  computeLatency(NodeSUnit);
420  }
421 
422  // Find all call operands.
423  while (!CallSUnits.empty()) {
424  SUnit *SU = CallSUnits.pop_back_val();
425  for (const SDNode *SUNode = SU->getNode(); SUNode;
426  SUNode = SUNode->getGluedNode()) {
427  if (SUNode->getOpcode() != ISD::CopyToReg)
428  continue;
429  SDNode *SrcN = SUNode->getOperand(2).getNode();
430  if (isPassiveNode(SrcN)) continue; // Not scheduled.
431  SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
432  SrcSU->isCallOp = true;
433  }
434  }
435 }
436 
437 void ScheduleDAGSDNodes::AddSchedEdges() {
439 
440  // Check to see if the scheduler cares about latencies.
441  bool UnitLatencies = forceUnitLatencies();
442 
443  // Pass 2: add the preds, succs, etc.
444  for (SUnit &SU : SUnits) {
445  SDNode *MainNode = SU.getNode();
446 
447  if (MainNode->isMachineOpcode()) {
448  unsigned Opc = MainNode->getMachineOpcode();
449  const MCInstrDesc &MCID = TII->get(Opc);
450  for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
451  if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
452  SU.isTwoAddress = true;
453  break;
454  }
455  }
456  if (MCID.isCommutable())
457  SU.isCommutable = true;
458  }
459 
460  // Find all predecessors and successors of the group.
461  for (SDNode *N = SU.getNode(); N; N = N->getGluedNode()) {
462  if (N->isMachineOpcode() &&
463  TII->get(N->getMachineOpcode()).getImplicitDefs()) {
464  SU.hasPhysRegClobbers = true;
465  unsigned NumUsed = InstrEmitter::CountResults(N);
466  while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
467  --NumUsed; // Skip over unused values at the end.
468  if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
469  SU.hasPhysRegDefs = true;
470  }
471 
472  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
473  SDNode *OpN = N->getOperand(i).getNode();
474  unsigned DefIdx = N->getOperand(i).getResNo();
475  if (isPassiveNode(OpN)) continue; // Not scheduled.
476  SUnit *OpSU = &SUnits[OpN->getNodeId()];
477  assert(OpSU && "Node has no SUnit!");
478  if (OpSU == &SU)
479  continue; // In the same group.
480 
481  EVT OpVT = N->getOperand(i).getValueType();
482  assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
483  bool isChain = OpVT == MVT::Other;
484 
485  unsigned PhysReg = 0;
486  int Cost = 1;
487  // Determine if this is a physical register dependency.
488  CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
489  assert((PhysReg == 0 || !isChain) &&
490  "Chain dependence via physreg data?");
491  // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
492  // emits a copy from the physical register to a virtual register unless
493  // it requires a cross class copy (cost < 0). That means we are only
494  // treating "expensive to copy" register dependency as physical register
495  // dependency. This may change in the future though.
496  if (Cost >= 0 && !StressSched)
497  PhysReg = 0;
498 
499  // If this is a ctrl dep, latency is 1.
500  unsigned OpLatency = isChain ? 1 : OpSU->Latency;
501  // Special-case TokenFactor chains as zero-latency.
502  if(isChain && OpN->getOpcode() == ISD::TokenFactor)
503  OpLatency = 0;
504 
505  SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
506  : SDep(OpSU, SDep::Data, PhysReg);
507  Dep.setLatency(OpLatency);
508  if (!isChain && !UnitLatencies) {
509  computeOperandLatency(OpN, N, i, Dep);
510  ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep);
511  }
512 
513  if (!SU.addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
514  // Multiple register uses are combined in the same SUnit. For example,
515  // we could have a set of glued nodes with all their defs consumed by
516  // another set of glued nodes. Register pressure tracking sees this as
517  // a single use, so to keep pressure balanced we reduce the defs.
518  //
519  // We can't tell (without more book-keeping) if this results from
520  // glued nodes or duplicate operands. As long as we don't reduce
521  // NumRegDefsLeft to zero, we handle the common cases well.
522  --OpSU->NumRegDefsLeft;
523  }
524  }
525  }
526  }
527 }
528 
529 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
530 /// are input. This SUnit graph is similar to the SelectionDAG, but
531 /// excludes nodes that aren't interesting to scheduling, and represents
532 /// glued together nodes with a single SUnit.
534  // Cluster certain nodes which should be scheduled together.
535  ClusterNodes();
536  // Populate the SUnits array.
537  BuildSchedUnits();
538  // Compute all the scheduling dependencies between nodes.
539  AddSchedEdges();
540 }
541 
542 // Initialize NumNodeDefs for the current Node's opcode.
543 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
544  // Check for phys reg copy.
545  if (!Node)
546  return;
547 
548  if (!Node->isMachineOpcode()) {
549  if (Node->getOpcode() == ISD::CopyFromReg)
550  NodeNumDefs = 1;
551  else
552  NodeNumDefs = 0;
553  return;
554  }
555  unsigned POpc = Node->getMachineOpcode();
556  if (POpc == TargetOpcode::IMPLICIT_DEF) {
557  // No register need be allocated for this.
558  NodeNumDefs = 0;
559  return;
560  }
561  if (POpc == TargetOpcode::PATCHPOINT &&
562  Node->getValueType(0) == MVT::Other) {
563  // PATCHPOINT is defined to have one result, but it might really have none
564  // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
565  // real definition.
566  NodeNumDefs = 0;
567  return;
568  }
569  unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
570  // Some instructions define regs that are not represented in the selection DAG
571  // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
572  NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
573  DefIdx = 0;
574 }
575 
576 // Construct a RegDefIter for this SUnit and find the first valid value.
578  const ScheduleDAGSDNodes *SD)
579  : SchedDAG(SD), Node(SU->getNode()) {
580  InitNodeNumDefs();
581  Advance();
582 }
583 
584 // Advance to the next valid value defined by the SUnit.
586  for (;Node;) { // Visit all glued nodes.
587  for (;DefIdx < NodeNumDefs; ++DefIdx) {
588  if (!Node->hasAnyUseOfValue(DefIdx))
589  continue;
590  ValueType = Node->getSimpleValueType(DefIdx);
591  ++DefIdx;
592  return; // Found a normal regdef.
593  }
594  Node = Node->getGluedNode();
595  if (!Node) {
596  return; // No values left to visit.
597  }
598  InitNodeNumDefs();
599  }
600 }
601 
603  assert(SU->NumRegDefsLeft == 0 && "expect a new node");
604  for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
605  assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
606  ++SU->NumRegDefsLeft;
607  }
608 }
609 
611  SDNode *N = SU->getNode();
612 
613  // TokenFactor operands are considered zero latency, and some schedulers
614  // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
615  // whenever node latency is nonzero.
616  if (N && N->getOpcode() == ISD::TokenFactor) {
617  SU->Latency = 0;
618  return;
619  }
620 
621  // Check to see if the scheduler cares about latencies.
622  if (forceUnitLatencies()) {
623  SU->Latency = 1;
624  return;
625  }
626 
627  if (!InstrItins || InstrItins->isEmpty()) {
628  if (N && N->isMachineOpcode() &&
629  TII->isHighLatencyDef(N->getMachineOpcode()))
631  else
632  SU->Latency = 1;
633  return;
634  }
635 
636  // Compute the latency for the node. We use the sum of the latencies for
637  // all nodes glued together into this SUnit.
638  SU->Latency = 0;
639  for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
640  if (N->isMachineOpcode())
642 }
643 
645  unsigned OpIdx, SDep& dep) const{
646  // Check to see if the scheduler cares about latencies.
647  if (forceUnitLatencies())
648  return;
649 
650  if (dep.getKind() != SDep::Data)
651  return;
652 
653  unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
654  if (Use->isMachineOpcode())
655  // Adjust the use operand index by num of defs.
656  OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
657  int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
658  if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
659  !BB->succ_empty()) {
660  unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
662  // This copy is a liveout value. It is likely coalesced, so reduce the
663  // latency so not to penalize the def.
664  // FIXME: need target specific adjustment here?
665  Latency = (Latency > 1) ? Latency - 1 : 1;
666  }
667  if (Latency >= 0)
668  dep.setLatency(Latency);
669 }
670 
671 void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const {
672 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
673  dumpNodeName(SU);
674  dbgs() << ": ";
675 
676  if (!SU.getNode()) {
677  dbgs() << "PHYS REG COPY\n";
678  return;
679  }
680 
681  SU.getNode()->dump(DAG);
682  dbgs() << "\n";
683  SmallVector<SDNode *, 4> GluedNodes;
684  for (SDNode *N = SU.getNode()->getGluedNode(); N; N = N->getGluedNode())
685  GluedNodes.push_back(N);
686  while (!GluedNodes.empty()) {
687  dbgs() << " ";
688  GluedNodes.back()->dump(DAG);
689  dbgs() << "\n";
690  GluedNodes.pop_back();
691  }
692 #endif
693 }
694 
696 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
697  if (EntrySU.getNode() != nullptr)
699  for (const SUnit &SU : SUnits)
700  dumpNodeAll(SU);
701  if (ExitSU.getNode() != nullptr)
703 #endif
704 }
705 
706 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
708  for (const SUnit *SU : Sequence) {
709  if (SU)
710  dumpNode(*SU);
711  else
712  dbgs() << "**** NOOP ****\n";
713  }
714 }
715 #endif
716 
717 #ifndef NDEBUG
718 /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
719 /// their state is consistent with the nodes listed in Sequence.
720 ///
722  unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
723  unsigned Noops = llvm::count(Sequence, nullptr);
724  assert(Sequence.size() - Noops == ScheduledNodes &&
725  "The number of nodes scheduled doesn't match the expected number!");
726 }
727 #endif // NDEBUG
728 
729 /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
730 static void
732  SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
733  DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) {
734  if (!N->getHasDebugValue())
735  return;
736 
737  /// Returns true if \p DV has any VReg operand locations which don't exist in
738  /// VRBaseMap.
739  auto HasUnknownVReg = [&VRBaseMap](SDDbgValue *DV) {
740  for (const SDDbgOperand &L : DV->getLocationOps()) {
741  if (L.getKind() == SDDbgOperand::SDNODE &&
742  VRBaseMap.count({L.getSDNode(), L.getResNo()}) == 0)
743  return true;
744  }
745  return false;
746  };
747 
748  // Opportunistically insert immediate dbg_value uses, i.e. those with the same
749  // source order number as N.
750  MachineBasicBlock *BB = Emitter.getBlock();
751  MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
752  for (auto DV : DAG->GetDbgValues(N)) {
753  if (DV->isEmitted())
754  continue;
755  unsigned DVOrder = DV->getOrder();
756  if (Order != 0 && DVOrder != Order)
757  continue;
758  // If DV has any VReg location operands which haven't been mapped then
759  // either that node is no longer available or we just haven't visited the
760  // node yet. In the former case we should emit an undef dbg_value, but we
761  // can do it later. And for the latter we'll want to wait until all
762  // dependent nodes have been visited.
763  if (!DV->isInvalidated() && HasUnknownVReg(DV))
764  continue;
765  MachineInstr *DbgMI = Emitter.EmitDbgValue(DV, VRBaseMap);
766  if (!DbgMI)
767  continue;
768  Orders.push_back({DVOrder, DbgMI});
769  BB->insert(InsertPos, DbgMI);
770  }
771 }
772 
773 // ProcessSourceNode - Process nodes with source order numbers. These are added
774 // to a vector which EmitSchedule uses to determine how to insert dbg_value
775 // instructions in the right order.
776 static void
778  DenseMap<SDValue, Register> &VRBaseMap,
779  SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders,
780  SmallSet<Register, 8> &Seen, MachineInstr *NewInsn) {
781  unsigned Order = N->getIROrder();
782  if (!Order || Seen.count(Order)) {
783  // Process any valid SDDbgValues even if node does not have any order
784  // assigned.
785  ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
786  return;
787  }
788 
789  // If a new instruction was generated for this Order number, record it.
790  // Otherwise, leave this order number unseen: we will either find later
791  // instructions for it, or leave it unseen if there were no instructions at
792  // all.
793  if (NewInsn) {
794  Seen.insert(Order);
795  Orders.push_back({Order, NewInsn});
796  }
797 
798  // Even if no instruction was generated, a Value may have become defined via
799  // earlier nodes. Try to process them now.
800  ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
801 }
802 
803 void ScheduleDAGSDNodes::
804 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
805  MachineBasicBlock::iterator InsertPos) {
806  for (const SDep &Pred : SU->Preds) {
807  if (Pred.isCtrl())
808  continue; // ignore chain preds
809  if (Pred.getSUnit()->CopyDstRC) {
810  // Copy to physical register.
812  VRBaseMap.find(Pred.getSUnit());
813  assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
814  // Find the destination physical register.
815  Register Reg;
816  for (const SDep &Succ : SU->Succs) {
817  if (Succ.isCtrl())
818  continue; // ignore chain preds
819  if (Succ.getReg()) {
820  Reg = Succ.getReg();
821  break;
822  }
823  }
824  BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
825  .addReg(VRI->second);
826  } else {
827  // Copy from physical register.
828  assert(Pred.getReg() && "Unknown physical register!");
830  bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
831  (void)isNew; // Silence compiler warning.
832  assert(isNew && "Node emitted out of order - early");
833  BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
834  .addReg(Pred.getReg());
835  }
836  break;
837  }
838 }
839 
840 /// EmitSchedule - Emit the machine code in scheduled order. Return the new
841 /// InsertPos and MachineBasicBlock that contains this insertion
842 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
843 /// not necessarily refer to returned BB. The emitter may split blocks.
846  InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos,
848  DenseMap<SDValue, Register> VRBaseMap;
849  DenseMap<SUnit*, Register> CopyVRBaseMap;
852  bool HasDbg = DAG->hasDebugValues();
853 
854  // Emit a node, and determine where its first instruction is for debuginfo.
855  // Zero, one, or multiple instructions can be created when emitting a node.
856  auto EmitNode =
857  [&](SDNode *Node, bool IsClone, bool IsCloned,
858  DenseMap<SDValue, Register> &VRBaseMap) -> MachineInstr * {
859  // Fetch instruction prior to this, or end() if nonexistant.
860  auto GetPrevInsn = [&](MachineBasicBlock::iterator I) {
861  if (I == BB->begin())
862  return BB->end();
863  else
864  return std::prev(Emitter.getInsertPos());
865  };
866 
867  MachineBasicBlock::iterator Before = GetPrevInsn(Emitter.getInsertPos());
868  Emitter.EmitNode(Node, IsClone, IsCloned, VRBaseMap);
869  MachineBasicBlock::iterator After = GetPrevInsn(Emitter.getInsertPos());
870 
871  // If the iterator did not change, no instructions were inserted.
872  if (Before == After)
873  return nullptr;
874 
875  MachineInstr *MI;
876  if (Before == BB->end()) {
877  // There were no prior instructions; the new ones must start at the
878  // beginning of the block.
879  MI = &Emitter.getBlock()->instr_front();
880  } else {
881  // Return first instruction after the pre-existing instructions.
882  MI = &*std::next(Before);
883  }
884 
885  if (MI->isCandidateForCallSiteEntry() &&
888 
889  if (DAG->getNoMergeSiteInfo(Node)) {
890  MI->setFlag(MachineInstr::MIFlag::NoMerge);
891  }
892 
893  return MI;
894  };
895 
896  // If this is the first BB, emit byval parameter dbg_value's.
897  if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
900  for (; PDI != PDE; ++PDI) {
901  MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
902  if (DbgMI) {
903  BB->insert(InsertPos, DbgMI);
904  // We re-emit the dbg_value closer to its use, too, after instructions
905  // are emitted to the BB.
906  (*PDI)->clearIsEmitted();
907  }
908  }
909  }
910 
911  for (SUnit *SU : Sequence) {
912  if (!SU) {
913  // Null SUnit* is a noop.
914  TII->insertNoop(*Emitter.getBlock(), InsertPos);
915  continue;
916  }
917 
918  // For pre-regalloc scheduling, create instructions corresponding to the
919  // SDNode and any glued SDNodes and append them to the block.
920  if (!SU->getNode()) {
921  // Emit a copy.
922  EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
923  continue;
924  }
925 
926  SmallVector<SDNode *, 4> GluedNodes;
927  for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
928  GluedNodes.push_back(N);
929  while (!GluedNodes.empty()) {
930  SDNode *N = GluedNodes.back();
931  auto NewInsn = EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap);
932  // Remember the source order of the inserted instruction.
933  if (HasDbg)
934  ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn);
935 
936  if (MDNode *MD = DAG->getHeapAllocSite(N))
937  if (NewInsn && NewInsn->isCall())
938  NewInsn->setHeapAllocMarker(MF, MD);
939 
940  GluedNodes.pop_back();
941  }
942  auto NewInsn =
943  EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
944  // Remember the source order of the inserted instruction.
945  if (HasDbg)
946  ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen,
947  NewInsn);
948 
949  if (MDNode *MD = DAG->getHeapAllocSite(SU->getNode())) {
950  if (NewInsn && NewInsn->isCall())
951  NewInsn->setHeapAllocMarker(MF, MD);
952  }
953  }
954 
955  // Insert all the dbg_values which have not already been inserted in source
956  // order sequence.
957  if (HasDbg) {
959 
960  // Sort the source order instructions and use the order to insert debug
961  // values. Use stable_sort so that DBG_VALUEs are inserted in the same order
962  // regardless of the host's implementation fo std::sort.
963  llvm::stable_sort(Orders, less_first());
965  [](const SDDbgValue *LHS, const SDDbgValue *RHS) {
966  return LHS->getOrder() < RHS->getOrder();
967  });
968 
971  // Now emit the rest according to source order.
972  unsigned LastOrder = 0;
973  for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
974  unsigned Order = Orders[i].first;
975  MachineInstr *MI = Orders[i].second;
976  // Insert all SDDbgValue's whose order(s) are before "Order".
977  assert(MI);
978  for (; DI != DE; ++DI) {
979  if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
980  break;
981  if ((*DI)->isEmitted())
982  continue;
983 
984  MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
985  if (DbgMI) {
986  if (!LastOrder)
987  // Insert to start of the BB (after PHIs).
988  BB->insert(BBBegin, DbgMI);
989  else {
990  // Insert at the instruction, which may be in a different
991  // block, if the block was split by a custom inserter.
993  MI->getParent()->insert(Pos, DbgMI);
994  }
995  }
996  }
997  LastOrder = Order;
998  }
999  // Add trailing DbgValue's before the terminator. FIXME: May want to add
1000  // some of them before one or more conditional branches?
1002  for (; DI != DE; ++DI) {
1003  if ((*DI)->isEmitted())
1004  continue;
1005  assert((*DI)->getOrder() >= LastOrder &&
1006  "emitting DBG_VALUE out of order");
1007  if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
1008  DbgMIs.push_back(DbgMI);
1009  }
1010 
1011  MachineBasicBlock *InsertBB = Emitter.getBlock();
1013  InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
1014 
1017  // Now emit the rest according to source order.
1018  LastOrder = 0;
1019  for (const auto &InstrOrder : Orders) {
1020  unsigned Order = InstrOrder.first;
1021  MachineInstr *MI = InstrOrder.second;
1022  if (!MI)
1023  continue;
1024 
1025  // Insert all SDDbgLabel's whose order(s) are before "Order".
1026  for (; DLI != DLE &&
1027  (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
1028  ++DLI) {
1029  MachineInstr *DbgMI = Emitter.EmitDbgLabel(*DLI);
1030  if (DbgMI) {
1031  if (!LastOrder)
1032  // Insert to start of the BB (after PHIs).
1033  BB->insert(BBBegin, DbgMI);
1034  else {
1035  // Insert at the instruction, which may be in a different
1036  // block, if the block was split by a custom inserter.
1038  MI->getParent()->insert(Pos, DbgMI);
1039  }
1040  }
1041  }
1042  if (DLI == DLE)
1043  break;
1044 
1045  LastOrder = Order;
1046  }
1047  }
1048 
1049  InsertPos = Emitter.getInsertPos();
1050  // In some cases, DBG_VALUEs might be inserted after the first terminator,
1051  // which results in an invalid MBB. If that happens, move the DBG_VALUEs
1052  // before the first terminator.
1053  MachineBasicBlock *InsertBB = Emitter.getBlock();
1054  auto FirstTerm = InsertBB->getFirstTerminator();
1055  if (FirstTerm != InsertBB->end()) {
1056  assert(!FirstTerm->isDebugValue() &&
1057  "first terminator cannot be a debug value");
1059  make_range(std::next(FirstTerm), InsertBB->end()))) {
1060  // Only scan up to insertion point.
1061  if (&MI == InsertPos)
1062  break;
1063 
1064  if (!MI.isDebugValue())
1065  continue;
1066 
1067  // The DBG_VALUE was referencing a value produced by a terminator. By
1068  // moving the DBG_VALUE, the referenced value also needs invalidating.
1069  MI.getOperand(0).ChangeToRegister(0, false);
1070  MI.moveBefore(&*FirstTerm);
1071  }
1072  }
1073  return InsertBB;
1074 }
1075 
1076 /// Return the basic block label.
1077 std::string ScheduleDAGSDNodes::getDAGName() const {
1078  return "sunit-dag." + BB->getFullName();
1079 }
i
i
Definition: README.txt:29
llvm::ScheduleDAGSDNodes::computeLatency
virtual void computeLatency(SUnit *SU)
computeLatency - Compute node latency.
Definition: ScheduleDAGSDNodes.cpp:610
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::InstrEmitter
Definition: InstrEmitter.h:32
llvm::ScheduleDAG::MRI
MachineRegisterInfo & MRI
Virtual/real register map.
Definition: ScheduleDAG.h:561
llvm::SDDbgValue
Holds the information from a dbg_value node through SDISel.
Definition: SDNodeDbgValue.h:133
llvm::SelectionDAG::GetDbgValues
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
Definition: SelectionDAG.h:1778
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::SUnit::isScheduleLow
bool isScheduleLow
True if preferable to schedule low.
Definition: ScheduleDAG.h:286
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::ScheduleDAGSDNodes
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Definition: ScheduleDAGSDNodes.h:46
llvm::TargetInstrInfo::areLoadsFromSameBasePtr
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Definition: TargetInstrInfo.h:1324
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::ScheduleDAGSDNodes::VerifyScheduledSequence
void VerifyScheduledSequence(bool isBottomUp)
VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of sc...
Definition: ScheduleDAGSDNodes.cpp:721
llvm::SDNode::op_values
iterator_range< value_op_iterator > op_values() const
Definition: SelectionDAGNodes.h:931
llvm::SDDbgInfo::DbgLabelIterator
SmallVectorImpl< SDDbgLabel * >::iterator DbgLabelIterator
Definition: SelectionDAG.h:197
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
Statistic.h
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9055
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2867
llvm::SelectionDAG::getRoot
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Definition: SelectionDAG.h:525
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineSDNode::memoperands_begin
mmo_iterator memoperands_begin() const
Definition: SelectionDAGNodes.h:2909
llvm::SUnit::isCommutable
bool isCommutable
Is a commutable instruction.
Definition: ScheduleDAG.h:278
CheckForPhysRegDependency
static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost)
CheckForPhysRegDependency - Check if the dependency between def and use of a specified operand is a p...
Definition: ScheduleDAGSDNodes.cpp:110
llvm::SUnit::isCall
bool isCall
Is a function call.
Definition: ScheduleDAG.h:275
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::SelectionDAG::hasDebugValues
bool hasDebugValues() const
Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
Definition: SelectionDAG.h:1785
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::SDNode::use_iterator
This class provides iterator support for SDUse operands that use a specific SDNode.
Definition: SelectionDAGNodes.h:733
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:114
DenseMap.h
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::SUnit::Succs
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::ScheduleDAGSDNodes::newSUnit
SUnit * newSUnit(SDNode *N)
NewSUnit - Creates a new SUnit and return a ptr to it.
Definition: ScheduleDAGSDNodes.cpp:68
llvm::InstrEmitter::CountResults
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Definition: InstrEmitter.cpp:43
llvm::SDDbgOperand
Holds the information for a single machine location through SDISel; either an SDNode,...
Definition: SDNodeDbgValue.h:31
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:654
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
SDNodeDbgValue.h
llvm::ScheduleDAGSDNodes::DAG
SelectionDAG * DAG
Definition: ScheduleDAGSDNodes.h:49
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::ScheduleDAGSDNodes::ScheduleDAGSDNodes
ScheduleDAGSDNodes(MachineFunction &mf)
Definition: ScheduleDAGSDNodes.cpp:49
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::SelectionDAG::DbgBegin
SDDbgInfo::DbgIterator DbgBegin() const
Definition: SelectionDAG.h:1787
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1645
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CommandLine.h
llvm::ScheduleDAGSDNodes::RegDefIter::RegDefIter
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD)
Definition: ScheduleDAGSDNodes.cpp:577
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
bb
< i1 > br i1 label label bb bb
Definition: README.txt:978
llvm::SDNode::getOpcode
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Definition: SelectionDAGNodes.h:632
MCInstrItineraries.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::AAResults
Definition: AliasAnalysis.h:511
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SUnit::isScheduleHigh
bool isScheduleHigh
True if preferable to schedule high.
Definition: ScheduleDAG.h:285
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:455
llvm::SUnit::Latency
unsigned short Latency
Node latency.
Definition: ScheduleDAG.h:273
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::less_first
Function object to check whether the first component of a std::pair compares less than the first comp...
Definition: STLExtras.h:1344
llvm::ScheduleDAGSDNodes::getDAGName
std::string getDAGName() const override
Return the basic block label.
Definition: ScheduleDAGSDNodes.cpp:1077
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3392
llvm::ScheduleDAGSDNodes::InstrItins
const InstrItineraryData * InstrItins
Definition: ScheduleDAGSDNodes.h:50
llvm::SUnit::NodeNum
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:264
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::InstrEmitter::getInsertPos
MachineBasicBlock::iterator getInsertPos()
getInsertPos - Return the current insertion position.
Definition: InstrEmitter.h:152
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:587
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:65
llvm::SelectionDAG::DbgLabelBegin
SDDbgInfo::DbgLabelIterator DbgLabelBegin() const
Definition: SelectionDAG.h:1797
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:478
CloneNodeWithValues
static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef< EVT > VTs, SDValue ExtraOper=SDValue())
Definition: ScheduleDAGSDNodes.cpp:139
llvm::TargetInstrInfo::shouldScheduleLoadsNear
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Definition: TargetInstrInfo.h:1338
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
ScheduleDAGSDNodes.h
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:822
llvm::SDep::Data
@ Data
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
llvm::SUnit::isVRegCycle
bool isVRegCycle
May use and def the same vreg.
Definition: ScheduleDAG.h:274
SmallPtrSet.h
llvm::SUnit::OrigNode
SUnit * OrigNode
If not this, the node from which this node was cloned.
Definition: ScheduleDAG.h:250
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::SUnit::hasPhysRegClobbers
bool hasPhysRegClobbers
Has any physreg defs, used or not.
Definition: ScheduleDAG.h:281
llvm::SUnit::isCallOp
bool isCallOp
Is a function call operand.
Definition: ScheduleDAG.h:276
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ScheduleDAGSDNodes::RegDefIter::Advance
void Advance()
Definition: ScheduleDAGSDNodes.cpp:585
llvm::ScheduleDAG::VerifyScheduledDAG
unsigned VerifyScheduledDAG(bool isBottomUp)
Verifies that all SUnits were scheduled and that their state is consistent.
Definition: ScheduleDAG.cpp:390
llvm::MCInstrDesc::hasImplicitDefOfPhysReg
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:32
llvm::ScheduleDAGSDNodes::computeOperandLatency
virtual void computeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
Definition: ScheduleDAGSDNodes.cpp:644
llvm::ScheduleDAGSDNodes::forceUnitLatencies
virtual bool forceUnitLatencies() const
ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one.
Definition: ScheduleDAGSDNodes.h:173
HighLatencyCycles
static cl::opt< int > HighLatencyCycles("sched-high-latency-cycles", cl::Hidden, cl::init(10), cl::desc("Roughly estimate the number of cycles that 'long latency'" "instructions take for targets with no itinerary"))
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::SelectionDAG::ByvalParmDbgBegin
SDDbgInfo::DbgIterator ByvalParmDbgBegin() const
Definition: SelectionDAG.h:1790
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:435
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::ScheduleDAGSDNodes::Clone
SUnit * Clone(SUnit *Old)
Clone - Creates a clone of the specified SUnit.
Definition: ScheduleDAGSDNodes.cpp:89
llvm::SDNode::use_begin
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
Definition: SelectionDAGNodes.h:787
llvm::InstrEmitter::getBlock
MachineBasicBlock * getBlock()
getBlock - Return the current basic block.
Definition: InstrEmitter.h:149
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:409
llvm::MachineFunction::addCallArgsForwardingRegs
void addCallArgsForwardingRegs(const MachineInstr *CallI, CallSiteInfoImpl &&CallInfo)
Start tracking the arguments passed to the call CallI.
Definition: MachineFunction.h:1210
llvm::count
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1699
llvm::SUnit::CopyDstRC
const TargetRegisterClass * CopyDstRC
Is a special copy node if != nullptr.
Definition: ScheduleDAG.h:302
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SUnit::NumRegDefsLeft
unsigned short NumRegDefsLeft
Definition: ScheduleDAG.h:272
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:285
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::InstrEmitter::EmitDbgLabel
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
Definition: InstrEmitter.cpp:910
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:716
llvm::SUnit::setNode
void setNode(SDNode *N)
Assigns the representative SDNode for this SUnit.
Definition: ScheduleDAG.h:348
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:908
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SDep::getReg
unsigned getReg() const
Returns the register associated with this edge.
Definition: ScheduleDAG.h:218
llvm::SelectionDAG::allnodes
iterator_range< allnodes_iterator > allnodes()
Definition: SelectionDAG.h:517
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:608
llvm::MachineBasicBlock::getFirstNonPHI
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: MachineBasicBlock.cpp:196
llvm::SDNode::dump
void dump() const
Dump this node, for debugging.
Definition: SelectionDAGDumper.cpp:543
llvm::SelectionDAG::MorphNodeTo
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
Definition: SelectionDAG.cpp:9392
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
llvm::Sched::None
@ None
Definition: TargetLowering.h:98
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::SDNode::getNodeId
int getNodeId() const
Return the unique node id.
Definition: SelectionDAGNodes.h:713
llvm::SDValue::getResNo
unsigned getResNo() const
get the index which selects a specific result in the SDNode
Definition: SelectionDAGNodes.h:148
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::ScheduleDAGSDNodes::EmitSchedule
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
Definition: ScheduleDAGSDNodes.cpp:845
llvm::SelectionDAG::getCallSiteInfo
CallSiteInfo getCallSiteInfo(const SDNode *Node)
Return CallSiteInfo associated with Node, or a default if none exists.
Definition: SelectionDAG.h:2160
llvm::ScheduleDAG::dumpNodeAll
void dumpNodeAll(const SUnit &SU) const
Definition: ScheduleDAG.cpp:363
llvm::ScheduleDAGSDNodes::Schedule
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::SelectionDAG::setNodeMemRefs
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
Definition: SelectionDAG.cpp:9261
llvm::MDNode
Metadata node.
Definition: Metadata.h:926
ProcessSDDbgValues
static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, SmallVectorImpl< std::pair< unsigned, MachineInstr * > > &Orders, DenseMap< SDValue, Register > &VRBaseMap, unsigned Order)
ProcessSDDbgValues - Process SDDbgValues associated with this node.
Definition: ScheduleDAGSDNodes.cpp:731
llvm::SDNode::isMachineOpcode
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
Definition: SelectionDAGNodes.h:687
llvm::ScheduleDAGSDNodes::Run
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
Definition: ScheduleDAGSDNodes.cpp:54
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ScheduleDAG::StressSched
bool StressSched
Definition: ScheduleDAG.h:569
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:356
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SDep::getSUnit
SUnit * getSUnit() const
Definition: ScheduleDAG.h:480
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SDNode::use_end
static use_iterator use_end()
Definition: SelectionDAGNodes.h:791
llvm::MachineBasicBlock::getFullName
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
Definition: MachineBasicBlock.cpp:318
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
llvm::SDep::Barrier
@ Barrier
An unknown scheduling barrier.
Definition: ScheduleDAG.h:69
TargetSubtargetInfo.h
InstrEmitter.h
ProcessSourceNode
static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, DenseMap< SDValue, Register > &VRBaseMap, SmallVectorImpl< std::pair< unsigned, MachineInstr * >> &Orders, SmallSet< Register, 8 > &Seen, MachineInstr *NewInsn)
Definition: ScheduleDAGSDNodes.cpp:777
llvm::ScheduleDAG::EntrySU
SUnit EntrySU
Special node for the region entry.
Definition: ScheduleDAG.h:563
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:209
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::SUnit::SchedulingPref
Sched::Preference SchedulingPref
Scheduling preference.
Definition: ScheduleDAG.h:290
llvm::MachineBasicBlock::instr_front
MachineInstr & instr_front()
Definition: MachineBasicBlock.h:251
llvm::PointerUnion< const Value *, const PseudoSourceValue * >
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ScheduleDAGSDNodes::RegDefIter
RegDefIter - In place iteration over the values defined by an SUnit.
Definition: ScheduleDAGSDNodes.h:138
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::ScheduleDAGSDNodes::dumpSchedule
void dumpSchedule() const
Definition: ScheduleDAGSDNodes.cpp:707
llvm::TargetOptions::EmitCallSiteInfo
unsigned EmitCallSiteInfo
The flag enables call site info production.
Definition: TargetOptions.h:324
llvm::SelectionDAG::ByvalParmDbgEnd
SDDbgInfo::DbgIterator ByvalParmDbgEnd() const
Definition: SelectionDAG.h:1793
llvm::InstrEmitter::EmitNode
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap< SDValue, Register > &VRBaseMap)
EmitNode - Generate machine code for a node and needed dependencies.
Definition: InstrEmitter.h:140
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
llvm::stable_sort
void stable_sort(R &&Range)
Definition: STLExtras.h:1751
llvm::ScheduleDAGSDNodes::BB
MachineBasicBlock * BB
Definition: ScheduleDAGSDNodes.h:48
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::SmallVectorImpl::assign
void assign(size_type NumElts, ValueParamT Elt)
Definition: SmallVector.h:688
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1308
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::SUnit::getNode
SDNode * getNode() const
Returns the representative SDNode for this SUnit.
Definition: ScheduleDAG.h:355
llvm::SDep::setLatency
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
llvm::SelectionDAG::getHeapAllocSite
MDNode * getHeapAllocSite(const SDNode *Node) const
Return HeapAllocSite associated with Node, or nullptr if none exists.
Definition: SelectionDAG.h:2170
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1552
llvm::SDDbgOperand::SDNODE
@ SDNODE
Value is the result of an expression.
Definition: SDNodeDbgValue.h:34
llvm::SelectionDAG::getNoMergeSiteInfo
bool getNoMergeSiteInfo(const SDNode *Node) const
Return NoMerge info associated with Node.
Definition: SelectionDAG.h:2180
llvm::MachineSDNode::memoperands_end
mmo_iterator memoperands_end() const
Definition: SelectionDAGNodes.h:2910
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::SUnit::addPred
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
Definition: ScheduleDAG.cpp:107
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:967
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1150
llvm::SUnit::hasPhysRegDefs
bool hasPhysRegDefs
Has physreg defs that are being used.
Definition: ScheduleDAG.h:280
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:878
llvm::SUnit::isTwoAddress
bool isTwoAddress
Is a two-address instruction.
Definition: ScheduleDAG.h:277
llvm::SUnit::isCloned
bool isCloned
True if this node has been cloned.
Definition: ScheduleDAG.h:287
llvm::SelectionDAG::DbgEnd
SDDbgInfo::DbgIterator DbgEnd() const
Definition: SelectionDAG.h:1788
llvm::SDep::getKind
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:486
llvm::SDNode::getMachineOpcode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
Definition: SelectionDAGNodes.h:692
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
AddGlue
static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG)
Definition: ScheduleDAGSDNodes.cpp:160
AA
llvm::ScheduleDAGSDNodes::dump
void dump() const override
Definition: ScheduleDAGSDNodes.cpp:695
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::ScheduleDAGSDNodes::dumpNode
void dumpNode(const SUnit &SU) const override
Definition: ScheduleDAGSDNodes.cpp:671
N
#define N
llvm::ScheduleDAG::dumpNodeName
void dumpNodeName(const SUnit &SU) const
Definition: ScheduleDAG.cpp:354
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1088
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SUnit::Preds
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::cl::desc
Definition: CommandLine.h:405
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
llvm::SelectionDAG::getUseInstrRefDebugInfo
bool getUseInstrRefDebugInfo() const
Definition: SelectionDAG.h:1814
raw_ostream.h
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1288
llvm::ScheduleDAGSDNodes::Sequence
std::vector< SUnit * > Sequence
The schedule. Null SUnit*'s represent noop instructions.
Definition: ScheduleDAGSDNodes.h:53
llvm::SDDbgInfo::DbgIterator
SmallVectorImpl< SDDbgValue * >::iterator DbgIterator
Definition: SelectionDAG.h:196
llvm::ScheduleDAGSDNodes::BuildSchedGraph
void BuildSchedGraph(AAResults *AA)
BuildSchedGraph - Build the SUnit graph from the selection dag that we are input.
Definition: ScheduleDAGSDNodes.cpp:533
llvm::ScheduleDAGSDNodes::InitNumRegDefsLeft
void InitNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
Definition: ScheduleDAGSDNodes.cpp:602
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::InstrItineraryData::isEmpty
bool isEmpty() const
Returns true if there are no itineraries.
Definition: MCInstrItineraries.h:126
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::ScheduleDAGSDNodes::isPassiveNode
static bool isPassiveNode(SDNode *Node)
isPassiveNode - Return true if the node is a non-scheduled leaf.
Definition: ScheduleDAGSDNodes.h:65
llvm::SDep::isCtrl
bool isCtrl() const
Shorthand for getKind() != SDep::Data.
Definition: ScheduleDAG.h:161
llvm::ScheduleDAG::clearDAG
void clearDAG()
Clears the DAG state (between regions).
Definition: ScheduleDAG.cpp:64
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:453
TargetRegisterInfo.h
Debug.h
llvm::ScheduleDAG::ExitSU
SUnit ExitSU
Special node for the region exit.
Definition: ScheduleDAG.h:564
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::SelectionDAG::DbgLabelEnd
SDDbgInfo::DbgLabelIterator DbgLabelEnd() const
Definition: SelectionDAG.h:1800
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::SDNode::getGluedNode
SDNode * getGluedNode() const
If this node has a glue operand, return the node to which the glue operand points.
Definition: SelectionDAGNodes.h:943
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::InstrEmitter::EmitDbgValue
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
Definition: InstrEmitter.cpp:672
SmallSet.h
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
RemoveUnusedGlue
static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG)
Definition: ScheduleDAGSDNodes.cpp:185