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32 #define DEBUG_TYPE "aarch64-subtarget"
34 #define GET_SUBTARGETINFO_CTOR
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #include "AArch64GenSubtargetInfo.inc"
49 cl::desc(
"Call nonlazybind functions via direct GOT load"),
53 cl::desc(
"Enable the use of AA during codegen."));
56 "aarch64-insert-extract-base-cost",
69 if (CPUString.
empty())
70 CPUString =
"generic";
72 if (TuneCPUString.
empty())
73 TuneCPUString = CPUString;
76 initializeProperties();
81 void AArch64Subtarget::initializeProperties() {
261 const std::string &TuneCPU,
262 const std::string &
FS,
264 unsigned MinSVEVectorSizeInBitsOverride,
265 unsigned MaxSVEVectorSizeInBitsOverride)
267 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
268 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
269 IsLittle(LittleEndian),
270 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
271 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
272 InstrInfo(initializeSubtargetDependencies(
FS, CPU, TuneCPU)),
322 if (!
TM.shouldAssumeDSOLocal(*GV->
getParent(), GV)) {
341 if (AllowTaggedGlobals && !isa<FunctionType>(GV->
getValueType()))
356 auto *
F = dyn_cast<Function>(GV);
369 unsigned NumRegionInstrs)
const {
397 std::unique_ptr<PBQPRAConstraint>
399 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() :
nullptr;
bool isMaxCallFrameSizeComputed() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
This class provides the information for the target register banks.
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
This is an optimization pass for GlobalISel generic memory operations.
unsigned getVectorInsertExtractBaseCost() const
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned MaxJumpTableSize
std::unique_ptr< RegisterBankInfo > RegBankInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
uint8_t MaxInterleaveFactor
std::unique_ptr< InstructionSelector > InstSelector
Triple - Helper class for working with autoconf configuration names.
bool isDriverKit() const
Is this an Apple DriverKit triple.
uint16_t MinPrefetchStride
uint8_t VectorInsertExtractBaseCost
unsigned MaxBytesForLoopAlignment
unsigned PrefLoopLogAlignment
bool hasExternalWeakLinkage() const
const AArch64TargetLowering * getTargetLowering() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
const InlineAsmLowering * getInlineAsmLowering() const override
InstructionSelector * getInstructionSelector() const override
bool enableEarlyIfConversion() const override
void mirFileLoaded(MachineFunction &MF) const override
bool DisableLatencyHeuristic
Represents a version number in the form major[.minor[.subminor[.build]]].
bool hasInternalLinkage() const
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
bool isX18ReservedByDefault(const Triple &TT)
unsigned PrefFunctionLogAlignment
const CallLowering * getCallLowering() const override
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
BitVector ReserveXRegister
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Module * getParent()
Get the module that this global value is contained inside of...
bool useSmallAddressing() const
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
initializer< Ty > init(const Ty &Val)
Primary interface to the complete machine description for the target machine.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned MinVectorRegisterBitWidth
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
StringRef - Represent a constant reference to a string, i.e.
Analysis the ScalarEvolution expression for r is this
const Triple & getTargetTriple() const
bool isiOS() const
Is this an iOS triple.
const AArch64RegisterInfo * getRegisterInfo() const override
const RegisterBankInfo * getRegBankInfo() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
This class provides the information for the target register banks.
uint16_t PrefetchDistance
unsigned MaxPrefetchIterationsAhead
bool isTargetMachO() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
bool hasDLLImportStorageClass() const
const LegalizerInfo * getLegalizerInfo() const override
Type * getValueType() const
const char LLVMTargetMachineRef TM
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
bool useAA() const override
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)