LLVM 19.0.0git
AArch64Subtarget.cpp
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1//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Subtarget.h"
14
15#include "AArch64.h"
16#include "AArch64InstrInfo.h"
17#include "AArch64PBQPRegAlloc.h"
26#include "llvm/IR/GlobalValue.h"
28
29using namespace llvm;
30
31#define DEBUG_TYPE "aarch64-subtarget"
32
33#define GET_SUBTARGETINFO_CTOR
34#define GET_SUBTARGETINFO_TARGET_DESC
35#include "AArch64GenSubtargetInfo.inc"
36
37static cl::opt<bool>
38EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
39 "converter pass"), cl::init(true), cl::Hidden);
40
41// If OS supports TBI, use this flag to enable it.
42static cl::opt<bool>
43UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
44 "an address is ignored"), cl::init(false), cl::Hidden);
45
46static cl::opt<bool>
47 UseNonLazyBind("aarch64-enable-nonlazybind",
48 cl::desc("Call nonlazybind functions via direct GOT load"),
49 cl::init(false), cl::Hidden);
50
51static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
52 cl::desc("Enable the use of AA during codegen."));
53
55 "aarch64-insert-extract-base-cost",
56 cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
57
58// Reserve a list of X# registers, so they are unavailable for register
59// allocator, but can still be used as ABI requests, such as passing arguments
60// to function call.
62ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
63 "registers, so they can't be used by register allocator. "
64 "Should only be used for testing register allocator."),
66
68 "force-streaming-compatible-sve",
70 "Force the use of streaming-compatible SVE code for all functions"),
72
74 AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",
76 cl::desc("Override the variant of check applied "
77 "to authenticated LR during tail call"),
79
81 "aarch64-min-jump-table-entries", cl::init(13), cl::Hidden,
82 cl::desc("Set minimum number of entries to use a jump table on AArch64"));
83
85 if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
88}
89
90AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
91 StringRef FS, StringRef CPUString, StringRef TuneCPUString,
92 bool HasMinSize) {
93 // Determine default and user-specified characteristics
94
95 if (CPUString.empty())
96 CPUString = "generic";
97
98 if (TuneCPUString.empty())
99 TuneCPUString = CPUString;
100
101 ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
102 initializeProperties(HasMinSize);
103
104 return *this;
105}
106
107void AArch64Subtarget::initializeProperties(bool HasMinSize) {
108 // Initialize CPU specific properties. We should add a tablegen feature for
109 // this in the future so we can specify it together with the subtarget
110 // features.
111 switch (ARMProcFamily) {
112 case Others:
113 break;
114 case Carmel:
115 CacheLineSize = 64;
116 break;
117 case CortexA35:
118 case CortexA53:
119 case CortexA55:
123 break;
124 case CortexA57:
129 break;
130 case CortexA65:
132 break;
133 case CortexA72:
134 case CortexA73:
135 case CortexA75:
139 break;
140 case CortexA76:
141 case CortexA77:
142 case CortexA78:
143 case CortexA78C:
144 case CortexR82:
145 case CortexX1:
146 case CortexX1C:
150 break;
151 case CortexA510:
152 case CortexA520:
154 VScaleForTuning = 1;
157 break;
158 case CortexA710:
159 case CortexA715:
160 case CortexA720:
161 case CortexX2:
162 case CortexX3:
163 case CortexX4:
165 VScaleForTuning = 1;
168 break;
169 case A64FX:
170 CacheLineSize = 256;
174 PrefetchDistance = 128;
175 MinPrefetchStride = 1024;
177 VScaleForTuning = 4;
178 break;
179 case AppleA7:
180 case AppleA10:
181 case AppleA11:
182 case AppleA12:
183 case AppleA13:
184 case AppleA14:
185 case AppleA15:
186 case AppleA16:
187 case AppleA17:
188 CacheLineSize = 64;
189 PrefetchDistance = 280;
190 MinPrefetchStride = 2048;
192 switch (ARMProcFamily) {
193 case AppleA14:
194 case AppleA15:
195 case AppleA16:
196 case AppleA17:
198 break;
199 default:
200 break;
201 }
202 break;
203 case ExynosM3:
205 MaxJumpTableSize = 20;
208 break;
209 case Falkor:
211 // FIXME: remove this to enable 64-bit SLP if performance looks good.
213 CacheLineSize = 128;
214 PrefetchDistance = 820;
215 MinPrefetchStride = 2048;
217 break;
218 case Kryo:
221 CacheLineSize = 128;
222 PrefetchDistance = 740;
223 MinPrefetchStride = 1024;
225 // FIXME: remove this to enable 64-bit SLP if performance looks good.
227 break;
228 case NeoverseE1:
230 break;
231 case NeoverseN1:
235 break;
236 case NeoverseN2:
237 case NeoverseV2:
241 VScaleForTuning = 1;
242 break;
243 case NeoverseV1:
247 VScaleForTuning = 2;
249 break;
250 case Neoverse512TVB:
252 VScaleForTuning = 1;
254 break;
255 case Saphira:
257 // FIXME: remove this to enable 64-bit SLP if performance looks good.
259 break;
260 case ThunderX2T99:
261 CacheLineSize = 64;
265 PrefetchDistance = 128;
266 MinPrefetchStride = 1024;
268 // FIXME: remove this to enable 64-bit SLP if performance looks good.
270 break;
271 case ThunderX:
272 case ThunderXT88:
273 case ThunderXT81:
274 case ThunderXT83:
275 CacheLineSize = 128;
278 // FIXME: remove this to enable 64-bit SLP if performance looks good.
280 break;
281 case TSV110:
282 CacheLineSize = 64;
285 break;
286 case ThunderX3T110:
287 CacheLineSize = 64;
291 PrefetchDistance = 128;
292 MinPrefetchStride = 1024;
294 // FIXME: remove this to enable 64-bit SLP if performance looks good.
296 break;
297 case Ampere1:
298 case Ampere1A:
299 case Ampere1B:
300 CacheLineSize = 64;
304 break;
305 }
306
307 if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)
309}
310
312 StringRef TuneCPU, StringRef FS,
313 const TargetMachine &TM, bool LittleEndian,
314 unsigned MinSVEVectorSizeInBitsOverride,
315 unsigned MaxSVEVectorSizeInBitsOverride,
316 bool StreamingSVEMode,
317 bool StreamingCompatibleSVEMode,
318 bool HasMinSize)
319 : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
320 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
321 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
322 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
323 IsLittle(LittleEndian), StreamingSVEMode(StreamingSVEMode),
324 StreamingCompatibleSVEMode(StreamingCompatibleSVEMode),
325 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
326 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
327 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),
328 TLInfo(TM, *this) {
331
334 Legalizer.reset(new AArch64LegalizerInfo(*this));
335
336 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
337
338 // FIXME: At this point, we can't rely on Subtarget having RBI.
339 // It's awkward to mix passing RBI and the Subtarget; should we pass
340 // TII/TRI as well?
342 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
343
344 RegBankInfo.reset(RBI);
345
346 auto TRI = getRegisterInfo();
347 StringSet<> ReservedRegNames;
348 ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end());
349 for (unsigned i = 0; i < 29; ++i) {
350 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
352 }
353 // X30 is named LR, so we can't use TRI->getName to check X30.
354 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))
356 // X29 is named FP, so we can't use TRI->getName to check X29.
357 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))
359
360 AddressCheckPSV.reset(new AddressCheckPseudoSourceValue(TM));
361}
362
364 return CallLoweringInfo.get();
365}
366
368 return InlineAsmLoweringInfo.get();
369}
370
372 return InstSelector.get();
373}
374
376 return Legalizer.get();
377}
378
380 return RegBankInfo.get();
381}
382
383/// Find the target operand flags that describe how a global value should be
384/// referenced for the current subtarget.
385unsigned
387 const TargetMachine &TM) const {
388 // MachO large model always goes via a GOT, simply to get a single 8-byte
389 // absolute relocation on all global addresses.
390 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
391 return AArch64II::MO_GOT;
392
393 // All globals dynamically protected by MTE must have their address tags
394 // synthesized. This is done by having the loader stash the tag in the GOT
395 // entry. Force all tagged globals (even ones with internal linkage) through
396 // the GOT.
397 if (GV->isTagged())
398 return AArch64II::MO_GOT;
399
400 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
401 if (GV->hasDLLImportStorageClass()) {
403 }
404 if (getTargetTriple().isOSWindows())
406 return AArch64II::MO_GOT;
407 }
408
409 // The small code model's direct accesses use ADRP, which cannot
410 // necessarily produce the value 0 (if the code is above 4GB).
411 // Same for the tiny code model, where we have a pc relative LDR.
412 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
414 return AArch64II::MO_GOT;
415
416 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
417 // that their nominal addresses are tagged and outside of the code model. In
418 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
419 // tag if necessary based on MO_TAGGED.
420 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
422
424}
425
427 const GlobalValue *GV, const TargetMachine &TM) const {
428 // MachO large model always goes via a GOT, because we don't have the
429 // relocations available to do anything else..
430 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
431 !GV->hasInternalLinkage())
432 return AArch64II::MO_GOT;
433
434 // NonLazyBind goes via GOT unless we know it's available locally.
435 auto *F = dyn_cast<Function>(GV);
436 if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
437 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
438 return AArch64II::MO_GOT;
439
440 if (getTargetTriple().isOSWindows()) {
441 if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {
442 if (GV->hasDLLImportStorageClass()) {
443 // On Arm64EC, if we're calling a symbol from the import table
444 // directly, use MO_ARM64EC_CALLMANGLE.
447 }
448 if (GV->hasExternalLinkage()) {
449 // If we're calling a symbol directly, use the mangled form in the
450 // call instruction.
452 }
453 }
454
455 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
456 return ClassifyGlobalReference(GV, TM);
457 }
458
460}
461
463 unsigned NumRegionInstrs) const {
464 // LNT run (at least on Cyclone) showed reasonably significant gains for
465 // bi-directional scheduling. 253.perlbmk.
466 Policy.OnlyTopDown = false;
467 Policy.OnlyBottomUp = false;
468 // Enabling or Disabling the latency heuristic is a close call: It seems to
469 // help nearly no benchmark on out-of-order architectures, on the other hand
470 // it regresses register pressure on a few benchmarking.
471 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
472}
473
476}
477
480 return false;
481
483 return true;
484 if (TargetTriple.isiOS()) {
486 }
487
488 return false;
489}
490
491std::unique_ptr<PBQPRAConstraint>
493 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
494}
495
497 // We usually compute max call frame size after ISel. Do the computation now
498 // if the .mir file didn't specify it. Note that this will probably give you
499 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
500 // instructions, specify explicitly if you need it to be correct.
501 MachineFrameInfo &MFI = MF.getFrameInfo();
504}
505
506bool AArch64Subtarget::useAA() const { return UseAA; }
507
510}
511
513 return hasNEON() &&
514 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
515}
516
518 return hasSVE() &&
519 (hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
520}
521
522// If return address signing is enabled, tail calls are emitted as follows:
523//
524// ```
525// <authenticate LR>
526// <check LR>
527// TCRETURN ; the callee may sign and spill the LR in its prologue
528// ```
529//
530// LR may require explicit checking because if FEAT_FPAC is not implemented
531// and LR was tampered with, then `<authenticate LR>` will not generate an
532// exception on its own. Later, if the callee spills the signed LR value and
533// neither FEAT_PAuth2 nor FEAT_EPAC are implemented, the valid PAC replaces
534// the higher bits of LR thus hiding the authentication failure.
537 if (AuthenticatedLRCheckMethod.getNumOccurrences())
539
540 // At now, use None by default because checks may introduce an unexpected
541 // performance regression or incompatibility with execute-only mappings.
543}
544
546 return getSchedModel().hasInstrSchedModel();
547}
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for AArch64.
#define AUTH_CHECK_METHOD_CL_VALUES_LR
This file declares the targeting of the RegisterBankInfo class for AArch64.
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
static cl::opt< bool > ForceStreamingCompatibleSVE("force-streaming-compatible-sve", cl::desc("Force the use of streaming-compatible SVE code for all functions"), cl::Hidden)
static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))
static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This class provides the information for the target register banks.
const CallLowering * getCallLowering() const override
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEMode=false, bool StreamingCompatibleSVEMode=false, bool HasMinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool useSmallAddressing() const
bool isStreamingCompatible() const
Returns true if the function has a streaming-compatible body.
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
const Triple & getTargetTriple() const
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isStreaming() const
Returns true if the function has a streaming body.
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const
Choose a method of checking LR before performing a tail call.
bool isSVEAvailable() const
Returns true if the target has SVE and can use the full range of SVE instructions,...
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
BitVector & set()
Definition: BitVector.h:351
bool hasExternalLinkage() const
Definition: GlobalValue.h:510
bool isTagged() const
Definition: GlobalValue.h:364
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:528
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:278
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
bool hasInternalLinkage() const
Definition: GlobalValue.h:525
Type * getValueType() const
Definition: GlobalValue.h:296
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
bool isMaxCallFrameSizeComputed() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Holds all the information related to register banks.
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
Definition: StringMap.h:277
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:34
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:537
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:515
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
Definition: Triple.cpp:1307
bool isFunctionTy() const
True if this is an instance of FunctionType.
Definition: Type.h:246
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:29
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
AuthCheckMethod
Variants of check performed on an authenticated pointer.
@ None
Do not check the value at all.
bool isX18ReservedByDefault(const Triple &TT)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:718
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
@ CommaSeparated
Definition: CommandLine.h:164
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.