31#define DEBUG_TYPE "aarch64-subtarget"
33#define GET_SUBTARGETINFO_CTOR
34#define GET_SUBTARGETINFO_TARGET_DESC
35#include "AArch64GenSubtargetInfo.inc"
47 "aarch64-macho-enable-nonlazybind",
48 cl::desc(
"Call nonlazybind functions via direct GOT load for Mach-O"),
52 cl::desc(
"Enable the use of AA during codegen."));
55 "aarch64-insert-extract-base-cost",
63 "registers, so they can't be used by register allocator. "
64 "Should only be used for testing register allocator."),
68 "force-streaming-compatible-sve",
70 "Force the use of streaming-compatible SVE code for all functions"),
76 cl::desc(
"Override the variant of check applied "
77 "to authenticated LR during tail call"),
82 cl::desc(
"Set minimum number of entries to use a jump table on AArch64"));
95 if (CPUString.
empty())
96 CPUString =
"generic";
98 if (TuneCPUString.
empty())
99 TuneCPUString = CPUString;
102 initializeProperties(HasMinSize);
107void AArch64Subtarget::initializeProperties(
bool HasMinSize) {
315 unsigned MinSVEVectorSizeInBitsOverride,
316 unsigned MaxSVEVectorSizeInBitsOverride,
317 bool StreamingSVEMode,
318 bool StreamingCompatibleSVEMode,
321 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
322 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
323 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
324 IsLittle(LittleEndian), StreamingSVEMode(StreamingSVEMode),
325 StreamingCompatibleSVEMode(StreamingCompatibleSVEMode),
326 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
327 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
328 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),
350 for (
unsigned i = 0; i < 29; ++i) {
351 if (ReservedRegNames.
count(
TRI->getName(AArch64::X0 + i)))
355 if (ReservedRegNames.
count(
"X30") || ReservedRegNames.
count(
"LR"))
358 if (ReservedRegNames.
count(
"X29") || ReservedRegNames.
count(
"FP"))
361 AddressCheckPSV.reset(
new AddressCheckPseudoSourceValue(
TM));
401 if (!
TM.shouldAssumeDSOLocal(GV)) {
421 if (AllowTaggedGlobals && !isa<FunctionType>(GV->
getValueType()))
436 auto *
F = dyn_cast<Function>(GV);
438 F->hasFnAttribute(Attribute::NonLazyBind) && !
TM.shouldAssumeDSOLocal(GV))
464 unsigned NumRegionInstrs)
const {
479 !Def->isInstr() || !
Use->isInstr() ||
480 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&
481 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))
490 if (
Op.isReg() &&
Op.isDef() &&
Op.getReg() == Reg) {
492 DefOpIdx =
Op.getOperandNo();
502 if (
Op.isReg() &&
Op.isUse() &&
Op.getReg() == Reg) {
504 UseOpIdx =
Op.getOperandNo();
531std::unique_ptr<PBQPRAConstraint>
533 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() :
nullptr;
586 return getSchedModel().hasInstrSchedModel();
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
This file declares the targeting of the Machinelegalizer class for AArch64.
#define AUTH_CHECK_METHOD_CL_VALUES_LR
This file declares the targeting of the RegisterBankInfo class for AArch64.
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
static cl::opt< bool > ForceStreamingCompatibleSVE("force-streaming-compatible-sve", cl::desc("Force the use of streaming-compatible SVE code for all functions"), cl::Hidden)
static cl::opt< bool > MachOUseNonLazyBind("aarch64-macho-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"), cl::Hidden)
static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))
static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This class provides the information for the target register banks.
BitVector ReserveXRegisterForRA
BitVector ReserveXRegister
const CallLowering * getCallLowering() const override
bool isNeonAvailable() const
Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool StreamingSVEMode=false, bool StreamingCompatibleSVEMode=false, bool HasMinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool useSmallAddressing() const
bool isStreamingCompatible() const
Returns true if the function has a streaming-compatible body.
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned MaxPrefetchIterationsAhead
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
uint8_t VectorInsertExtractBaseCost
const AArch64TargetLowering * getTargetLowering() const override
bool isTargetMachO() const
uint16_t PrefetchDistance
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
bool StreamingCompatibleSVEMode
Align PrefFunctionAlignment
const Triple & getTargetTriple() const
unsigned MinVectorRegisterBitWidth
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
uint16_t MinPrefetchStride
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned MaxJumpTableSize
bool isWindowsArm64EC() const
bool isStreaming() const
Returns true if the function has a streaming body.
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const
Choose a method of checking LR before performing a tail call.
bool isSVEAvailable() const
Returns true if the target has SVE and can use the full range of SVE instructions,...
unsigned MinimumJumpTableEntries
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
uint8_t MaxInterleaveFactor
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxBytesForLoopAlignment
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
This class represents an Operation in the Expression.
bool hasExternalLinkage() const
bool hasExternalWeakLinkage() const
bool hasDLLImportStorageClass() const
bool hasInternalLinkage() const
Type * getValueType() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void computeMaxCallFrameSize(MachineFunction &MF, std::vector< MachineBasicBlock::iterator > *FrameSDOps=nullptr)
Computes the maximum size of a callframe.
bool isMaxCallFrameSizeComputed() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Kind getKind() const
Returns an enum value representing the kind of the dependence.
@ Data
Regular data dependence (aka true-dependence).
void setLatency(unsigned Lat)
Sets the latency for this edge.
unsigned getReg() const
Returns the register associated with this edge.
Scheduling unit. This is a node in the scheduling DAG.
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
StringSet - A wrapper for StringMap that provides set-like functionality.
std::pair< typename Base::iterator, bool > insert(StringRef key)
Primary interface to the complete machine description for the target machine.
Provide an instruction scheduling machine model to CodeGen passes.
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
Triple - Helper class for working with autoconf configuration names.
bool isDriverKit() const
Is this an Apple DriverKit triple.
bool isiOS() const
Is this an iOS triple.
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
bool isFunctionTy() const
True if this is an instance of FunctionType.
A Use represents the edge between a Value definition and its users.
Represents a version number in the form major[.minor[.subminor[.build]]].
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
AuthCheckMethod
Variants of check performed on an authenticated pointer.
@ None
Do not check the value at all.
bool isX18ReservedByDefault(const Triple &TT)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
bool DisableLatencyHeuristic