LLVM  14.0.0git
AArch64Subtarget.cpp
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1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64PBQPRegAlloc.h"
18 #include "AArch64TargetMachine.h"
25 #include "llvm/IR/GlobalValue.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38  "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43  "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46  UseNonLazyBind("aarch64-enable-nonlazybind",
47  cl::desc("Call nonlazybind functions via direct GOT load"),
48  cl::init(false), cl::Hidden);
49 
50 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
51  cl::desc("Enable the use of AA during codegen."));
52 
54 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
55  StringRef CPUString) {
56  // Determine default and user-specified characteristics
57 
58  if (CPUString.empty())
59  CPUString = "generic";
60 
61  ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
62  initializeProperties();
63 
64  return *this;
65 }
66 
67 void AArch64Subtarget::initializeProperties() {
68  // Initialize CPU specific properties. We should add a tablegen feature for
69  // this in the future so we can specify it together with the subtarget
70  // features.
71  switch (ARMProcFamily) {
72  case Others:
73  break;
74  case Carmel:
75  CacheLineSize = 64;
76  break;
77  case CortexA35:
78  break;
79  case CortexA53:
80  case CortexA55:
82  break;
83  case CortexA57:
86  break;
87  case CortexA65:
89  break;
90  case CortexA72:
91  case CortexA73:
92  case CortexA75:
93  case CortexA76:
94  case CortexA77:
95  case CortexA78:
96  case CortexA78C:
97  case CortexR82:
98  case CortexX1:
100  break;
101  case A64FX:
102  CacheLineSize = 256;
106  PrefetchDistance = 128;
107  MinPrefetchStride = 1024;
109  break;
110  case AppleA7:
111  case AppleA10:
112  case AppleA11:
113  case AppleA12:
114  case AppleA13:
115  case AppleA14:
116  CacheLineSize = 64;
117  PrefetchDistance = 280;
118  MinPrefetchStride = 2048;
120  break;
121  case ExynosM3:
123  MaxJumpTableSize = 20;
126  break;
127  case Falkor:
129  // FIXME: remove this to enable 64-bit SLP if performance looks good.
131  CacheLineSize = 128;
132  PrefetchDistance = 820;
133  MinPrefetchStride = 2048;
135  break;
136  case Kryo:
139  CacheLineSize = 128;
140  PrefetchDistance = 740;
141  MinPrefetchStride = 1024;
143  // FIXME: remove this to enable 64-bit SLP if performance looks good.
145  break;
146  case NeoverseE1:
148  break;
149  case NeoverseN1:
150  case NeoverseN2:
151  case NeoverseV1:
153  break;
154  case Saphira:
156  // FIXME: remove this to enable 64-bit SLP if performance looks good.
158  break;
159  case ThunderX2T99:
160  CacheLineSize = 64;
164  PrefetchDistance = 128;
165  MinPrefetchStride = 1024;
167  // FIXME: remove this to enable 64-bit SLP if performance looks good.
169  break;
170  case ThunderX:
171  case ThunderXT88:
172  case ThunderXT81:
173  case ThunderXT83:
174  CacheLineSize = 128;
177  // FIXME: remove this to enable 64-bit SLP if performance looks good.
179  break;
180  case TSV110:
181  CacheLineSize = 64;
184  break;
185  case ThunderX3T110:
186  CacheLineSize = 64;
190  PrefetchDistance = 128;
191  MinPrefetchStride = 1024;
193  // FIXME: remove this to enable 64-bit SLP if performance looks good.
195  break;
196  }
197 }
198 
199 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
200  const std::string &FS,
201  const TargetMachine &TM, bool LittleEndian,
202  unsigned MinSVEVectorSizeInBitsOverride,
203  unsigned MaxSVEVectorSizeInBitsOverride)
204  : AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
205  ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
206  CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
207  IsLittle(LittleEndian),
208  MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
209  MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
210  FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS, CPU)),
211  TSInfo(), TLInfo(TM, *this) {
213  ReserveXRegister.set(18);
214 
217  Legalizer.reset(new AArch64LegalizerInfo(*this));
218 
219  auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
220 
221  // FIXME: At this point, we can't rely on Subtarget having RBI.
222  // It's awkward to mix passing RBI and the Subtarget; should we pass
223  // TII/TRI as well?
225  *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
226 
227  RegBankInfo.reset(RBI);
228 }
229 
231  return CallLoweringInfo.get();
232 }
233 
235  return InlineAsmLoweringInfo.get();
236 }
237 
239  return InstSelector.get();
240 }
241 
243  return Legalizer.get();
244 }
245 
247  return RegBankInfo.get();
248 }
249 
250 /// Find the target operand flags that describe how a global value should be
251 /// referenced for the current subtarget.
252 unsigned
254  const TargetMachine &TM) const {
255  // MachO large model always goes via a GOT, simply to get a single 8-byte
256  // absolute relocation on all global addresses.
257  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
258  return AArch64II::MO_GOT;
259 
260  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
261  if (GV->hasDLLImportStorageClass())
263  if (getTargetTriple().isOSWindows())
265  return AArch64II::MO_GOT;
266  }
267 
268  // The small code model's direct accesses use ADRP, which cannot
269  // necessarily produce the value 0 (if the code is above 4GB).
270  // Same for the tiny code model, where we have a pc relative LDR.
271  if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
273  return AArch64II::MO_GOT;
274 
275  // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
276  // that their nominal addresses are tagged and outside of the code model. In
277  // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
278  // tag if necessary based on MO_TAGGED.
279  if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
281 
282  return AArch64II::MO_NO_FLAG;
283 }
284 
286  const GlobalValue *GV, const TargetMachine &TM) const {
287  // MachO large model always goes via a GOT, because we don't have the
288  // relocations available to do anything else..
289  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
290  !GV->hasInternalLinkage())
291  return AArch64II::MO_GOT;
292 
293  // NonLazyBind goes via GOT unless we know it's available locally.
294  auto *F = dyn_cast<Function>(GV);
295  if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
296  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
297  return AArch64II::MO_GOT;
298 
299  // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
300  if (getTargetTriple().isOSWindows())
301  return ClassifyGlobalReference(GV, TM);
302 
303  return AArch64II::MO_NO_FLAG;
304 }
305 
307  unsigned NumRegionInstrs) const {
308  // LNT run (at least on Cyclone) showed reasonably significant gains for
309  // bi-directional scheduling. 253.perlbmk.
310  Policy.OnlyTopDown = false;
311  Policy.OnlyBottomUp = false;
312  // Enabling or Disabling the latency heuristic is a close call: It seems to
313  // help nearly no benchmark on out-of-order architectures, on the other hand
314  // it regresses register pressure on a few benchmarking.
316 }
317 
319  return EnableEarlyIfConvert;
320 }
321 
324  return false;
325 
326  if (TargetTriple.isiOS()) {
327  unsigned Major, Minor, Micro;
328  TargetTriple.getiOSVersion(Major, Minor, Micro);
329  return Major >= 8;
330  }
331 
332  return false;
333 }
334 
335 std::unique_ptr<PBQPRAConstraint>
337  return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
338 }
339 
341  // We usually compute max call frame size after ISel. Do the computation now
342  // if the .mir file didn't specify it. Note that this will probably give you
343  // bogus values after PEI has eliminated the callframe setup/destroy pseudo
344  // instructions, specify explicitly if you need it to be correct.
345  MachineFrameInfo &MFI = MF.getFrameInfo();
346  if (!MFI.isMaxCallFrameSizeComputed())
347  MFI.computeMaxCallFrameSize(MF);
348 }
349 
351  // Prefer NEON unless larger SVE registers are available.
352  return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
353 }
354 
355 bool AArch64Subtarget::useAA() const { return UseAA; }
AArch64LegalizerInfo.h
llvm::AArch64Subtarget::CortexA53
@ CortexA53
Definition: AArch64Subtarget.h:51
llvm::MachineSchedPolicy::OnlyBottomUp
bool OnlyBottomUp
Definition: MachineScheduler.h:184
llvm::AArch64Subtarget::AppleA11
@ AppleA11
Definition: AArch64Subtarget.h:45
llvm::MachineFrameInfo::isMaxCallFrameSizeComputed
bool isMaxCallFrameSizeComputed() const
Definition: MachineFrameInfo.h:629
llvm::AArch64Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::AArch64RegisterBankInfo
This class provides the information for the target register banks.
Definition: AArch64RegisterBankInfo.h:104
llvm::AArch64Subtarget::supportsAddressTopByteIgnored
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
Definition: AArch64Subtarget.cpp:322
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::AArch64Subtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Definition: AArch64Subtarget.h:83
llvm::AArch64Subtarget::ThunderX2T99
@ ThunderX2T99
Definition: AArch64Subtarget.h:72
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
AArch64.h
llvm::AArch64Subtarget::MaxJumpTableSize
unsigned MaxJumpTableSize
Definition: AArch64Subtarget.h:262
llvm::AArch64Subtarget::CortexA57
@ CortexA57
Definition: AArch64Subtarget.h:53
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::AArch64Subtarget::ThunderXT81
@ ThunderXT81
Definition: AArch64Subtarget.h:74
AArch64RegisterBankInfo.h
llvm::AArch64Subtarget::ThunderX3T110
@ ThunderX3T110
Definition: AArch64Subtarget.h:77
llvm::AArch64Subtarget::CortexA77
@ CortexA77
Definition: AArch64Subtarget.h:59
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::Triple::getiOSVersion
void getiOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const
getiOSVersion - Parse the version number as with getOSVersion.
Definition: Triple.cpp:1154
llvm::AArch64Subtarget::getMinSVEVectorSizeInBits
unsigned getMinSVEVectorSizeInBits() const
Definition: AArch64Subtarget.h:638
llvm::AArch64Subtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: AArch64Subtarget.h:289
llvm::AArch64Subtarget::CortexA72
@ CortexA72
Definition: AArch64Subtarget.h:55
llvm::AArch64Subtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: AArch64Subtarget.h:285
llvm::AArch64Subtarget::NeoverseN2
@ NeoverseN2
Definition: AArch64Subtarget.h:69
llvm::AArch64Subtarget::DisableLatencySchedHeuristic
bool DisableLatencySchedHeuristic
Definition: AArch64Subtarget.h:244
llvm::AArch64Subtarget::hasSVE
bool hasSVE() const
Definition: AArch64Subtarget.h:463
llvm::AArch64Subtarget::CortexA76
@ CortexA76
Definition: AArch64Subtarget.h:58
llvm::AArch64Subtarget::MaxInterleaveFactor
uint8_t MaxInterleaveFactor
Definition: AArch64Subtarget.h:254
llvm::AArch64Subtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: AArch64Subtarget.h:287
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::AArch64Subtarget::MinPrefetchStride
uint16_t MinPrefetchStride
Definition: AArch64Subtarget.h:258
llvm::AArch64Subtarget::VectorInsertExtractBaseCost
uint8_t VectorInsertExtractBaseCost
Definition: AArch64Subtarget.h:255
InstructionSelect.h
llvm::AArch64Subtarget::useSVEForFixedLengthVectors
bool useSVEForFixedLengthVectors() const
Definition: AArch64Subtarget.cpp:350
llvm::AArch64Subtarget::Carmel
@ Carmel
Definition: AArch64Subtarget.h:49
llvm::AArch64Subtarget::ThunderX
@ ThunderX
Definition: AArch64Subtarget.h:73
llvm::AArch64Subtarget::TSV110
@ TSV110
Definition: AArch64Subtarget.h:78
llvm::AArch64Subtarget::AppleA12
@ AppleA12
Definition: AArch64Subtarget.h:46
TargetParser.h
llvm::AArch64Subtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
Definition: AArch64Subtarget.h:261
llvm::AArch64Subtarget::CortexA78
@ CortexA78
Definition: AArch64Subtarget.h:60
llvm::AArch64Subtarget::NeoverseN1
@ NeoverseN1
Definition: AArch64Subtarget.h:68
llvm::GlobalValue::hasExternalWeakLinkage
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:446
llvm::AArch64Subtarget::getTargetLowering
const AArch64TargetLowering * getTargetLowering() const override
Definition: AArch64Subtarget.h:316
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AArch64Subtarget::NeoverseV1
@ NeoverseV1
Definition: AArch64Subtarget.h:70
AArch64PBQPRegAlloc.h
llvm::AArch64Subtarget::AArch64Subtarget
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0)
This constructor initializes the data members to match that of the specified triple.
Definition: AArch64Subtarget.cpp:199
llvm::AArch64Subtarget::getCustomPBQPConstraints
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
Definition: AArch64Subtarget.cpp:336
GlobalValue.h
AArch64TargetMachine.h
llvm::AArch64Subtarget::getInlineAsmLowering
const InlineAsmLowering * getInlineAsmLowering() const override
Definition: AArch64Subtarget.cpp:234
AArch64InstrInfo.h
llvm::AArch64Subtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: AArch64Subtarget.cpp:238
llvm::AArch64Subtarget::A64FX
@ A64FX
Definition: AArch64Subtarget.h:42
llvm::Legalizer
Definition: Legalizer.h:31
llvm::AArch64Subtarget::CacheLineSize
uint16_t CacheLineSize
Definition: AArch64Subtarget.h:256
llvm::AArch64Subtarget::enableEarlyIfConversion
bool enableEarlyIfConversion() const override
Definition: AArch64Subtarget.cpp:318
llvm::AArch64Subtarget::Others
@ Others
Definition: AArch64Subtarget.h:41
llvm::AArch64Subtarget::mirFileLoaded
void mirFileLoaded(MachineFunction &MF) const override
Definition: AArch64Subtarget.cpp:340
llvm::MachineSchedPolicy::DisableLatencyHeuristic
bool DisableLatencyHeuristic
Definition: MachineScheduler.h:188
AArch64GenSubtargetInfo
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:25
llvm::AArch64Subtarget::balanceFPOps
bool balanceFPOps() const
Definition: AArch64Subtarget.h:387
llvm::AArch64Subtarget::CortexA78C
@ CortexA78C
Definition: AArch64Subtarget.h:61
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:443
UseNonLazyBind
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
UseAddressTopByteIgnored
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
llvm::AArch64::isX18ReservedByDefault
bool isX18ReservedByDefault(const Triple &TT)
Definition: AArch64TargetParser.cpp:200
llvm::AArch64Subtarget::PrefFunctionLogAlignment
unsigned PrefFunctionLogAlignment
Definition: AArch64Subtarget.h:260
AArch64AddressingModes.h
llvm::AArch64Subtarget::CortexX1
@ CortexX1
Definition: AArch64Subtarget.h:63
llvm::AArch64Subtarget::ThunderXT88
@ ThunderXT88
Definition: AArch64Subtarget.h:76
llvm::cl::opt< bool >
llvm::AArch64Subtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: AArch64Subtarget.cpp:230
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::AArch64Subtarget::ReserveXRegister
BitVector ReserveXRegister
Definition: AArch64Subtarget.h:266
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: AArch64BaseInfo.h:729
llvm::AArch64Subtarget::CortexA75
@ CortexA75
Definition: AArch64Subtarget.h:57
AArch64CallLowering.h
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
llvm::AArch64Subtarget::useSmallAddressing
bool useSmallAddressing() const
Definition: AArch64Subtarget.h:557
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition: AArch64BaseInfo.h:718
llvm::MachineFrameInfo::computeMaxCallFrameSize
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
Definition: MachineFrameInfo.cpp:187
llvm::AArch64Subtarget::AppleA14
@ AppleA14
Definition: AArch64Subtarget.h:48
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:670
llvm::AArch64Subtarget::AllowTaggedGlobals
bool AllowTaggedGlobals
Definition: AArch64Subtarget.h:250
llvm::AArch64Subtarget::NeoverseE1
@ NeoverseE1
Definition: AArch64Subtarget.h:67
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::AArch64Subtarget::MinVectorRegisterBitWidth
unsigned MinVectorRegisterBitWidth
Definition: AArch64Subtarget.h:223
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AArch64Subtarget::classifyGlobalFunctionReference
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: AArch64Subtarget.cpp:285
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::AArch64Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: AArch64Subtarget.h:328
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:463
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::AArch64Subtarget::AppleA7
@ AppleA7
Definition: AArch64Subtarget.h:43
llvm::AArch64Subtarget::ThunderXT83
@ ThunderXT83
Definition: AArch64Subtarget.h:75
llvm::AArch64Subtarget::CortexA35
@ CortexA35
Definition: AArch64Subtarget.h:50
llvm::AArch64Subtarget::CortexA55
@ CortexA55
Definition: AArch64Subtarget.h:52
llvm::AArch64Subtarget::getRegisterInfo
const AArch64RegisterInfo * getRegisterInfo() const override
Definition: AArch64Subtarget.h:320
llvm::AArch64CallLowering
Definition: AArch64CallLowering.h:32
llvm::AArch64Subtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: AArch64Subtarget.cpp:246
llvm::AArch64Subtarget::ExynosM3
@ ExynosM3
Definition: AArch64Subtarget.h:64
llvm::MachineSchedPolicy::OnlyTopDown
bool OnlyTopDown
Definition: MachineScheduler.h:183
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:253
llvm::AArch64Subtarget::InlineAsmLoweringInfo
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
Definition: AArch64Subtarget.h:286
llvm::AArch64LegalizerInfo
This class provides the information for the target register banks.
Definition: AArch64LegalizerInfo.h:28
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AArch64Subtarget::Kryo
@ Kryo
Definition: AArch64Subtarget.h:66
llvm::AArch64Subtarget::PrefetchDistance
uint16_t PrefetchDistance
Definition: AArch64Subtarget.h:257
llvm::AArch64Subtarget::MaxPrefetchIterationsAhead
unsigned MaxPrefetchIterationsAhead
Definition: AArch64Subtarget.h:259
llvm::AArch64Subtarget::isTargetMachO
bool isTargetMachO() const
Definition: AArch64Subtarget.h:512
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
MachineScheduler.h
AArch64Subtarget.h
llvm::AArch64Subtarget::CortexA73
@ CortexA73
Definition: AArch64Subtarget.h:56
UseAA
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
llvm::AArch64Subtarget::Saphira
@ Saphira
Definition: AArch64Subtarget.h:71
llvm::AArch64Subtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: AArch64Subtarget.h:277
llvm::GlobalValue::hasDLLImportStorageClass
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:259
llvm::AArch64Subtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: AArch64Subtarget.cpp:242
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1110
llvm::GlobalValue::getValueType
Type * getValueType() const
Definition: GlobalValue.h:273
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64Subtarget::CortexR82
@ CortexR82
Definition: AArch64Subtarget.h:62
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: AArch64BaseInfo.h:708
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:174
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:745
llvm::cl::desc
Definition: CommandLine.h:414
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64InstructionSelector
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
Definition: AArch64InstructionSelector.cpp:6479
llvm::AArch64Subtarget::useAA
bool useAA() const override
Definition: AArch64Subtarget.cpp:355
llvm::CallLowering
Definition: CallLowering.h:43
EnableEarlyIfConvert
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:713
llvm::AArch64Subtarget::Falkor
@ Falkor
Definition: AArch64Subtarget.h:65
llvm::AArch64Subtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: AArch64Subtarget.cpp:306
llvm::AArch64Subtarget::AppleA10
@ AppleA10
Definition: AArch64Subtarget.h:44
llvm::AArch64Subtarget::AppleA13
@ AppleA13
Definition: AArch64Subtarget.h:47
llvm::AArch64Subtarget::CortexA65
@ CortexA65
Definition: AArch64Subtarget.h:54