LLVM 19.0.0git
AArch64Subtarget.cpp
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1//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64 specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Subtarget.h"
14
15#include "AArch64.h"
16#include "AArch64InstrInfo.h"
17#include "AArch64PBQPRegAlloc.h"
26#include "llvm/IR/GlobalValue.h"
28
29using namespace llvm;
30
31#define DEBUG_TYPE "aarch64-subtarget"
32
33#define GET_SUBTARGETINFO_CTOR
34#define GET_SUBTARGETINFO_TARGET_DESC
35#include "AArch64GenSubtargetInfo.inc"
36
37static cl::opt<bool>
38EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
39 "converter pass"), cl::init(true), cl::Hidden);
40
41// If OS supports TBI, use this flag to enable it.
42static cl::opt<bool>
43UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
44 "an address is ignored"), cl::init(false), cl::Hidden);
45
47 "aarch64-macho-enable-nonlazybind",
48 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),
50
51static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
52 cl::desc("Enable the use of AA during codegen."));
53
55 "aarch64-insert-extract-base-cost",
56 cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
57
58// Reserve a list of X# registers, so they are unavailable for register
59// allocator, but can still be used as ABI requests, such as passing arguments
60// to function call.
62ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
63 "registers, so they can't be used by register allocator. "
64 "Should only be used for testing register allocator."),
66
68 AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",
70 cl::desc("Override the variant of check applied "
71 "to authenticated LR during tail call"),
73
75 "aarch64-min-jump-table-entries", cl::init(13), cl::Hidden,
76 cl::desc("Set minimum number of entries to use a jump table on AArch64"));
77
79 if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
82}
83
84AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
85 StringRef FS, StringRef CPUString, StringRef TuneCPUString,
86 bool HasMinSize) {
87 // Determine default and user-specified characteristics
88
89 if (CPUString.empty())
90 CPUString = "generic";
91
92 if (TuneCPUString.empty())
93 TuneCPUString = CPUString;
94
95 ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
96 initializeProperties(HasMinSize);
97
98 return *this;
99}
100
101void AArch64Subtarget::initializeProperties(bool HasMinSize) {
102 // Initialize CPU specific properties. We should add a tablegen feature for
103 // this in the future so we can specify it together with the subtarget
104 // features.
105 switch (ARMProcFamily) {
106 case Others:
107 break;
108 case Carmel:
109 CacheLineSize = 64;
110 break;
111 case CortexA35:
112 case CortexA53:
113 case CortexA55:
114 case CortexR82:
115 case CortexR82AE:
119 break;
120 case CortexA57:
125 break;
126 case CortexA65:
128 break;
129 case CortexA72:
130 case CortexA73:
131 case CortexA75:
135 break;
136 case CortexA76:
137 case CortexA77:
138 case CortexA78:
139 case CortexA78AE:
140 case CortexA78C:
141 case CortexX1:
145 break;
146 case CortexA510:
147 case CortexA520:
149 VScaleForTuning = 1;
152 break;
153 case CortexA710:
154 case CortexA715:
155 case CortexA720:
156 case CortexA725:
157 case CortexX2:
158 case CortexX3:
159 case CortexX4:
160 case CortexX925:
162 VScaleForTuning = 1;
165 break;
166 case A64FX:
167 CacheLineSize = 256;
171 PrefetchDistance = 128;
172 MinPrefetchStride = 1024;
174 VScaleForTuning = 4;
175 break;
176 case AppleA7:
177 case AppleA10:
178 case AppleA11:
179 case AppleA12:
180 case AppleA13:
181 case AppleA14:
182 case AppleA15:
183 case AppleA16:
184 case AppleA17:
185 case AppleM4:
186 CacheLineSize = 64;
187 PrefetchDistance = 280;
188 MinPrefetchStride = 2048;
190 switch (ARMProcFamily) {
191 case AppleA14:
192 case AppleA15:
193 case AppleA16:
194 case AppleA17:
195 case AppleM4:
197 break;
198 default:
199 break;
200 }
201 break;
202 case ExynosM3:
204 MaxJumpTableSize = 20;
207 break;
208 case Falkor:
210 // FIXME: remove this to enable 64-bit SLP if performance looks good.
212 CacheLineSize = 128;
213 PrefetchDistance = 820;
214 MinPrefetchStride = 2048;
216 break;
217 case Kryo:
220 CacheLineSize = 128;
221 PrefetchDistance = 740;
222 MinPrefetchStride = 1024;
224 // FIXME: remove this to enable 64-bit SLP if performance looks good.
226 break;
227 case NeoverseE1:
229 break;
230 case NeoverseN1:
234 break;
235 case NeoverseN2:
236 case NeoverseN3:
237 case NeoverseV2:
238 case NeoverseV3:
242 VScaleForTuning = 1;
243 break;
244 case NeoverseV1:
248 VScaleForTuning = 2;
250 break;
251 case Neoverse512TVB:
253 VScaleForTuning = 1;
255 break;
256 case Saphira:
258 // FIXME: remove this to enable 64-bit SLP if performance looks good.
260 break;
261 case ThunderX2T99:
262 CacheLineSize = 64;
266 PrefetchDistance = 128;
267 MinPrefetchStride = 1024;
269 // FIXME: remove this to enable 64-bit SLP if performance looks good.
271 break;
272 case ThunderX:
273 case ThunderXT88:
274 case ThunderXT81:
275 case ThunderXT83:
276 CacheLineSize = 128;
279 // FIXME: remove this to enable 64-bit SLP if performance looks good.
281 break;
282 case TSV110:
283 CacheLineSize = 64;
286 break;
287 case ThunderX3T110:
288 CacheLineSize = 64;
292 PrefetchDistance = 128;
293 MinPrefetchStride = 1024;
295 // FIXME: remove this to enable 64-bit SLP if performance looks good.
297 break;
298 case Ampere1:
299 case Ampere1A:
300 case Ampere1B:
301 CacheLineSize = 64;
305 break;
306 case Oryon:
307 CacheLineSize = 64;
310 PrefetchDistance = 128;
311 MinPrefetchStride = 1024;
312 break;
313 }
314
315 if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)
317}
318
320 StringRef TuneCPU, StringRef FS,
321 const TargetMachine &TM, bool LittleEndian,
322 unsigned MinSVEVectorSizeInBitsOverride,
323 unsigned MaxSVEVectorSizeInBitsOverride,
324 bool IsStreaming, bool IsStreamingCompatible,
325 bool HasMinSize)
326 : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
327 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
328 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
329 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
330 IsLittle(LittleEndian), IsStreaming(IsStreaming),
331 IsStreamingCompatible(IsStreamingCompatible),
332 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
333 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
334 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),
335 TLInfo(TM, *this) {
338
341 Legalizer.reset(new AArch64LegalizerInfo(*this));
342
343 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
344
345 // FIXME: At this point, we can't rely on Subtarget having RBI.
346 // It's awkward to mix passing RBI and the Subtarget; should we pass
347 // TII/TRI as well?
349 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
350
351 RegBankInfo.reset(RBI);
352
353 auto TRI = getRegisterInfo();
354 StringSet<> ReservedRegNames;
355 ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end());
356 for (unsigned i = 0; i < 29; ++i) {
357 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
359 }
360 // X30 is named LR, so we can't use TRI->getName to check X30.
361 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))
363 // X29 is named FP, so we can't use TRI->getName to check X29.
364 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))
366
367 AddressCheckPSV.reset(new AddressCheckPseudoSourceValue(TM));
368}
369
371 return CallLoweringInfo.get();
372}
373
375 return InlineAsmLoweringInfo.get();
376}
377
379 return InstSelector.get();
380}
381
383 return Legalizer.get();
384}
385
387 return RegBankInfo.get();
388}
389
390/// Find the target operand flags that describe how a global value should be
391/// referenced for the current subtarget.
392unsigned
394 const TargetMachine &TM) const {
395 // MachO large model always goes via a GOT, simply to get a single 8-byte
396 // absolute relocation on all global addresses.
397 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
398 return AArch64II::MO_GOT;
399
400 // All globals dynamically protected by MTE must have their address tags
401 // synthesized. This is done by having the loader stash the tag in the GOT
402 // entry. Force all tagged globals (even ones with internal linkage) through
403 // the GOT.
404 if (GV->isTagged())
405 return AArch64II::MO_GOT;
406
407 if (!TM.shouldAssumeDSOLocal(GV)) {
408 if (GV->hasDLLImportStorageClass()) {
410 }
411 if (getTargetTriple().isOSWindows())
413 return AArch64II::MO_GOT;
414 }
415
416 // The small code model's direct accesses use ADRP, which cannot
417 // necessarily produce the value 0 (if the code is above 4GB).
418 // Same for the tiny code model, where we have a pc relative LDR.
419 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
421 return AArch64II::MO_GOT;
422
423 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
424 // that their nominal addresses are tagged and outside of the code model. In
425 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
426 // tag if necessary based on MO_TAGGED.
427 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
429
431}
432
434 const GlobalValue *GV, const TargetMachine &TM) const {
435 // MachO large model always goes via a GOT, because we don't have the
436 // relocations available to do anything else..
437 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
438 !GV->hasInternalLinkage())
439 return AArch64II::MO_GOT;
440
441 // NonLazyBind goes via GOT unless we know it's available locally.
442 auto *F = dyn_cast<Function>(GV);
443 if ((!isTargetMachO() || MachOUseNonLazyBind) && F &&
444 F->hasFnAttribute(Attribute::NonLazyBind) && !TM.shouldAssumeDSOLocal(GV))
445 return AArch64II::MO_GOT;
446
447 if (getTargetTriple().isOSWindows()) {
448 if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {
449 if (GV->hasDLLImportStorageClass()) {
450 // On Arm64EC, if we're calling a symbol from the import table
451 // directly, use MO_ARM64EC_CALLMANGLE.
454 }
455 if (GV->hasExternalLinkage()) {
456 // If we're calling a symbol directly, use the mangled form in the
457 // call instruction.
459 }
460 }
461
462 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
463 return ClassifyGlobalReference(GV, TM);
464 }
465
467}
468
470 unsigned NumRegionInstrs) const {
471 // LNT run (at least on Cyclone) showed reasonably significant gains for
472 // bi-directional scheduling. 253.perlbmk.
473 Policy.OnlyTopDown = false;
474 Policy.OnlyBottomUp = false;
475 // Enabling or Disabling the latency heuristic is a close call: It seems to
476 // help nearly no benchmark on out-of-order architectures, on the other hand
477 // it regresses register pressure on a few benchmarking.
478 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
479}
480
482 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep,
483 const TargetSchedModel *SchedModel) const {
484 if (!SchedModel || Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||
485 !Def->isInstr() || !Use->isInstr() ||
486 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&
487 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))
488 return;
489
490 // If the Def is a BUNDLE, find the last instruction in the bundle that defs
491 // the register.
492 const MachineInstr *DefMI = Def->getInstr();
493 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {
494 Register Reg = DefMI->getOperand(DefOpIdx).getReg();
495 for (const auto &Op : const_mi_bundle_ops(*DefMI)) {
496 if (Op.isReg() && Op.isDef() && Op.getReg() == Reg) {
497 DefMI = Op.getParent();
498 DefOpIdx = Op.getOperandNo();
499 }
500 }
501 }
502
503 // If the Use is a BUNDLE, find the first instruction that uses the Reg.
504 const MachineInstr *UseMI = Use->getInstr();
505 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) {
506 Register Reg = UseMI->getOperand(UseOpIdx).getReg();
507 for (const auto &Op : const_mi_bundle_ops(*UseMI)) {
508 if (Op.isReg() && Op.isUse() && Op.getReg() == Reg) {
509 UseMI = Op.getParent();
510 UseOpIdx = Op.getOperandNo();
511 break;
512 }
513 }
514 }
515
516 Dep.setLatency(
517 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx));
518}
519
522}
523
526 return false;
527
529 return true;
530 if (TargetTriple.isiOS()) {
532 }
533
534 return false;
535}
536
537std::unique_ptr<PBQPRAConstraint>
539 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
540}
541
543 // We usually compute max call frame size after ISel. Do the computation now
544 // if the .mir file didn't specify it. Note that this will probably give you
545 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
546 // instructions, specify explicitly if you need it to be correct.
547 MachineFrameInfo &MFI = MF.getFrameInfo();
550}
551
552bool AArch64Subtarget::useAA() const { return UseAA; }
553
554// If return address signing is enabled, tail calls are emitted as follows:
555//
556// ```
557// <authenticate LR>
558// <check LR>
559// TCRETURN ; the callee may sign and spill the LR in its prologue
560// ```
561//
562// LR may require explicit checking because if FEAT_FPAC is not implemented
563// and LR was tampered with, then `<authenticate LR>` will not generate an
564// exception on its own. Later, if the callee spills the signed LR value and
565// neither FEAT_PAuth2 nor FEAT_EPAC are implemented, the valid PAC replaces
566// the higher bits of LR thus hiding the authentication failure.
569 if (AuthenticatedLRCheckMethod.getNumOccurrences())
571
572 // At now, use None by default because checks may introduce an unexpected
573 // performance regression or incompatibility with execute-only mappings.
575}
576
578 return getSchedModel().hasInstrSchedModel();
579}
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
This file declares the targeting of the Machinelegalizer class for AArch64.
#define AUTH_CHECK_METHOD_CL_VALUES_LR
This file declares the targeting of the RegisterBankInfo class for AArch64.
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)
static cl::opt< bool > MachOUseNonLazyBind("aarch64-macho-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"), cl::Hidden)
static cl::opt< unsigned > AArch64MinimumJumpTableEntries("aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on AArch64"))
static cl::opt< AArch64PAuth::AuthCheckMethod > AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method", cl::Hidden, cl::desc("Override the variant of check applied " "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR))
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::list< std::string > ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical " "registers, so they can't be used by register allocator. " "Should only be used for testing register allocator."), cl::CommaSeparated, cl::Hidden)
static cl::opt< unsigned > OverrideVectorInsertExtractBaseCost("aarch64-insert-extract-base-cost", cl::desc("Base cost of vector insert/extract element"), cl::Hidden)
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This class provides the information for the target register banks.
AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)
This constructor initializes the data members to match that of the specified triple.
const CallLowering * getCallLowering() const override
const AArch64RegisterInfo * getRegisterInfo() const override
TailFoldingOpts DefaultSVETFOpts
std::unique_ptr< InstructionSelector > InstSelector
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useSmallAddressing() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool enableEarlyIfConversion() const override
const InlineAsmLowering * getInlineAsmLowering() const override
unsigned getVectorInsertExtractBaseCost() const
bool enableMachinePipeliner() const override
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool useAA() const override
const AArch64TargetLowering * getTargetLowering() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.
const Triple & getTargetTriple() const
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override
void mirFileLoaded(MachineFunction &MF) const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
InstructionSelector * getInstructionSelector() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const
Choose a method of checking LR before performing a tail call.
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
const RegisterBankInfo * getRegBankInfo() const override
std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo
BitVector & set()
Definition: BitVector.h:351
This class represents an Operation in the Expression.
bool hasExternalLinkage() const
Definition: GlobalValue.h:510
bool isTagged() const
Definition: GlobalValue.h:364
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:528
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:277
bool hasInternalLinkage() const
Definition: GlobalValue.h:525
Type * getValueType() const
Definition: GlobalValue.h:295
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void computeMaxCallFrameSize(MachineFunction &MF, std::vector< MachineBasicBlock::iterator > *FrameSDOps=nullptr)
Computes the maximum size of a callframe.
bool isMaxCallFrameSizeComputed() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:566
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:576
Register getReg() const
getReg - Returns the register number.
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Scheduling dependency.
Definition: ScheduleDAG.h:49
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:504
@ Data
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
unsigned getReg() const
Returns the register associated with this edge.
Definition: ScheduleDAG.h:218
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
size_type count(StringRef Key) const
count - Return 1 if the element is in the map, 0 otherwise.
Definition: StringMap.h:276
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:38
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
Provide an instruction scheduling machine model to CodeGen passes.
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:553
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:531
VersionTuple getiOSVersion() const
Parse the version number as with getOSVersion.
Definition: Triple.cpp:1417
bool isFunctionTy() const
True if this is an instance of FunctionType.
Definition: Type.h:246
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:29
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
AuthCheckMethod
Variants of check performed on an authenticated pointer.
@ None
Do not check the value at all.
bool isX18ReservedByDefault(const Triple &TT)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:711
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
@ CommaSeparated
Definition: CommandLine.h:163
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.