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MachinePipeliner.h
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1 //===- MachinePipeliner.h - Machine Software Pipeliner Pass -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // An implementation of the Swing Modulo Scheduling (SMS) software pipeliner.
10 //
11 // Software pipelining (SWP) is an instruction scheduling technique for loops
12 // that overlap loop iterations and exploits ILP via a compiler transformation.
13 //
14 // Swing Modulo Scheduling is an implementation of software pipelining
15 // that generates schedules that are near optimal in terms of initiation
16 // interval, register requirements, and stage count. See the papers:
17 //
18 // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa,
19 // A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996
20 // Conference on Parallel Architectures and Compilation Techiniques.
21 //
22 // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J.
23 // Llosa, E. Ayguade, A. Gonzalez, M. Valero, and J. Eckhardt. In IEEE
24 // Transactions on Computers, Vol. 50, No. 3, 2001.
25 //
26 // "An Implementation of Swing Modulo Scheduling With Extensions for
27 // Superblocks", by T. Lattner, Master's Thesis, University of Illinois at
28 // Urbana-Champaign, 2005.
29 //
30 //
31 // The SMS algorithm consists of three main steps after computing the minimal
32 // initiation interval (MII).
33 // 1) Analyze the dependence graph and compute information about each
34 // instruction in the graph.
35 // 2) Order the nodes (instructions) by priority based upon the heuristics
36 // described in the algorithm.
37 // 3) Attempt to schedule the nodes in the specified order using the MII.
38 //
39 //===----------------------------------------------------------------------===//
40 #ifndef LLVM_CODEGEN_MACHINEPIPELINER_H
41 #define LLVM_CODEGEN_MACHINEPIPELINER_H
42 
43 #include "llvm/ADT/SetVector.h"
50 #include "llvm/InitializePasses.h"
51 
52 #include <deque>
53 
54 namespace llvm {
55 
56 class AAResults;
57 class NodeSet;
58 class SMSchedule;
59 
60 extern cl::opt<bool> SwpEnableCopyToPhi;
61 
62 /// The main class in the implementation of the target independent
63 /// software pipeliner pass.
65 public:
66  MachineFunction *MF = nullptr;
68  const MachineLoopInfo *MLI = nullptr;
69  const MachineDominatorTree *MDT = nullptr;
71  const TargetInstrInfo *TII = nullptr;
73  bool disabledByPragma = false;
74  unsigned II_setByPragma = 0;
75 
76 #ifndef NDEBUG
77  static int NumTries;
78 #endif
79 
80  /// Cache the target analysis information about the loop.
81  struct LoopInfo {
82  MachineBasicBlock *TBB = nullptr;
83  MachineBasicBlock *FBB = nullptr;
87  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> LoopPipelinerInfo =
88  nullptr;
89  };
91 
92  static char ID;
93 
96  }
97 
98  bool runOnMachineFunction(MachineFunction &MF) override;
99 
100  void getAnalysisUsage(AnalysisUsage &AU) const override;
101 
102 private:
103  void preprocessPhiNodes(MachineBasicBlock &B);
104  bool canPipelineLoop(MachineLoop &L);
105  bool scheduleLoop(MachineLoop &L);
106  bool swingModuloScheduler(MachineLoop &L);
107  void setPragmaPipelineOptions(MachineLoop &L);
108 };
109 
110 /// This class builds the dependence graph for the instructions in a loop,
111 /// and attempts to schedule the instructions using the SMS algorithm.
114  /// The minimum initiation interval between iterations for this schedule.
115  unsigned MII = 0;
116  /// The maximum initiation interval between iterations for this schedule.
117  unsigned MAX_II = 0;
118  /// Set to true if a valid pipelined schedule is found for the loop.
119  bool Scheduled = false;
120  MachineLoop &Loop;
121  LiveIntervals &LIS;
122  const RegisterClassInfo &RegClassInfo;
123  unsigned II_setByPragma = 0;
124  TargetInstrInfo::PipelinerLoopInfo *LoopPipelinerInfo = nullptr;
125 
126  /// A toplogical ordering of the SUnits, which is needed for changing
127  /// dependences and iterating over the SUnits.
129 
130  struct NodeInfo {
131  int ASAP = 0;
132  int ALAP = 0;
133  int ZeroLatencyDepth = 0;
134  int ZeroLatencyHeight = 0;
135 
136  NodeInfo() = default;
137  };
138  /// Computed properties for each node in the graph.
139  std::vector<NodeInfo> ScheduleInfo;
140 
141  enum OrderKind { BottomUp = 0, TopDown = 1 };
142  /// Computed node ordering for scheduling.
143  SetVector<SUnit *> NodeOrder;
144 
149 
150  /// Instructions to change when emitting the final schedule.
152 
153  /// We may create a new instruction, so remember it because it
154  /// must be deleted when the pass is finished.
156 
157  /// Ordered list of DAG postprocessing steps.
158  std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
159 
160  /// Helper class to implement Johnson's circuit finding algorithm.
161  class Circuits {
162  std::vector<SUnit> &SUnits;
163  SetVector<SUnit *> Stack;
164  BitVector Blocked;
167  // Node to Index from ScheduleDAGTopologicalSort
168  std::vector<int> *Node2Idx;
169  unsigned NumPaths;
170  static unsigned MaxPaths;
171 
172  public:
173  Circuits(std::vector<SUnit> &SUs, ScheduleDAGTopologicalSort &Topo)
174  : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {
175  Node2Idx = new std::vector<int>(SUs.size());
176  unsigned Idx = 0;
177  for (const auto &NodeNum : Topo)
178  Node2Idx->at(NodeNum) = Idx++;
179  }
180 
181  ~Circuits() { delete Node2Idx; }
182 
183  /// Reset the data structures used in the circuit algorithm.
184  void reset() {
185  Stack.clear();
186  Blocked.reset();
187  B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
188  NumPaths = 0;
189  }
190 
191  void createAdjacencyStructure(SwingSchedulerDAG *DAG);
192  bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false);
193  void unblock(int U);
194  };
195 
196  struct CopyToPhiMutation : public ScheduleDAGMutation {
197  void apply(ScheduleDAGInstrs *DAG) override;
198  };
199 
200 public:
202  const RegisterClassInfo &rci, unsigned II,
204  : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
205  RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),
206  Topo(SUnits, &ExitSU) {
207  P.MF->getSubtarget().getSMSMutations(Mutations);
208  if (SwpEnableCopyToPhi)
209  Mutations.push_back(std::make_unique<CopyToPhiMutation>());
210  }
211 
212  void schedule() override;
213  void finishBlock() override;
214 
215  /// Return true if the loop kernel has been scheduled.
216  bool hasNewSchedule() { return Scheduled; }
217 
218  /// Return the earliest time an instruction may be scheduled.
219  int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; }
220 
221  /// Return the latest time an instruction my be scheduled.
222  int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; }
223 
224  /// The mobility function, which the number of slots in which
225  /// an instruction may be scheduled.
226  int getMOV(SUnit *Node) { return getALAP(Node) - getASAP(Node); }
227 
228  /// The depth, in the dependence graph, for a node.
229  unsigned getDepth(SUnit *Node) { return Node->getDepth(); }
230 
231  /// The maximum unweighted length of a path from an arbitrary node to the
232  /// given node in which each edge has latency 0
234  return ScheduleInfo[Node->NodeNum].ZeroLatencyDepth;
235  }
236 
237  /// The height, in the dependence graph, for a node.
238  unsigned getHeight(SUnit *Node) { return Node->getHeight(); }
239 
240  /// The maximum unweighted length of a path from the given node to an
241  /// arbitrary node in which each edge has latency 0
243  return ScheduleInfo[Node->NodeNum].ZeroLatencyHeight;
244  }
245 
246  /// Return true if the dependence is a back-edge in the data dependence graph.
247  /// Since the DAG doesn't contain cycles, we represent a cycle in the graph
248  /// using an anti dependence from a Phi to an instruction.
249  bool isBackedge(SUnit *Source, const SDep &Dep) {
250  if (Dep.getKind() != SDep::Anti)
251  return false;
252  return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
253  }
254 
255  bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
256 
257  /// The distance function, which indicates that operation V of iteration I
258  /// depends on operations U of iteration I-distance.
259  unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) {
260  // Instructions that feed a Phi have a distance of 1. Computing larger
261  // values for arrays requires data dependence information.
262  if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
263  return 1;
264  return 0;
265  }
266 
267  void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule);
268 
269  void fixupRegisterOverlaps(std::deque<SUnit *> &Instrs);
270 
271  /// Return the new base register that was stored away for the changed
272  /// instruction.
273  unsigned getInstrBaseReg(SUnit *SU) {
275  InstrChanges.find(SU);
276  if (It != InstrChanges.end())
277  return It->second.first;
278  return 0;
279  }
280 
281  void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
282  Mutations.push_back(std::move(Mutation));
283  }
284 
285  static bool classof(const ScheduleDAGInstrs *DAG) { return true; }
286 
287 private:
288  void addLoopCarriedDependences(AAResults *AA);
289  void updatePhiDependences();
290  void changeDependences();
291  unsigned calculateResMII();
292  unsigned calculateRecMII(NodeSetType &RecNodeSets);
293  void findCircuits(NodeSetType &NodeSets);
294  void fuseRecs(NodeSetType &NodeSets);
295  void removeDuplicateNodes(NodeSetType &NodeSets);
296  void computeNodeFunctions(NodeSetType &NodeSets);
297  void registerPressureFilter(NodeSetType &NodeSets);
298  void colocateNodeSets(NodeSetType &NodeSets);
299  void checkNodeSets(NodeSetType &NodeSets);
300  void groupRemainingNodes(NodeSetType &NodeSets);
301  void addConnectedNodes(SUnit *SU, NodeSet &NewSet,
302  SetVector<SUnit *> &NodesAdded);
303  void computeNodeOrder(NodeSetType &NodeSets);
304  void checkValidNodeOrder(const NodeSetType &Circuits) const;
305  bool schedulePipeline(SMSchedule &Schedule);
306  bool computeDelta(MachineInstr &MI, unsigned &Delta);
307  MachineInstr *findDefInLoop(Register Reg);
308  bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
309  unsigned &OffsetPos, unsigned &NewBase,
310  int64_t &NewOffset);
311  void postprocessDAG();
312  /// Set the Minimum Initiation Interval for this schedule attempt.
313  void setMII(unsigned ResMII, unsigned RecMII);
314  /// Set the Maximum Initiation Interval for this schedule attempt.
315  void setMAX_II();
316 };
317 
318 /// A NodeSet contains a set of SUnit DAG nodes with additional information
319 /// that assigns a priority to the set.
320 class NodeSet {
321  SetVector<SUnit *> Nodes;
322  bool HasRecurrence = false;
323  unsigned RecMII = 0;
324  int MaxMOV = 0;
325  unsigned MaxDepth = 0;
326  unsigned Colocate = 0;
327  SUnit *ExceedPressure = nullptr;
328  unsigned Latency = 0;
329 
330 public:
332 
333  NodeSet() = default;
334  NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {
335  Latency = 0;
336  for (unsigned i = 0, e = Nodes.size(); i < e; ++i) {
337  DenseMap<SUnit *, unsigned> SuccSUnitLatency;
338  for (const SDep &Succ : Nodes[i]->Succs) {
339  auto SuccSUnit = Succ.getSUnit();
340  if (!Nodes.count(SuccSUnit))
341  continue;
342  unsigned CurLatency = Succ.getLatency();
343  unsigned MaxLatency = 0;
344  if (SuccSUnitLatency.count(SuccSUnit))
345  MaxLatency = SuccSUnitLatency[SuccSUnit];
346  if (CurLatency > MaxLatency)
347  SuccSUnitLatency[SuccSUnit] = CurLatency;
348  }
349  for (auto SUnitLatency : SuccSUnitLatency)
350  Latency += SUnitLatency.second;
351  }
352  }
353 
354  bool insert(SUnit *SU) { return Nodes.insert(SU); }
355 
356  void insert(iterator S, iterator E) { Nodes.insert(S, E); }
357 
358  template <typename UnaryPredicate> bool remove_if(UnaryPredicate P) {
359  return Nodes.remove_if(P);
360  }
361 
362  unsigned count(SUnit *SU) const { return Nodes.count(SU); }
363 
364  bool hasRecurrence() { return HasRecurrence; };
365 
366  unsigned size() const { return Nodes.size(); }
367 
368  bool empty() const { return Nodes.empty(); }
369 
370  SUnit *getNode(unsigned i) const { return Nodes[i]; };
371 
372  void setRecMII(unsigned mii) { RecMII = mii; };
373 
374  void setColocate(unsigned c) { Colocate = c; };
375 
376  void setExceedPressure(SUnit *SU) { ExceedPressure = SU; }
377 
378  bool isExceedSU(SUnit *SU) { return ExceedPressure == SU; }
379 
380  int compareRecMII(NodeSet &RHS) { return RecMII - RHS.RecMII; }
381 
382  int getRecMII() { return RecMII; }
383 
384  /// Summarize node functions for the entire node set.
386  for (SUnit *SU : *this) {
387  MaxMOV = std::max(MaxMOV, SSD->getMOV(SU));
388  MaxDepth = std::max(MaxDepth, SSD->getDepth(SU));
389  }
390  }
391 
392  unsigned getLatency() { return Latency; }
393 
394  unsigned getMaxDepth() { return MaxDepth; }
395 
396  void clear() {
397  Nodes.clear();
398  RecMII = 0;
399  HasRecurrence = false;
400  MaxMOV = 0;
401  MaxDepth = 0;
402  Colocate = 0;
403  ExceedPressure = nullptr;
404  }
405 
406  operator SetVector<SUnit *> &() { return Nodes; }
407 
408  /// Sort the node sets by importance. First, rank them by recurrence MII,
409  /// then by mobility (least mobile done first), and finally by depth.
410  /// Each node set may contain a colocate value which is used as the first
411  /// tie breaker, if it's set.
412  bool operator>(const NodeSet &RHS) const {
413  if (RecMII == RHS.RecMII) {
414  if (Colocate != 0 && RHS.Colocate != 0 && Colocate != RHS.Colocate)
415  return Colocate < RHS.Colocate;
416  if (MaxMOV == RHS.MaxMOV)
417  return MaxDepth > RHS.MaxDepth;
418  return MaxMOV < RHS.MaxMOV;
419  }
420  return RecMII > RHS.RecMII;
421  }
422 
423  bool operator==(const NodeSet &RHS) const {
424  return RecMII == RHS.RecMII && MaxMOV == RHS.MaxMOV &&
425  MaxDepth == RHS.MaxDepth;
426  }
427 
428  bool operator!=(const NodeSet &RHS) const { return !operator==(RHS); }
429 
430  iterator begin() { return Nodes.begin(); }
431  iterator end() { return Nodes.end(); }
432  void print(raw_ostream &os) const;
433 
434 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
435  LLVM_DUMP_METHOD void dump() const;
436 #endif
437 };
438 
439 // 16 was selected based on the number of ProcResource kinds for all
440 // existing Subtargets, so that SmallVector don't need to resize too often.
441 static const int DefaultProcResSize = 16;
442 
444 private:
445  const MCSubtargetInfo *STI;
446  const MCSchedModel &SM;
447  const bool UseDFA;
448  std::unique_ptr<DFAPacketizer> DFAResources;
449  /// Each processor resource is associated with a so-called processor resource
450  /// mask. This vector allows to correlate processor resource IDs with
451  /// processor resource masks. There is exactly one element per each processor
452  /// resource declared by the scheduling model.
454 
456 
457 public:
459  : STI(ST), SM(ST->getSchedModel()), UseDFA(ST->useDFAforSMS()),
460  ProcResourceMasks(SM.getNumProcResourceKinds(), 0),
461  ProcResourceCount(SM.getNumProcResourceKinds(), 0) {
462  if (UseDFA)
463  DFAResources.reset(ST->getInstrInfo()->CreateTargetScheduleState(*ST));
464  initProcResourceVectors(SM, ProcResourceMasks);
465  }
466 
467  void initProcResourceVectors(const MCSchedModel &SM,
469  /// Check if the resources occupied by a MCInstrDesc are available in
470  /// the current state.
471  bool canReserveResources(const MCInstrDesc *MID) const;
472 
473  /// Reserve the resources occupied by a MCInstrDesc and change the current
474  /// state to reflect that change.
475  void reserveResources(const MCInstrDesc *MID);
476 
477  /// Check if the resources occupied by a machine instruction are available
478  /// in the current state.
479  bool canReserveResources(const MachineInstr &MI) const;
480 
481  /// Reserve the resources occupied by a machine instruction and change the
482  /// current state to reflect that change.
483  void reserveResources(const MachineInstr &MI);
484 
485  /// Reset the state
486  void clearResources();
487 };
488 
489 /// This class represents the scheduled code. The main data structure is a
490 /// map from scheduled cycle to instructions. During scheduling, the
491 /// data structure explicitly represents all stages/iterations. When
492 /// the algorithm finshes, the schedule is collapsed into a single stage,
493 /// which represents instructions from different loop iterations.
494 ///
495 /// The SMS algorithm allows negative values for cycles, so the first cycle
496 /// in the schedule is the smallest cycle value.
497 class SMSchedule {
498 private:
499  /// Map from execution cycle to instructions.
500  DenseMap<int, std::deque<SUnit *>> ScheduledInstrs;
501 
502  /// Map from instruction to execution cycle.
503  std::map<SUnit *, int> InstrToCycle;
504 
505  /// Keep track of the first cycle value in the schedule. It starts
506  /// as zero, but the algorithm allows negative values.
507  int FirstCycle = 0;
508 
509  /// Keep track of the last cycle value in the schedule.
510  int LastCycle = 0;
511 
512  /// The initiation interval (II) for the schedule.
513  int InitiationInterval = 0;
514 
515  /// Target machine information.
516  const TargetSubtargetInfo &ST;
517 
518  /// Virtual register information.
519  MachineRegisterInfo &MRI;
520 
521  ResourceManager ProcItinResources;
522 
523 public:
525  : ST(mf->getSubtarget()), MRI(mf->getRegInfo()), ProcItinResources(&ST) {}
526 
527  void reset() {
528  ScheduledInstrs.clear();
529  InstrToCycle.clear();
530  FirstCycle = 0;
531  LastCycle = 0;
532  InitiationInterval = 0;
533  }
534 
535  /// Set the initiation interval for this schedule.
536  void setInitiationInterval(int ii) { InitiationInterval = ii; }
537 
538  /// Return the initiation interval for this schedule.
539  int getInitiationInterval() const { return InitiationInterval; }
540 
541  /// Return the first cycle in the completed schedule. This
542  /// can be a negative value.
543  int getFirstCycle() const { return FirstCycle; }
544 
545  /// Return the last cycle in the finalized schedule.
546  int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; }
547 
548  /// Return the cycle of the earliest scheduled instruction in the dependence
549  /// chain.
550  int earliestCycleInChain(const SDep &Dep);
551 
552  /// Return the cycle of the latest scheduled instruction in the dependence
553  /// chain.
554  int latestCycleInChain(const SDep &Dep);
555 
556  void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
557  int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG);
558  bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
559 
560  /// Iterators for the cycle to instruction map.
562  using const_sched_iterator =
564 
565  /// Return true if the instruction is scheduled at the specified stage.
566  bool isScheduledAtStage(SUnit *SU, unsigned StageNum) {
567  return (stageScheduled(SU) == (int)StageNum);
568  }
569 
570  /// Return the stage for a scheduled instruction. Return -1 if
571  /// the instruction has not been scheduled.
572  int stageScheduled(SUnit *SU) const {
573  std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
574  if (it == InstrToCycle.end())
575  return -1;
576  return (it->second - FirstCycle) / InitiationInterval;
577  }
578 
579  /// Return the cycle for a scheduled instruction. This function normalizes
580  /// the first cycle to be 0.
581  unsigned cycleScheduled(SUnit *SU) const {
582  std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
583  assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled.");
584  return (it->second - FirstCycle) % InitiationInterval;
585  }
586 
587  /// Return the maximum stage count needed for this schedule.
588  unsigned getMaxStageCount() {
589  return (LastCycle - FirstCycle) / InitiationInterval;
590  }
591 
592  /// Return the instructions that are scheduled at the specified cycle.
593  std::deque<SUnit *> &getInstructions(int cycle) {
594  return ScheduledInstrs[cycle];
595  }
596 
600 
601  bool
606  void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
607  std::deque<SUnit *> &Insts);
610  MachineOperand &MO);
611  void print(raw_ostream &os) const;
612  void dump() const;
613 };
614 
615 } // end namespace llvm
616 
617 #endif // LLVM_CODEGEN_MACHINEPIPELINER_H
i
i
Definition: README.txt:29
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This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
Definition: MachinePipeliner.h:112
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#define LLVM_DUMP_METHOD
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This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
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@ Def
Definition: TGLexer.h:50
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Definition: MachinePipeliner.h:83
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The height, in the dependence graph, for a node.
Definition: MachinePipeliner.h:238
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Definition: MachinePipeliner.cpp:651
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Definition: MachinePipeliner.cpp:2994
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Definition: MachinePipeliner.h:66
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Definition: MachineRegisterInfo.h:50
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Represents a single loop in the control flow graph.
Definition: LoopInfo.h:546
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
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Definition: MachinePipeliner.h:201
ScheduleDAGInstrs.h
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Definition: SetVector.h:77
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Definition: MachinePipeliner.h:380
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Definition: SmallVector.h:1185
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Definition: MachinePipeliner.h:331
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Definition: MachinePipeliner.cpp:2737
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All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:151
llvm::SDep::Anti
@ Anti
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:54
llvm::SwingSchedulerDAG::schedule
void schedule() override
We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing ...
Definition: MachinePipeliner.cpp:472
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
RegisterClassInfo.h
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
llvm::SetVector::const_iterator
typename vector_type::const_iterator const_iterator
Definition: SetVector.h:49
llvm::DenseMapIterator
Definition: DenseMap.h:57
TargetInstrInfo.h
llvm::SwingSchedulerDAG::isLoopCarriedDep
bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc=true)
Return true for an order or output dependence that is loop carried potentially.
Definition: MachinePipeliner.cpp:2272
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::SwingSchedulerDAG::getZeroLatencyHeight
int getZeroLatencyHeight(SUnit *Node)
The maximum unweighted length of a path from the given node to an arbitrary node in which each edge h...
Definition: MachinePipeliner.h:242
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::NodeSet::empty
bool empty() const
Definition: MachinePipeliner.h:368
llvm::SMSchedule::insert
bool insert(SUnit *SU, int StartCycle, int EndCycle, int II)
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the E...
Definition: MachinePipeliner.cpp:2358
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachinePipeliner::LoopInfo::BrCond
SmallVector< MachineOperand, 4 > BrCond
Definition: MachinePipeliner.h:84
llvm::SetVector::remove_if
bool remove_if(UnaryPredicate P)
Remove items from the set vector based on a predicate function.
Definition: SetVector.h:199
llvm::SMSchedule::SMSchedule
SMSchedule(MachineFunction *mf)
Definition: MachinePipeliner.h:524
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:89
llvm::SwpEnableCopyToPhi
cl::opt< bool > SwpEnableCopyToPhi
llvm::MachinePipeliner::LI
LoopInfo LI
Definition: MachinePipeliner.h:90
llvm::ScheduleDAGTopologicalSort
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
Definition: ScheduleDAG.h:694
llvm::TargetInstrInfo::PipelinerLoopInfo
Object returned by analyzeLoopForPipelining.
Definition: TargetInstrInfo.h:728
llvm::ResourceManager::ResourceManager
ResourceManager(const TargetSubtargetInfo *ST)
Definition: MachinePipeliner.h:458
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::cl::apply
void apply(Opt *O, const Mod &M, const Mods &... Ms)
Definition: CommandLine.h:1280
llvm::SetVector::begin
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:82
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SMSchedule::dump
void dump() const
Utility function used for debugging to print the schedule.
Definition: MachinePipeliner.cpp:3019
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::SwingSchedulerDAG::getDistance
unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep)
The distance function, which indicates that operation V of iteration I depends on operations U of ite...
Definition: MachinePipeliner.h:259
llvm::SwingSchedulerDAG::isBackedge
bool isBackedge(SUnit *Source, const SDep &Dep)
Return true if the dependence is a back-edge in the data dependence graph.
Definition: MachinePipeliner.h:249
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SwingSchedulerDAG::getMOV
int getMOV(SUnit *Node)
The mobility function, which the number of slots in which an instruction may be scheduled.
Definition: MachinePipeliner.h:226
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::SMSchedule::getFinalCycle
int getFinalCycle() const
Return the last cycle in the finalized schedule.
Definition: MachinePipeliner.h:546
llvm::SMSchedule::getFirstCycle
int getFirstCycle() const
Return the first cycle in the completed schedule.
Definition: MachinePipeliner.h:543
false
Definition: StackSlotColoring.cpp:141
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SMSchedule::setInitiationInterval
void setInitiationInterval(int ii)
Set the initiation interval for this schedule.
Definition: MachinePipeliner.h:536
llvm::SMSchedule::isValidSchedule
bool isValidSchedule(SwingSchedulerDAG *SSD)
Definition: MachinePipeliner.cpp:2779
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::SMSchedule::orderDependence
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts)
Order the instructions within a cycle so that the definitions occur before the uses.
Definition: MachinePipeliner.cpp:2531
llvm::SMSchedule::reset
void reset()
Definition: MachinePipeliner.h:527
llvm::BitVector
Definition: BitVector.h:75
llvm::initializeMachinePipelinerPass
void initializeMachinePipelinerPass(PassRegistry &)
c
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
Definition: README.txt:418
llvm::NodeSet
A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...
Definition: MachinePipeliner.h:320
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::NodeSet::setColocate
void setColocate(unsigned c)
Definition: MachinePipeliner.h:374
llvm::SMSchedule::isLoopCarried
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi)
Return true if the scheduled Phi has a loop carried operand.
Definition: MachinePipeliner.cpp:2659
llvm::NodeSet::operator!=
bool operator!=(const NodeSet &RHS) const
Definition: MachinePipeliner.h:428
llvm::NodeSet::setExceedPressure
void setExceedPressure(SUnit *SU)
Definition: MachinePipeliner.h:376
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachinePipeliner
The main class in the implementation of the target independent software pipeliner pass.
Definition: MachinePipeliner.h:64
llvm::ResourceManager::canReserveResources
bool canReserveResources(const MCInstrDesc *MID) const
Check if the resources occupied by a MCInstrDesc are available in the current state.
Definition: MachinePipeliner.cpp:3066
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::NodeSet::begin
iterator begin()
Definition: MachinePipeliner.h:430
llvm::SMSchedule::computeStart
void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG)
Compute the scheduling start slot for the instruction.
Definition: MachinePipeliner.cpp:2470
llvm::SwingSchedulerDAG::classof
static bool classof(const ScheduleDAGInstrs *DAG)
Definition: MachinePipeliner.h:285
llvm::DefaultProcResSize
static const int DefaultProcResSize
Definition: MachinePipeliner.h:441
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::MachinePipeliner::LoopInfo::LoopPipelinerInfo
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > LoopPipelinerInfo
Definition: MachinePipeliner.h:87
llvm::MachinePipeliner::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachinePipeliner.cpp:446
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:112
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SMSchedule::getInitiationInterval
int getInitiationInterval() const
Return the initiation interval for this schedule.
Definition: MachinePipeliner.h:539
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::NodeSet::getRecMII
int getRecMII()
Definition: MachinePipeliner.h:382
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
llvm::NodeSet::getMaxDepth
unsigned getMaxDepth()
Definition: MachinePipeliner.h:394
llvm::MachinePipeliner::ORE
MachineOptimizationRemarkEmitter * ORE
Definition: MachinePipeliner.h:67
llvm::MachinePipeliner::InstrItins
const InstrItineraryData * InstrItins
Definition: MachinePipeliner.h:70
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::SwingSchedulerDAG::getALAP
int getALAP(SUnit *Node)
Return the latest time an instruction my be scheduled.
Definition: MachinePipeliner.h:222
llvm::NodeSet::size
unsigned size() const
Definition: MachinePipeliner.h:366
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
llvm::MachinePipeliner::LoopInfo::LoopCompare
MachineInstr * LoopCompare
Definition: MachinePipeliner.h:86
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachinePipeliner::MachinePipeliner
MachinePipeliner()
Definition: MachinePipeliner.h:94
llvm::MachinePipeliner::LoopInfo::LoopInductionVar
MachineInstr * LoopInductionVar
Definition: MachinePipeliner.h:85
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::SMSchedule::isLoopCarriedDefOfUse
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO)
Return true if the instruction is a definition that is loop carried and defines the use on the next i...
Definition: MachinePipeliner.cpp:2687
llvm::NodeSet::setRecMII
void setRecMII(unsigned mii)
Definition: MachinePipeliner.h:372
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1256
llvm::SMSchedule::getInstructions
std::deque< SUnit * > & getInstructions(int cycle)
Return the instructions that are scheduled at the specified cycle.
Definition: MachinePipeliner.h:593
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
ScheduleDAGMutation.h
llvm::SwingSchedulerDAG::getZeroLatencyDepth
int getZeroLatencyDepth(SUnit *Node)
The maximum unweighted length of a path from an arbitrary node to the given node in which each edge h...
Definition: MachinePipeliner.h:233
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:99
llvm::SDep::getSUnit
SUnit * getSUnit() const
Definition: ScheduleDAG.h:480
llvm::NodeSet::operator==
bool operator==(const NodeSet &RHS) const
Definition: MachinePipeliner.h:423
llvm::MachinePipeliner::RegClassInfo
RegisterClassInfo RegClassInfo
Definition: MachinePipeliner.h:72
llvm::MachinePipeliner::ID
static char ID
Definition: MachinePipeliner.h:92
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
Mutation
PowerPC VSX FMA Mutation
Definition: PPCVSXFMAMutate.cpp:387
llvm::NodeSet::hasRecurrence
bool hasRecurrence()
Definition: MachinePipeliner.h:364
Node
Definition: ItaniumDemangle.h:155
llvm::SMSchedule::isScheduledAtStage
bool isScheduledAtStage(SUnit *SU, unsigned StageNum)
Return true if the instruction is scheduled at the specified stage.
Definition: MachinePipeliner.h:566
llvm::NodeSet::count
unsigned count(SUnit *SU) const
Definition: MachinePipeliner.h:362
llvm::SMSchedule::finalizeSchedule
void finalizeSchedule(SwingSchedulerDAG *SSD)
After the schedule has been formed, call this function to combine the instructions from the different...
Definition: MachinePipeliner.cpp:2949
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::ResourceManager::reserveResources
void reserveResources(const MCInstrDesc *MID)
Reserve the resources occupied by a MCInstrDesc and change the current state to reflect that change.
Definition: MachinePipeliner.cpp:3107
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::SetVector::clear
void clear()
Completely clear the SetVector.
Definition: SetVector.h:220
llvm::ScheduleDAGInstrs::MLI
const MachineLoopInfo * MLI
Definition: ScheduleDAGInstrs.h:121
llvm::NodeSet::remove_if
bool remove_if(UnaryPredicate P)
Definition: MachinePipeliner.h:358
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
llvm::ResourceManager::initProcResourceVectors
void initProcResourceVectors(const MCSchedModel &SM, SmallVectorImpl< uint64_t > &Masks)
Definition: MachinePipeliner.cpp:3024
llvm::SwingSchedulerDAG::getDepth
unsigned getDepth(SUnit *Node)
The depth, in the dependence graph, for a node.
Definition: MachinePipeliner.h:229
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::NodeSet::clear
void clear()
Definition: MachinePipeliner.h:396
llvm::MachinePipeliner::TII
const TargetInstrInfo * TII
Definition: MachinePipeliner.h:71
llvm::SMSchedule::computeUnpipelineableNodes
SmallSet< SUnit *, 8 > computeUnpipelineableNodes(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
Determine transitive dependences of unpipelineable instructions.
Definition: MachinePipeliner.cpp:2710
llvm::SwingSchedulerDAG::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Definition: MachinePipeliner.h:281
llvm::SetVector::count
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
Definition: SetVector.h:215
llvm::NodeSet::computeNodeSetInfo
void computeNodeSetInfo(SwingSchedulerDAG *SSD)
Summarize node functions for the entire node set.
Definition: MachinePipeliner.h:385
llvm::ResourceManager::clearResources
void clearResources()
Reset the state.
Definition: MachinePipeliner.cpp:3155
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SMSchedule::print
void print(raw_ostream &os) const
Print the schedule information to the given output.
Definition: MachinePipeliner.cpp:3004
llvm::SwingSchedulerDAG::applyInstrChange
void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule)
Apply changes to the instruction if needed.
Definition: MachinePipeliner.cpp:2217
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:385
llvm::SDep::getKind
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:486
AA
llvm::NodeSet::isExceedSU
bool isExceedSU(SUnit *SU)
Definition: MachinePipeliner.h:378
llvm::MachinePipeliner::disabledByPragma
bool disabledByPragma
Definition: MachinePipeliner.h:73
llvm::SMSchedule::earliestCycleInChain
int earliestCycleInChain(const SDep &Dep)
Return the cycle of the earliest scheduled instruction in the dependence chain.
Definition: MachinePipeliner.cpp:2411
llvm::SetVector::end
iterator end()
Get an iterator to the end of the SetVector.
Definition: SetVector.h:92
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::MachinePipeliner::LoopInfo
Cache the target analysis information about the loop.
Definition: MachinePipeliner.h:81
llvm::MachinePipeliner::NumTries
static int NumTries
Definition: MachinePipeliner.h:77
llvm::rdf::NodeSet
std::set< NodeId > NodeSet
Definition: RDFGraph.h:513
llvm::MachinePipeliner::LoopInfo::TBB
MachineBasicBlock * TBB
Definition: MachinePipeliner.h:82
llvm::NodeSet::getNode
SUnit * getNode(unsigned i) const
Definition: MachinePipeliner.h:370
llvm::MachinePipeliner::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
The "main" function for implementing Swing Modulo Scheduling.
Definition: MachinePipeliner.cpp:194
llvm::ScheduleDAGMutation
Mutate the DAG as a postpass after normal DAG building.
Definition: ScheduleDAGMutation.h:22
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::NodeSet::insert
bool insert(SUnit *SU)
Definition: MachinePipeliner.h:354
llvm::NodeSet::insert
void insert(iterator S, iterator E)
Definition: MachinePipeliner.h:356
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::MachinePipeliner::II_setByPragma
unsigned II_setByPragma
Definition: MachinePipeliner.h:74
llvm::SMSchedule::getMaxStageCount
unsigned getMaxStageCount()
Return the maximum stage count needed for this schedule.
Definition: MachinePipeliner.h:588
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::NodeSet::getLatency
unsigned getLatency()
Definition: MachinePipeliner.h:392
llvm::NodeSet::NodeSet
NodeSet()=default
llvm::SMSchedule::cycleScheduled
unsigned cycleScheduled(SUnit *SU) const
Return the cycle for a scheduled instruction.
Definition: MachinePipeliner.h:581
llvm::SMSchedule::latestCycleInChain
int latestCycleInChain(const SDep &Dep)
Return the cycle of the latest scheduled instruction in the dependence chain.
Definition: MachinePipeliner.cpp:2434
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
llvm::MachinePipeliner::MLI
const MachineLoopInfo * MLI
Definition: MachinePipeliner.h:68
llvm::SwingSchedulerDAG::fixupRegisterOverlaps
void fixupRegisterOverlaps(std::deque< SUnit * > &Instrs)
Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes ...
Definition: MachinePipeliner.cpp:2900
llvm::NodeSet::operator>
bool operator>(const NodeSet &RHS) const
Sort the node sets by importance.
Definition: MachinePipeliner.h:412
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
InitializePasses.h
llvm::ResourceManager
Definition: MachinePipeliner.h:443
llvm::SwingSchedulerDAG::getASAP
int getASAP(SUnit *Node)
Return the earliest time an instruction may be scheduled.
Definition: MachinePipeliner.h:219
llvm::NodeSet::NodeSet
NodeSet(iterator S, iterator E)
Definition: MachinePipeliner.h:334
llvm::ScheduleDAG::ExitSU
SUnit ExitSU
Special node for the region exit.
Definition: ScheduleDAG.h:564
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SwingSchedulerDAG::hasNewSchedule
bool hasNewSchedule()
Return true if the loop kernel has been scheduled.
Definition: MachinePipeliner.h:216
llvm::SMSchedule::stageScheduled
int stageScheduled(SUnit *SU) const
Return the stage for a scheduled instruction.
Definition: MachinePipeliner.h:572
SetVector.h
llvm::SMSchedule
This class represents the scheduled code.
Definition: MachinePipeliner.h:497
MachineDominators.h
llvm::SwingSchedulerDAG::getInstrBaseReg
unsigned getInstrBaseReg(SUnit *SU)
Return the new base register that was stored away for the changed instruction.
Definition: MachinePipeliner.h:273
llvm::MachinePipeliner::MDT
const MachineDominatorTree * MDT
Definition: MachinePipeliner.h:69