LLVM  13.0.0git
MachinePipeliner.h
Go to the documentation of this file.
1 //===- MachinePipeliner.h - Machine Software Pipeliner Pass -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // An implementation of the Swing Modulo Scheduling (SMS) software pipeliner.
10 //
11 // Software pipelining (SWP) is an instruction scheduling technique for loops
12 // that overlap loop iterations and exploits ILP via a compiler transformation.
13 //
14 // Swing Modulo Scheduling is an implementation of software pipelining
15 // that generates schedules that are near optimal in terms of initiation
16 // interval, register requirements, and stage count. See the papers:
17 //
18 // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa,
19 // A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996
20 // Conference on Parallel Architectures and Compilation Techiniques.
21 //
22 // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J.
23 // Llosa, E. Ayguade, A. Gonzalez, M. Valero, and J. Eckhardt. In IEEE
24 // Transactions on Computers, Vol. 50, No. 3, 2001.
25 //
26 // "An Implementation of Swing Modulo Scheduling With Extensions for
27 // Superblocks", by T. Lattner, Master's Thesis, University of Illinois at
28 // Urbana-Champaign, 2005.
29 //
30 //
31 // The SMS algorithm consists of three main steps after computing the minimal
32 // initiation interval (MII).
33 // 1) Analyze the dependence graph and compute information about each
34 // instruction in the graph.
35 // 2) Order the nodes (instructions) by priority based upon the heuristics
36 // described in the algorithm.
37 // 3) Attempt to schedule the nodes in the specified order using the MII.
38 //
39 //===----------------------------------------------------------------------===//
40 #ifndef LLVM_CODEGEN_MACHINEPIPELINER_H
41 #define LLVM_CODEGEN_MACHINEPIPELINER_H
42 
48 #include "llvm/InitializePasses.h"
49 
50 namespace llvm {
51 
52 class AAResults;
53 class NodeSet;
54 class SMSchedule;
55 
56 extern cl::opt<bool> SwpEnableCopyToPhi;
57 
58 /// The main class in the implementation of the target independent
59 /// software pipeliner pass.
61 public:
62  MachineFunction *MF = nullptr;
64  const MachineLoopInfo *MLI = nullptr;
65  const MachineDominatorTree *MDT = nullptr;
67  const TargetInstrInfo *TII = nullptr;
69  bool disabledByPragma = false;
70  unsigned II_setByPragma = 0;
71 
72 #ifndef NDEBUG
73  static int NumTries;
74 #endif
75 
76  /// Cache the target analysis information about the loop.
77  struct LoopInfo {
78  MachineBasicBlock *TBB = nullptr;
79  MachineBasicBlock *FBB = nullptr;
83  };
85 
86  static char ID;
87 
90  }
91 
92  bool runOnMachineFunction(MachineFunction &MF) override;
93 
94  void getAnalysisUsage(AnalysisUsage &AU) const override;
95 
96 private:
97  void preprocessPhiNodes(MachineBasicBlock &B);
98  bool canPipelineLoop(MachineLoop &L);
99  bool scheduleLoop(MachineLoop &L);
100  bool swingModuloScheduler(MachineLoop &L);
101  void setPragmaPipelineOptions(MachineLoop &L);
102 };
103 
104 /// This class builds the dependence graph for the instructions in a loop,
105 /// and attempts to schedule the instructions using the SMS algorithm.
108  /// The minimum initiation interval between iterations for this schedule.
109  unsigned MII = 0;
110  /// The maximum initiation interval between iterations for this schedule.
111  unsigned MAX_II = 0;
112  /// Set to true if a valid pipelined schedule is found for the loop.
113  bool Scheduled = false;
114  MachineLoop &Loop;
115  LiveIntervals &LIS;
116  const RegisterClassInfo &RegClassInfo;
117  unsigned II_setByPragma = 0;
118 
119  /// A toplogical ordering of the SUnits, which is needed for changing
120  /// dependences and iterating over the SUnits.
122 
123  struct NodeInfo {
124  int ASAP = 0;
125  int ALAP = 0;
126  int ZeroLatencyDepth = 0;
127  int ZeroLatencyHeight = 0;
128 
129  NodeInfo() = default;
130  };
131  /// Computed properties for each node in the graph.
132  std::vector<NodeInfo> ScheduleInfo;
133 
134  enum OrderKind { BottomUp = 0, TopDown = 1 };
135  /// Computed node ordering for scheduling.
136  SetVector<SUnit *> NodeOrder;
137 
142 
143  /// Instructions to change when emitting the final schedule.
145 
146  /// We may create a new instruction, so remember it because it
147  /// must be deleted when the pass is finished.
149 
150  /// Ordered list of DAG postprocessing steps.
151  std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
152 
153  /// Helper class to implement Johnson's circuit finding algorithm.
154  class Circuits {
155  std::vector<SUnit> &SUnits;
156  SetVector<SUnit *> Stack;
157  BitVector Blocked;
160  // Node to Index from ScheduleDAGTopologicalSort
161  std::vector<int> *Node2Idx;
162  unsigned NumPaths;
163  static unsigned MaxPaths;
164 
165  public:
166  Circuits(std::vector<SUnit> &SUs, ScheduleDAGTopologicalSort &Topo)
167  : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {
168  Node2Idx = new std::vector<int>(SUs.size());
169  unsigned Idx = 0;
170  for (const auto &NodeNum : Topo)
171  Node2Idx->at(NodeNum) = Idx++;
172  }
173 
174  ~Circuits() { delete Node2Idx; }
175 
176  /// Reset the data structures used in the circuit algorithm.
177  void reset() {
178  Stack.clear();
179  Blocked.reset();
180  B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
181  NumPaths = 0;
182  }
183 
184  void createAdjacencyStructure(SwingSchedulerDAG *DAG);
185  bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false);
186  void unblock(int U);
187  };
188 
189  struct CopyToPhiMutation : public ScheduleDAGMutation {
190  void apply(ScheduleDAGInstrs *DAG) override;
191  };
192 
193 public:
195  const RegisterClassInfo &rci, unsigned II)
196  : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
197  RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
198  P.MF->getSubtarget().getSMSMutations(Mutations);
199  if (SwpEnableCopyToPhi)
200  Mutations.push_back(std::make_unique<CopyToPhiMutation>());
201  }
202 
203  void schedule() override;
204  void finishBlock() override;
205 
206  /// Return true if the loop kernel has been scheduled.
207  bool hasNewSchedule() { return Scheduled; }
208 
209  /// Return the earliest time an instruction may be scheduled.
210  int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; }
211 
212  /// Return the latest time an instruction my be scheduled.
213  int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; }
214 
215  /// The mobility function, which the number of slots in which
216  /// an instruction may be scheduled.
217  int getMOV(SUnit *Node) { return getALAP(Node) - getASAP(Node); }
218 
219  /// The depth, in the dependence graph, for a node.
220  unsigned getDepth(SUnit *Node) { return Node->getDepth(); }
221 
222  /// The maximum unweighted length of a path from an arbitrary node to the
223  /// given node in which each edge has latency 0
225  return ScheduleInfo[Node->NodeNum].ZeroLatencyDepth;
226  }
227 
228  /// The height, in the dependence graph, for a node.
229  unsigned getHeight(SUnit *Node) { return Node->getHeight(); }
230 
231  /// The maximum unweighted length of a path from the given node to an
232  /// arbitrary node in which each edge has latency 0
234  return ScheduleInfo[Node->NodeNum].ZeroLatencyHeight;
235  }
236 
237  /// Return true if the dependence is a back-edge in the data dependence graph.
238  /// Since the DAG doesn't contain cycles, we represent a cycle in the graph
239  /// using an anti dependence from a Phi to an instruction.
240  bool isBackedge(SUnit *Source, const SDep &Dep) {
241  if (Dep.getKind() != SDep::Anti)
242  return false;
243  return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
244  }
245 
246  bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
247 
248  /// The distance function, which indicates that operation V of iteration I
249  /// depends on operations U of iteration I-distance.
250  unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) {
251  // Instructions that feed a Phi have a distance of 1. Computing larger
252  // values for arrays requires data dependence information.
253  if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
254  return 1;
255  return 0;
256  }
257 
258  void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule);
259 
260  void fixupRegisterOverlaps(std::deque<SUnit *> &Instrs);
261 
262  /// Return the new base register that was stored away for the changed
263  /// instruction.
264  unsigned getInstrBaseReg(SUnit *SU) {
266  InstrChanges.find(SU);
267  if (It != InstrChanges.end())
268  return It->second.first;
269  return 0;
270  }
271 
272  void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
273  Mutations.push_back(std::move(Mutation));
274  }
275 
276  static bool classof(const ScheduleDAGInstrs *DAG) { return true; }
277 
278 private:
279  void addLoopCarriedDependences(AAResults *AA);
280  void updatePhiDependences();
281  void changeDependences();
282  unsigned calculateResMII();
283  unsigned calculateRecMII(NodeSetType &RecNodeSets);
284  void findCircuits(NodeSetType &NodeSets);
285  void fuseRecs(NodeSetType &NodeSets);
286  void removeDuplicateNodes(NodeSetType &NodeSets);
287  void computeNodeFunctions(NodeSetType &NodeSets);
288  void registerPressureFilter(NodeSetType &NodeSets);
289  void colocateNodeSets(NodeSetType &NodeSets);
290  void checkNodeSets(NodeSetType &NodeSets);
291  void groupRemainingNodes(NodeSetType &NodeSets);
292  void addConnectedNodes(SUnit *SU, NodeSet &NewSet,
293  SetVector<SUnit *> &NodesAdded);
294  void computeNodeOrder(NodeSetType &NodeSets);
295  void checkValidNodeOrder(const NodeSetType &Circuits) const;
296  bool schedulePipeline(SMSchedule &Schedule);
297  bool computeDelta(MachineInstr &MI, unsigned &Delta);
298  MachineInstr *findDefInLoop(Register Reg);
299  bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
300  unsigned &OffsetPos, unsigned &NewBase,
301  int64_t &NewOffset);
302  void postprocessDAG();
303  /// Set the Minimum Initiation Interval for this schedule attempt.
304  void setMII(unsigned ResMII, unsigned RecMII);
305  /// Set the Maximum Initiation Interval for this schedule attempt.
306  void setMAX_II();
307 };
308 
309 /// A NodeSet contains a set of SUnit DAG nodes with additional information
310 /// that assigns a priority to the set.
311 class NodeSet {
312  SetVector<SUnit *> Nodes;
313  bool HasRecurrence = false;
314  unsigned RecMII = 0;
315  int MaxMOV = 0;
316  unsigned MaxDepth = 0;
317  unsigned Colocate = 0;
318  SUnit *ExceedPressure = nullptr;
319  unsigned Latency = 0;
320 
321 public:
323 
324  NodeSet() = default;
325  NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {
326  Latency = 0;
327  for (unsigned i = 0, e = Nodes.size(); i < e; ++i) {
328  DenseMap<SUnit *, unsigned> SuccSUnitLatency;
329  for (const SDep &Succ : Nodes[i]->Succs) {
330  auto SuccSUnit = Succ.getSUnit();
331  if (!Nodes.count(SuccSUnit))
332  continue;
333  unsigned CurLatency = Succ.getLatency();
334  unsigned MaxLatency = 0;
335  if (SuccSUnitLatency.count(SuccSUnit))
336  MaxLatency = SuccSUnitLatency[SuccSUnit];
337  if (CurLatency > MaxLatency)
338  SuccSUnitLatency[SuccSUnit] = CurLatency;
339  }
340  for (auto SUnitLatency : SuccSUnitLatency)
341  Latency += SUnitLatency.second;
342  }
343  }
344 
345  bool insert(SUnit *SU) { return Nodes.insert(SU); }
346 
347  void insert(iterator S, iterator E) { Nodes.insert(S, E); }
348 
349  template <typename UnaryPredicate> bool remove_if(UnaryPredicate P) {
350  return Nodes.remove_if(P);
351  }
352 
353  unsigned count(SUnit *SU) const { return Nodes.count(SU); }
354 
355  bool hasRecurrence() { return HasRecurrence; };
356 
357  unsigned size() const { return Nodes.size(); }
358 
359  bool empty() const { return Nodes.empty(); }
360 
361  SUnit *getNode(unsigned i) const { return Nodes[i]; };
362 
363  void setRecMII(unsigned mii) { RecMII = mii; };
364 
365  void setColocate(unsigned c) { Colocate = c; };
366 
367  void setExceedPressure(SUnit *SU) { ExceedPressure = SU; }
368 
369  bool isExceedSU(SUnit *SU) { return ExceedPressure == SU; }
370 
371  int compareRecMII(NodeSet &RHS) { return RecMII - RHS.RecMII; }
372 
373  int getRecMII() { return RecMII; }
374 
375  /// Summarize node functions for the entire node set.
377  for (SUnit *SU : *this) {
378  MaxMOV = std::max(MaxMOV, SSD->getMOV(SU));
379  MaxDepth = std::max(MaxDepth, SSD->getDepth(SU));
380  }
381  }
382 
383  unsigned getLatency() { return Latency; }
384 
385  unsigned getMaxDepth() { return MaxDepth; }
386 
387  void clear() {
388  Nodes.clear();
389  RecMII = 0;
390  HasRecurrence = false;
391  MaxMOV = 0;
392  MaxDepth = 0;
393  Colocate = 0;
394  ExceedPressure = nullptr;
395  }
396 
397  operator SetVector<SUnit *> &() { return Nodes; }
398 
399  /// Sort the node sets by importance. First, rank them by recurrence MII,
400  /// then by mobility (least mobile done first), and finally by depth.
401  /// Each node set may contain a colocate value which is used as the first
402  /// tie breaker, if it's set.
403  bool operator>(const NodeSet &RHS) const {
404  if (RecMII == RHS.RecMII) {
405  if (Colocate != 0 && RHS.Colocate != 0 && Colocate != RHS.Colocate)
406  return Colocate < RHS.Colocate;
407  if (MaxMOV == RHS.MaxMOV)
408  return MaxDepth > RHS.MaxDepth;
409  return MaxMOV < RHS.MaxMOV;
410  }
411  return RecMII > RHS.RecMII;
412  }
413 
414  bool operator==(const NodeSet &RHS) const {
415  return RecMII == RHS.RecMII && MaxMOV == RHS.MaxMOV &&
416  MaxDepth == RHS.MaxDepth;
417  }
418 
419  bool operator!=(const NodeSet &RHS) const { return !operator==(RHS); }
420 
421  iterator begin() { return Nodes.begin(); }
422  iterator end() { return Nodes.end(); }
423  void print(raw_ostream &os) const;
424 
425 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
426  LLVM_DUMP_METHOD void dump() const;
427 #endif
428 };
429 
430 // 16 was selected based on the number of ProcResource kinds for all
431 // existing Subtargets, so that SmallVector don't need to resize too often.
432 static const int DefaultProcResSize = 16;
433 
435 private:
436  const MCSubtargetInfo *STI;
437  const MCSchedModel &SM;
438  const bool UseDFA;
439  std::unique_ptr<DFAPacketizer> DFAResources;
440  /// Each processor resource is associated with a so-called processor resource
441  /// mask. This vector allows to correlate processor resource IDs with
442  /// processor resource masks. There is exactly one element per each processor
443  /// resource declared by the scheduling model.
445 
447 
448 public:
450  : STI(ST), SM(ST->getSchedModel()), UseDFA(ST->useDFAforSMS()),
451  ProcResourceMasks(SM.getNumProcResourceKinds(), 0),
452  ProcResourceCount(SM.getNumProcResourceKinds(), 0) {
453  if (UseDFA)
454  DFAResources.reset(ST->getInstrInfo()->CreateTargetScheduleState(*ST));
455  initProcResourceVectors(SM, ProcResourceMasks);
456  }
457 
458  void initProcResourceVectors(const MCSchedModel &SM,
460  /// Check if the resources occupied by a MCInstrDesc are available in
461  /// the current state.
462  bool canReserveResources(const MCInstrDesc *MID) const;
463 
464  /// Reserve the resources occupied by a MCInstrDesc and change the current
465  /// state to reflect that change.
466  void reserveResources(const MCInstrDesc *MID);
467 
468  /// Check if the resources occupied by a machine instruction are available
469  /// in the current state.
470  bool canReserveResources(const MachineInstr &MI) const;
471 
472  /// Reserve the resources occupied by a machine instruction and change the
473  /// current state to reflect that change.
474  void reserveResources(const MachineInstr &MI);
475 
476  /// Reset the state
477  void clearResources();
478 };
479 
480 /// This class represents the scheduled code. The main data structure is a
481 /// map from scheduled cycle to instructions. During scheduling, the
482 /// data structure explicitly represents all stages/iterations. When
483 /// the algorithm finshes, the schedule is collapsed into a single stage,
484 /// which represents instructions from different loop iterations.
485 ///
486 /// The SMS algorithm allows negative values for cycles, so the first cycle
487 /// in the schedule is the smallest cycle value.
488 class SMSchedule {
489 private:
490  /// Map from execution cycle to instructions.
491  DenseMap<int, std::deque<SUnit *>> ScheduledInstrs;
492 
493  /// Map from instruction to execution cycle.
494  std::map<SUnit *, int> InstrToCycle;
495 
496  /// Keep track of the first cycle value in the schedule. It starts
497  /// as zero, but the algorithm allows negative values.
498  int FirstCycle = 0;
499 
500  /// Keep track of the last cycle value in the schedule.
501  int LastCycle = 0;
502 
503  /// The initiation interval (II) for the schedule.
504  int InitiationInterval = 0;
505 
506  /// Target machine information.
507  const TargetSubtargetInfo &ST;
508 
509  /// Virtual register information.
510  MachineRegisterInfo &MRI;
511 
512  ResourceManager ProcItinResources;
513 
514 public:
516  : ST(mf->getSubtarget()), MRI(mf->getRegInfo()), ProcItinResources(&ST) {}
517 
518  void reset() {
519  ScheduledInstrs.clear();
520  InstrToCycle.clear();
521  FirstCycle = 0;
522  LastCycle = 0;
523  InitiationInterval = 0;
524  }
525 
526  /// Set the initiation interval for this schedule.
527  void setInitiationInterval(int ii) { InitiationInterval = ii; }
528 
529  /// Return the initiation interval for this schedule.
530  int getInitiationInterval() const { return InitiationInterval; }
531 
532  /// Return the first cycle in the completed schedule. This
533  /// can be a negative value.
534  int getFirstCycle() const { return FirstCycle; }
535 
536  /// Return the last cycle in the finalized schedule.
537  int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; }
538 
539  /// Return the cycle of the earliest scheduled instruction in the dependence
540  /// chain.
541  int earliestCycleInChain(const SDep &Dep);
542 
543  /// Return the cycle of the latest scheduled instruction in the dependence
544  /// chain.
545  int latestCycleInChain(const SDep &Dep);
546 
547  void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
548  int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG);
549  bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
550 
551  /// Iterators for the cycle to instruction map.
553  using const_sched_iterator =
555 
556  /// Return true if the instruction is scheduled at the specified stage.
557  bool isScheduledAtStage(SUnit *SU, unsigned StageNum) {
558  return (stageScheduled(SU) == (int)StageNum);
559  }
560 
561  /// Return the stage for a scheduled instruction. Return -1 if
562  /// the instruction has not been scheduled.
563  int stageScheduled(SUnit *SU) const {
564  std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
565  if (it == InstrToCycle.end())
566  return -1;
567  return (it->second - FirstCycle) / InitiationInterval;
568  }
569 
570  /// Return the cycle for a scheduled instruction. This function normalizes
571  /// the first cycle to be 0.
572  unsigned cycleScheduled(SUnit *SU) const {
573  std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
574  assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled.");
575  return (it->second - FirstCycle) % InitiationInterval;
576  }
577 
578  /// Return the maximum stage count needed for this schedule.
579  unsigned getMaxStageCount() {
580  return (LastCycle - FirstCycle) / InitiationInterval;
581  }
582 
583  /// Return the instructions that are scheduled at the specified cycle.
584  std::deque<SUnit *> &getInstructions(int cycle) {
585  return ScheduledInstrs[cycle];
586  }
587 
590  void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
591  std::deque<SUnit *> &Insts);
594  MachineOperand &MO);
595  void print(raw_ostream &os) const;
596  void dump() const;
597 };
598 
599 } // end namespace llvm
600 
601 #endif // LLVM_CODEGEN_MACHINEPIPELINER_H
i
i
Definition: README.txt:29
llvm::SwingSchedulerDAG
This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
Definition: MachinePipeliner.h:106
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:499
llvm
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachinePipeliner::LoopInfo::FBB
MachineBasicBlock * FBB
Definition: MachinePipeliner.h:79
llvm::SwingSchedulerDAG::getHeight
unsigned getHeight(SUnit *Node)
The height, in the dependence graph, for a node.
Definition: MachinePipeliner.h:229
llvm::SwingSchedulerDAG::finishBlock
void finishBlock() override
Clean up after the software pipeliner runs.
Definition: MachinePipeliner.cpp:651
llvm::NodeSet::print
void print(raw_ostream &os) const
Definition: MachinePipeliner.cpp:2935
llvm::NodeSet::dump
LLVM_DUMP_METHOD void dump() const
Definition: MachinePipeliner.cpp:2961
llvm::NodeSet::end
iterator end()
Definition: MachinePipeliner.h:422
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:32
llvm::MachinePipeliner::MF
MachineFunction * MF
Definition: MachinePipeliner.h:62
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
ScheduleDAGInstrs.h
llvm::SetVector::size
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:77
it
Reference model for inliner Oz decision policy Note this model is also referenced by test Transforms Inline ML tests if replacing it
Definition: README.txt:3
llvm::NodeSet::compareRecMII
int compareRecMII(NodeSet &RHS)
Definition: MachinePipeliner.h:371
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::NodeSet::iterator
SetVector< SUnit * >::const_iterator iterator
Definition: MachinePipeliner.h:322
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:144
llvm::SDep::Anti
@ Anti
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:54
llvm::SwingSchedulerDAG::schedule
void schedule() override
We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing ...
Definition: MachinePipeliner.cpp:472
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
RegisterClassInfo.h
llvm::SetVector::const_iterator
typename vector_type::const_iterator const_iterator
Definition: SetVector.h:49
llvm::DenseMapIterator
Definition: DenseMap.h:56
TargetInstrInfo.h
llvm::SwingSchedulerDAG::isLoopCarriedDep
bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc=true)
Return true for an order or output dependence that is loop carried potentially.
Definition: MachinePipeliner.cpp:2278
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
llvm::SwingSchedulerDAG::getZeroLatencyHeight
int getZeroLatencyHeight(SUnit *Node)
The maximum unweighted length of a path from the given node to an arbitrary node in which each edge h...
Definition: MachinePipeliner.h:233
llvm::NodeSet::empty
bool empty() const
Definition: MachinePipeliner.h:359
llvm::SMSchedule::insert
bool insert(SUnit *SU, int StartCycle, int EndCycle, int II)
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the E...
Definition: MachinePipeliner.cpp:2364
llvm::MachinePipeliner::LoopInfo::BrCond
SmallVector< MachineOperand, 4 > BrCond
Definition: MachinePipeliner.h:80
llvm::SetVector::remove_if
bool remove_if(UnaryPredicate P)
Remove items from the set vector based on a predicate function.
Definition: SetVector.h:199
llvm::SMSchedule::SMSchedule
SMSchedule(MachineFunction *mf)
Definition: MachinePipeliner.h:515
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
llvm::MachinePipeliner::LI
LoopInfo LI
Definition: MachinePipeliner.h:84
llvm::ScheduleDAGTopologicalSort
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
Definition: ScheduleDAG.h:694
llvm::ResourceManager::ResourceManager
ResourceManager(const TargetSubtargetInfo *ST)
Definition: MachinePipeliner.h:449
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::cl::apply
void apply(Opt *O, const Mod &M, const Mods &... Ms)
Definition: CommandLine.h:1305
llvm::SetVector::begin
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:82
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SMSchedule::dump
void dump() const
Utility function used for debugging to print the schedule.
Definition: MachinePipeliner.cpp:2960
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::SwingSchedulerDAG::getDistance
unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep)
The distance function, which indicates that operation V of iteration I depends on operations U of ite...
Definition: MachinePipeliner.h:250
llvm::SwingSchedulerDAG::isBackedge
bool isBackedge(SUnit *Source, const SDep &Dep)
Return true if the dependence is a back-edge in the data dependence graph.
Definition: MachinePipeliner.h:240
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SwingSchedulerDAG::getMOV
int getMOV(SUnit *Node)
The mobility function, which the number of slots in which an instruction may be scheduled.
Definition: MachinePipeliner.h:217
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::SMSchedule::getFinalCycle
int getFinalCycle() const
Return the last cycle in the finalized schedule.
Definition: MachinePipeliner.h:537
llvm::SMSchedule::getFirstCycle
int getFirstCycle() const
Return the first cycle in the completed schedule.
Definition: MachinePipeliner.h:534
false
Definition: StackSlotColoring.cpp:142
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SMSchedule::setInitiationInterval
void setInitiationInterval(int ii)
Set the initiation interval for this schedule.
Definition: MachinePipeliner.h:527
llvm::SMSchedule::isValidSchedule
bool isValidSchedule(SwingSchedulerDAG *SSD)
Definition: MachinePipeliner.cpp:2720
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::SMSchedule::orderDependence
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts)
Order the instructions within a cycle so that the definitions occur before the uses.
Definition: MachinePipeliner.cpp:2537
llvm::SMSchedule::reset
void reset()
Definition: MachinePipeliner.h:518
llvm::BitVector
Definition: BitVector.h:74
llvm::initializeMachinePipelinerPass
void initializeMachinePipelinerPass(PassRegistry &)
c
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
Definition: README.txt:418
llvm::NodeSet
A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...
Definition: MachinePipeliner.h:311
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
llvm::NodeSet::setColocate
void setColocate(unsigned c)
Definition: MachinePipeliner.h:365
llvm::SMSchedule::isLoopCarried
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi)
Return true if the scheduled Phi has a loop carried operand.
Definition: MachinePipeliner.cpp:2666
llvm::NodeSet::operator!=
bool operator!=(const NodeSet &RHS) const
Definition: MachinePipeliner.h:419
llvm::NodeSet::setExceedPressure
void setExceedPressure(SUnit *SU)
Definition: MachinePipeliner.h:367
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachinePipeliner
The main class in the implementation of the target independent software pipeliner pass.
Definition: MachinePipeliner.h:60
llvm::ResourceManager::canReserveResources
bool canReserveResources(const MCInstrDesc *MID) const
Check if the resources occupied by a MCInstrDesc are available in the current state.
Definition: MachinePipeliner.cpp:3007
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::NodeSet::begin
iterator begin()
Definition: MachinePipeliner.h:421
llvm::SMSchedule::computeStart
void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG)
Compute the scheduling start slot for the instruction.
Definition: MachinePipeliner.cpp:2476
llvm::SwingSchedulerDAG::classof
static bool classof(const ScheduleDAGInstrs *DAG)
Definition: MachinePipeliner.h:276
llvm::DefaultProcResSize
static const int DefaultProcResSize
Definition: MachinePipeliner.h:432
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::MachinePipeliner::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachinePipeliner.cpp:446
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:111
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SMSchedule::getInitiationInterval
int getInitiationInterval() const
Return the initiation interval for this schedule.
Definition: MachinePipeliner.h:530
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::NodeSet::getRecMII
int getRecMII()
Definition: MachinePipeliner.h:373
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
llvm::NodeSet::getMaxDepth
unsigned getMaxDepth()
Definition: MachinePipeliner.h:385
llvm::MachinePipeliner::ORE
MachineOptimizationRemarkEmitter * ORE
Definition: MachinePipeliner.h:63
llvm::MachinePipeliner::InstrItins
const InstrItineraryData * InstrItins
Definition: MachinePipeliner.h:66
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::SwingSchedulerDAG::getALAP
int getALAP(SUnit *Node)
Return the latest time an instruction my be scheduled.
Definition: MachinePipeliner.h:213
llvm::NodeSet::size
unsigned size() const
Definition: MachinePipeliner.h:357
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::MachinePipeliner::LoopInfo::LoopCompare
MachineInstr * LoopCompare
Definition: MachinePipeliner.h:82
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachinePipeliner::MachinePipeliner
MachinePipeliner()
Definition: MachinePipeliner.h:88
llvm::MachinePipeliner::LoopInfo::LoopInductionVar
MachineInstr * LoopInductionVar
Definition: MachinePipeliner.h:81
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:30
llvm::SMSchedule::isLoopCarriedDefOfUse
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO)
Return true if the instruction is a definition that is loop carried and defines the use on the next i...
Definition: MachinePipeliner.cpp:2694
llvm::NodeSet::setRecMII
void setRecMII(unsigned mii)
Definition: MachinePipeliner.h:363
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1243
llvm::SMSchedule::getInstructions
std::deque< SUnit * > & getInstructions(int cycle)
Return the instructions that are scheduled at the specified cycle.
Definition: MachinePipeliner.h:584
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::SwingSchedulerDAG::getZeroLatencyDepth
int getZeroLatencyDepth(SUnit *Node)
The maximum unweighted length of a path from an arbitrary node to the given node in which each edge h...
Definition: MachinePipeliner.h:224
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:98
llvm::SDep::getSUnit
SUnit * getSUnit() const
Definition: ScheduleDAG.h:480
llvm::NodeSet::operator==
bool operator==(const NodeSet &RHS) const
Definition: MachinePipeliner.h:414
llvm::MachinePipeliner::RegClassInfo
RegisterClassInfo RegClassInfo
Definition: MachinePipeliner.h:68
llvm::MachinePipeliner::ID
static char ID
Definition: MachinePipeliner.h:86
llvm::SwpEnableCopyToPhi
cl::opt< bool > SwpEnableCopyToPhi
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
const_iterator
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
Mutation
PowerPC VSX FMA Mutation
Definition: PPCVSXFMAMutate.cpp:391
llvm::NodeSet::hasRecurrence
bool hasRecurrence()
Definition: MachinePipeliner.h:355
Node
Definition: ItaniumDemangle.h:114
llvm::SMSchedule::isScheduledAtStage
bool isScheduledAtStage(SUnit *SU, unsigned StageNum)
Return true if the instruction is scheduled at the specified stage.
Definition: MachinePipeliner.h:557
llvm::NodeSet::count
unsigned count(SUnit *SU) const
Definition: MachinePipeliner.h:353
llvm::SMSchedule::finalizeSchedule
void finalizeSchedule(SwingSchedulerDAG *SSD)
After the schedule has been formed, call this function to combine the instructions from the different...
Definition: MachinePipeliner.cpp:2886
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::ResourceManager::reserveResources
void reserveResources(const MCInstrDesc *MID)
Reserve the resources occupied by a MCInstrDesc and change the current state to reflect that change.
Definition: MachinePipeliner.cpp:3048
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::SetVector::clear
void clear()
Completely clear the SetVector.
Definition: SetVector.h:220
llvm::ScheduleDAGInstrs::MLI
const MachineLoopInfo * MLI
Definition: ScheduleDAGInstrs.h:121
llvm::NodeSet::remove_if
bool remove_if(UnaryPredicate P)
Definition: MachinePipeliner.h:349
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
llvm::ResourceManager::initProcResourceVectors
void initProcResourceVectors(const MCSchedModel &SM, SmallVectorImpl< uint64_t > &Masks)
Definition: MachinePipeliner.cpp:2965
llvm::SwingSchedulerDAG::getDepth
unsigned getDepth(SUnit *Node)
The depth, in the dependence graph, for a node.
Definition: MachinePipeliner.h:220
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:83
llvm::NodeSet::clear
void clear()
Definition: MachinePipeliner.h:387
llvm::MachinePipeliner::TII
const TargetInstrInfo * TII
Definition: MachinePipeliner.h:67
llvm::SwingSchedulerDAG::SwingSchedulerDAG
SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis, const RegisterClassInfo &rci, unsigned II)
Definition: MachinePipeliner.h:194
llvm::SwingSchedulerDAG::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Definition: MachinePipeliner.h:272
llvm::SetVector::count
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
Definition: SetVector.h:215
llvm::NodeSet::computeNodeSetInfo
void computeNodeSetInfo(SwingSchedulerDAG *SSD)
Summarize node functions for the entire node set.
Definition: MachinePipeliner.h:376
llvm::ResourceManager::clearResources
void clearResources()
Reset the state.
Definition: MachinePipeliner.cpp:3096
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:245
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SMSchedule::print
void print(raw_ostream &os) const
Print the schedule information to the given output.
Definition: MachinePipeliner.cpp:2945
llvm::SwingSchedulerDAG::applyInstrChange
void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule)
Apply changes to the instruction if needed.
Definition: MachinePipeliner.cpp:2223
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:384
llvm::SDep::getKind
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:486
llvm::NodeSet::isExceedSU
bool isExceedSU(SUnit *SU)
Definition: MachinePipeliner.h:369
llvm::MachinePipeliner::disabledByPragma
bool disabledByPragma
Definition: MachinePipeliner.h:69
llvm::SMSchedule::earliestCycleInChain
int earliestCycleInChain(const SDep &Dep)
Return the cycle of the earliest scheduled instruction in the dependence chain.
Definition: MachinePipeliner.cpp:2417
llvm::SetVector::end
iterator end()
Get an iterator to the end of the SetVector.
Definition: SetVector.h:92
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::MachinePipeliner::LoopInfo
Cache the target analysis information about the loop.
Definition: MachinePipeliner.h:77
llvm::MachinePipeliner::NumTries
static int NumTries
Definition: MachinePipeliner.h:73
llvm::rdf::NodeSet
std::set< NodeId > NodeSet
Definition: RDFGraph.h:513
llvm::MachinePipeliner::LoopInfo::TBB
MachineBasicBlock * TBB
Definition: MachinePipeliner.h:78
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::NodeSet::getNode
SUnit * getNode(unsigned i) const
Definition: MachinePipeliner.h:361
llvm::MachinePipeliner::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
The "main" function for implementing Swing Modulo Scheduling.
Definition: MachinePipeliner.cpp:196
llvm::ScheduleDAGMutation
Mutate the DAG as a postpass after normal DAG building.
Definition: ScheduleDAGMutation.h:22
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::NodeSet::insert
bool insert(SUnit *SU)
Definition: MachinePipeliner.h:345
llvm::NodeSet::insert
void insert(iterator S, iterator E)
Definition: MachinePipeliner.h:347
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::MachinePipeliner::II_setByPragma
unsigned II_setByPragma
Definition: MachinePipeliner.h:70
llvm::SMSchedule::getMaxStageCount
unsigned getMaxStageCount()
Return the maximum stage count needed for this schedule.
Definition: MachinePipeliner.h:579
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::NodeSet::getLatency
unsigned getLatency()
Definition: MachinePipeliner.h:383
llvm::NodeSet::NodeSet
NodeSet()=default
llvm::SMSchedule::cycleScheduled
unsigned cycleScheduled(SUnit *SU) const
Return the cycle for a scheduled instruction.
Definition: MachinePipeliner.h:572
llvm::SMSchedule::latestCycleInChain
int latestCycleInChain(const SDep &Dep)
Return the cycle of the latest scheduled instruction in the dependence chain.
Definition: MachinePipeliner.cpp:2440
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1789
llvm::MachinePipeliner::MLI
const MachineLoopInfo * MLI
Definition: MachinePipeliner.h:64
llvm::SwingSchedulerDAG::fixupRegisterOverlaps
void fixupRegisterOverlaps(std::deque< SUnit * > &Instrs)
Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes ...
Definition: MachinePipeliner.cpp:2837
llvm::NodeSet::operator>
bool operator>(const NodeSet &RHS) const
Sort the node sets by importance.
Definition: MachinePipeliner.h:403
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
InitializePasses.h
llvm::ResourceManager
Definition: MachinePipeliner.h:434
llvm::SwingSchedulerDAG::getASAP
int getASAP(SUnit *Node)
Return the earliest time an instruction may be scheduled.
Definition: MachinePipeliner.h:210
llvm::NodeSet::NodeSet
NodeSet(iterator S, iterator E)
Definition: MachinePipeliner.h:325
llvm::ScheduleDAG::ExitSU
SUnit ExitSU
Special node for the region exit.
Definition: ScheduleDAG.h:564
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SwingSchedulerDAG::hasNewSchedule
bool hasNewSchedule()
Return true if the loop kernel has been scheduled.
Definition: MachinePipeliner.h:207
llvm::SMSchedule::stageScheduled
int stageScheduled(SUnit *SU) const
Return the stage for a scheduled instruction.
Definition: MachinePipeliner.h:563
llvm::SMSchedule
This class represents the scheduled code.
Definition: MachinePipeliner.h:488
MachineDominators.h
llvm::SwingSchedulerDAG::getInstrBaseReg
unsigned getInstrBaseReg(SUnit *SU)
Return the new base register that was stored away for the changed instruction.
Definition: MachinePipeliner.h:264
llvm::MachinePipeliner::MDT
const MachineDominatorTree * MDT
Definition: MachinePipeliner.h:65