LLVM  15.0.0git
HexagonSubtarget.cpp
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1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonSubtarget.h"
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <map>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "hexagon-subtarget"
37 
38 #define GET_SUBTARGETINFO_CTOR
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #include "HexagonGenSubtargetInfo.inc"
41 
42 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
44 
45 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
47 
48 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
50  cl::desc("Enable the scheduler to generate .cur"));
51 
52 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
54  cl::desc("Disable Hexagon MI Scheduling"));
55 
56 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
58  cl::desc("Enable subregister liveness tracking for Hexagon"));
59 
60 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
62  cl::desc("If present, forces/disables the use of long calls"));
63 
64 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
66  cl::desc("Consider calls to be predicable"));
67 
68 static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
70 
71 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
73 
74 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
76  cl::desc("Enable checking for cache bank conflicts"));
77 
79  "force-hvx-float", cl::Hidden, cl::ZeroOrMore, cl::init(false),
80  cl::desc("Enable the code-generation for vector float instructions on v68."));
81 
83  StringRef FS, const TargetMachine &TM)
84  : HexagonGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
85  OptLevel(TM.getOptLevel()),
86  CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))),
87  TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
88  RegInfo(getHwMode()), TLInfo(TM, *this),
89  InstrItins(getInstrItineraryForCPU(CPUString)) {
91  // Beware of the default constructor of InstrItineraryData: it will
92  // reset all members to 0.
93  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
94 }
95 
98  Optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString);
99  if (ArchVer)
100  HexagonArchVersion = *ArchVer;
101  else
102  llvm_unreachable("Unrecognized Hexagon processor version");
103 
104  UseHVX128BOps = false;
105  UseHVX64BOps = false;
106  UseAudioOps = false;
107  UseLongCalls = false;
108 
109  SubtargetFeatures Features(FS);
110 
111  // Turn on QFloat if the HVX version is v68+.
112  // The function ParseSubtargetFeatures will set feature bits and initialize
113  // subtarget's variables all in one, so there isn't a good way to preprocess
114  // the feature string, other than by tinkering with it directly.
115  auto IsQFloatFS = [](StringRef F) {
116  return F == "+hvx-qfloat" || F == "-hvx-qfloat";
117  };
118  if (!llvm::count_if(Features.getFeatures(), IsQFloatFS)) {
119  auto getHvxVersion = [&Features](StringRef FS) -> StringRef {
120  for (StringRef F : llvm::reverse(Features.getFeatures())) {
121  if (F.startswith("+hvxv"))
122  return F;
123  }
124  for (StringRef F : llvm::reverse(Features.getFeatures())) {
125  if (F == "-hvx")
126  return StringRef();
127  if (F.startswith("+hvx") || F == "-hvx")
128  return F.take_front(4); // Return "+hvx" or "-hvx".
129  }
130  return StringRef();
131  };
132 
133  bool AddQFloat = false;
134  StringRef HvxVer = getHvxVersion(FS);
135  if (HvxVer.startswith("+hvxv")) {
136  int Ver = 0;
137  if (!HvxVer.drop_front(5).consumeInteger(10, Ver) && Ver >= 68)
138  AddQFloat = true;
139  } else if (HvxVer == "+hvx") {
140  if (hasV68Ops())
141  AddQFloat = true;
142  }
143 
144  if (AddQFloat)
145  Features.AddFeature("+hvx-qfloat");
146  }
147 
148  std::string FeatureString = Features.getString();
149  ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FeatureString);
150 
151  // Enable float code generation only if the flag(s) are set and
152  // the feature is enabled. v68 is guarded by additional flags.
153  bool GreaterThanV68 = false;
154  if (useHVXV69Ops())
155  GreaterThanV68 = true;
156 
157  // Support for deprecated qfloat/ieee codegen flags
158  if (!GreaterThanV68) {
160  UseHVXFloatingPoint = true;
161  } else {
162  UseHVXFloatingPoint = true;
163  }
164 
165  if (UseHVXQFloatOps && UseHVXIEEEFPOps && UseHVXFloatingPoint)
166  LLVM_DEBUG(
167  dbgs() << "Behavior is undefined for simultaneous qfloat and ieee hvx codegen...");
168 
170  UseLongCalls = OverrideLongCalls;
171 
173 
174  if (isTinyCore()) {
175  // Tiny core has a single thread, so back-to-back scheduling is enabled by
176  // default.
178  UseBSBScheduling = false;
179  }
180 
181  FeatureBitset FeatureBits = getFeatureBits();
183  setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex));
184  setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits));
185 
186  return *this;
187 }
188 
189 bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const {
190  if (!useHVXOps())
191  return false;
192  if (Ty.isVector())
193  Ty = Ty.getVectorElementType();
194  if (IncludeBool && Ty == MVT::i1)
195  return true;
196  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
197  return llvm::is_contained(ElemTypes, Ty);
198 }
199 
200 bool HexagonSubtarget::isHVXVectorType(MVT VecTy, bool IncludeBool) const {
201  if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
202  return false;
203  MVT ElemTy = VecTy.getVectorElementType();
204  if (!IncludeBool && ElemTy == MVT::i1)
205  return false;
206 
207  unsigned HwLen = getVectorLength();
208  unsigned NumElems = VecTy.getVectorNumElements();
209  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
210 
211  if (IncludeBool && ElemTy == MVT::i1) {
212  // Boolean HVX vector types are formed from regular HVX vector types
213  // by replacing the element type with i1.
214  for (MVT T : ElemTypes)
215  if (NumElems * T.getSizeInBits() == 8 * HwLen)
216  return true;
217  return false;
218  }
219 
220  unsigned VecWidth = VecTy.getSizeInBits();
221  if (VecWidth != 8 * HwLen && VecWidth != 16 * HwLen)
222  return false;
223  return llvm::is_contained(ElemTypes, ElemTy);
224 }
225 
226 bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const {
227  if (!VecTy->isVectorTy() || isa<ScalableVectorType>(VecTy))
228  return false;
229  // Avoid types like <2 x i32*>.
230  Type *ScalTy = VecTy->getScalarType();
231  if (!ScalTy->isIntegerTy() &&
232  !(ScalTy->isFloatingPointTy() && useHVXFloatingPoint()))
233  return false;
234  // The given type may be something like <17 x i32>, which is not MVT,
235  // but can be represented as (non-simple) EVT.
236  EVT Ty = EVT::getEVT(VecTy, /*HandleUnknown*/false);
237  if (Ty.getSizeInBits() <= 64 || !Ty.getVectorElementType().isSimple())
238  return false;
239 
240  auto isHvxTy = [this, IncludeBool](MVT SimpleTy) {
241  if (isHVXVectorType(SimpleTy, IncludeBool))
242  return true;
243  auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy);
244  return Action == TargetLoweringBase::TypeWidenVector;
245  };
246 
247  // Round up EVT to have power-of-2 elements, and keep checking if it
248  // qualifies for HVX, dividing it in half after each step.
249  MVT ElemTy = Ty.getVectorElementType().getSimpleVT();
250  unsigned VecLen = PowerOf2Ceil(Ty.getVectorNumElements());
251  while (ElemTy.getSizeInBits() * VecLen > 64) {
252  MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen);
253  if (SimpleTy.isValid() && isHvxTy(SimpleTy))
254  return true;
255  VecLen /= 2;
256  }
257 
258  return false;
259 }
260 
262  for (SUnit &SU : DAG->SUnits) {
263  if (!SU.isInstr())
264  continue;
265  SmallVector<SDep, 4> Erase;
266  for (auto &D : SU.Preds)
267  if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
268  Erase.push_back(D);
269  for (auto &E : Erase)
270  SU.removePred(E);
271  }
272 }
273 
275  for (SUnit &SU : DAG->SUnits) {
276  // Update the latency of chain edges between v60 vector load or store
277  // instructions to be 1. These instruction cannot be scheduled in the
278  // same packet.
279  MachineInstr &MI1 = *SU.getInstr();
280  auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
281  bool IsStoreMI1 = MI1.mayStore();
282  bool IsLoadMI1 = MI1.mayLoad();
283  if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
284  continue;
285  for (SDep &SI : SU.Succs) {
286  if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
287  continue;
288  MachineInstr &MI2 = *SI.getSUnit()->getInstr();
289  if (!QII->isHVXVec(MI2))
290  continue;
291  if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
292  SI.setLatency(1);
293  SU.setHeightDirty();
294  // Change the dependence in the opposite direction too.
295  for (SDep &PI : SI.getSUnit()->Preds) {
296  if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
297  continue;
298  PI.setLatency(1);
299  SI.getSUnit()->setDepthDirty();
300  }
301  }
302  }
303  }
304 }
305 
306 // Check if a call and subsequent A2_tfrpi instructions should maintain
307 // scheduling affinity. We are looking for the TFRI to be consumed in
308 // the next instruction. This should help reduce the instances of
309 // double register pairs being allocated and scheduled before a call
310 // when not used until after the call. This situation is exacerbated
311 // by the fact that we allocate the pair from the callee saves list,
312 // leading to excess spills and restores.
313 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
314  const HexagonInstrInfo &HII, const SUnit &Inst1,
315  const SUnit &Inst2) const {
316  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
317  return false;
318 
319  // TypeXTYPE are 64 bit operations.
320  unsigned Type = HII.getType(*Inst2.getInstr());
323 }
324 
326  ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
327  SUnit* LastSequentialCall = nullptr;
328  // Map from virtual register to physical register from the copy.
329  DenseMap<unsigned, unsigned> VRegHoldingReg;
330  // Map from the physical register to the instruction that uses virtual
331  // register. This is used to create the barrier edge.
332  DenseMap<unsigned, SUnit *> LastVRegUse;
333  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
334  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
335 
336  // Currently we only catch the situation when compare gets scheduled
337  // before preceding call.
338  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
339  // Remember the call.
340  if (DAG->SUnits[su].getInstr()->isCall())
341  LastSequentialCall = &DAG->SUnits[su];
342  // Look for a compare that defines a predicate.
343  else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
344  DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
345  // Look for call and tfri* instructions.
346  else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
347  shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
348  DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier));
349  // Prevent redundant register copies due to reads and writes of physical
350  // registers. The original motivation for this was the code generated
351  // between two calls, which are caused both the return value and the
352  // argument for the next call being in %r0.
353  // Example:
354  // 1: <call1>
355  // 2: %vreg = COPY %r0
356  // 3: <use of %vreg>
357  // 4: %r0 = ...
358  // 5: <call2>
359  // The scheduler would often swap 3 and 4, so an additional register is
360  // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
361  // this.
362  // The code below checks for all the physical registers, not just R0/D0/V0.
363  else if (SchedRetvalOptimization) {
364  const MachineInstr *MI = DAG->SUnits[su].getInstr();
365  if (MI->isCopy() &&
366  Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
367  // %vregX = COPY %r0
368  VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
369  LastVRegUse.erase(MI->getOperand(1).getReg());
370  } else {
371  for (const MachineOperand &MO : MI->operands()) {
372  if (!MO.isReg())
373  continue;
374  if (MO.isUse() && !MI->isCopy() &&
375  VRegHoldingReg.count(MO.getReg())) {
376  // <use of %vregX>
377  LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
378  } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
379  for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
380  ++AI) {
381  if (LastVRegUse.count(*AI) &&
382  LastVRegUse[*AI] != &DAG->SUnits[su])
383  // %r0 = ...
384  DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
385  LastVRegUse.erase(*AI);
386  }
387  }
388  }
389  }
390  }
391  }
392 }
393 
396  return;
397 
398  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
399 
400  // Create artificial edges between loads that could likely cause a bank
401  // conflict. Since such loads would normally not have any dependency
402  // between them, we cannot rely on existing edges.
403  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
404  SUnit &S0 = DAG->SUnits[i];
405  MachineInstr &L0 = *S0.getInstr();
406  if (!L0.mayLoad() || L0.mayStore() ||
408  continue;
409  int64_t Offset0;
410  unsigned Size0;
411  MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
412  // Is the access size is longer than the L1 cache line, skip the check.
413  if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
414  continue;
415  // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
416  for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
417  SUnit &S1 = DAG->SUnits[j];
418  MachineInstr &L1 = *S1.getInstr();
419  if (!L1.mayLoad() || L1.mayStore() ||
421  continue;
422  int64_t Offset1;
423  unsigned Size1;
424  MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
425  if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
426  BaseOp0->getReg() != BaseOp1->getReg())
427  continue;
428  // Check bits 3 and 4 of the offset: if they differ, a bank conflict
429  // is unlikely.
430  if (((Offset0 ^ Offset1) & 0x18) != 0)
431  continue;
432  // Bits 3 and 4 are the same, add an artificial edge and set extra
433  // latency.
434  SDep A(&S0, SDep::Artificial);
435  A.setLatency(1);
436  S1.addPred(A, true);
437  }
438  }
439 }
440 
441 /// Enable use of alias analysis during code generation (during MI
442 /// scheduling, DAGCombine, etc.).
444  if (OptLevel != CodeGenOpt::None)
445  return true;
446  return false;
447 }
448 
449 /// Perform target specific adjustments to the latency of a schedule
450 /// dependency.
452  SUnit *Dst, int DstOpIdx,
453  SDep &Dep) const {
454  if (!Src->isInstr() || !Dst->isInstr())
455  return;
456 
457  MachineInstr *SrcInst = Src->getInstr();
458  MachineInstr *DstInst = Dst->getInstr();
459  const HexagonInstrInfo *QII = getInstrInfo();
460 
461  // Instructions with .new operands have zero latency.
462  SmallSet<SUnit *, 4> ExclSrc;
463  SmallSet<SUnit *, 4> ExclDst;
464  if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
465  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
466  Dep.setLatency(0);
467  return;
468  }
469 
470  // Set the latency for a copy to zero since we hope that is will get
471  // removed.
472  if (DstInst->isCopy())
473  Dep.setLatency(0);
474 
475  // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine
476  // the correct latency.
477  // If there are multiple uses of the def of COPY/REG_SEQUENCE, set the latency
478  // only if the latencies on all the uses are equal, otherwise set it to
479  // default.
480  if ((DstInst->isRegSequence() || DstInst->isCopy())) {
481  Register DReg = DstInst->getOperand(0).getReg();
482  int DLatency = -1;
483  for (const auto &DDep : Dst->Succs) {
484  MachineInstr *DDst = DDep.getSUnit()->getInstr();
485  int UseIdx = -1;
486  for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
487  const MachineOperand &MO = DDst->getOperand(OpNum);
488  if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
489  UseIdx = OpNum;
490  break;
491  }
492  }
493 
494  if (UseIdx == -1)
495  continue;
496 
497  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0,
498  *DDst, UseIdx));
499  // Set DLatency for the first time.
500  DLatency = (DLatency == -1) ? Latency : DLatency;
501 
502  // For multiple uses, if the Latency is different across uses, reset
503  // DLatency.
504  if (DLatency != Latency) {
505  DLatency = -1;
506  break;
507  }
508  }
509 
510  DLatency = std::max(DLatency, 0);
511  Dep.setLatency((unsigned)DLatency);
512  }
513 
514  // Try to schedule uses near definitions to generate .cur.
515  ExclSrc.clear();
516  ExclDst.clear();
517  if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
518  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
519  Dep.setLatency(0);
520  return;
521  }
522  int Latency = Dep.getLatency();
523  bool IsArtificial = Dep.isArtificial();
524  Latency = updateLatency(*SrcInst, *DstInst, IsArtificial, Latency);
525  Dep.setLatency(Latency);
526 }
527 
529  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
530  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
531  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
532  Mutations.push_back(std::make_unique<BankConflictMutation>());
533 }
534 
536  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
537  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
538  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
539 }
540 
541 // Pin the vtable to this file.
542 void HexagonSubtarget::anchor() {}
543 
546  return !DisableHexagonMISched;
547  return true;
548 }
549 
551  return EnablePredicatedCalls;
552 }
553 
554 int HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
555  MachineInstr &DstInst, bool IsArtificial,
556  int Latency) const {
557  if (IsArtificial)
558  return 1;
559  if (!hasV60Ops())
560  return Latency;
561 
562  auto &QII = static_cast<const HexagonInstrInfo &>(*getInstrInfo());
563  // BSB scheduling.
564  if (QII.isHVXVec(SrcInst) || useBSBScheduling())
565  Latency = (Latency + 1) >> 1;
566  return Latency;
567 }
568 
569 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
570  MachineInstr *SrcI = Src->getInstr();
571  for (auto &I : Src->Succs) {
572  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
573  continue;
574  Register DepR = I.getReg();
575  int DefIdx = -1;
576  for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
577  const MachineOperand &MO = SrcI->getOperand(OpNum);
578  bool IsSameOrSubReg = false;
579  if (MO.isReg()) {
580  Register MOReg = MO.getReg();
581  if (DepR.isVirtual()) {
582  IsSameOrSubReg = (MOReg == DepR);
583  } else {
584  IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
585  }
586  if (MO.isDef() && IsSameOrSubReg)
587  DefIdx = OpNum;
588  }
589  }
590  assert(DefIdx >= 0 && "Def Reg not found in Src MI");
591  MachineInstr *DstI = Dst->getInstr();
592  SDep T = I;
593  for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
594  const MachineOperand &MO = DstI->getOperand(OpNum);
595  if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
596  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
597  DefIdx, *DstI, OpNum));
598 
599  // For some instructions (ex: COPY), we might end up with < 0 latency
600  // as they don't have any Itinerary class associated with them.
601  Latency = std::max(Latency, 0);
602  bool IsArtificial = I.isArtificial();
603  Latency = updateLatency(*SrcI, *DstI, IsArtificial, Latency);
604  I.setLatency(Latency);
605  }
606  }
607 
608  // Update the latency of opposite edge too.
609  T.setSUnit(Src);
610  auto F = find(Dst->Preds, T);
611  assert(F != Dst->Preds.end());
612  F->setLatency(I.getLatency());
613  }
614 }
615 
616 /// Change the latency between the two SUnits.
617 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
618  const {
619  for (auto &I : Src->Succs) {
620  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
621  continue;
622  SDep T = I;
623  I.setLatency(Lat);
624 
625  // Update the latency of opposite edge too.
626  T.setSUnit(Src);
627  auto F = find(Dst->Preds, T);
628  assert(F != Dst->Preds.end());
629  F->setLatency(Lat);
630  }
631 }
632 
633 /// If the SUnit has a zero latency edge, return the other SUnit.
635  for (auto &I : Deps)
636  if (I.isAssignedRegDep() && I.getLatency() == 0 &&
637  !I.getSUnit()->getInstr()->isPseudo())
638  return I.getSUnit();
639  return nullptr;
640 }
641 
642 // Return true if these are the best two instructions to schedule
643 // together with a zero latency. Only one dependence should have a zero
644 // latency. If there are multiple choices, choose the best, and change
645 // the others, if needed.
646 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
647  const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
648  SmallSet<SUnit*, 4> &ExclDst) const {
649  MachineInstr &SrcInst = *Src->getInstr();
650  MachineInstr &DstInst = *Dst->getInstr();
651 
652  // Ignore Boundary SU nodes as these have null instructions.
653  if (Dst->isBoundaryNode())
654  return false;
655 
656  if (SrcInst.isPHI() || DstInst.isPHI())
657  return false;
658 
659  if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
660  !TII->canExecuteInBundle(SrcInst, DstInst))
661  return false;
662 
663  // The architecture doesn't allow three dependent instructions in the same
664  // packet. So, if the destination has a zero latency successor, then it's
665  // not a candidate for a zero latency predecessor.
666  if (getZeroLatency(Dst, Dst->Succs) != nullptr)
667  return false;
668 
669  // Check if the Dst instruction is the best candidate first.
670  SUnit *Best = nullptr;
671  SUnit *DstBest = nullptr;
672  SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
673  if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
674  // Check that Src doesn't have a better candidate.
675  DstBest = getZeroLatency(Src, Src->Succs);
676  if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
677  Best = Dst;
678  }
679  if (Best != Dst)
680  return false;
681 
682  // The caller frequently adds the same dependence twice. If so, then
683  // return true for this case too.
684  if ((Src == SrcBest && Dst == DstBest ) ||
685  (SrcBest == nullptr && Dst == DstBest) ||
686  (Src == SrcBest && Dst == nullptr))
687  return true;
688 
689  // Reassign the latency for the previous bests, which requires setting
690  // the dependence edge in both directions.
691  if (SrcBest != nullptr) {
692  if (!hasV60Ops())
693  changeLatency(SrcBest, Dst, 1);
694  else
695  restoreLatency(SrcBest, Dst);
696  }
697  if (DstBest != nullptr) {
698  if (!hasV60Ops())
699  changeLatency(Src, DstBest, 1);
700  else
701  restoreLatency(Src, DstBest);
702  }
703 
704  // Attempt to find another opprotunity for zero latency in a different
705  // dependence.
706  if (SrcBest && DstBest)
707  // If there is an edge from SrcBest to DstBst, then try to change that
708  // to 0 now.
709  changeLatency(SrcBest, DstBest, 0);
710  else if (DstBest) {
711  // Check if the previous best destination instruction has a new zero
712  // latency dependence opportunity.
713  ExclSrc.insert(Src);
714  for (auto &I : DstBest->Preds)
715  if (ExclSrc.count(I.getSUnit()) == 0 &&
716  isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
717  changeLatency(I.getSUnit(), DstBest, 0);
718  } else if (SrcBest) {
719  // Check if previous best source instruction has a new zero latency
720  // dependence opportunity.
721  ExclDst.insert(Dst);
722  for (auto &I : SrcBest->Succs)
723  if (ExclDst.count(I.getSUnit()) == 0 &&
724  isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
725  changeLatency(SrcBest, I.getSUnit(), 0);
726  }
727 
728  return true;
729 }
730 
732  return 32;
733 }
734 
736  return 32;
737 }
738 
740  return EnableSubregLiveness;
741 }
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::HexagonSubtarget::hasV68Ops
bool hasV68Ops() const
Definition: HexagonSubtarget.h:189
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:295
llvm::cl::Option::getPosition
unsigned getPosition() const
Definition: CommandLine.h:298
llvm::HexagonSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:286
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:519
ScheduleDAG.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
SchedPredsCloser
static cl::opt< bool > SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::ZeroOrMore, cl::init(true))
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
llvm::SDep::Artificial
@ Artificial
Arbitrary strong DAG edge (no real dependence).
Definition: ScheduleDAG.h:72
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
T
StringRef.h
ScheduleDAGInstrs.h
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1013
llvm::SubtargetFeatures::AddFeature
void AddFeature(StringRef String, bool Enable=true)
Adds Features.
Definition: SubtargetFeature.cpp:37
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:309
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::HexagonSubtarget::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: HexagonSubtarget.cpp:82
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
EnablePredicatedCalls
static cl::opt< bool > EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Consider calls to be predicable"))
llvm::HexagonSubtarget::useHVXFloatingPoint
bool useHVXFloatingPoint() const
Definition: HexagonSubtarget.h:221
HexagonSubtarget.h
ErrorHandling.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:549
llvm::HexagonInstrInfo::getAddrMode
unsigned getAddrMode(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3287
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:304
llvm::ScheduleDAGInstrs::addEdge
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Definition: ScheduleDAGInstrs.cpp:1195
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::SUnit::Succs
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
llvm::Optional
Definition: APInt.h:33
llvm::HexagonSubtarget::HexagonArchVersion
Hexagon::ArchEnum HexagonArchVersion
Definition: HexagonSubtarget.h:71
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::HexagonSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: HexagonSubtarget.cpp:739
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1293
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
SchedRetvalOptimization
static cl::opt< bool > SchedRetvalOptimization("sched-retval-optimization", cl::Hidden, cl::ZeroOrMore, cl::init(true))
STLExtras.h
llvm::PowerOf2Ceil
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
Definition: MathExtras.h:729
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:163
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::count_if
auto count_if(R &&Range, UnaryPredicate P)
Wrapper function around std::count_if to count the number of times an element satisfying a given pred...
Definition: STLExtras.h:1704
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:226
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::HexagonSubtarget::BankConflictMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:394
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::HexagonSubtarget::useHVXV69Ops
bool useHVXV69Ops() const
Definition: HexagonSubtarget.h:243
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
llvm::HexagonSubtarget::getHVXElementTypes
ArrayRef< MVT > getHVXElementTypes() const
Definition: HexagonSubtarget.h:304
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
llvm::SDep::isArtificial
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for c...
Definition: ScheduleDAG.h:200
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:334
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:731
CommandLine.h
llvm::HexagonSubtarget::getSMSMutations
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:535
llvm::HexagonTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: HexagonISelLowering.cpp:2151
llvm::HexagonSubtarget::UseBSBScheduling
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
Definition: HexagonSubtarget.h:76
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::SUnit::removePred
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
Definition: ScheduleDAG.cpp:175
TargetMachine.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::HexagonSubtarget::OptLevel
CodeGenOpt::Level OptLevel
Definition: HexagonSubtarget.h:73
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:308
llvm::SUnit::NodeNum
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:264
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::HexagonSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: HexagonSubtarget.cpp:544
llvm::SubtargetFeatures::getFeatures
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Definition: SubtargetFeature.h:196
llvm::SubtargetFeatures
Manages the enabling and disabling of subtarget specific features.
Definition: SubtargetFeature.h:183
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
EnableBSBSched
static cl::opt< bool > EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:222
llvm::HexagonInstrInfo::getType
uint64_t getType(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4623
llvm::HexagonSubtarget::isTinyCore
bool isTinyCore() const
Definition: HexagonSubtarget.h:214
HexagonGenSubtargetInfo
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:395
llvm::SDep::Output
@ Output
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
llvm::InstrItineraryData::Itineraries
const InstrItinerary * Itineraries
Array of itineraries selected.
Definition: MCInstrItineraries.h:116
HexagonInstrInfo.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::HexagonInstrInfo::getBaseAndOffset
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
Definition: HexagonInstrInfo.cpp:3296
Hexagon.h
llvm::HexagonSubtarget::isHVXVectorType
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:200
llvm::SDep::Order
@ Order
Any other ordering dependency.
Definition: ScheduleDAG.h:56
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:735
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:116
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
DisableHexagonMISched
static cl::opt< bool > DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
llvm::HexagonII::TypeS_2op
@ TypeS_2op
Definition: HexagonDepITypes.h:61
EnableV68FloatCodeGen
static cl::opt< bool > EnableV68FloatCodeGen("force-hvx-float", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable the code-generation for vector float instructions on v68."))
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::SubtargetFeatures::getString
std::string getString() const
Returns features as a string.
Definition: SubtargetFeature.cpp:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::cl::opt< bool >
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
getZeroLatency
static SUnit * getZeroLatency(SUnit *N, SmallVector< SDep, 4 > &Deps)
If the SUnit has a zero latency edge, return the other SUnit.
Definition: HexagonSubtarget.cpp:634
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::HexagonSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: HexagonSubtarget.cpp:443
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1625
llvm::HexagonII::TypeALU64
@ TypeALU64
Definition: HexagonDepITypes.h:21
EnableDotCurSched
static cl::opt< bool > EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
llvm::HexagonSubtarget::CallMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:325
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:561
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1670
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:850
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:864
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::Hexagon::getCpu
Optional< Hexagon::ArchEnum > getCpu(StringRef CPU)
Definition: HexagonDepArch.h:21
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1257
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::HexagonSubtarget::usePredicatedCalls
bool usePredicatedCalls() const
Definition: HexagonSubtarget.cpp:550
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1187
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::HexagonSubtarget::isHVXElementType
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:189
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::HexagonSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:528
llvm::SDep::Barrier
@ Barrier
An unknown scheduling barrier.
Definition: ScheduleDAG.h:69
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::StringRef::consumeInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:544
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:71
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::HexagonSubtarget::UsrOverflowMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:261
OverrideLongCalls
static cl::opt< bool > OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1285
j
return j(j<< 16)
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
std
Definition: BitVector.h:851
llvm::StringRef::drop_front
LLVM_NODISCARD StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
Definition: StringRef.h:653
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:125
llvm::HexagonSubtarget::initializeSubtargetDependencies
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
Definition: HexagonSubtarget.cpp:97
llvm::HexagonSubtarget::getTargetLowering
const HexagonTargetLowering * getTargetLowering() const override
Definition: HexagonSubtarget.h:128
EnableTCLatencySched
static cl::opt< bool > EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
llvm::SUnit::setHeightDirty
void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
Definition: ScheduleDAG.cpp:232
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1026
llvm::HexagonII::TypeS_3op
@ TypeS_3op
Definition: HexagonDepITypes.h:62
llvm::SDep::setLatency
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
llvm::HexagonSubtarget::useBSBScheduling
bool useBSBScheduling() const
Definition: HexagonSubtarget.h:255
llvm::SUnit::addPred
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
Definition: ScheduleDAG.cpp:107
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:140
MachineScheduler.h
SmallVector.h
llvm::SUnit::isInstr
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:362
N
#define N
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonInstrInfo::isToBeScheduledASAP
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition: HexagonInstrInfo.cpp:2721
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonInstrInfo::canExecuteInBundle
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
Definition: HexagonInstrInfo.cpp:3091
llvm::SmallSet::clear
void clear()
Definition: SmallSet.h:220
llvm::HexagonInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
Definition: HexagonInstrInfo.cpp:4333
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:439
llvm::SUnit::Preds
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::X86AS::FS
@ FS
Definition: X86.h:188
EnableCheckBankConflict
static cl::opt< bool > EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts"))
llvm::HexagonSubtarget::hasV60Ops
bool hasV60Ops() const
Definition: HexagonSubtarget.h:159
llvm::HexagonSubtarget::adjustSchedDependency
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Definition: HexagonSubtarget.cpp:451
llvm::HexagonSubtarget::HVXMemLatencyMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:274
llvm::SDep::getLatency
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:142
EnableSubregLiveness
static cl::opt< bool > EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
llvm::HexagonII::TypeM
@ TypeM
Definition: HexagonDepITypes.h:55
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
SpecialSubKind::string
@ string
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
SmallSet.h